Semiconductor package structure

Abstract

The semiconductor package structure provided by the present disclosure forms a metal layer on both end surfaces of a metal sheet (e.g., a copper foil) serving as a carrier by electroplating, and the metal layer reacts with the metal sheet to form an intermetallic compound (IMC) in a heating and pressing process. Since the melting point of the intermetallic compound (e.g., CuGa2) is higher than that of the metal layer (e.g., Ga) and is in a solid state, the whole forms a thermal interface material (TIM) that bonds a chip and a heat dissipation structure. The use of the metal sheet as the carrier can also meet the requirement that the height of the TIM exceeds 100 um. Compared with a conventional polymer material TIM, the thermal conductivity coefficient can be increased by more than 300%, and the heat dissipation performance of the chip is greatly improved.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, specifically to semiconductor packaging structures. Background Technology

[0002] With the development of multi-functional high-end chips, their thermal design power (TDP) continues to rise. TDP refers to the maximum heat a chip can generate when executing actual applications. When TDP is matched with the chip, the heat sink can effectively cool the chip. The higher the TDP, the more heat the chip will generate per unit time during operation. For heat dissipation systems, TDP is the minimum standard for heat dissipation design. That is to say, the heat dissipation system must be able to dissipate at least the heat represented by the TDP value per unit time.

[0003] The heat dissipation system uses a thermal interface material (TIM) with a high thermal conductivity to adhere to the chip surface, dissipating the heat generated by the chip to the outside. Current TIM materials are mainly formed by polymer materials containing metal powder. In recent years, soft metals with low melting points, such as gallium (Ga) or indium (In), have been used to prepare TIMs and uniformly coat them onto the chip surface for heat dissipation. However, taking gallium (Ga), with its low melting point (approximately 29.76°C), as an example, it is relatively soft at room temperature and easily liquefies during lamination, making it impossible to form a thin film. Furthermore, the TIM itself requires a certain height (approximately 80-100 μm). If gallium is used exclusively as the TIM, the cost is relatively high, and exceeding its melting point will cause it to liquefy and flow out, rendering it ineffective and resulting in low yield. Summary of the Invention

[0004] This disclosure provides a semiconductor packaging structure.

[0005] In a first aspect, this disclosure provides a semiconductor packaging structure, including:

[0006] chip;

[0007] Heat dissipation structure;

[0008] A thermal interface material is disposed between the chip and the heat dissipation structure. The thermal interface material includes a metal sheet, a first intermetallic compound layer disposed on the upper surface of the metal sheet and in contact with the heat dissipation structure, and a second intermetallic compound layer disposed on the lower surface of the metal sheet and in contact with the chip.

[0009] In some alternative embodiments, a first portion of the first intermetallic compound layer is generated by reacting a portion of the first metal layer with a portion of the metal sheet.

[0010] In some alternative embodiments, a first portion of the second intermetallic compound layer is generated by reacting a portion of the second metal layer with a portion of the metal sheet.

[0011] In some alternative embodiments, the first or second metal layer is gallium or indium, and the metal sheet is copper or nickel.

[0012] In some alternative embodiments, the first metal layer or the second metal layer is gallium, the metal sheet is copper, a first portion of the first intermetallic compound layer is CuGa2 generated by the reaction of a portion of the first metal layer and a portion of the metal sheet, and a first portion of the second intermetallic compound layer is CuGa2 generated by the reaction of a portion of the second metal layer and a portion of the metal sheet.

[0013] In some optional embodiments, the semiconductor package structure further includes:

[0014] A first metallization layer is disposed between the thermal interface material and the heat dissipation structure.

[0015] In some alternative embodiments, the first metallization layer is formed by nickel plating on the surface of the heat dissipation structure.

[0016] In some alternative embodiments, the second portion of the first intermetallic compound layer is generated by reacting a portion of the first metal layer with a portion of the first metallization layer.

[0017] In some alternative embodiments, the first metal layer is gallium, and the second portion of the first intermetallic compound layer is CuGa2 or Ga4Ni generated by reacting a portion of the first metal layer with a portion of the first metallization layer.

[0018] In some alternative embodiments, a second portion of the first intermetallic compound layer is generated by reacting a portion of the first metal layer with a portion of the heat dissipation structure.

[0019] In some optional embodiments, the semiconductor package structure further includes:

[0020] A second metallization layer is disposed between the thermal interface material and the chip.

[0021] In some alternative embodiments, the second metallization layer is formed by plating copper or nickel onto the chip surface.

[0022] In some alternative embodiments, a second portion of the second intermetallic compound layer is formed by reacting a portion of the second metal layer with a portion of the second metallization layer.

[0023] In some alternative embodiments, the second metal layer is gallium, and the second portion of the second intermetallic compound layer is CuGa2 or Ga4Ni generated by the reaction of a portion of the second metal layer with a portion of the second metallization layer.

[0024] The semiconductor packaging structure disclosed herein utilizes electroplating to form metal layers on both ends of a metal sheet (e.g., copper foil) serving as a carrier. During heating and pressing, the metal layers react with the metal sheet to generate an intermetallic compound (IMC). Since the IMC (e.g., CuGa2) has a higher melting point than the metal layer (e.g., Ga) and is solid, it forms a thermal interface material (TIM) that bonds the chip to the heat dissipation structure. Furthermore, using a metal sheet as a carrier can meet the requirement of a TIM height exceeding 100µm. Compared to TIMs made from traditional polymer materials, this increases the thermal conductivity by approximately 300% or more, significantly improving the chip's heat dissipation performance. Additionally, it effectively addresses the high cost associated with fabricating TIMs using only low-melting-point, soft metal materials, thus offering a cost advantage. Attached Figure Description

[0025] Other features, objects, and advantages of this disclosure will become more apparent from the following detailed description of non-limiting embodiments with reference to the accompanying drawings:

[0026] Figure 1 This is a first structural schematic diagram of the semiconductor packaging structure according to the present disclosure;

[0027] Figure 2 This is a second structural schematic diagram of the semiconductor packaging structure according to the present disclosure;

[0028] Figures 3-7 This is a schematic diagram of the manufacturing process of the semiconductor packaging structure according to the present disclosure.

[0029] Symbol explanation:

[0030] 1-Chip, 2-Heat dissipation structure, 3-Thermal interface material, 31-Metal sheet, 32-Second intermetallic compound layer, 33-First intermetallic compound layer, 4-Second metallization layer, 5-Second metal layer, 6-First metal layer, 7-First metallization layer. Detailed Implementation

[0031] The specific embodiments of this disclosure will be described below with reference to the accompanying drawings and examples. Those skilled in the art can easily understand the technical problems solved by this disclosure and the resulting technical effects through the content described herein. It is understood that the specific embodiments described herein are merely illustrative of the relevant invention and not intended to limit the invention. Furthermore, for ease of description, only the parts relevant to the invention are shown in the accompanying drawings.

[0032] It should be noted that the structures, proportions, sizes, etc., depicted in the accompanying drawings are only for illustrative purposes to aid those skilled in the art in understanding and reading the content described herein, and are not intended to limit the implementation conditions of this disclosure. Therefore, they have no substantial technical significance. Any modifications to the structure, changes in proportions, or adjustments to size, without affecting the effectiveness and purpose of this disclosure, should still fall within the scope of the technical content disclosed herein. Furthermore, terms such as "above," "first," "second," and "a" used in this specification are merely for clarity of description and are not intended to limit the scope of this disclosure. Changes or adjustments to their relative relationships, without substantially altering the technical content, should also be considered within the scope of this disclosure's implementation.

[0033] Furthermore, the embodiments and features described herein can be combined with each other, unless otherwise specified. This disclosure will now be described in detail with reference to the accompanying drawings and embodiments.

[0034] Figure 1 This is a first structural schematic diagram of the semiconductor packaging structure according to this disclosure. (See attached diagram.) Figure 1 As shown, the semiconductor package structure may include a chip 1, a heat dissipation structure 2, a thermal interface material 3, and a second metallization layer 4. The thermal interface material 3 may be disposed between the chip 1 and the heat dissipation structure 2. The second metallization layer 4 may be disposed between the thermal interface material 3 and the chip 1. The thermal interface material 3 may include a metal sheet 31, a first intermetallic compound layer 33, and a second intermetallic compound layer 32. The first intermetallic compound layer 33 may be disposed on the upper surface of the metal sheet 31 and in contact with the heat dissipation structure 2. The second intermetallic compound layer 32 may be disposed on the lower surface of the metal sheet 31 and in contact with the chip 1.

[0035] In this embodiment, chip 1 may be, for example, a power management integrated circuit (PMIC). The heat dissipation structure 2 can perform heat dissipation and may be a heat sink or other conductive materials such as aluminum (Al), copper (Cu), chromium (Cr), tin (Sn), gold (Au), silver (Ag), nickel (Ni), or stainless steel. The metal sheet 31 may be made of a metallic material, such as copper or nickel.

[0036] In this embodiment, the second metallization layer 4 can be formed by plating copper or nickel on the surface of chip 1. During the manufacturing process, such as... Figure 6 As shown, since the main component of chip 1 is silicon (Si), and the second metal layer 5 (e.g. Ga) is difficult to react with Si, a metallization process is required on the surface of chip 1, namely, electroplating metal (e.g. Cu or Ni) to form the second metallization layer 4.

[0037] In this embodiment, the first intermetallic compound layer 33 can be, for example, an intermetallic compound, such as CuGa2. During the manufacturing process, as... Figure 6 As shown, the first portion of the first intermetallic compound layer 33 can be formed by the reaction of a portion of the first metal layer 6 with a portion of the metal sheet 31. The first metal layer 6 can be a low-melting-point soft metal material, such as gallium or indium. For example, if the first metal layer 6 is gallium and the metal sheet 31 is copper, then the first portion of the first intermetallic compound layer 33 can be CuGa2 formed by the reaction of a portion of the first metal layer 6 with a portion of the metal sheet 31. When the heat dissipation structure 2 is a metal heat sink (e.g., a copper sheet), the second portion of the first intermetallic compound layer 33 can be formed by the reaction of a portion of the first metal layer 6 with a portion of the heat dissipation structure 2.

[0038] In this embodiment, the second intermetallic compound layer 32 can be, for example, an intermetallic compound, such as CuGa2. During the fabrication process, as... Figure 6 As shown, the first portion of the second intermetallic compound layer 32 can be formed by reacting a portion of the second metal layer 5 with a portion of the metal sheet 31. The second metal layer 5 can be a low-melting-point, soft metallic material, such as gallium or indium. For example, if the second metal layer 5 is gallium and the metal sheet 31 is copper, the first portion of the second intermetallic compound layer 32 can be CuGa2 formed by reacting a portion of the second metal layer 5 with a portion of the metal sheet 31. The second portion of the second intermetallic compound layer 32 can be formed by reacting a portion of the second metal layer 5 with a portion of the second metallization layer 4. For example, if the second metal layer 5 is gallium and the second metallization layer 4 is copper or nickel, then the second portion of the second intermetallic compound layer 32 can be CuGa2 or Ga4Ni formed by reacting a portion of the second metal layer 5 with a portion of the second metallization layer 4.

[0039] Figure 2 This is a second structural schematic diagram of a semiconductor packaging structure according to this disclosure. Relative to... Figure 1 In the semiconductor packaging structure shown, when the heat dissipation structure 2 is a copper sheet, for aesthetic reasons and to prevent copper oxidation, Figure 2 The semiconductor structure shown also includes a first metallization layer 7. The first metallization layer 7 can be disposed between the thermal interface material 3 and the heat dissipation structure 2. The first metallization layer 7 can be formed by nickel plating on the surface of the heat dissipation structure 2. In the manufacturing process, such as... Figure 7 As shown, the surface of the heat dissipation structure 2 needs to be metallized, i.e., electroplated with nickel, to form a first metallization layer 7. Then, the second part of the first intermetallic compound layer 33 can be formed by the reaction of a portion of the first metal layer 6 and a portion of the first metallization layer 7. For example, if the first metal layer 6 is gallium and the first metallization layer 7 is nickel, then the second part of the first intermetallic compound layer 33 can be formed by the reaction of a portion of the first metal layer 6 and a portion of the first metallization layer 7 to produce Ga4Ni.

[0040] Figures 3 to 7 This is a schematic diagram of the manufacturing process of the semiconductor packaging structure according to the present disclosure. The figures have been simplified for better understanding of various aspects of the present disclosure.

[0041] like Figure 3 As shown, a metal sheet 31 is provided.

[0042] like Figure 4 As shown, a first metal layer 6 is formed on one surface of the metal sheet 31. A second metal layer 5 is formed on the other surface of the metal sheet 31.

[0043] like Figure 5 As shown, a portion of the first metal layer 6 and a portion of the metal sheet 31 react to form a first portion of the first intermetallic compound layer 33. This first portion of the first intermetallic compound layer 33 can serve as a bonding layer between the first metal layer 6 and the metal sheet 31. A portion of the second metal layer 5 and a portion of the metal sheet 31 react to form a first portion of the second intermetallic compound layer 32. This first portion of the second intermetallic compound layer 32 can serve as a bonding layer between the second metal layer 5 and the metal sheet 31.

[0044] like Figure 6 As shown, a second metallization layer 4 is formed on the surface of chip 1. It is bonded to both chip 1 and heat dissipation structure 2. The unreacted second metal layer 5 reacts with a portion of the second metallization layer 4 to form a second portion of the second intermetallic compound layer 32. A portion of the first metal layer 6 reacts with a portion of the heat dissipation structure 2 to form a second portion of the first intermetallic compound layer 33, resulting in the semiconductor package structure shown in Figure 1.

[0045] Here, when the heat dissipation structure 2 is a metal heat sink, it can directly react with the first metal layer 6 (e.g., Ga).

[0046] like Figure 7As shown, a second metallization layer 4 is formed on the surface of chip 1. A first metallization layer 7 is formed on the surface of heat dissipation structure 2. Both are bonded to chip 1 and heat dissipation structure 2 respectively. The unreacted second metal layer 5 reacts with a portion of the second metallization layer 4 to form a second portion of the second intermetallic compound layer 32. A portion of the first metal layer 6 reacts with a portion of the first metallization layer 7 to form a second portion of the first intermetallic compound layer 33, resulting in the semiconductor package structure shown in Figure 2.

[0047] Here, when the heat dissipation structure 2 is a copper sheet, in order to improve the appearance and prevent the oxidation of copper, the surface of the heat dissipation structure 2 needs to be metallized, that is, electroplated with nickel to form the first metallization layer 7.

[0048] The semiconductor packaging structure disclosed herein utilizes electroplating to form a first metal layer 6 and a second metal layer 5 on both ends of a metal sheet 31 (e.g., copper foil) serving as a carrier. The second metal layer 5 reacts with the metal sheet 31 to form a first portion of a second intermetallic compound layer 32. The second metal layer 5 reacts with a second metallization layer 4 to form a second portion of the second intermetallic compound layer 32. The first metal layer 6 reacts with the metal sheet 31 to form a first portion of a first intermetallic compound layer 33. The first metal layer 6 reacts with a first metallization layer 7 / heat dissipation structure 2 to form a second portion of the first intermetallic compound layer 33.

[0049] Because the melting point of the first intermetallic compound layer 33 / second intermetallic compound layer 32 (e.g., CuGa2) is higher than that of the first metal layer 6 / second metal layer 5 (e.g., Ga) and they are solid, the entire structure forms a thermal interface material (TIM) 3 that bonds the chip 1 and the heat dissipation structure 2. Furthermore, using a metal sheet 31 as a carrier also meets the requirement of a TIM height exceeding 100µm. Compared to TIMs made from traditional polymer materials, this increases the thermal conductivity by approximately 300% or more, significantly improving the chip's heat dissipation performance. In addition, it effectively addresses the high cost of fabricating TIMs using only low-melting-point, soft metal materials, thus improving cost-effectiveness.

[0050] Although this disclosure has been described and illustrated with reference to specific embodiments thereof, such descriptions and illustrations are not limiting of this disclosure. It will be readily understood by those skilled in the art that various changes can be made and equivalent elements can be substituted within embodiments without departing from the true spirit and scope of this disclosure as defined by the appended claims. Illustrations may not be drawn to scale. Differences may exist between the technical representation in this disclosure and actual implementation due to variables in the manufacturing process, etc. Other embodiments of this disclosure may exist that are not specifically described. The description and illustrations should be considered illustrative rather than restrictive. Modifications can be made to adapt particular circumstances, materials, composition, methods, or processes to the objectives, spirit, and scope of this disclosure. All such modifications fall within the scope of the appended claims. While the methods disclosed herein have been described with reference to specific operations performed in a particular order, it should be understood that these operations can be combined, subdivided, or reordered to form equivalent methods without departing from the teachings of this disclosure. Therefore, unless specifically indicated herein, the order and grouping of operations do not limit this disclosure.

Claims

1. A semiconductor package structure, comprising: chip; Heat dissipation structure; A thermal interface material is disposed between the chip and the heat dissipation structure. The thermal interface material includes a metal sheet, a first intermetallic compound layer disposed on the upper surface of the metal sheet and in contact with the heat dissipation structure, and a second intermetallic compound layer disposed on the lower surface of the metal sheet and in contact with the chip. The metal sheet is made of copper or nickel; Wherein, the first portion of the first intermetallic compound layer is generated by the reaction of a portion of the first metal layer with a portion of the metal sheet; Wherein, the second part of the first intermetallic compound layer is generated by the reaction of a portion of the first metal layer with a portion of the heat dissipation structure, or, when a first metallization layer is formed on the surface of the heat dissipation structure between the thermal interface material and the heat dissipation structure, the second part of the first intermetallic compound layer is generated by the reaction of a portion of the first metal layer with a portion of the first metallization layer. The first part of the second intermetallic compound layer is generated by the reaction of a portion of the second metal layer with a portion of the metal sheet; The chip surface is provided with a second metallization layer between the thermal interface material and the chip, and the second part of the second intermetallic compound layer is generated by the reaction of a portion of the second metal layer and a portion of the second metallization layer.

2. The semiconductor packaging structure according to claim 1, wherein, The first metal layer or the second metal layer is gallium or indium.

3. The semiconductor packaging structure according to claim 2, wherein, The first or second metal layer is gallium, the metal sheet is copper, the first part of the first intermetallic compound layer is CuGa2 generated by the reaction of a portion of the first metal layer and a portion of the metal sheet, and the first part of the second intermetallic compound layer is CuGa2 generated by the reaction of a portion of the second metal layer and a portion of the metal sheet.

4. The semiconductor packaging structure according to claim 1, wherein, The first metallization layer is formed by plating nickel on the surface of the heat dissipation structure.

5. The semiconductor packaging structure according to claim 1, wherein, The first metal layer is gallium, and the second part of the first intermetallic compound layer is CuGa2 or Ga4Ni generated by the reaction of a portion of the first metal layer with a portion of the first metallization layer.

6. The semiconductor packaging structure according to claim 1, wherein, The second metallization layer is formed by plating copper or nickel on the surface of the chip.

7. The semiconductor packaging structure according to claim 1, wherein, The second metal layer is gallium, and the second part of the second intermetallic compound layer is CuGa2 or Ga4Ni generated by the reaction of a portion of the second metal layer with a portion of the second metallization layer.

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