Semiconductor package including stacked semiconductor chips

Abstract

The present application discloses a semiconductor package including stacked semiconductor chips. The semiconductor package includes: a substrate; a sub-semiconductor package disposed above the substrate, the sub-semiconductor package including a sub-semiconductor chip, a sub-molding layer, and a redistribution conductive layer; a die pad on an active surface of the sub-semiconductor chip facing the substrate; a sub-molding layer surrounding a side surface of the sub-semiconductor chip; a sub-molding layer having a surface facing the substrate; and a redistribution conductive layer connected to the die pad and extending below the surface of the sub-molding layer; a signal sub-interconnector having an upper surface connected to the signal redistribution pad and a lower surface connected to the substrate; a power sub-interconnector having an upper surface connected to the power redistribution pad and a lower surface connected to the substrate; and at least one main semiconductor chip formed above the sub-semiconductor package and electrically connected to the substrate.

Description

Technical Field

[0001] This patent document relates to a semiconductor package, and more particularly, to a semiconductor package in which a plurality of semiconductor chips are stacked in a vertical direction. Background Art

[0002] As electronic products become smaller and smaller, they require large-capacity data processing. Therefore, there is an increasing demand for increasing the integration level of semiconductor devices used in these electronic products.

[0003] However, due to limitations in semiconductor integration technology, it is difficult to satisfy required functions using only a single semiconductor chip, and thus, semiconductor packages having a plurality of semiconductor chips embedded therein have been manufactured. Summary of the Invention

[0004] In an embodiment, a semiconductor package may include: a substrate; a sub-semiconductor package disposed over the substrate, the sub-semiconductor package including a sub-semiconductor chip, a sub-molding layer, and a redistribution conductive layer, the sub-semiconductor chip having a chip pad on an active surface facing the substrate, the sub-molding layer surrounding a side surface of the sub-semiconductor chip, the sub-molding layer having a surface facing the substrate, the redistribution conductive layer connected to the chip pad and extending below the surface of the sub-molding layer, wherein the redistribution conductive layer includes a signal redistribution conductive layer and a power redistribution conductive layer extending toward an edge of the sub-molding layer, the signal redistribution conductive layer having a signal redistribution pad at an end thereof, the power redistribution conductive layer having a length shorter than that of the signal redistribution conductive layer, and the power redistribution conductive layer having a power redistribution pad at an end thereof; a signal sub-interconnector having an upper surface connected to the signal redistribution pad and a lower surface connected to the substrate; a power sub-interconnector having an upper surface connected to the power redistribution pad and a lower surface connected to the substrate; and at least one main semiconductor chip formed over the sub-semiconductor package and electrically connected to the substrate.

[0005] In another embodiment, a semiconductor package may include: a substrate; a sub-semiconductor package arranged over the substrate, the sub-semiconductor package including a sub-semiconductor chip, a sub-molding layer, and a signal redistribution conductive layer and a power redistribution conductive layer, the sub-semiconductor chip having a chip pad on an effective surface facing the substrate, the sub-molding layer surrounding a side surface of the sub-semiconductor chip, the sub-molding layer having a surface facing the substrate, the signal redistribution conductive layer and the power redistribution conductive layer connected to the chip pad and extending below the surface of the sub-molding layer to an edge of the sub-molding layer; a signal sub-interconnector having an upper surface connected to a signal redistribution pad formed at an end of the signal redistribution conductive layer and a lower surface connected to the substrate; a second power sub-interconnector having an upper surface connected to a second power redistribution pad formed at an end of the power redistribution conductive layer and a lower surface connected to the substrate; a first power sub-interconnector having an upper surface connected to a first power redistribution pad formed at a portion of the power redistribution conductive layer excluding the end of the power redistribution conductive layer and a lower surface connected to the substrate; and at least one main semiconductor chip formed over the sub-semiconductor package and electrically connected to the substrate.

[0006] In an embodiment, a semiconductor package may include: a substrate; a sub-semiconductor package having a sub-semiconductor chip disposed over the substrate, the sub-semiconductor package further comprising: a chip pad on a surface of the sub-semiconductor chip facing the substrate; a sub-molding layer surrounding a side surface of the sub-semiconductor chip such that the sub-molding layer has a surface facing the substrate, wherein the surface of the sub-molding layer is at the same level as the surface of the sub-semiconductor chip facing the substrate; and a redistribution conductive layer connected to the chip pad, wherein the redistribution conductive layer includes a signal redistribution conductive layer and a power redistribution conductive layer, wherein the signal redistribution conductive layer has a signal redistribution pad at an end thereof and the power redistribution conductive layer has a power redistribution pad at an end thereof, and wherein a length of the power redistribution conductive layer is shorter than a length of the signal redistribution conductive layer; a signal sub-interconnector having an upper surface connected to the signal redistribution pad and a lower surface connected to the substrate; a power sub-interconnector having an upper surface connected to the power redistribution pad and a lower surface connected to the substrate; and at least one main semiconductor chip formed over the sub-semiconductor package and electrically connected to the substrate. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1 is a plan view of a sub-semiconductor package according to an embodiment of the present disclosure when viewed from the top.

[0008] Figure 2 It is along Figure 1 A cross-sectional view taken along line A1-A1'.

[0009] Figure 3 It is along Figure 1 A cross-sectional view taken along line A2-A2'.

[0010] Figure 4 is a plan view illustrating a semiconductor package according to an embodiment of the present disclosure when viewed from the top.

[0011] Figure 5 It is an example Figure 4 A plan view of the upper surface of a substrate of a semiconductor package.

[0012] Figure 6 and Figure 7 It is an example Figure 4 A cross-sectional view of a semiconductor package.

[0013] Figure 8A are diagrams illustrating examples of effects of the semiconductor package according to the embodiments of the present disclosure.

[0014] Figure 8B 1 and 2 are diagrams illustrating the effects of a semiconductor package according to a comparative example.

[0015] Figure 9 is a plan view illustrating a sub-semiconductor package according to another embodiment of the present disclosure.

[0016] Figure 10 is a plan view illustrating a sub-semiconductor package according to another embodiment of the present disclosure when viewed from the top.

[0017] Figure 11 It is along Figure 10 A cross-sectional view taken along line A3-A3'.

[0018] Figure 12 is a plan view illustrating a semiconductor package according to another embodiment of the present disclosure when viewed from the top.

[0019] Figure 13 It is an example Figure 12 A plan view of the upper surface of a substrate of a semiconductor package.

[0020] Figure 14 It is an example Figure 12 A cross-sectional view of a semiconductor package.

[0021] Figure 15 A block diagram illustrating an electronic system employing a memory card including a semiconductor package according to an embodiment is shown.

[0022] Figure 16 A block diagram illustrating another electronic system including a semiconductor package according to an embodiment is shown. DETAILED DESCRIPTION

[0023] Hereinafter, various embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0024] The drawings are not necessarily drawn to scale. In some cases, the proportions of at least some of the structures in the drawings may have been exaggerated in order to clearly illustrate specific features of the described embodiments. When a specific example in a drawing or description is presented with two or more layers in a multilayer structure, the relative positioning relationship of these layers or the order in which the layers are arranged as shown reflects the specific implementation of the example described or shown, and different relative positioning relationships or orders of the layers may be possible. In addition, the described or shown examples of multilayer structures may not reflect all the layers present in the particular multilayer structure (for example, one or more additional layers may be present between the two shown layers). As a specific example, when the first layer in the described or shown multilayer structure is referred to as being "on" or "above" the second layer or "on" or "above" the substrate, the first layer may be formed directly on the second layer or substrate, but it may also represent a structure in which one or more other intermediate layers may be present between the first layer and the second layer or substrate.

[0025] In the following description of the embodiments, when a parameter is referred to as "predetermined," it may be intended to mean that the value of the parameter is predetermined when the parameter is used in a process or algorithm. The value of the parameter may be set at the start of the process or algorithm, or may be set during the execution of the process or algorithm.

[0026] It will be understood that although the terms "first," "second," "third," etc. are used herein to describe various elements, these elements should not be limited by these terms. These terms are merely used to distinguish one element from another. Thus, a first element in some embodiments may be referred to as a second element in other embodiments without departing from the technology of the present disclosure.

[0027] Furthermore, it will be understood that when an element is referred to as being “connected” or “coupled” to another element, it can be directly connected or coupled to the other element or intervening elements may be present. In contrast, when an element is referred to as being “directly connected” or “directly coupled” to another element, there are no intervening elements.

[0028] A semiconductor package according to an embodiment of the present disclosure may include a main semiconductor chip that performs a main function and a sub-semiconductor chip that performs various functions required for the operation of the main semiconductor chip. The main semiconductor chip may include a non-volatile memory such as a NAND flash memory, and in this case, the sub-semiconductor chip may include a memory controller. However, the present disclosure is not limited thereto, and each of the main semiconductor chip and the sub-semiconductor chip may include various types of memory, logic circuits, etc. In this embodiment, the sub-semiconductor chip may be packaged and implemented as a sub-semiconductor package, and the main semiconductor chip may be formed above the sub-semiconductor package.

[0029] Hereinafter, before describing the semiconductor package of the present embodiment, a sub-semiconductor package included in the semiconductor package will be described first.

[0030] Figure 1 is a plan view of a sub-semiconductor package according to an embodiment of the present disclosure when viewed from the top. Figure 2 It is along Figure 1 A cross-sectional view taken along line A1-A1'. Figure 3 It is along Figure 1 A cross-sectional view taken along line A2-A2'. Figure 2 and Figure 3 A state is shown in which the active surface of the sub-semiconductor chip faces upward.

[0031] Reference Figures 1 to 3 The sub-semiconductor package 110 of this embodiment may include a sub-semiconductor chip 114 , a sub-mold layer 116 , a redistribution structure 118 , and a sub-interconnector 119 .

[0032] The sub-semiconductor chip 114 may have an active surface 114A provided with a plurality of sub-chip pads 115, an inactive surface 114B located on the opposite side of the active surface 114A, and a side surface 114C connecting the active surface 114A and the inactive surface 114B. In this embodiment, the sub-semiconductor chip 114 may have four side surfaces 114C, which may have a rectangular shape in plan view. The four side surfaces 114C may be located on both sides in a first direction and on both sides in a second direction, the second direction being perpendicular to the first direction.

[0033] The plurality of sub-chip pads 115 can be arranged in various forms while having upper surfaces exposed from the active surface 114A. As an example, the sub-chip pads 115 can be arranged along the entire edge of the sub-semiconductor chip 114. That is, the sub-chip pads 115 can be provided at two side edges (the first side edge and the second side edge) of the sub-semiconductor chip 114 in the first direction and at two side edges (the third side edge and the fourth side edge) of the sub-semiconductor chip 114 in the second direction. In this case, a large number of sub-chip pads 115 can be formed in the sub-semiconductor chip 114 having a relatively small planar area, and therefore a large number of input / output signals can be transmitted through the sub-semiconductor chip 114.

[0034] The sub-semiconductor chip 114 may be located in a central region of the sub-semiconductor package 110. This may be to reduce variations in length of a plurality of signal redistribution conductive layers 118B-S (described later).

[0035] The sub-mold layer 116 may have one surface 116A that is substantially level with the active surface 114A of the sub-semiconductor chip 114 while surrounding the side surface 114C of the sub-semiconductor chip 114. Thus, the sub-mold layer 116 may expose the active surface 114A and the sub-chip pad 115 of the sub-semiconductor chip 114. In this embodiment, the sub-mold layer 116 may cover the inactive surface 114B of the sub-semiconductor chip 114. However, the present disclosure is not limited thereto. In another embodiment, the sub-mold layer 116 may have another surface 116B located on the opposite side of the one surface 116A and substantially level with the inactive surface 114B of the sub-semiconductor chip 114. The sub-mold layer 116 may include various molding materials, such as epoxy molding compound (EMC).

[0036] A redistribution structure 118 may be formed over an active surface 114A of the sub-semiconductor chip 114 and one surface 116A of the sub-mold layer 116. The redistribution structure 118 may include a redistribution conductive layer 118B extending into the one surface 116A of the sub-mold layer 116 and electrically connected to the sub-chip pad 115. That is, the sub-semiconductor package 110 according to this embodiment may be a fan-out package.

[0037] More specifically, the redistribution structure 118 may include a first redistribution insulation layer 118A, a redistribution conductive layer 118B, and a second redistribution insulation layer 118C.

[0038] A first redistribution insulating layer 118A may cover an active surface 114A of the sub-semiconductor chip 114 and one surface 116A of the sub-mold layer 116. The first redistribution insulating layer 118A may have an opening that exposes the sub-chip pad 115. A redistribution conductive layer 118B may be formed over the first redistribution insulating layer 118A. The redistribution conductive layer 118B may be electrically connected to the sub-chip pad 115 through the opening in the first redistribution insulating layer 118A. The redistribution conductive layer 118B may include a signal redistribution conductive layer 118B-S and a power redistribution conductive layer 118B-P. A second redistribution insulating layer 118C may cover the first redistribution insulating layer 118A and the redistribution conductive layer 118B. The second redistribution insulating layer 118C may have an opening that exposes ends of the signal redistribution conductive layer 118B-S and the power redistribution conductive layer 118B-P. The end portion of the signal redistribution conductive layer 118B-S exposed through the opening of the second redistribution insulating layer 118C will be referred to as a signal redistribution pad 118BP-S, and the end portion of the power redistribution conductive layer 118B-P exposed through the opening of the second redistribution insulating layer 118C will be referred to as a power redistribution pad 118BP-P. The signal redistribution conductive layer 118B-S, the signal redistribution pad 118BP-S, the power redistribution conductive layer 118B-P, and the power redistribution pad 118BP-P will be described in more detail below. The first redistribution insulating layer 118A and / or the second redistribution insulating layer 118C may include an insulating material such as an oxide, a nitride, or an oxynitride. Alternatively, the first redistribution insulating layer 118A and / or the second redistribution insulating layer 118C may include a resin material such as an epoxy resin, polyimide, polybenzoxazole (PBO), benzocyclobutene (BCB), silicone resin, or epoxy resin. The redistribution conductive layer 118B may include a metal material such as copper or a copper alloy.

[0039] The signal redistribution conductive layers 118B-S can be used for signal transmission between the sub-semiconductor chip 114 and other components. For example, the signal redistribution conductive layers 118B-S can be used for signal exchange between the sub-semiconductor chip 114 and a main semiconductor chip (described later), or between the sub-semiconductor chip 114 and a substrate (described later). Hereinafter, signals exchanged between the sub-semiconductor chip 114 and the main semiconductor chip will be referred to as internal signals, and signals exchanged between the sub-semiconductor chip 114 and the substrate will be referred to as external signals.

[0040] The plurality of signal redistribution conductive layers 118B-S may extend toward both side edges of the sub-mold layer 116 in the first direction. For example, the signal redistribution conductive layers 118B-S connected to the sub-chip pads 115 disposed at the first and third side edges of the sub-semiconductor chip 114 in the first and second directions, respectively, may extend to the first side edge of the sub-mold layer 116 in the first direction. Furthermore, the signal redistribution conductive layers 118B-S connected to the sub-chip pads 115 disposed at the second and fourth side edges of the sub-semiconductor chip 114 in the first and second directions, respectively, may extend to the second side edge of the sub-mold layer 116 in the first direction. The signal redistribution conductive layers 118B-S extending from both side edges of the sub-semiconductor chip 114 in the second direction may have a shape that curves toward both side edges of the sub-mold layer 116 in the first direction. On the other hand, the signal redistribution conductive layers 118B-S extending from both side edges of the sub-semiconductor chip 114 in the first direction may not need to bend. However, the signal redistribution conductive layer 118B-S extending from both side edges of the sub-semiconductor chip 114 in the first direction may also have a curved shape so as to have a length similar to the length of the signal redistribution conductive layer 118B-S extending from both side edges of the sub-semiconductor chip 114 in the second direction. As a result, the signal redistribution conductive layer 118B-S may have a spiral shape centered on the sub-semiconductor chip 114. With this connection scheme, variations in the length of the signal redistribution conductive layer 118B-S can be reduced.

[0041] Depending on the arrangement of the signal redistribution conductive layers 118B-S, the signal redistribution pads 118BP-S may be arranged along the second direction at each of the two side edges of the sub-mold layer 116 in the first direction. For reference, the signal redistribution conductive layers 118B-S may have a linear portion with a relatively small width extending from the sub-chip pads 115. The signal redistribution conductive layers 118B-S may also have a plate-shaped end portion with a relatively large width located at the end of the linear portion. The opening of the second redistribution insulating layer 118C may expose the plate-shaped end portion of the signal redistribution conductive layer 118B-S and may have a planar area that is less than or equal to the planar area of ​​the plate-shaped end portion while overlapping with the plate-shaped end portion.

[0042] The power redistribution conductive layer 118B-P may be used to supply power from a substrate (described later) to the sub-semiconductor chip 114. Various levels of power voltage or ground voltage may be supplied to the sub-semiconductor chip 114 through the power redistribution conductive layer 118B-P.

[0043] A plurality of power redistribution conductive layers 118B-P may be connected to the chiplet pads 115 and may extend onto one surface 116A of the sub-molding layer 116. The power redistribution conductive layers 118B-P may be shorter than the signal redistribution conductive layers 118B-S. That is, unlike the signal redistribution conductive layers 118B-S, the power redistribution conductive layers 118B-P may not extend to the edge of the sub-molding layer 116. The power redistribution conductive layers 118B-P may be substantially parallel to a portion of an adjacent signal redistribution conductive layer 118B-S. This may be to prevent electrical shorting between the power redistribution conductive layers 118B-P and the signal redistribution conductive layers 118B-S.

[0044] Depending on the arrangement of power redistribution conductive layer 118B-P, multiple power redistribution pads 118BP-P may be arranged at predetermined intervals around sub-semiconductor chip 114. For reference, power redistribution conductive layer 118B-P may have a linear portion with a relatively small width extending from sub-chip pad 115. Power redistribution conductive layer 118B-P may also have a plate-shaped end portion with a relatively large width located at the end of the linear portion. The opening in second redistribution insulating layer 118C may expose the plate-shaped end portion of power redistribution conductive layer 118B-P and may have a planar area that is less than or equal to the planar area of ​​the plate-shaped end portion while overlapping with the plate-shaped end portion.

[0045] The sub-interconnectors 119 may include a signal sub-interconnector 119-S that overlaps and is connected to the signal redistribution pad 118BP-S and a power sub-interconnector 119-P that overlaps and is connected to the power redistribution pad 118BP-P. Since the positions of the signal redistribution pad 118BP-S and the signal sub-interconnector 119-S are substantially the same in a plan view and the positions of the power redistribution pad 118BP-P and the power sub-interconnector 119-P are substantially the same in a plan view, the signal redistribution pad 118BP-S and the signal sub-interconnector 119-S are substantially the same in a plan view. Figure 1 are shown together in the plan view, and the power redistribution pad 118BP-P and the power sub-interconnect 119-P are in Figure 1 A plurality of signal sub-interconnectors 119-S may be provided along the second direction at both side edges of the sub-mold layer 116 in the first direction. A plurality of power sub-interconnectors 119-P may be arranged to surround the sub-semiconductor chip 114 at predetermined intervals.

[0046] Sub-interconnectors 119 may be connected to signal redistribution pads 118BP-S or power redistribution pads 118BP-P through openings in second redistribution insulating layer 118C and may protrude above the surface of second redistribution insulating layer 118C. Sub-interconnectors 119 may include solder balls, metal bumps, or a combination thereof. However, the present embodiment is not limited thereto, and various forms of electrical interconnectors that protrude above the surface of second redistribution insulating layer 118C while being connected to signal redistribution pads 118BP-S or power redistribution pads 118BP-P may be used as sub-interconnectors 119.

[0047] In addition, the signal redistribution pads 118BP-S and the signal sub-interconnects 119-S can be categorized as those that exchange the aforementioned internal signals and those that exchange the aforementioned external signals. The signal redistribution pads 118BP-S and the signal sub-interconnects 119-S that exchange internal signals will be referred to as internal signal redistribution pads 118BP-S1 and internal signal sub-interconnects 119-S1, respectively. Furthermore, the signal redistribution pads 118BP-S and the signal sub-interconnects 119-S that exchange external signals will be referred to as external signal redistribution pads 118BP-S2 and external signal sub-interconnects 119-S2, respectively.

[0048] The following will refer to Figures 4 to 7 A semiconductor package having the above-described sub-semiconductor package 110 is described.

[0049] Figure 4 is a plan view illustrating a semiconductor package according to an embodiment of the present disclosure, viewed from the top. Figure 5 It is an example Figure 4 A plan view of the upper surface of a substrate of a semiconductor package. Figure 6 and Figure 7 It is an example Figure 4 Specifically, Figure 6 It is an example Figure 4 A cross-sectional view of internal signal exchange between the first and second main chip stacks and the sub-semiconductor packages in FIG. Figure 7 It is an example Figure 4 A cross-sectional view of external signal exchange between the sub-semiconductor package and the substrate, power transmission between the first and second main chip stacks and the substrate, and power transmission between the sub-semiconductor package and the substrate.

[0050] Reference Figures 4 to 7 , a semiconductor package according to an embodiment of the present disclosure may include a substrate 100 , a sub-semiconductor package 110 disposed over the substrate 100 , and first and second main chip stacks 120 and 130 disposed over the sub-semiconductor package 110 .

[0051] The substrate 100 may be a substrate for a semiconductor package, which has a circuit and / or wiring structure to transmit an electrical signal. For example, the substrate 100 may include a printed circuit board (PCB).

[0052] The substrate 100 may have an upper surface 100A, a lower surface 100B on an opposite side of the upper surface 100A, and a side surface connecting the upper surface 100A and the lower surface 100B.

[0053] The sub-semiconductor package 110, the first main chip stack 120, and the second main chip stack 130 may be disposed above the upper surface 100A of the substrate 100. Specifically, the sub-semiconductor package 110 may be mounted above the substrate 100 such that the active surface 114A of the sub-semiconductor chip 114 and one surface 116A of the sub-mold layer 116 face the upper surface 100A of the substrate 100. That is, the sub-semiconductor package 110 may be mounted above the substrate 100 in a face-down manner. Figure 4 In the plan view, detailed components included in the sub-semiconductor package 110 may not be visible except for the other surface 116B of the sub-mold layer 116. However, for convenience of description, some components of the sub-semiconductor package 110 that are not covered by the first main chip stack 120 and the second main chip stack 130 are shown in FIG. Figure 4 In addition, for the convenience of description, the detailed components of the sub-semiconductor package 110 are shown in FIG. Figure 5 For reference, since the sub-semiconductor package 110 is mounted on the substrate 100 in a face-down manner, Figure 4 and Figure 5 The detailed components of the sub-semiconductor package 110 are shown in FIG. Figure 1 Compared to upside down. The external connection terminals 140 that connect the semiconductor package of this embodiment to the external components can be arranged above the lower surface 100B of the substrate 100. For reference, the upper surface and the lower surface to be described below are expressions indicating the relative positions of various surfaces of the components, rather than expressions indicating absolute positions. For example, unlike the illustration, when the semiconductor package is upside down, the surface on which the sub-semiconductor package 110 and the first main chip stack 120 and the second main chip stack 130 are arranged can be the lower surface of the substrate 100, and the surface on which the external connection terminals 140 are arranged can be the upper surface of the substrate 100.

[0054] The sub-substrate pads 102S, the first main substrate pads 102M1, and the second main substrate pads 102M2 may be disposed on the upper surface 100A of the substrate 100. The sub-substrate pads 102S may be electrically connected to the sub-semiconductor package 110, the first main substrate pads 102M1 may be electrically connected to the first main chip stack 120, and the second main substrate pads 102M2 may be electrically connected to the second main chip stack 130. The lower surface substrate pads 104 for connection to the external connection terminals 140 may be disposed on the lower surface 100B of the substrate 100. For reference, a substrate pad may refer to a conductive element or terminal exposed on the surface of the substrate 100 to electrically connect the substrate 100 to other components. These substrate pads may be connected to circuits and / or wiring structures inside the substrate 100.

[0055] The submount pad 102S may overlap and connect with the sub-interconnector 119. When the sub-interconnector 119 includes a metal bump, the submount pad 102S may include a bump bonding finger.

[0056] Sub-substrate pads 102S may include power sub-substrate pads 102S-P connected to power sub-interconnect 119-P and signal sub-substrate pads 102S-S connected to signal sub-interconnect 119-S. Furthermore, signal sub-substrate pads 102S-S may include internal signal sub-substrate pads 102S-S1 connected to internal signal sub-interconnect 119-S1 and external signal sub-substrate pads 102S-S2 connected to external signal sub-interconnect 119-S2. Multiple power sub-substrate pads 102S-P may overlap and connect to power sub-interconnects 119-P, respectively. Thus, power sub-substrate pads 102S-P may be arranged to surround sub-semiconductor chip 114 on upper surface 100A of substrate 100. A plurality of signal sub-substrate pads 102S-S may overlap and connect with the signal sub-interconnectors 119 -S, respectively, and the signal sub-substrate pads 102S-S may be arranged to overlap each of both side edges of the sub-mold layer 116 in the first direction on the upper surface 100A of the substrate 100 .

[0057] The first main substrate pad 102M1 can be connected to the first main interconnect 127 (described later), and the second main substrate pad 102M2 can be connected to the second main interconnect 137 (described later). When the first main interconnect 127 and the second main interconnect 137 are bonding wires, the first main substrate pad 102M1 and the second main substrate pad 102M2 may include wire bonding fingers. A plurality of first main substrate pads 102M1 may be arranged at the first side edge of the substrate 100 in the first direction along the second direction. A plurality of second main substrate pads 102M2 may be arranged at the second side edge of the substrate 100 in the first direction along the second direction. The first main substrate pad 102M1 and the second main substrate pad 102M2 may be exposed without being covered by the sub-semiconductor package 110. To this end, the sub-semiconductor package 110 may have a width smaller than the width of the upper surface 100A of the substrate 100 in the first direction, and may be relatively arranged in the center of the substrate 100. In addition, the first and second main substrate pads 102M1 and 102M2 may be exposed without being covered by the first and second main chip stacks 120 and 130 .

[0058] The first main substrate pads 102M1 may include: first signal main substrate pads 102M1-S, which exchange internal signals between the sub-semiconductor package 110 and the first main chip stack 120; and first power main substrate pads 102M1-P, which are used to supply power to the first main chip stack 120. In this case, the first signal main substrate pads 102M1-S may be electrically connected to the internal signal sub-substrate pads 102S-S1 that overlap the first side edge of the sub-mold layer 116 via connection lines CL formed in the substrate 100. The connection lines CL may connect the first signal main substrate pads 102M1-S, to which the first main chip stack 120 is electrically connected, and the internal signal sub-substrate pads 102S-S1, to which the sub-semiconductor package 110 is electrically connected. Thus, electrical connection between the first main chip stack 120 and the sub-semiconductor package 110 can be established. In the cross-sectional view, the connection line CL may be located at the same level as the first signal main substrate pad 102M1-S and the internal signal sub-substrate pad 102S-S1. In addition, the connection line CL may have a linear shape so that the distance between the first signal main substrate pad 102M1-S and the internal signal sub-substrate pad 102S-S1 in the plan view is the shortest. This may be to form an internal signal transmission path with the shortest distance between the first signal main substrate pad 102M1-S and the internal signal sub-substrate pad 102S-S1. However, the present disclosure is not limited to this, and as long as the first signal main substrate pad 102M1-S and the internal signal sub-substrate pad 102S-S1 are connected to each other in the substrate 100, the position and shape of the connection line CL may be modified in various ways.

[0059] The second main substrate pads 102M2 may include: second signal main substrate pads 102M2-S, which exchange internal signals between the sub-semiconductor package 110 and the second main chip stack 130; and second power main substrate pads 102M2-P, which supply power to the second main chip stack 130. In this case, the second signal main substrate pads 102M2-S may be electrically connected to the internal signal sub-substrate pads 102S-S1 overlapping the second side edge of the sub-mold layer 116 via connection lines CL formed in the substrate 100. The connection lines CL may connect the second signal main substrate pads 102M2-S, to which the second main chip stack 130 is electrically connected, to the internal signal sub-substrate pads 102S-S1, to which the sub-semiconductor package 110 is electrically connected. Thus, electrical connection between the second main chip stack 130 and the sub-semiconductor package 110 may be established. In the cross-sectional view, the connection line CL may be located at the same level as the second signal main substrate pad 102M2-S and the internal signal sub-substrate pad 102S-S1. In addition, the connection line CL may have a linear shape so that the distance between the second signal main substrate pad 102M2-S and the internal signal sub-substrate pad 102S-S1 in the plan view is the shortest. This may be to form an internal signal transmission path with the shortest distance between the second signal main substrate pad 102M2-S and the internal signal sub-substrate pad 102S-S1. However, the present disclosure is not limited to this, and as long as the second signal main substrate pad 102M2-S and the internal signal sub-substrate pad 102S-S1 are connected to each other in the substrate 100, the position and shape of the connection line CL may be modified in various ways.

[0060] The lower surface substrate pad 104 may be connected to the external connection terminal 140. When the external connection terminal 140 includes a solder ball, the lower surface substrate pad 104 may include a ball pad.

[0061] Since the detailed configuration of the sub-semiconductor package 110 has been described, its detailed description will be omitted. The sub-semiconductor package 110 can be electrically connected to the substrate 100 through the sub-interconnector 119. Specifically, referring to Figure 5 and Figure 7, the power sub-interconnector 119-P can be connected to the power sub-substrate pad 102S-P. Therefore, an electrical path (i.e., a power supply path) can be formed passing through the sub-semiconductor chip 114, the power redistribution conductive layer 118B-P, the power sub-interconnector 119-P and the power sub-substrate pad 102S-P. In this case, since the length of the power redistribution conductive layer 118B-P connected to the power sub-interconnector 119-P is relatively short compared to the length of the signal redistribution conductive layer 118B-S, the length of the power supply path can be reduced. Although not shown, the power sub-substrate pad 102S-P can be electrically connected to the external connection terminal 140 through the circuit and / or wiring structure inside the substrate 100, thereby being connected to an external component (not shown) and being powered from the external component. In addition, referring to Figure 5 and Figure 7 , the external signal sub-interconnector 119-S2 can be connected to the external signal sub-substrate pad 102S-S2. Therefore, an electrical path (i.e., an external signal transmission path) can be formed through the sub-semiconductor chip 114, the signal redistribution conductive layer 118B-S, the external signal sub-interconnector 119-S2 and the external signal sub-substrate pad 102S-S2. Although not shown, the external signal sub-substrate pad 102S-S2 can be electrically connected to the external connection terminal 140 through the circuit and / or wiring structure inside the substrate 100, thereby connecting to an external component (not shown) and exchanging signals with the external component. In addition, referring to Figure 5 and Figure 6 , the internal signal sub-interconnector 119-S1 can be connected to the internal signal sub-substrate pad 102S-S1. As will be described later, the internal signal sub-substrate pad 102S-S1 can be connected to the first signal main substrate pad 102M1-S and the second signal main substrate pad 102M2-S through the connection line CL. Therefore, electrical connection between each of the first main chip stack 120 and the second main chip stack 130 and the sub-semiconductor chip 114 can be made. This will be described together with the description of the first main chip stack 120 and the second main chip stack 130. The power supply path through the power redistribution conductive layer 118B-P of the substrate 100, the power sub-interconnector 119-P and the power sub-substrate pad 102S-P can be shorter than the signal transmission path through the signal redistribution conductive layer 118B-S, the signal sub-interconnector 119-S and the signal sub-substrate pad 102S-S of the substrate 100.

[0062] The first main chip stack 120 may include a plurality of first main semiconductor chips 124. The first main semiconductor chips 124 may be formed above the sub-semiconductor package 110 and may be stacked in a vertical direction relative to the upper surface 100A of the substrate 100. Although the present embodiment illustrates a case where the first main chip stack 120 includes four first main semiconductor chips 124, the present disclosure is not limited thereto, and the number of first main semiconductor chips 124 included in the first main chip stack 120 may be modified in various ways to one or more first main semiconductor chips 124.

[0063] The first main semiconductor chip 124 may be arranged in a direction toward the second side in the first direction (eg, in a direction toward Figure 4 The lower side and Figure 6 and Figure 7 The first main semiconductor chips 124 are stacked with a predetermined offset (in the direction of the right side in the middle). Therefore, a first main chip stack 120 having a stepped shape when viewed as a whole can be formed. The offset stacking direction of the first main semiconductor chips 124 will be referred to as a first offset direction. According to this offset stacking, the first side edge of the upper surface of each of the remaining first main semiconductor chips 124 except the uppermost first main semiconductor chip 124 among the first main semiconductor chips 124 can be exposed without being covered by the first main semiconductor chip 124 directly thereon. For example, Figure 4 an upper side edge of the upper surface of each of the remaining first master semiconductor chips 124 in the Figure 6 and Figure 7 The left side edge of the upper surface of each of the remaining first main semiconductor chips 124 in the stack may be exposed. The first side edge of the upper surface of the uppermost first main semiconductor chip 124 may be exposed without being covered by the lowermost second main semiconductor chip 134 of the second main chip stack 130 (to be described later). The first chip pads 125 may be provided on these exposed portions of the first main semiconductor chips 124. A plurality of first chip pads 125 may be arranged in a row along the second direction at the first side edge of the upper surface of each first main semiconductor chip 124. However, the present disclosure is not limited thereto, and the number and arrangement of the first chip pads 125 at the first side edge of the upper surface of each first main semiconductor chip 124 may be modified in various ways. For reference, since Figure 1 The portion of the first master chip stack 120 hidden by the second master chip stack 130 is not shown in the plan view, so the remaining portion of the first master chip stack 120 (eg, the first side edge of the lowermost first master semiconductor chip 124) is shown.

[0064] Each first main semiconductor chip 124 may be attached to the sub-semiconductor package 110 or the first main semiconductor chip 124 directly thereunder through a first adhesive layer 122. The first adhesive layer 122 may be formed on a lower surface of each first main semiconductor chip 124 to have a shape overlapping the lower surface.

[0065] The first main chip stack 120 or the first main semiconductor chip 124 may have a smaller planar area than the sub-semiconductor package 110 and may have a larger planar area than the sub-semiconductor chip 114. The first main chip stack 120 may be provided to expose at least the first main substrate pads 102M1 and the second main substrate pads 102M2 provided at both side edges of the substrate 100 in the first direction.

[0066] The first main chip stack 120 may be connected to the substrate 100 and the sub-semiconductor package 110 through a first main interconnector 127. In the present embodiment, the first main chip stack 120 may be electrically connected to the substrate 100 to receive power required for the operation of the first main chip stack 120 from the substrate 100. In addition, the first main chip stack 120 may be electrically connected to the sub-semiconductor package 110 to exchange internal signals with the sub-semiconductor chip 114. Among the first main interconnectors 127, the interconnector connecting the first main chip stack 120 and the substrate 100 will be referred to as a first power main interconnector 127P. In addition, the interconnector connecting the first main chip stack 120 and the sub-semiconductor package 110 among the first main interconnectors 127 will be referred to as a first signal main interconnector 127S.

[0067] Specifically, refer to Figure 4 and Figure 6 , the first signal main interconnect 127S can connect adjacent first chip pads 125 to each other in the vertical direction, and can connect the first chip pad 125 of the lowermost first main semiconductor chip 124 to the first signal main substrate pad 102M1-2. Therefore, the first main semiconductor chips 124 can be electrically connected to each other, and the first main chip stack 120 can be electrically connected to the sub-semiconductor package 110 through the substrate 100. More specifically, an electrical path (i.e., a signal transmission path) can be formed that passes through the first main chip stack 120, the first signal main interconnect 127S, the first signal main substrate pad 102M1-S, the connection line CL, the internal signal sub-substrate pad 102S-S1, the internal signal sub-interconnect 119-S1, the signal redistribution conductive layer 118B-S, and the sub-semiconductor chip 114.

[0068] In addition, specifically, refer to Figure 4 and Figure 7, the first power main interconnector 127P can connect adjacent first chip pads 125 to each other in a vertical direction, and can connect the first chip pad 125 of the lowermost first main semiconductor chip 124 to the first power main substrate pad 102M1-P of the substrate 100. Therefore, the first main semiconductor chips 124 can be electrically connected to each other, and the first main chip stack 120 can be electrically connected to the substrate 100. More specifically, an electrical path (i.e., a power supply path) can be formed through the first main chip stack 120, the first power main interconnector 127P, and the first power main substrate pad 102M1-P.

[0069] The first main interconnector 127 may be a bonding wire. However, the present embodiment is not limited thereto, and various types of electrical interconnectors may be used as the first main interconnector 127 .

[0070] The second main chip stack 130 may include a plurality of second main semiconductor chips 134. The second main semiconductor chips 134 may be formed above the first main chip stack 120 and may be stacked in a vertical direction. Although the present embodiment illustrates a case where the second main chip stack 130 includes four second main semiconductor chips 134, the present disclosure is not limited thereto, and the number of second main semiconductor chips 134 included in the second main chip stack 130 may be modified in various ways to one or more second main semiconductor chips 134. In addition, although in the present embodiment, the number of second main semiconductor chips 134 included in the second main chip stack 130 is the same as the number of first main semiconductor chips 124 included in the first main chip stack 120, it should be noted that these numbers may be different from each other.

[0071] The second master semiconductor chip 134 may be arranged in a direction toward the first side in the first direction (eg, in a direction toward the Figure 4 The upper side and Figure 6 and Figure 7 The second main semiconductor chips 134 are stacked with a predetermined offset (in the direction of the left side in the figure). Therefore, a second main chip stack 130 having a stepped shape when viewed as a whole can be formed. The offset stacking direction of the second main semiconductor chips 134 will be referred to as a second offset direction. The second offset direction may be opposite to the first offset direction. According to this offset stacking, the second side edge of the upper surface of each of the remaining second main semiconductor chips 134 except the uppermost second main semiconductor chip 134 among the second main semiconductor chips 134 may be exposed without being covered by the second main semiconductor chip 134 directly thereon. For example, Figure 4 The lower side edge of the upper surface of each of the remaining second main semiconductor chips 134 in Figure 6 and Figure 7The right side edge of the upper surface of each of the remaining second main semiconductor chips 134 in the uppermost second main semiconductor chip 134 may be exposed. The uppermost second main semiconductor chip 134 may be in a state where its entire upper surface is exposed. The second chip pads 135 may be provided on the exposed portions of the remaining second main semiconductor chips 134 other than the uppermost second main semiconductor chip 134, and the second chip pads 135 of the uppermost second main semiconductor chip 134 may also be provided at the same position as the second chip pads 135 of the remaining second main semiconductor chips 134. A plurality of second chip pads 135 may be arranged in a row along the second direction at the second side edge of the upper surface of each second main semiconductor chip 134. However, the present disclosure is not limited thereto, and the number and arrangement of the second chip pads 135 at the second side edge of the upper surface of each second main semiconductor chip 134 may be modified in various ways.

[0072] In the case where the second main semiconductor chips 134 are the same semiconductor chips as the first main semiconductor chips 124 , each second main semiconductor chip 134 may correspond to a state in which each first main semiconductor chip 124 is rotated 180 degrees around an axis extending in a vertical direction.

[0073] Each second main semiconductor chip 134 may be attached to the second main semiconductor chip 134 located directly therebelow or the uppermost first main semiconductor chip 124 of the first main chip stack 120 through the second adhesive layer 132. The second adhesive layer 132 may be formed on the lower surface of each second main semiconductor chip 134 to have a shape overlapping the lower surface.

[0074] The second main chip stack 130 or the second main semiconductor chip 134 may have a smaller planar area than the sub-semiconductor package 110 and may have a larger planar area than the sub-semiconductor chip 114. The second main chip stack 130 may be provided to expose at least the first main substrate pads 102M1 and the second main substrate pads 102M2 provided at both side edges of the substrate 100 in the first direction.

[0075] The second main chip stack 130 may be connected to the substrate 100 and the sub-semiconductor package 110 via a second main interconnector 137. In the present embodiment, the second main chip stack 130 may be electrically connected to the substrate 100 to receive power required for the operation of the second main chip stack 130 from the substrate 100. In addition, the second main chip stack 130 may be electrically connected to the sub-semiconductor package 110 to exchange internal signals with the sub-semiconductor chip 114. Among the second main interconnectors 137, the interconnector connecting the second main chip stack 130 and the substrate 100 will be referred to as a second power main interconnector 137P. In addition, the interconnector connecting the second main chip stack 130 and the sub-semiconductor package 110 among the second main interconnectors 137 will be referred to as a second signal main interconnector 137S.

[0076] Specifically, refer to Figure 4 and Figure 6 , the second signal main interconnect 137S can connect adjacent second chip pads 135 to each other in the vertical direction, and can connect the second chip pad 135 of the lowermost second main semiconductor chip 134 to the second signal main substrate pad 102M2-2. Therefore, the second main semiconductor chips 134 can be electrically connected to each other, and the second main chip stack 130 can be electrically connected to the sub-semiconductor package 110 through the substrate 100. More specifically, an electrical path (i.e., a signal transmission path) can be formed that passes through the second main chip stack 130, the second signal main interconnect 137S, the second signal main substrate pad 102M2-S, the connection line CL, the internal signal sub-substrate pad 102S-S1, the internal signal sub-interconnect 119-S1, the signal redistribution conductive layer 118B-S, and the sub-semiconductor chip 114.

[0077] In addition, specifically, refer to Figure 4 and Figure 7 The second power main interconnect 137P can connect adjacent second chip pads 135 to each other in a vertical direction, and can connect the second chip pad 135 of the lowermost second main semiconductor chip 134 to the second power main substrate pad 102M2-P of the substrate 100. Therefore, the second main semiconductor chips 134 can be electrically connected to each other, and the second main chip stack 130 can be electrically connected to the substrate 100. More specifically, an electrical path (i.e., a power supply path) can be formed through the second main chip stack 130, the second power main interconnect 137P, and the second power main substrate pad 102M2-P.

[0078] The second main interconnector 137 may be a bonding wire. However, the present embodiment is not limited thereto, and various types of electrical interconnectors may be used as the second main interconnector 137 .

[0079] For reference, in Figure 4 and Figure 5 In the plan view of FIG, for convenience of description, the first main interconnector 127 and the second main interconnector 137 are shown by different dotted lines. However, it should be noted that, of course, these dotted lines do not reflect the actual shapes of the first main interconnector 127 and the second main interconnector 137.

[0080] The sub-semiconductor package 110, the first main chip stack 120, and the second main chip stack 130 may be covered by a mold layer 150 formed over the substrate 100. The mold layer 150 may include various molding materials such as EMC.

[0081] The external connection terminals 140 may include solder balls. However, the present disclosure is not limited thereto, and various conductive terminals such as bumps may be used as the external connection terminals 140 .

[0082] In the semiconductor package of the present embodiment, the first main chip stack 120 can be identified as a single semiconductor chip group while being connected to the substrate 100 and the sub-semiconductor package 110 through the first main interconnector 127. In addition, the second main chip stack 130 can be identified as another single semiconductor chip group different from the first main chip stack 120 while being connected to the substrate 100 and the sub-semiconductor package 110 through the second main interconnector 137. The sub-semiconductor chip 114 can be connected to the substrate 100 through the redistribution structure 118 and the sub-interconnector 119.

[0083] According to the above-described semiconductor package, the following advantages can be obtained.

[0084] First, since the sub-chip pads 115 are arranged along the entire edge of the sub-semiconductor chip 114, a relatively large number of sub-chip pads 115 can be arranged compared to the size of the sub-semiconductor chip 114. In addition, by redistributing the sub-chip pads 115 using fan-out technology, the arrangement of the sub-chip pads 115 can be facilitated.

[0085] In addition, since some sub-chip pads 115 are redistributed to the internal signal redistribution pad 118BP-S1 using fan-out technology, and the internal signal redistribution pad 118BP-S1 is connected to the first signal main substrate pad 102M1-S and the second signal main substrate pad 102M2-S through the internal signal sub-interconnector 119-S1, the internal signal sub-substrate pad 102S-S1 and the connecting line CL inside the substrate 100, the signal transmission distance between the sub-semiconductor chip 114 and the first main chip stack 120 and the second main chip stack 130 can be reduced.

[0086] Furthermore, since the sub-semiconductor package 110, which is larger than the first and second main chip stacks 120 and 130, is disposed below the first and second main chip stacks 120 and 130 using fan-out technology, the first and second main chip stacks 120 and 130 can be stably formed. In a structure where the first and second main chip stacks 120 and 130 are formed above the sub-semiconductor chip 114, if the sub-semiconductor chip 114 is smaller than the first and second main semiconductor chips 124 and 134, this may cause the first and second main chip stacks 120 and 130 to tilt. However, by significantly increasing the area of ​​the sub-semiconductor chip 114 using fan-out technology, this problem is eliminated.

[0087] Furthermore, by adjusting the shape and / or arrangement of the signal redistribution conductive layers 118B-S so that they have similar lengths, the operational characteristics of the semiconductor package can be maintained. For example, when there is a first channel connecting the first main chip stack 120 to the sub-semiconductor package 110 and a second channel connecting the second main chip stack 130 to the sub-semiconductor package 110, the path of the first channel and the path of the second channel can have similar lengths. This minimizes variations in signal transmission rates between channels.

[0088] Furthermore, since the length of the power redistribution conductive layer 118B-P is shorter than the length of the signal redistribution conductive layer 118B-S, and the power redistribution conductive layer 118B-P and the substrate 100 are connected via the power sub-interconnector 119, power can be easily supplied to the sub-semiconductor chip 114. In this case, the length of the power supply path from the substrate 100 to the sub-semiconductor chip 114 can be shortened, and thus, the impedance of the power supply path can be reduced. This will be referred to Figure 8A and Figure 8B Further description.

[0089] Figure 8A is a diagram illustrating an example of the effect of the semiconductor package according to the embodiment of the present disclosure, Figure 8B : is a diagram illustrating the effect of the semiconductor package according to the comparative example. Unlike this embodiment, Figure 8B It is illustrated that the power redistribution conductive layer extends to the edge of the sub-mold layer similar to the signal redistribution conductive layer, and the end of the power redistribution conductive layer is connected to the substrate through a bonding wire.

[0090] Reference Figure 8A , a relatively short current path can be formed (see the dotted arrow), which passes through the power redistribution conductive layer 118B-P with a shorter length, the power sub-interconnector 119-P arranged under and connected to the power redistribution conductive layer 118B-P, the substrate 100, and the external connection terminal 140 for power supply.

[0091] On the other hand, refer to Figure 8B , a relatively long current path can be formed (see the dotted arrow), which passes through the long power redistribution conductive layer 118B-P', the power sub-interconnector 119-P' arranged under and connected to the power redistribution conductive layer 118B-P', the substrate 100' and the external connection terminal 140' for power supply.

[0092] In other words, in Figure 8BIn the comparative example, regardless of the position of the external connection terminal 140' for supplying power to the substrate 100', a power supply path extending to the edge of the sub-molding layer through the long power redistribution conductive layer 118B-P' can be formed. Figure 8A Compared to the implementation scheme of FIG. 5 , relatively long power supply paths may be unavoidable.

[0093] As a result, according to this embodiment, Figure 8A As shown, a shorter current path can be formed, and thus the impedance of the power supply path can be reduced. Therefore, power supply can be facilitated.

[0094] Furthermore, in the above embodiment, all the redistribution conductive layers 118B extend outward from the edge of the sub-semiconductor chip 114. However, since the power redistribution conductive layer 118B-P among the redistribution conductive layers 118B has a relatively short length, it may extend inward from the edge of the sub-semiconductor chip 114. This will be described below with reference to Figure 9 Described exemplarily.

[0095] Figure 9 is a plan view illustrating a sub-semiconductor package according to another embodiment of the present disclosure. Figure 9 For parts substantially the same as those in the above-described embodiment, detailed description thereof will be omitted.

[0096] Reference Figure 9 The sub-semiconductor package 210 of this embodiment may include a sub-semiconductor chip 214 , a sub-mold layer 216 , a redistribution conductive layer 218B, and a sub-interconnector 219 .

[0097] A plurality of sub-chip pads 215 may be disposed on the active surface 214A of the sub-semiconductor chip 214 .

[0098] The sub-mold layer 216 may surround side surfaces of the sub-semiconductor chip 214 and may have one surface 216A substantially at the same level as the active surface 214A of the sub-semiconductor chip 214. Thus, the active surface 214A and the sub-chip pad 215 may be exposed.

[0099] The redistribution conductive layer 218B may include a signal redistribution conductive layer 218B-S and a power redistribution conductive layer 218B-P.

[0100] The signal redistribution conductive layers 218B-S may extend outward from the edge of the sub-semiconductor chip 214 while being connected to the sub-chip pads 215. The plurality of signal redistribution conductive layers 218B-S may extend to both side edges of the sub-mold layer 216 in the first direction, such that the plurality of signal redistribution pads 218BP-S may extend along the second direction at both side edges of the sub-mold layer 216 in the first direction. The signal redistribution pads 218BP-S may include inner signal redistribution pads 218BP-S1 and outer signal redistribution pads 218BP-S2.

[0101] On the other hand, the power redistribution conductive layer 218B-P can extend inward from the edge of the sub-semiconductor chip 214 while being connected to the sub-chip pad 215. Because the power redistribution conductive layer 218B-P has a relatively short length, multiple power redistribution conductive layers 218B-P can overlap with the sub-semiconductor chip 214 and can be alternately arranged so as not to short-circuit each other. Although not shown, due to the first redistribution insulating layer being interposed between the power redistribution conductive layer 218B-P and the sub-semiconductor chip 214, the power redistribution conductive layer 218B-P and the sub-semiconductor chip 214 can be separated and insulated from each other, except for being connected via the sub-chip pad 215.

[0102] According to the arrangement of the power redistribution conductive layer 218B-P as described above, the power redistribution pads 218BP-P may be arranged to be spaced apart from each other in a region overlapping the sub-semiconductor chip 214 .

[0103] Signal sub-interconnector 219-S may be connected to signal redistribution pad 218BP-S. Specifically, internal signal sub-interconnector 219-S1 may be connected to internal signal redistribution pad 218BP-S1, and external signal sub-interconnector 219-S2 may be connected to external signal redistribution pad 218BP-S2. Power sub-interconnector 219-P may be connected to power redistribution pad 218BP-P. That is, power sub-interconnector 219-P may also overlap with sub-semiconductor chip 214.

[0104] In the present embodiment, all the effects of the above-described embodiments can be achieved, and further, an electrical short circuit between the signal redistribution conductive layer 218B-S and the power redistribution conductive layer 218B-P can be prevented.

[0105] Furthermore, in the above embodiment, the case where the power redistribution conductive layers 118B-P and 218B-P are shorter than the signal redistribution conductive layers 118B-S and 218B-S is described. However, the present disclosure is not limited thereto, and the length of the power redistribution conductive layers may be the same as or similar to the length of the signal redistribution conductive layers. In this case, by using power sub-interconnectors connected to the points of the power redistribution conductive layers, the power supply path of the sub-semiconductor chips can be shortened. This will be referred to Figures 10 to 14 Described exemplarily.

[0106] Figure 10 is a plan view illustrating a sub-semiconductor package according to another embodiment of the present disclosure, viewed from the top. Figure 11 It is along Figure 10 A cross-sectional view taken along line A3-A3'. Figure 10 and Figure 11 A state is shown in which the active surface of the sub-semiconductor chip faces downward. Figure 12 is a plan view illustrating a semiconductor package according to another embodiment of the present disclosure, viewed from the top. Figure 13 It is an example Figure 12 A plan view of the upper surface of a substrate of a semiconductor package. Figure 14 It is an example Figure 12 Specifically, Figure 14 The sub-semiconductor package is shown along Figure 13 A cross section taken along line A4-A4', Figure 14 The remaining part is used to describe the power transmission between the first and second main chip laminates and the substrate. Detailed description of parts that are substantially the same as those in the above embodiment will be omitted.

[0107] First, refer to Figure 10 and Figure 11 The sub-semiconductor package 310 of this embodiment may include a sub-semiconductor chip 314 , a sub-mold layer 316 , a redistribution structure 318 , and a sub-interconnector 319 .

[0108] The semiconductor sub-chip 314 may have an active surface 314A on which a plurality of chiplet pads 315 are disposed, an inactive surface 314B located on opposite sides of the active surface 314A, and a side surface 314C connecting the active surface 314A and the inactive surface 314B. The chiplet pads 315 may be arranged along the entire edge of the semiconductor sub-chip 314.

[0109] The sub-mold layer 316 may have one surface 316A that is substantially at the same level as the active surface 314A of the sub-semiconductor chip 314 while surrounding the side surface 314C of the sub-semiconductor chip 314. Thus, the sub-mold layer 316 may expose the active surface 314A of the sub-semiconductor chip 314 and the sub-chip pad 315. Another surface 316B of the sub-mold layer 316 may be opposite to the one surface 316A.

[0110] A redistribution structure 318 may be formed over an active surface 314A of the semiconductor sub-chip 314 and one surface 316A of the sub-mold layer 316. The redistribution structure 318 may include a first redistribution insulating layer 318A, a redistribution conductive layer 318B, and a second redistribution insulating layer 318C. The redistribution conductive layer 318B may extend onto one surface 316A of the sub-mold layer 316 while being electrically connected to the chiplet pad 315.

[0111] The redistribution conductive layer 318B may include a signal redistribution conductive layer 318B-S and a power redistribution conductive layer 318B-P. In this embodiment, regardless of the signal redistribution conductive layer 318B-S or the power redistribution conductive layer 318B-P, all redistribution conductive layers 318B may extend toward both side edges of the sub-mold layer 316 in the first direction. By way of example, the signal redistribution conductive layer 318B-S and the power redistribution conductive layer 318B-P, respectively connected to the sub-chip pads 315 disposed at the first and third side edges of the sub-semiconductor chip 314 in the first and second directions, may extend toward the first side edge of the sub-mold layer 316 in the first direction. Furthermore, the signal redistribution conductive layer 318B-S and the power redistribution conductive layer 318B-P, respectively connected to the sub-chip pads 315 disposed at the second and fourth side edges of the sub-semiconductor chip 314 in the first and second directions, may extend toward the second side edge of the sub-mold layer 316 in the first direction. As a result, the redistribution conductive layer 318B may have a spiral shape centered on the sub-semiconductor chip 314. Through this connection method, variations in the length of the redistribution conductive layer 318B may be reduced.

[0112] Depending on the arrangement of the signal redistribution conductive layer 318B-S and the power redistribution conductive layer 318B-P, as described above, the ends of the signal redistribution conductive layer 318B-S and the power redistribution conductive layer 318B-P may be arranged along the second direction at each of the two side edges of the sub-mold layer 316 in the first direction. The ends of the signal redistribution conductive layer 318B-S may be exposed through openings in the second redistribution insulating layer 318C to form signal redistribution pads 318BP-S. The signal redistribution pads 318BP-S may include inner signal redistribution pads 318BP-S1 and outer signal redistribution pads 318BP-S2. Alternatively, the ends of the power redistribution conductive layer 318B-P may be exposed through the openings in the second redistribution insulating layer 318C, and a predetermined portion of the power redistribution conductive layer 319B-P located between the sub-semiconductor chip 314 and the ends may be exposed through the openings in the second redistribution insulating layer 318C. The end portion of the power redistribution conductive layer 318B-P exposed through the second redistribution insulating layer 318C will be referred to as a second power redistribution pad 318BP-P2, and the predetermined portion of the power redistribution conductive layer 318B-P exposed through the second redistribution insulating layer 318C will be referred to as a first power redistribution pad 318BP-P1. That is, the first power redistribution pad 318BP-P1 may be disposed closer to the sub-semiconductor chip 314 than the second power redistribution pad 318BP-P2. The first power redistribution pad 318BP-P1 and the second power redistribution pad 318BP-P2 will be referred to as power redistribution pads 318BP-P.

[0113] The sub-interconnect 319 may include a signal sub-interconnect 319-S that overlaps and connects to the signal redistribution pad 318BP-S, and a power sub-interconnect 319-P that overlaps and connects to the power redistribution pad 318BP-P. The signal sub-interconnect 319-S may include an internal signal sub-interconnect 319-S1 that overlaps and connects to the internal signal redistribution pad 318BP-S1, and an external signal sub-interconnect 319-S2 that overlaps and connects to the external signal redistribution pad 318BP-S2. The power sub-interconnect 319-P may include a first power sub-interconnect 319-P1 that overlaps and connects to the first power redistribution pad 318BP-P1, and a second power sub-interconnect 319-P2 that overlaps and connects to the second power redistribution pad 318BP-P2.

[0114] Next, we will refer to Figures 12 to 14 Description Figure 10 and Figure 11 The semiconductor package of the sub-semiconductor package 310 is shown.

[0115] Reference Figures 12 to 14A semiconductor package according to another embodiment of the present disclosure may include a substrate 300 , a sub-semiconductor package 310 disposed over the substrate 300 , and a first main chip stack 320 and a second main chip stack 330 disposed over the sub-semiconductor package 310 .

[0116] The substrate 300 may have an upper surface 300A, a lower surface 300B on an opposite side of the upper surface 300A, and a side surface connecting the upper surface 300A and the lower surface 300B.

[0117] The sub-semiconductor package 310, the first main chip stack 320, and the second main chip stack 330 may be disposed above the upper surface 300A of the substrate 300. Specifically, the sub-semiconductor package 310 may be mounted above the substrate 100 such that the active surface 314A of the sub-semiconductor chip 314 and one surface 316A of the sub-mold layer 316 face the upper surface 300A of the substrate 300. That is, the sub-semiconductor package 310 may be mounted above the substrate 300 in a face-down manner. For ease of description, some components of the sub-semiconductor package 310 that are not covered by the first main chip stack 320 and the second main chip stack 330 are shown in FIG. Figure 12 In addition, for the convenience of description, the detailed components of the sub-semiconductor package 310 are shown in FIG. Figure 13 For reference, since the sub-semiconductor package 310 is mounted on the substrate 300 in a face-down manner, Figure 12 and Figure 13 The detailed components of the sub-semiconductor package 310 are shown in FIG. Figure 10 External connection terminals 340 that connect the semiconductor package of the present embodiment to external components may be provided above the lower surface 300B of the substrate 300 .

[0118] Sub-substrate pads 302S, first main substrate pads 302M1, and second main substrate pads 302M2 may be provided on the upper surface 300A of the substrate 300. Sub-substrate pads 302S may be electrically connected to the sub-semiconductor package 310, first main substrate pads 302M1 may be electrically connected to the first main chip stack 320, and second main substrate pads 302M2 may be electrically connected to the second main chip stack 330. Lower surface substrate pads 304 for connection to external connection terminals 340 may be provided on the lower surface 300B of the substrate 300.

[0119] Sub-substrate pads 302S may overlap and connect to sub-interconnect 319. Sub-substrate pads 302S may include power sub-substrate pads 302S-P connected to power sub-interconnect 319-P and signal sub-substrate pads 302S-S connected to signal sub-interconnect 319-S. Power sub-substrate pads 302S-P may include first power sub-substrate pads 302S-P1 connected to first power sub-interconnect 319-P1 and second power sub-substrate pads 302S-P2 connected to second power sub-interconnect 319-P2. Signal sub-substrate pads 302S-S may include internal signal sub-substrate pads 302S-S1 connected to internal signal sub-interconnect 319-S1 and external signal sub-substrate pads 302S-S2 connected to external signal sub-interconnect 319-S2. A plurality of first power sub-substrate pads 302S-P1 may be arranged to surround the sub-semiconductor chip 314 on the upper surface 300A of the substrate 300. A plurality of signal sub-substrate pads 302S-S and a plurality of second power sub-substrate pads 302S-P2 may be arranged to overlap each of two side edges of the sub-mold layer 316 in the first direction on the upper surface 300A of the substrate 300.

[0120] The first main substrate pad 302M1 can be connected to the first main interconnect 327 (described later), and the second main substrate pad 302M2 can be connected to the second main interconnect 337 (described later). A plurality of first main substrate pads 302M1 can be arranged along the second direction at the first side edge of the substrate 300 in the first direction. A plurality of second main substrate pads 302M2 can be arranged along the second direction at the second side edge of the substrate 300 in the first direction. The first main substrate pad 302M1 and the second main substrate pad 302M2 can be exposed without being covered by the sub-semiconductor package 310. In addition, the first main substrate pad 302M1 and the second main substrate pad 302M2 can be exposed without being covered by the first main chip stack 320 and the second main chip stack 330.

[0121] The first main substrate pads 302M1 may include first signal main substrate pads 302M1-S that exchange internal signals between the sub-semiconductor package 310 and the first main chip stack 320, and first power main substrate pads 302M1-P that supply power to the first main chip stack 320. In this case, the first signal main substrate pads 302M1-S may be electrically connected to the internal signal sub-substrate pads 302S-S1 through connection lines CL formed in the substrate 300.

[0122] The second main substrate pads 302M2 may include second signal main substrate pads 302M2-S that exchange internal signals between the sub-semiconductor package 310 and the second main chip stack 330, and second power main substrate pads 302M2-P that supply power to the second main chip stack 330. In this case, the second signal main substrate pads 302M2-S may be electrically connected to the internal signal sub-substrate pads 302S-S1 through connection lines CL formed in the substrate 300.

[0123] Since the detailed configuration of the sub-semiconductor package 310 has been described, a detailed description thereof will be omitted. The sub-semiconductor package 310 may be electrically connected to the substrate 300 through the sub-interconnector 319 .

[0124] Specifically, the first power sub-interconnector 319-P1 can be connected to the first power sub-substrate pad 302S-P1, and the second power sub-interconnector 319-P2 can be connected to the second power sub-substrate pad 302S-P2. Therefore, an electrical path (i.e., a power supply path) can be formed through the sub-semiconductor chip 314, the power redistribution conductive layer 318B-P, the first power sub-interconnector 319-P1 and the second power sub-interconnector 319-P2, and the first power sub-substrate pad 302S-P1 and the second power sub-substrate pad 302S-P2. In this case, the first power sub-interconnector 319-P1 can enable a shorter power supply path to be formed. In addition, the first power sub-interconnector 319-P1 and the second power sub-interconnector 319-P2 can enable multiple power supply paths to be formed. Although not shown, the first power sub-base pad 302S-P1 and the second power sub-base pad 302S-P2 can be electrically connected to the external connection terminal 340 through the circuit and / or wiring structure inside the substrate 300, thereby being connected to an external component (not shown) and powered from the external component.

[0125] In addition, external signal sub-interconnectors 319-S2 can be connected to external signal sub-substrate pads 302S-S2. Thus, an electrical path (i.e., an external signal transmission path) can be formed that passes through sub-semiconductor chip 314, signal redistribution conductive layer 318B-S, external signal sub-interconnectors 319-S2, and external signal sub-substrate pads 302S-S2. Although not shown, external signal sub-substrate pads 302S-S2 can be electrically connected to external connection terminals 340 via circuits and / or wiring structures within substrate 300, thereby connecting to external components (not shown) and exchanging signals with the external components.

[0126] In addition, the internal signal sub-interconnector 319-S1 can be connected to the internal signal sub-substrate pad 302S-S1. The internal signal sub-substrate pad 302S-S1 can be connected to the first signal main substrate pad 302M1-S and the second signal main substrate pad 302M2-S via the connection line CL. Therefore, an electrical connection can be made between each of the first main chip stack 320 and the second main chip stack 330 and the sub-semiconductor chip 314. The structure of the first main chip stack 320, the connection relationship between the substrate 300 and the first main chip stack 320, and the connection relationship between the sub-semiconductor package 310 and the first main chip stack 320 can be substantially the same as in the above-mentioned embodiment. In addition, the structure of the second main chip stack 330, the connection relationship between the substrate 300 and the second main chip stack 330, and the connection relationship between the sub-semiconductor package 310 and the second main chip stack 330 can be substantially the same as in the above-mentioned embodiment. Unspecified reference numerals 324, 322, 325, 327, 327S, and 327P may represent a first main semiconductor chip, a first adhesive layer, a first chip pad, a first main interconnector, a first signal main interconnector, and a first power main interconnector, respectively. Furthermore, unspecified reference numerals 334, 332, 335, 337, 337S, and 337P may represent a second main semiconductor chip, a second adhesive layer, a second chip pad, a second main interconnector, a second signal main interconnector, and a second power main interconnector, respectively.

[0127] The sub-semiconductor package 310 , the first main chip stack 320 , and the second main chip stack 330 may be covered by a mold layer 350 formed over the substrate 300 .

[0128] In the case of this embodiment, all the effects of the above-mentioned embodiments can be ensured.

[0129] Furthermore, a current path can be formed from one power redistribution conductive layer 318B-P through the first power sub-interconnector 319-P1 and the second power sub-interconnector 319-P2. In other words, multiple current paths and short current paths can be formed. As a result, the impedance and inductance of the power supply path can be reduced, thereby facilitating power supply between the sub-semiconductor package 310 and the substrate 300.

[0130] Furthermore, the power redistribution conductive layer 318B-P disposed between the two signal redistribution conductive layers 318B-S can suppress interference between the two signal redistribution conductive layers 318B-S.

[0131] According to the above-described embodiments of the present disclosure, a high-capacity and multifunctional semiconductor package can be realized by forming a main chip stack including one or more main semiconductor chips over a sub-semiconductor package, and power supply to the sub-semiconductor package can be facilitated.

[0132] Figure 15 A block diagram illustrating an electronic system including a memory card 7800 employing at least one of the semiconductor packages according to the embodiments is shown. Memory card 7800 includes a memory 7810, such as a nonvolatile memory device, and a memory controller 7820. Memory 7810 and memory controller 7820 can store data or read stored data. At least one of memory 7810 and memory controller 7820 can include at least one of the semiconductor packages according to the described embodiments.

[0133] The memory 7810 may include a nonvolatile memory device to which the technology of the embodiments of the present disclosure is applied. The memory controller 7820 may control the memory 7810 so as to read out stored data or store data in response to a read / write request from the host 7830 .

[0134] Figure 16 A block diagram illustrating an electronic system 8710 including at least one of the semiconductor packages according to the described embodiments is shown. The electronic system 8710 may include a controller 8711, an input / output device 8712, and a memory 8713. The controller 8711, the input / output device 8712, and the memory 8713 may be coupled to each other via a bus 8715 that provides a path for data movement.

[0135] In embodiments, the controller 8711 may include one or more microprocessors, digital signal processors, microcontrollers, and / or logic devices capable of performing the same functions as these components. The controller 8711 or the memory 8713 may include one or more semiconductor packages according to embodiments of the present disclosure. The input / output device 8712 may include at least one selected from a keypad, a keyboard, a display device, a touch screen, and the like. The memory 8713 is a device for storing data. The memory 8713 may store data and / or commands to be executed by the controller 8711, and the like.

[0136] The memory 8713 may include a volatile memory device such as DRAM and / or a non-volatile memory device such as flash memory. For example, the flash memory may be installed in an information processing system such as a mobile terminal or a desktop computer. The flash memory may constitute a solid-state drive (SSD). In this case, the electronic system 8710 can stably store a large amount of data in the flash memory system.

[0137] The electronic system 8710 may further include an interface 8714 configured to send data to and receive data from a communication network. The interface 8714 may be a wired or wireless type. For example, the interface 8714 may include an antenna or a wired or wireless transceiver.

[0138] The electronic system 8710 may be implemented as a mobile system, a personal computer, an industrial computer, or a logic system that performs various functions. For example, the mobile system may be any one of a personal digital assistant (PDA), a portable computer, a tablet computer, a mobile phone, a smart phone, a wireless phone, a laptop computer, a memory card, a digital music system, and an information transmission / reception system.

[0139] If the electronic system 8710 represents a device capable of performing wireless communications, the electronic system 8710 can be used in a communication system using technology such as CDMA (Code Division Multiple Access), GSM (Global System for Mobile Communications), NADC (North American Digital Cellular), E-TDMA (Enhanced Time Division Multiple Access), WCDMA (Wideband Code Division Multiple Access), CDMA2000, LTE (Long Term Evolution), or Wibro (Wireless Broadband Internet).

[0140] Although various embodiments have been described for illustrative purposes, it will be apparent to those skilled in the art that various changes and modifications can be made without departing from the spirit and scope of the present teachings as defined in the following claims.

[0141] CROSS-REFERENCE TO RELATED APPLICATIONS

[0142] This application claims priority from Korean Patent Application No. 10-2020-0093000, filed on Jul. 27, 2020, which is hereby incorporated by reference in its entirety.

Claims

1. A semiconductor package, comprising: substrate; a sub-semiconductor package disposed above the substrate, the sub-semiconductor package comprising a sub-semiconductor chip, a sub-molding layer, and a redistribution conductive layer, wherein the sub-semiconductor chip has a chip pad on an effective surface facing the substrate, the sub-molding layer surrounds a side surface of the sub-semiconductor chip, the sub-molding layer has a surface facing the substrate, the redistribution conductive layer is connected to the chip pad and extends below the surface of the sub-molding layer, wherein the redistribution conductive layer comprises a signal redistribution conductive layer and a power redistribution conductive layer, the signal redistribution conductive layer extends toward an edge of the sub-molding layer, the signal redistribution conductive layer has a signal redistribution pad at an end thereof, the power redistribution conductive layer is shorter than the signal redistribution conductive layer, and the power redistribution conductive layer has a power redistribution pad at an end thereof; a signal sub-interconnector having an upper surface connected to the signal redistribution pad and a lower surface connected to the substrate; a power sub-interconnect having an upper surface connected to the power redistribution pad and a lower surface connected to the substrate; and at least one main semiconductor chip formed over the sub-semiconductor package and electrically connected to the substrate, The chip pad is arranged along a first side edge and a second side edge of the sub-semiconductor chip in a first direction and along a third side edge and a fourth side edge of the sub-semiconductor chip in a second direction, wherein the second direction is perpendicular to the first direction. The signal redistribution pads include a plurality of signal redistribution pads disposed at a first side edge and a second side edge of the sub-molding layer in the first direction. Wherein, the signal redistribution conductive layer includes a plurality of signal redistribution conductive layers, wherein the signal redistribution conductive layer connected to the chip pads disposed at the first side edge and the third side edge of the sub-semiconductor chip extends toward the signal redistribution pad disposed at the first side edge of the sub-mold layer, and The signal redistribution conductive layer connected to the chip pads disposed at the second and fourth side edges of the sub-semiconductor chip extends toward the signal redistribution pad disposed at the second side edge of the sub-molding layer.

2. The semiconductor package according to claim 1, wherein A power supply path passing through the power redistribution conductive layer, the power sub-interconnector, and the substrate is shorter than a signal transmission path passing through the signal redistribution conductive layer, the signal sub-interconnector, and the substrate.

3. The semiconductor package according to claim 1, wherein Each of the signal sub-interconnector and the power sub-interconnector includes a solder ball, a metal bump, or a combination thereof.

4. The semiconductor package according to claim 1, wherein The signal redistribution conductive layer extends outward from a portion of an edge of the sub-semiconductor chip, and The power redistribution conductive layer extends inward from another portion of the edge of the sub-semiconductor chip.

5. The semiconductor package according to claim 1 , further comprising: a main interconnector connecting the main semiconductor chip to the substrate, wherein the signal sub-interconnector comprises an internal signal sub-interconnector for exchanging signals between the main semiconductor chip and the sub-semiconductor chip, The main interconnector includes a signal main interconnector for exchanging the signal between the main semiconductor chip and the sub-semiconductor chip. wherein the substrate comprises an internal signal sub-substrate pad connected to the internal signal sub-interconnector and a signal main substrate pad connected to the signal main interconnector, and The internal signal sub-substrate pads and the signal main substrate pads are connected to each other through connection lines formed in the substrate.

6. The semiconductor package according to claim 1 , further comprising: a main interconnector connecting the main semiconductor chip to the substrate, and Wherein, the main interconnector comprises a bonding wire.

7. The semiconductor package according to claim 1, wherein The signal redistribution conductive layer has a spiral shape centered on the sub-semiconductor chip.

8. The semiconductor package according to claim 1, wherein The substrate includes substrate pads disposed at a first side edge and a second side edge of the substrate in a first direction, and Wherein, the main semiconductor chip includes: at least one first master semiconductor chip connected to the substrate pad provided at the first side edge of the substrate through a first master interconnector; and At least one second master semiconductor chip is connected to the substrate pad disposed at the second side edge of the substrate through a second master interconnector.

9. The semiconductor package according to claim 8, wherein The first main semiconductor chip includes a plurality of first main semiconductor chips stacked offset in a direction away from the first side edge of the substrate in the first direction, and The second main semiconductor chip includes a plurality of second main semiconductor chips offset and stacked in a direction away from the second side edge of the substrate in the first direction.

10. The semiconductor package according to claim 1, wherein The main semiconductor chip includes a memory, and Wherein, the sub-semiconductor chip includes a memory controller.

11. A semiconductor package, comprising: substrate; a sub-semiconductor package disposed above the substrate, the sub-semiconductor package comprising a sub-semiconductor chip, a sub-molding layer, and a signal redistribution conductive layer and a power redistribution conductive layer, wherein the sub-semiconductor chip has a chip pad on an active surface facing the substrate, the sub-molding layer surrounds a side surface of the sub-semiconductor chip, the sub-molding layer has a surface facing the substrate, the signal redistribution conductive layer and the power redistribution conductive layer are connected to the chip pad and extend below the surface of the sub-molding layer to an edge of the sub-molding layer; a signal sub-interconnector having an upper surface connected to a signal redistribution pad formed at an end of the signal redistribution conductive layer and a lower surface connected to the substrate; a second power sub-interconnector having an upper surface connected to a second power redistribution pad formed at an end of the power redistribution conductive layer and a lower surface connected to the substrate; a first power sub-interconnector having an upper surface connected to a first power redistribution pad formed at a portion of the power redistribution conductive layer excluding the end portion of the power redistribution conductive layer and a lower surface connected to the substrate; as well as at least one main semiconductor chip formed over the sub-semiconductor package and electrically connected to the substrate, The chip pad is arranged along a first side edge and a second side edge of the sub-semiconductor chip in a first direction and along a third side edge and a fourth side edge of the sub-semiconductor chip in a second direction, wherein the second direction is perpendicular to the first direction. The signal redistribution conductive layer includes a plurality of signal redistribution conductive layers having a plurality of signal redistribution pads formed at the end thereof. The power redistribution conductive layer includes a plurality of power redistribution conductive layers having a plurality of second power redistribution pads formed at the end thereof. The signal redistribution pad and the second power redistribution pad are arranged at a first side edge and a second side edge of the sub-molding layer in the first direction. wherein the signal redistribution conductive layer and the power redistribution conductive layer connected to the chip pads disposed at the first side edge and the third side edge of the sub-semiconductor chip extend toward the signal redistribution pad and the second power redistribution pad disposed at the first side edge of the sub-mold layer, and The signal redistribution conductive layer and the power redistribution conductive layer connected to the chip pads arranged at the second side edge and the fourth side edge of the sub-semiconductor chip extend toward the signal redistribution pad and the second power redistribution pad arranged at the second side edge of the sub-molding layer.

12. The semiconductor package according to claim 11, wherein A power supply path passing through the power redistribution conductive layer, the first power sub-interconnector, and the substrate is shorter than a signal transmission path passing through the signal redistribution conductive layer, the signal sub-interconnector, and the substrate.

13. The semiconductor package according to claim 11, wherein A first power supply path is formed through the power redistribution conductive layer, the first power sub-interconnector, and the substrate, and The second power supply path is formed to pass through the power redistribution conductive layer, the second power sub-interconnector and the substrate.

14. The semiconductor package according to claim 11, wherein Each of the signal sub-interconnect, the first power sub-interconnect, and the second power sub-interconnect includes a solder ball, a metal bump, or a combination thereof.

15. The semiconductor package according to claim 11, wherein The signal redistribution conductive layer and the power redistribution conductive layer have a spiral shape centered on the sub-semiconductor chip.

16. The semiconductor package according to claim 11, wherein The power redistribution conductive layer is interposed between the two signal redistribution conductive layers.

17. A semiconductor package, comprising: substrate; A sub-semiconductor package having a sub-semiconductor chip disposed above the substrate, the sub-semiconductor package further comprising: a chip pad located on a surface of the sub-semiconductor chip facing the substrate; a sub-molding layer surrounding a side surface of the sub-semiconductor chip such that the sub-molding layer has a surface facing the substrate, wherein the surface of the sub-molding layer is at the same level as the surface of the sub-semiconductor chip facing the substrate; and a redistribution conductive layer connected to the chip pad, wherein the redistribution conductive layer includes a signal redistribution conductive layer and a power redistribution conductive layer, wherein the signal redistribution conductive layer has a signal redistribution pad at an end thereof and the power redistribution conductive layer has a power redistribution pad at an end thereof, and wherein the power redistribution conductive layer is shorter than the signal redistribution conductive layer; a signal sub-interconnector having an upper surface connected to the signal redistribution pad and a lower surface connected to the substrate; a power sub-interconnect having an upper surface connected to the power redistribution pad and a lower surface connected to the substrate; and at least one main semiconductor chip formed over the sub-semiconductor package and electrically connected to the substrate, The chip pad is arranged along a first side edge and a second side edge of the sub-semiconductor chip in a first direction and along a third side edge and a fourth side edge of the sub-semiconductor chip in a second direction, wherein the second direction is perpendicular to the first direction. The signal redistribution pads include a plurality of signal redistribution pads disposed at a first side edge and a second side edge of the sub-molding layer in the first direction. Wherein, the signal redistribution conductive layer includes a plurality of signal redistribution conductive layers, wherein the signal redistribution conductive layer connected to the chip pads disposed at the first side edge and the third side edge of the sub-semiconductor chip extends toward the signal redistribution pad disposed at the first side edge of the sub-mold layer, and The signal redistribution conductive layer connected to the chip pads disposed at the second and fourth side edges of the sub-semiconductor chip extends toward the signal redistribution pad disposed at the second side edge of the sub-molding layer.

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