Low cost electrostatic discharge protection method

Abstract

The embodiment of the application discloses a low-cost electrostatic protection method, comprising: providing a first chip, arranging an integrated circuit on the first chip; providing a second chip, arranging an electrostatic protection circuit on the second chip, the electrostatic protection circuit comprising: a first power supply port, a second power supply port and a first capacitor; connecting the first power supply port with a power supply port of the integrated circuit; when an electrostatic pulse flows from the second power supply port, the first capacitor can absorb the electrostatic pulse, and inhibit the integrated circuit from being damaged by electrostatic, and the capacitor cost is relatively low, so that the method can realize electrostatic protection while the protection cost is relatively low. Moreover, the integrated circuit and the electrostatic protection circuit are arranged on different chips, and there is no need to design the electrostatic protection on the chip where the integrated circuit is arranged, thereby avoiding the problem that the electrostatic protection design cannot be performed on the integrated circuit due to the limitation of the base material of the chip where the integrated circuit is arranged, and the electrostatic protection of the new integrated circuit can be realized.

Description

Technical Field

[0001] This application relates to the field of integrated circuit technology, and in particular to a low-cost electrostatic discharge protection method. Background Technology

[0002] With the development of integrated circuit technology and its increasingly widespread application, electrostatic discharge (ESD) protection for integrated circuits has become increasingly important, and the cost of ESD protection for integrated circuits has also attracted more and more attention. Reducing the cost of ESD protection is also crucial for the development of integrated circuits. Therefore, providing a low-cost ESD protection method has become a research focus for those skilled in the art.

[0003] Furthermore, with the development of integrated circuit technology, novel material integrated circuits have become a major trend in integrated circuit development. These novel material integrated circuits use different substrate materials than silicon-based integrated circuits, resulting in superior performance and making them a rising star in improving computer speed and reducing power consumption in electronic devices. However, these novel material integrated circuits are typically very sensitive to electrostatic pulses and prone to electrostatic damage. Moreover, due to limitations in the characteristics of their substrate materials, existing integrated circuit electrostatic protection designs are often ineffective, making it difficult to provide effective electrostatic protection for these circuits. This leads to functional failure of these integrated circuits in practical applications due to electrostatic damage. Therefore, providing a method for electrostatic protection of these novel material integrated circuits has become a key research focus for those skilled in the art. Summary of the Invention

[0004] To address the aforementioned technical problems, this application provides a low-cost electrostatic discharge (ESD) protection method. This ESD protection circuit method for integrated circuits has a low cost, and the ESD protection can also be used for ESD protection of ESD-sensitive novel material integrated circuits, which helps ensure the reliability of integrated circuits and promotes the development of novel material integrated circuits.

[0005] To address the above problems, the embodiments of this application provide the following technical solutions:

[0006] A low-cost electrostatic discharge protection method includes:

[0007] A first chip is provided, and an integrated circuit is disposed on the first chip, wherein the integrated circuit includes a power port;

[0008] A second chip is provided, and an electrostatic discharge (ESD) protection circuit is disposed on the second chip. The ESD protection circuit includes: a power output port, a first capacitor, and a ground output port. The power output port includes a first power output port and a second power output port. The second power output port is connected to the first power output port through a first terminal of the first capacitor, and the second terminal of the first capacitor is connected to the ground output port.

[0009] The first power output port is connected to the power port of the integrated circuit so that the electrostatic discharge protection circuit can provide electrostatic protection for the integrated circuit.

[0010] Optionally, the first chip is a carbon-based chip, and the second chip is a silicon-based chip.

[0011] Optionally, the capacitance value of the first capacitor ranges from 0.05uF to 50uF, including the endpoint values.

[0012] Optionally, the electrostatic discharge protection circuit further includes: a second capacitor and a first N-type field-effect transistor disposed between the second power output port and the first terminal of the first capacitor, wherein the first terminal of the second capacitor is connected to the drain of the first N-type field-effect transistor, the gate of the first N-type field-effect transistor is connected to the second terminal of the second capacitor, the source is connected to the ground output port, and the ground output port is grounded; the method further includes:

[0013] The second power output port is connected sequentially to the first terminal of the second capacitor, the drain of the first N-type field-effect transistor, and the first terminal of the first capacitor.

[0014] The electrostatic discharge protection circuit further includes a first diode, and the method further includes:

[0015] Connect the negative terminal of the first diode to the first power supply output port, and connect the positive terminal to the ground output port.

[0016] Optionally, the integrated circuit further includes an input port, and the electrostatic discharge protection circuit further includes: an input output port, a second diode, and a third diode, wherein the input output port includes a first input output port and a second input output port, the second input output port is connected to the first input output port through the positive terminal of the second diode, the negative terminal of the second diode is connected to the first terminal of the second capacitor, the negative terminal of the third diode is connected to the positive terminal of the second diode, and the positive terminal is connected to the ground output port;

[0017] The electrostatic discharge protection circuit further includes: a first resistor and a second N-type field-effect transistor, wherein the first end of the first resistor is connected to the first input output port, the second end is connected to the positive terminal of the second diode, the drain of the second N-type field-effect transistor is connected to the first end of the first resistor, and the source is connected to the gate of the second N-type field-effect transistor and the ground output port respectively.

[0018] The method also includes:

[0019] The first input output port is connected to the input port of the integrated circuit so that the electrostatic discharge protection circuit provides electrostatic protection for the integrated circuit.

[0020] Optionally, the integrated circuit further includes an output port, and the electrostatic discharge protection circuit further includes: an output terminal, a fourth diode, and a fifth diode, wherein the output terminal includes a first output terminal and a second output terminal, the second output terminal is connected to the first output terminal through the positive terminal of the fourth diode, the negative terminal of the fourth diode is connected to the first power supply terminal, the negative terminal of the fifth diode is connected to the positive terminal of the fourth diode, and the positive terminal is connected to the ground terminal; the method further includes:

[0021] Connect the first output port to the output port of the integrated circuit so that the electrostatic discharge protection circuit can provide electrostatic discharge protection for the integrated circuit.

[0022] Optionally, the electrostatic discharge protection circuit further includes a second resistor; the method further includes:

[0023] Connect the first end of the second resistor to the first end of the first capacitor, and connect the second end to the second end of the first resistor.

[0024] Optionally, the first diode is a gate-controlled diode, the second diode is a gate-controlled diode, the third diode is a gate-controlled diode, the fourth diode is a gate-controlled diode, and the fifth diode is a gate-controlled diode.

[0025] Optionally, the electrostatic discharge protection circuit further includes a third resistor; the method further includes:

[0026] The first end of the third resistor is connected to the gate of the first N-type field-effect transistor, and the second end is connected to the ground terminal.

[0027] Optionally, the integrated circuit further includes a ground port, the ground output port including a first ground output port and a second ground output port; the method further includes:

[0028] Connect the first ground output port to the ground port of the integrated circuit, connect the second ground output port to the first ground output port, and ground the second ground output port.

[0029] Compared with existing technologies, the above technical solution has the following advantages:

[0030] The technical solution provided in this application includes: providing a first chip, on which an integrated circuit is disposed, the integrated circuit including a power port; providing a second chip, on which an electrostatic discharge (ESD) protection circuit is disposed, the ESD protection circuit including: a power output port, a first capacitor, and a ground output port, wherein the power output port includes a first power output port and a second power output port; connecting the first power output port to the power port of the integrated circuit enables the ESD protection circuit to be connected to the integrated circuit, so that when an ESD pulse flows in from the second power output port, the first capacitor absorbs the ESD pulse, suppressing the ESD pulse from flowing into the integrated circuit, thereby enabling the ESD protection method to provide ESD protection for the integrated circuit, which helps to ensure the reliability of the integrated circuit. Furthermore, the ESD protection circuit in the ESD protection method includes a first capacitor, which absorbs ESD pulses to provide ESD protection for the integrated circuit. Since capacitors are low-cost, the method provided in this application achieves ESD protection while keeping the protection cost low. Moreover, the ESD protection method only requires a single protective element, the first capacitor, to achieve ESD protection for the integrated circuit, which helps to reduce the cost of ESD protection. Furthermore, the electrostatic discharge (ESD) protection circuit is disposed on the second chip, while the integrated circuit is disposed on the first chip. This means that the integrated circuit and the ESD protection circuit are disposed on different chips, eliminating the need for ESD protection design on the first chip. In other words, ESD protection design is not required on the chip containing the integrated circuit, thus avoiding the problem of being unable to perform ESD protection design on the integrated circuit due to limitations in the substrate material of the chip containing the integrated circuit. This enables ESD protection for ESD-sensitive novel integrated circuits, thereby contributing to the reliability of novel material integrated circuits and promoting their development. Attached Figure Description

[0031] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0032] Figure 1A flowchart illustrating a low-cost electrostatic discharge protection method provided in this application embodiment;

[0033] Figure 2 This is a schematic diagram of the circuit structure in a low-cost electrostatic discharge protection method provided in an embodiment of this application. Detailed Implementation

[0034] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0035] Many specific details are set forth in the following description in order to provide a full understanding of this application. However, this application may also be implemented in other ways different from those described herein. Those skilled in the art can make similar extensions without departing from the spirit of this application. Therefore, this application is not limited to the specific embodiments disclosed below.

[0036] Secondly, this application provides a detailed description in conjunction with schematic diagrams. When detailing the embodiments of this application, for ease of explanation, the cross-sectional views illustrating the device structure may be partially enlarged, not adhering to the usual scale. Furthermore, the schematic diagrams are merely examples and should not limit the scope of protection of this application. In addition, actual fabrication should include three-dimensional spatial dimensions of length, width, and depth.

[0037] As described in the background section, reducing the cost of electrostatic discharge (ESD) protection is crucial for the development of integrated circuits. Therefore, providing a low-cost ESD protection method has become a research focus for those skilled in the art.

[0038] Furthermore, to overcome the physical limitations of traditional silicon-based integrated circuits, researchers have focused on deploying integrated circuits on novel materials. These novel materials differ from traditional silicon-based integrated circuits. Carbon-based integrated circuits, formed by deploying integrated circuits on carbon-based chips, exhibit superior performance, making them one of the most widely studied novel integrated circuit materials. The core component of carbon-based integrated circuits is the carbon-based transistor, which operates five times faster than a silicon-based transistor of the same size while consuming less than one-fifth the energy. This combination of higher speed and lower energy consumption makes carbon-based integrated circuits a promising technology for applications, attracting widespread research.

[0039] According to the inventors' research, most of these novel material integrated circuits are typically highly sensitive to electrostatic pulses and are referred to as electrostatic-sensitive novel material integrated circuits. They are prone to electrostatic damage. Furthermore, due to limitations in the characteristics of the substrate material of the chip on which these electrostatic-sensitive novel material integrated circuits are located, it is impossible to directly implement electrostatic protection design on the integrated circuit chip itself. In other words, it is impossible to achieve on-chip electrostatic protection design for integrated circuits. This makes it impossible for existing integrated circuit electrostatic protection designs to protect against electrostatic damage, thus failing to suppress electrostatic damage in such integrated circuits. As a result, in practical applications, these integrated circuits are prone to functional failure due to electrostatic damage, affecting the application and development of novel material integrated circuits.

[0040] For example, carbon-based integrated circuits suffer from problems such as thin carbon film, low conductivity, and poor heat dissipation. As a result, it is impossible to directly complete the electrostatic discharge (ESD) protection design for the carbon-based integrated circuit on the chip itself. In other words, it is impossible to achieve on-chip ESD protection for the integrated circuit, and thus it is impossible to effectively suppress ESD damage to the carbon-based integrated circuit, affecting its application.

[0041] Therefore, in order to promote the development of integrated circuits and achieve electrostatic protection for electrostatic sensitive novel material integrated circuits, providing a method to achieve electrostatic protection for the aforementioned electrostatic sensitive novel material integrated circuits has become a research focus for those skilled in the art.

[0042] Based on this, embodiments of this application provide a low-cost electrostatic discharge (ESD) protection method, which utilizes an ESD protection circuit to protect integrated circuits from ESD, such as... Figure 1 As shown, the method includes:

[0043] S1: As Figure 2 As shown, a first chip 100 is provided, and an integrated circuit is disposed on the first chip 100 to form an integrated circuit with a specific function. The integrated circuit includes a power port 01. The integrated circuit is a novel material integrated circuit, but this application does not limit it and it depends on the specific circumstances.

[0044] S2: Continue as follows Figure 2 As shown, a second chip 200 is provided, and an electrostatic discharge (ESD) protection circuit is disposed on the second chip 200 to form an ESD protection circuit with protective capabilities. The ESD protection circuit includes: a power output port, a first capacitor 11, and a ground output port 20.

[0045] The power output ports include a first power output port 111 and a second power output port 112. The second power output port 112 is connected to the first power output port 111 through the first end of the first capacitor 11. That is, the first end of the first capacitor 11 is connected to the first power output port 111 and the second power output port 112 respectively. The second end of the first capacitor 11 is connected to the ground output port 20.

[0046] S3: Connect the first power output port to the power port of the integrated circuit so that the electrostatic discharge protection circuit can provide electrostatic protection for the integrated circuit.

[0047] It should be noted that, in one embodiment of this application, the first capacitor can be directly fabricated on the second chip, with its first end connected to both the first and second power output ports, and its second end connected to the ground output port. In another embodiment of this application, the first capacitor can also be added during the packaging process, located on the package casing, with its first end connected to both the first and second power output ports, and its second end connected to the ground output port. Adding the first capacitor during the packaging process is less costly, and in practical applications, it is more commonly chosen to add it during packaging. However, this application does not limit this choice; it depends on the specific circumstances. It should also be noted that the first power output port of the electrostatic discharge (ESD) protection circuit is connected to the power port of the integrated circuit via wire bonding. Furthermore, the integrated circuit is disposed on the first chip, while the ESD protection circuit is disposed on the second chip. That is, the integrated circuit and the ESD protection circuit are disposed on different chips. Therefore, even if the first power output port is connected to the power port of the integrated circuit, and the first power output port is connected to the first end of the first capacitor, the power port of the integrated circuit will not be connected to the first end of the first capacitor.

[0048] It should be further noted that, in this embodiment, the power output port includes two power output ports: a first power output port and a second power output port. The integrated circuit includes one power port, but this application is not limited to this. In other embodiments of this application, the electrostatic discharge (ESD) protection circuit may also include one power output port or at least three power output ports, and the integrated circuit may include at least two power ports, depending on the specific circumstances. Furthermore, in this embodiment, the ESD protection circuit includes one first capacitor, but this application is not limited to this. In other embodiments of this application, depending on the area of ​​the second chip and the complexity of the circuit, the ESD protection circuit may include at least two first capacitors, increasing with the area of ​​the second chip and the complexity of the circuit. The first terminals of each of the at least two first capacitors are respectively connected to the first power output port and the second power output port, and the second terminals are both grounded. The at least two capacitors are located at different positions on the surface of the second chip according to actual needs.

[0049] Specifically, in this embodiment, the integrated circuit is disposed on the first chip, and the electrostatic discharge (ESD) protection circuit is disposed on the second chip. The power port of the integrated circuit is connected to the first power output port of the ESD protection circuit, enabling the ESD protection circuit to be connected to the integrated circuit. The first terminal of the first capacitor is connected to both the first and second power output ports, while the second terminal is grounded. This allows the first capacitor to absorb ESD pulses flowing into the integrated circuit from the second power output port, suppressing the pulses from flowing into the integrated circuit. This enables the ESD protection circuit to protect the integrated circuit from ESD damage, thus ensuring its reliability. Furthermore, the ESD protection circuit in this method includes a first capacitor. By absorbing ESD pulses, the integrated circuit is protected. Since capacitors are low-cost, the method provided in this embodiment achieves ESD protection at a low cost. Moreover, the ESD protection method only requires a single protective element (the first capacitor) to protect the integrated circuit, further reducing the cost of ESD protection.

[0050] Furthermore, due to limitations in the substrate material of the aforementioned known electrostatic-sensitive novel material integrated circuits, on-chip electrostatic protection designs cannot be implemented. This prevents existing electrostatic protection designs from effectively suppressing electrostatic damage to these circuits, thus hindering their practical application. However, the electrostatic protection circuit provided in this application is deployed on a second chip, while the integrated circuit is deployed on a first chip. This allows the integrated circuit and the electrostatic protection circuit to be located on different chips, eliminating the need for electrostatic protection design on the first chip. In other words, it avoids the problem of being unable to implement electrostatic protection design for the integrated circuit due to limitations in the substrate material of the chip. This enables electrostatic protection for electrostatic-sensitive novel integrated circuits, thereby improving the reliability of novel material integrated circuits and contributing to their development.

[0051] In addition, the electrostatic discharge (ESD) protection circuit provided in this embodiment is disposed on the second chip, while the integrated circuit is disposed on the first chip. This allows the integrated circuit and the ESD protection circuit to be disposed on different chips, enabling the ESD protection circuit to provide off-chip ESD protection for the integrated circuit. Consequently, the ESD protection circuit can also be applied to integrated circuits with high on-chip ESD protection design costs. Providing ESD protection for integrated circuits with high on-chip ESD protection design costs helps save on ESD protection costs for integrated circuits and contributes to the development of integrated circuits.

[0052] Based on the above embodiments, in this embodiment, the second power output port is connected to the first power output port through the first end of the first capacitor, and the second end of the first capacitor is connected to the ground output port. When an electrostatic pulse flows in from the second power output port, the electrostatic pulse will flow through the first end of the first capacitor and be absorbed by the first capacitor. Thus, when an electrostatic pulse flows in from the second power output port, the electrostatic protection circuit can suppress the electrostatic pulse from flowing into the integrated circuit, thereby enabling the electrostatic protection circuit to suppress electrostatic damage to the integrated circuit to a certain extent, which helps to ensure the reliability of the integrated circuit.

[0053] Optionally, in one embodiment of this application, the first chip is a carbon-based chip and the second chip is a silicon-based chip. However, this application is not limited to this. In other embodiments of this application, the first chip may also be other chips that cannot achieve on-chip electrostatic protection design, depending on the specific circumstances.

[0054] Optionally, in one embodiment of this application, the capacitance value of the first capacitor ranges from 0.05uF to 50uF, including the endpoint values. However, this application does not limit this value and it depends on the specific circumstances.

[0055] It should be noted that although the first capacitor can absorb the incoming electrostatic pulse, it has an upper limit. Therefore, in order to ensure the protection capability of the electrostatic discharge protection circuit for the integrated circuit, based on the above embodiments, in one embodiment of this application, the following is continued... Figure 2 As shown, the electrostatic discharge protection circuit further includes: a second capacitor 13 and a first N-type field-effect transistor 14 disposed between the second power output port 112 and the first terminal of the first capacitor 11, wherein the first terminal of the second capacitor 13 is connected to the drain of the first N-type field-effect transistor 14, the gate of the first N-type field-effect transistor 14 is connected to the second terminal of the second capacitor 13, the source is connected to the ground output port, and the ground output port is grounded; the method further includes:

[0056] S4: Connect the second power output port to the first power output port in sequence through the first terminal of the second capacitor, the drain of the first N-type field-effect transistor, and the first terminal of the first capacitor; since the first terminal of the first capacitor is connected to the first power output port, the second power output port can be connected to the first power output port in sequence through the first terminal of the second capacitor, the drain of the first N-type field-effect transistor, and the first terminal of the first capacitor, so that the electrostatic discharge protection circuit can provide electrostatic discharge protection for the integrated circuit.

[0057] The electrostatic discharge protection circuit further includes a first diode 12, and the method further includes:

[0058] S5: Connect the negative terminal of the first diode 12 to the first power output port 111, and connect the positive terminal to the ground output port; since the second power output port can be connected to the first power output port in sequence through the first terminal of the second capacitor, the drain of the first N-type field-effect transistor, and the first terminal of the first capacitor, the second power output port can be connected to the negative terminal of the first diode in sequence through the first terminal of the second capacitor, the drain of the first N-type field-effect transistor, the first terminal of the first capacitor, and the first power output port, so that the electrostatic discharge protection circuit can provide electrostatic discharge protection for the integrated circuit.

[0059] It should be noted that the first power output port is connected to the integrated circuit power port by a wire bonding, and the first power output port is connected to the negative terminal of the first diode by a metal wire bonding. Therefore, even if the first power output port is connected to the integrated circuit power port and the first power output port is connected to the negative terminal of the first diode, the integrated circuit power port will not be connected to the negative terminal of the first diode.

[0060] Specifically, in this embodiment, when a positive electrostatic pulse flows in from the second power output port, since the second power output port is connected to the first terminal of the first capacitor via the first terminal of the second capacitor and the drain of the first N-type field-effect transistor, the electrostatic pulse will be preferentially absorbed by the first capacitor after flowing into the second power output port, thereby suppressing electrostatic damage to the integrated circuit. The second power output port is connected to the first terminal of the first capacitor via the first terminal of the second capacitor and the drain of the first N-type field-effect transistor, so that the second power output port is connected to the drain of the first N-type field-effect transistor via the first terminal of the second capacitor. Therefore, when the electrostatic pulse flows into the second power output port, and the first capacitor reaches its absorption limit, the positive electrostatic pulse will flow through the first N-type field-effect transistor and out from the ground output port. The second power output port is also connected to the first power output port in sequence through the second terminal of the second capacitor, the drain of the first N-type field-effect transistor, and the first terminal of the first capacitor. The first power output port is also connected to the terminal port of the integrated circuit. Therefore, the positive electrostatic pulse flows in from the second power output port, and after the first capacitor reaches its absorption limit, it will also flow into the integrated circuit through the power port of the integrated circuit. It is known that the negative terminal of the first diode is connected to the first power output port, so the positive electrostatic pulse flowing in from the second power output port will not flow through the first diode. The principle of the positive electrostatic pulse flowing through the first N-type field-effect transistor is as follows: after flowing in from the second power output port, the positive electrostatic pulse couples with the second capacitor, causing the second capacitor to release charge to the gate of the first N-type field-effect transistor, raising the gate potential of the first N-type field-effect transistor, causing the first N-type field-effect transistor to conduct, thereby allowing the positive electrostatic pulse to flow through the first N-type field-effect transistor and out from the ground terminal.

[0061] It should be noted that integrated circuits typically include multiple electronic devices such as resistors, capacitors, and field-effect transistors, which have relatively high resistance. Therefore, in this embodiment, the resistance of the integrated circuit is greater than the resistance of the first N-type field-effect transistor. When parallel branches exist in a known circuit, the current intensity flowing into each parallel branch is related to the resistance of each branch. Branches with higher resistance have lower current intensity, while branches with lower resistance have higher current intensity. Thus, when the positive electrostatic pulse flows in, and after the first capacitor reaches its absorption limit, the intensity flowing through the first N-type field-effect transistor is greater than the intensity flowing into the integrated circuit, reducing the intensity of the electrostatic pulse flowing into the integrated circuit. Since the first capacitor can absorb electrostatic pulses flowing in from the second power supply output port, the positive electrostatic pulses will be preferentially absorbed by the first capacitor after they flow in. Only when the first capacitor reaches its absorption limit will the electrostatic pulses flow through the first N-type field-effect transistor and into the integrated circuit. Furthermore, since the intensity of the positive electrostatic pulses flowing through the first N-type field-effect transistor is greater than the intensity flowing into the integrated circuit, the electrostatic protection method can suppress the flow of electrostatic pulses into the integrated circuit, reduce the intensity of the electrostatic pulses flowing into the integrated circuit, and thus suppress electrostatic damage to the integrated circuit, which helps to ensure the reliability of the integrated circuit.

[0062] When a negative electrostatic pulse flows in from the second power output port, since the second power output port is connected to the first terminal of the second capacitor and the drain of the first N-type field-effect transistor (FET) in sequence, the negative electrostatic pulse will flow through the drain of the first N-type FET and the first terminal of the first capacitor, and will be preferentially absorbed by the first capacitor to suppress electrostatic damage to the integrated circuit. It is known that when the drain of the N-type FET is negatively charged, the PN junction of the N-type FET will conduct, making the N-type FET equivalent to a diode. Therefore, when the negative electrostatic pulse flows through the drain of the first N-type FET, the first N-type FET acts as a diode. Since the second power output port is connected to the drain of the first N-type FET through the first terminal of the second capacitor, and the source of the first N-type FET is grounded, the first N-type FET acts as a diode with its negative terminal connected to the second power output port and its positive terminal connected to the ground output port. This allows the negative electrostatic pulse to flow through the first N-type FET and out from the ground output port once the first capacitor reaches its absorption limit. Since the negative terminal of the first diode is connected to the first power supply output port, after the first capacitor reaches its absorption limit, the negative electrostatic pulse will still flow through the first diode and exit through the ground terminal. Simultaneously, the first power supply output port is connected to the power supply port of the integrated circuit, so after the first capacitor reaches its absorption limit, the negative electrostatic pulse will also flow into the integrated circuit. It is known that the integrated circuit has a relatively large resistance, greater than the resistance of the first N-type field-effect transistor 14 and the first diode. Therefore, after the first capacitor reaches its absorption limit, the pulse intensity flowing through the first diode and the first N-type field-effect transistor is greater than the intensity flowing into the integrated circuit. This causes most of the negative electrostatic pulse to flow out through the electrostatic protection circuit, thereby reducing the pulse intensity flowing into the integrated circuit and suppressing electrostatic damage to the integrated circuit to a certain extent, thus helping to ensure the reliability of the integrated circuit.

[0063] It should be noted that when a negative electrostatic pulse flows in, the first N-type field-effect transistor is equivalent to a diode. Therefore, when a negative electrostatic pulse flows in, the first N-type field-effect transistor and the first diode have the same conduction capability. Considering the small resistance on the wires in the circuit, the intensity of the negative electrostatic pulse flowing through the first N-type field-effect transistor and the first diode is related to the length of the wire between the first N-type field-effect transistor and the first diode and the second power supply output port. The shorter the wire, the greater the intensity of the path, and the longer the wire, the smaller the intensity of the path.

[0064] It should be noted that, in the electrostatic discharge (ESD) protection circuit provided in this application embodiment, the first capacitor is added during packaging by inserting a capacitor between the power supply output port and the ground output port, so that the first capacitor can absorb ESD pulses flowing in from the second power supply output port. According to the expression for the amount of charge stored in the capacitor:

[0065] Q=U*C

[0066] Where Q is the amount of charge stored in the first capacitor, in coulombs; U is the voltage across the first capacitor, in volts; and C is the capacitance of the first capacitor, in farads. According to the HBM model (Human Body Discharge Model), under 8000V HBM ESD (U=8000V, C=100pF), Q=8000*100*1e-12=8e-7 coulombs. When the capacitance of the first capacitor between the second power supply port and the ground port is 0.47uF, Q=8e-7=U*0.47*1e-6, and the clamping voltage U between the second power supply port and the ground port is 1.7V. Under this clamping voltage, the first diode can conduct, allowing negative electrostatic pulses to flow through it, thus reducing the intensity of electrostatic pulses flowing into the integrated circuit, thereby helping to suppress electrostatic damage to the integrated circuit and ensuring its reliability.

[0067] In addition, it should be noted that the above embodiments describe the case where electrostatic pulses flow into the integrated circuit from the outside through the second power output port. Another scenario is where electrostatic pulses exist inside the integrated circuit. The electrostatic protection circuit can also suppress electrostatic damage to the integrated circuit when electrostatic pulses exist inside the integrated circuit. Specifically, when an electrostatic pulse exists inside the integrated circuit and acts on the power port, if the electrostatic pulse is positive, since the second power output port is connected to the first power output port in sequence through the first terminal of the second capacitor, the drain of the first N-type field-effect transistor, and the first terminal of the first capacitor, and the integrated circuit power port is connected to the first power output port, a portion of the electrostatic pulse will remain inside the integrated circuit, while a portion will flow into the electrostatic protection circuit through the first power output port. After flowing into the electrostatic protection circuit, it will pass through the first terminal of the first capacitor and be preferentially absorbed by the first capacitor, reducing the pulse intensity remaining inside the integrated circuit and suppressing electrostatic damage to the integrated circuit. When the first capacitor reaches its absorption limit, the electrostatic pulse flowing into the electrostatic protection circuit will flow through the first N-type field-effect transistor and exit from the ground terminal. It is known that the resistance of the integrated circuit is greater than the resistance of the first N-type field-effect transistor. Therefore, when the first capacitor reaches its absorption limit, the pulse intensity flowing through the first N-type field-effect transistor is greater than the pulse intensity remaining inside the integrated circuit, which can reduce the pulse intensity remaining inside the integrated circuit and suppress electrostatic damage to the integrated circuit. It should be noted that the principle of this positive electrostatic pulse flowing through the first N-type field-effect transistor is the same as the principle of the positive electrostatic pulse flowing through the first N-type field-effect transistor when flowing in from the second power supply terminal, and will not be repeated here.

[0068] If the electrostatic pulse is negative, similarly, a portion of it will remain inside the integrated circuit, while a portion will flow into the electrostatic discharge (ESD) protection circuit through the first power output port. After flowing into the ESD protection circuit, it will pass through the first terminal of the first capacitor and be preferentially absorbed by it, reducing the pulse intensity remaining inside the integrated circuit and helping to suppress ESD damage. It is known that when a negative ESD pulse flows through the drain of the first N-type field-effect transistor (FET), the FET acts as a diode. Since the drain of the FET is connected to the first power output port through the first terminal of the first capacitor, and the source is connected to the ground output port, when the first capacitor reaches its absorption limit, the negative ESD pulse flowing into the ESD protection circuit will flow through the FET and exit from the ground output port. Simultaneously, the cathode of the first diode is connected to the first power output port, and the anode is connected to the ground output port. Therefore, when the first capacitor reaches its absorption limit, the negative ESD pulse flowing into the ESD protection circuit will also flow through the first diode and exit from the ground output port. It is known that the resistance of the integrated circuit is greater than the resistance of the first N-type field-effect transistor and the resistance of the first diode. Therefore, after the first capacitor reaches its absorption limit, the pulse intensity flowing through the first diode and the pulse intensity flowing through the first N-type field-effect transistor are greater than the intensity flowing into the integrated circuit. This allows the electrostatic discharge protection method to reduce the pulse intensity inside the integrated circuit, which can suppress electrostatic damage to the integrated circuit to a certain extent and help ensure the reliability of the integrated circuit.

[0069] Based on the above embodiments, in one embodiment of this application, the following continues... Figure 2 As shown, the integrated circuit also includes an input port 02, and the electrostatic discharge protection circuit also includes: an input output port, a second diode 31, and a third diode 32;

[0070] The input / output ports include a first input / output port 311 and a second input / output port 312. The second input / output port 312 is connected to the first input / output port 311 through the positive terminal of the second diode 31. That is, the positive terminal of the second diode 31 is connected to both the first input / output port 311 and the second input / output port 312. The negative terminal of the second diode 31 is connected to the first terminal of the second capacitor 13. The negative terminal of the third diode 32 is connected to the positive terminal of the second diode 31. Since the positive terminal of the second diode 31 is connected to both the first input / output port 311 and the second input / output port 312, the negative terminal of the third diode 32 is connected to both the first input / output port 311 and the second input / output port 312. The positive terminal of the third diode 32 is connected to the ground terminal.

[0071] The electrostatic discharge protection circuit further includes: a first resistor 33 and a second N-type field-effect transistor 34; wherein, the first end of the first resistor 33 is connected to the first input output port 311, and the second end is connected to the positive terminal of the second diode 31; since the negative terminal of the third diode 32 is connected to the positive terminal of the second diode 31, the negative terminal of the third diode 32 is connected to the second end of the first resistor 33; the drain of the second N-type field-effect transistor 34 is connected to the first end of the first resistor 33, and the source is connected to the gate of the second N-type field-effect transistor 34 and the ground output port 20 respectively; since the first end of the first resistor is connected to the first input output port, and the drain of the second N-type field-effect transistor is connected to the first end of the first resistor, the drain of the second N-type field-effect transistor is connected to the first input output port; and since the second end of the first resistor is connected to the second input output port, the drain of the second N-type field-effect transistor is connected to the second input output port through the first resistor.

[0072] The method also includes:

[0073] S6: Connect the first input output port to the input port of the integrated circuit so that the electrostatic discharge protection circuit can provide electrostatic protection for the integrated circuit.

[0074] It should be noted that the first input output port is connected to the integrated circuit input port via a wire bonding method, and the first input output port is connected to the anode of the second diode via a metal wire connection. Therefore, even if the first input output port is connected to the integrated circuit input port and also to the anode of the second diode, the integrated circuit input port will not be directly connected to the anode of the second diode. Furthermore, the first input output port is connected to the integrated circuit input port via a wire bonding method, and also to the first terminal of the first resistor via a metal wire connection. Therefore, even if the first input output port is connected to the integrated circuit input port and also to the first terminal of the first resistor, the integrated circuit input port will not be directly connected to the first terminal of the first resistor.

[0075] It should also be noted that, in the embodiments of this application, the input output port includes two input output ports: a first input output port and a second input output port. The integrated circuit includes one input port, but this application does not limit this. In other embodiments of this application, the electrostatic discharge protection circuit may also include one input output port or at least three input output ports, and the integrated circuit may include at least two input ports, depending on the specific circumstances.

[0076] Specifically, in this embodiment, the first input output port of the electrostatic discharge (ESD) protection circuit is connected to the input port of the integrated circuit, thereby connecting the ESD protection circuit to the integrated circuit. This allows the ESD protection circuit to provide ESD protection to the integrated circuit, suppressing ESD pulses from flowing into the integrated circuit through its input port, thus helping to prevent ESD damage to the integrated circuit and contributing to its development.

[0077] Based on the above embodiments, in this embodiment, when a positive electrostatic pulse flows in from the second input output port, it is known that the electrostatic pulse will flow through the second diode, be preferentially absorbed by the first capacitor, and after the first capacitor reaches its absorption limit, flow through the first N-type field-effect transistor and exit from the ground output port. The electrostatic discharge protection circuit includes an input output port, a second diode, and a third diode, such that the pulse flows through the second diode, through the first N-type field-effect transistor, and exits from the ground output port. The electrostatic discharge (ESD) protection circuit also includes a first resistor and a second N-type field-effect transistor (FET). After the first capacitor reaches its absorption limit, the positive ESD pulse will still flow through the first resistor and then through the drain of the second N-type FET. The gate and source of the second N-type FET are connected, and the gate is also connected to the ground terminal. This means the gate and source of the second N-type FET are short-circuited and both are grounded (referred to as Gate Ground NMOS, or GGNMOS). This keeps both the source and gate of the second N-type FET at a low potential. Therefore, when the positive ESD pulse flows through the drain of the second N-type FET and its intensity is low, the second N-type FET is in a closed state. When the positive ESD pulse intensity is high, the second N-type FET will conduct, and the positive ESD pulse will flow through the second N-type FET and exit from the ground terminal. Since the first input terminal is connected to the first end of the first resistor and also to the input port of the integrated circuit, the ESD pulse will also flow into the integrated circuit. Because the integrated circuit has a large resistance, greater than that of the first N-type field-effect transistor and the second N-type field-effect transistor, after the first capacitor reaches its absorption limit, the pulse intensity flowing through the first N-type field-effect transistor and the pulse intensity flowing through the second N-type field-effect transistor are greater than the intensity flowing into the integrated circuit. This allows the electrostatic discharge protection method to reduce the intensity of electrostatic pulses flowing into the integrated circuit, thereby suppressing electrostatic damage to the integrated circuit to a certain extent and helping to ensure the reliability of the integrated circuit.

[0078] It should be noted that GGNMOS is a MOS device frequently used in electrostatic discharge protection circuits, and its working principle is well known to those skilled in the art. Therefore, the specific working principle of GGNMOS will not be described in detail here.

[0079] When a negative electrostatic pulse flows in from the second input output port, the negative terminal of the third diode is connected to the second input output port. According to the forward conduction characteristic of the diode, the negative electrostatic pulse will flow through the third diode and exit from the ground output port. The first resistor is connected to the second input output port, and the first input output port is connected to the second input output port through the first resistor. Furthermore, the first input output port is connected to the input port of the integrated circuit. Therefore, the negative electrostatic pulse will also flow through the first resistor and then into the integrated circuit. Simultaneously, the drain of the second N-type field-effect transistor is connected to the first terminal of the first resistor, and the negative electrostatic pulse will also flow through the drain of the second N-type field-effect transistor. It is known that when the drain of an N-type field-effect transistor (FET) is connected to a negative voltage, the PN junction of the N-type FET conducts, acting as a diode. In this embodiment, the drain of the second N-type FET is connected to the first terminal of the first resistor, and the source is connected to the ground terminal. Therefore, the second N-type FET functions as a diode with its negative terminal connected to the first terminal of the first resistor and its positive terminal connected to the ground terminal, allowing the negative electrostatic pulse to flow through it. Given that the resistance of the integrated circuit is relatively large, exceeding the resistance of the third diode and the second N-type FET, the intensity of the negative electrostatic pulse flowing through the third diode and the second N-type FET after entering from the second input terminal is greater than the intensity flowing into the integrated circuit. This causes most of the negative electrostatic pulse to flow out through the electrostatic protection circuit, thereby reducing the intensity of the electrostatic pulse flowing into the integrated circuit and suppressing electrostatic damage to the integrated circuit to a certain extent, thus helping to ensure the reliability of the integrated circuit.

[0080] Furthermore, when an electrostatic pulse exists inside the integrated circuit and acts on its input port, if the pulse is positive, since the input port is connected to the first input output port, part of the positive pulse remains inside the integrated circuit, while the other part flows into the electrostatic protection circuit through the first input output port. When the pulse intensity flowing into the integrated circuit is low and cannot turn on the second N-type field-effect transistor, after a portion of the positive pulse flows into the electrostatic protection circuit through the first input output port, it is preferentially absorbed by the first capacitor after flowing into the electrostatic protection circuit, because the first end of the first resistor is connected to the first input output port, the second end is connected to the positive terminal of the second diode, and the negative terminal of the second diode is connected to the first end of the first capacitor through the first end of the second capacitor and the drain of the first N-type field-effect transistor. This suppresses the flow of the electrostatic pulse into the integrated circuit, thereby preventing electrostatic damage to the integrated circuit. Furthermore, since the negative terminal of the second diode is connected to the first terminal of the first capacitor in sequence through the first terminal of the second capacitor and the drain of the first N-type field-effect transistor, the electrostatic pulse will still flow through the first N-type field-effect transistor and exit from the ground terminal after the first capacitor reaches its absorption limit. It is known that the resistance of the integrated circuit is greater than the resistance of the first N-type field-effect transistor, thus the pulse intensity flowing through the first N-type field-effect transistor is greater than the pulse intensity remaining inside the integrated circuit. This allows the electrostatic protection method to reduce the pulse intensity remaining inside the electrostatic circuit, helping to suppress electrostatic damage to the integrated circuit and ensuring its reliability. It should be noted that the principle of the positive electrostatic pulse flowing through the first N-type field-effect transistor is the same as the principle of the positive electrostatic pulse flowing through the first N-type field-effect transistor when it enters from the second power supply terminal, and will not be repeated here.

[0081] If the electrostatic pulse is negative, similarly, part of it remains inside the integrated circuit, and part flows into the electrostatic discharge (ESD) protection circuit through the first input output port. After flowing into the ESD protection circuit, it flows through the drain of the second N-type field-effect transistor (FET). It is known that at this time, the second N-type FET is equivalent to a diode whose negative terminal is connected to the first end of the first resistor and whose positive terminal is connected to the ground output port. Since the first end of the first resistor is connected to the first input output port, the second N-type FET is equivalent to a diode whose negative terminal is connected to the first input output port and whose positive terminal is connected to the ground output port. Therefore, after the negative ESD pulse flows into the ESD protection circuit, it will flow through the second N-type FET and exit from the ground output port. Since the second end of the first resistor is connected to the negative terminal of the third diode, after the negative ESD pulse flows into the ESD protection circuit, it will also flow through the third diode and exit from the ground output port. Because the integrated circuit has a large resistance, greater than the resistance of the second N-type field-effect transistor and greater than the resistance of the first resistor, and because the diode has a small resistance, the integrated circuit has a greater resistance than the path formed by the first resistor and the third diode. This results in the intensity of the electrostatic pulse flowing through the second N-type field-effect transistor and through the path formed by the first resistor and the third diode being greater than the intensity remaining inside the integrated circuit. As a result, the electrostatic protection method can reduce the pulse intensity remaining inside the integrated circuit, suppressing electrostatic damage to the integrated circuit to a certain extent and helping to ensure the reliability of the integrated circuit.

[0082] Based on the above embodiments, in one embodiment of this application, the following continues... Figure 2 As shown, the integrated circuit also includes an output port 03, and the electrostatic discharge protection circuit also includes: an output port, a fourth diode 41, and a fifth diode 42;

[0083] The output ports include a first output port 411 and a second output port 412. The second output port 412 is connected to the first output port 411 through the positive terminal of the fourth diode 41. That is, the positive terminal of the fourth diode 41 is connected to both the first output port 411 and the second output port 412. The negative terminal of the fourth diode 41 is connected to the first power output port 111. Since the first power output port 111 is connected to the first terminal of the first capacitor 11, the drain of the first N-type field-effect transistor 14, and the first terminal of the second capacitor 13 in sequence, the negative terminal of the fourth diode 41 is connected to the first power output port 111, the first terminal of the first capacitor 11, the drain of the first N-type field-effect transistor 14, and the first terminal of the second capacitor 13 in sequence. The negative terminal of the fifth diode 42 is connected to the positive terminal of the fourth diode 41, and the positive terminal is connected to the ground output port. Since the positive terminal of the fourth diode is connected to both the first output port and the second output port, and the negative terminal of the fifth diode is connected to the positive terminal of the fourth diode, the negative terminal of the fifth diode is connected to both the first output port and the second output port; the method further includes:

[0084] S7: Connect the first output port to the output port of the integrated circuit so that the electrostatic discharge protection circuit can provide electrostatic discharge protection for the integrated circuit.

[0085] It should be noted that the first output port is connected to the output port of the integrated circuit by a wire bonding method, and the first output port is connected to the positive terminal of the fourth diode by a metal wire. Therefore, even if the first output port is connected to the output port of the integrated circuit and is also connected to the positive terminal of the fourth diode, the output port of the integrated circuit will not be directly connected to the positive terminal of the fourth diode.

[0086] It should also be noted that, in the embodiments of this application, the output port includes two output ports: a first output port and a second output port, and the integrated circuit includes one output port. However, this application does not limit this. In other embodiments of this application, the electrostatic protection circuit may also include one output port or at least three output ports, and the integrated circuit may include at least two output ports, depending on the specific circumstances.

[0087] Specifically, in this embodiment, the first output port of the electrostatic discharge protection circuit is connected to the output port of the integrated circuit, thereby connecting the electrostatic discharge protection circuit to the integrated circuit. This allows the electrostatic discharge protection circuit to provide electrostatic protection to the integrated circuit, suppressing electrostatic pulses from flowing into the integrated circuit through its output port, thus helping to prevent electrostatic damage to the integrated circuit and contributing to its development.

[0088] Based on the above embodiments, in this embodiment, when a positive electrostatic pulse flows in from the second output port, due to the forward conduction characteristic of the diode, the positive electrostatic pulse will not flow through the fifth diode, but will flow through the fourth diode. After flowing through the fourth diode, it will be absorbed by the first capacitor to suppress the electrostatic pulse from flowing into the integrated circuit, thereby suppressing electrostatic damage to the integrated circuit. When the first capacitor reaches its absorption limit, since the negative terminal of the fourth diode is sequentially connected to the first terminal of the second capacitor through the first power output port, the first terminal of the first capacitor, and the drain of the first N-type field-effect transistor, the positive electrostatic pulse will flow through the first N-type field-effect transistor, exit from the ground terminal, and also flow into the integrated circuit through the first power output port. Furthermore, since the second output port is connected to the first output port through the positive terminal of the fourth diode, and the first output port is connected to the output port of the integrated circuit, the positive electrostatic pulse flows in from the second output port, and after the first capacitor reaches its absorption limit, it will also flow into the integrated circuit through the first output port. It is known that the resistance of the integrated circuit is greater than the resistance of the first N-type field-effect transistor. Therefore, the positive electrostatic pulse flows in from the second output port. After the first capacitor reaches its absorption limit, the pulse intensity flowing through the first N-type field-effect transistor is greater than the pulse intensity flowing into the integrated circuit through the first output port and also greater than the pulse intensity flowing into the integrated circuit through the first power output port. This means that after the first capacitor reaches its absorption limit, most of the remaining intensity of the electrostatic pulse flows out through the electrostatic protection circuit. The remaining portion of the electrostatic pulse is the portion of the electrostatic pulse flowing into the second output port after deducting the portion absorbed by the first capacitor. This allows the electrostatic protection method to reduce the intensity of the electrostatic pulse flowing into the integrated circuit, suppressing electrostatic damage to the integrated circuit to a certain extent and ensuring its reliability. It should be noted that the principle of the positive electrostatic pulse flowing through the first N-type field-effect transistor is the same as the principle of the positive electrostatic pulse flowing through the first N-type field-effect transistor when flowing into the second power output port, and will not be repeated here.

[0089] When a negative electrostatic pulse flows in from the second input port, according to the forward conduction characteristic of the diode, the negative electrostatic pulse will flow through the fifth diode and out from the ground port. Since the negative terminal of the fifth diode is connected to both the first and second output ports, the negative and positive electrostatic pulses flowing in from the second output port will also flow into the integrated circuit through the first output port. Given that the resistance of the integrated circuit is greater than the resistance of the fifth diode, the intensity of the negative and positive electrostatic pulses flowing through the fifth diode after entering from the second output port is greater than the intensity flowing into the integrated circuit. This causes most of the negative electrostatic pulse to flow out through the electrostatic protection circuit, enabling the electrostatic protection method to reduce the pulse intensity flowing into the integrated circuit, suppress electrostatic damage to the integrated circuit, and help ensure the reliability of the integrated circuit.

[0090] Furthermore, when an electrostatic pulse (ESP) exists inside the integrated circuit and acts on its output port, since the output port is connected to the first output port, if the ESP is positive, a portion of it remains inside the integrated circuit, while a portion flows into the ESP protection circuit through the first output port. Given that the anode of the fourth diode is connected to the first output port, this portion of the positive ESP, after flowing into the ESP protection circuit through the first output port, will pass through the fourth diode and be preferentially absorbed by the first capacitor. This reduces the intensity of the ESP inside the integrated circuit, helping to suppress ESP damage. After the first capacitor reaches its absorption limit, the pulse flows through the first N-type field-effect transistor and exits from the ground port. Since the resistance of the integrated circuit is greater than the resistance of the first N-type field-effect transistor, the intensity of the pulse flowing through the first N-type field-effect transistor after the first capacitor reaches its absorption limit is greater than the intensity remaining inside the integrated circuit. This allows the ESP protection method to reduce the intensity of the ESP inside the integrated circuit, thereby suppressing ESP damage to a certain extent and helping to ensure the reliability of the integrated circuit. It should be noted that the principle by which the positive electrostatic pulse flows through the first N-type field-effect transistor is the same as the principle by which the positive electrostatic pulse flows through the first N-type field-effect transistor when it enters from the second power supply output port, and will not be repeated here.

[0091] If the electrostatic pulse is a negative electrostatic pulse, since the negative terminal of the fifth diode is connected to the first output port, a portion of the negative electrostatic pulse flows into the electrostatic protection circuit and then through the fifth diode before exiting from the ground port. Given that the resistance of the integrated circuit is greater than that of the fifth diode, the pulse intensity flowing through the fifth diode after the negative electrostatic pulse enters the electrostatic protection circuit is greater than the pulse intensity inside the integrated circuit. This allows the electrostatic protection method to reduce the electrostatic pulse intensity inside the integrated circuit, thereby suppressing electrostatic damage to the integrated circuit to a certain extent and helping to ensure the reliability of the integrated circuit.

[0092] Based on the above embodiments, in one embodiment of this application, when an electrostatic pulse flows in from the second power supply output port, the second input output port, or the second output output port, the first capacitor absorbs the electrostatic pulse, limiting the voltage across the first capacitor to a low level, making the voltage across the first capacitor lower than the breakdown voltage of each field-effect transistor in the electrostatic protection circuit. Since diodes are known to have low operating voltages, even when the voltage across the first capacitor is low, it will still be higher than the operating voltage of each diode in the electrostatic protection circuit. Furthermore, since the first terminal of the first capacitor is connected to the power supply output port and the second terminal is grounded, the voltage across the first capacitor is the same as the voltage between the power supply output port and the ground output port of the electrostatic discharge protection circuit. Therefore, when the voltage across the first capacitor is higher than the operating voltage of each diode in the electrostatic discharge protection circuit and lower than the breakdown voltage of each field-effect transistor in the electrostatic discharge protection circuit, all diodes in the electrostatic discharge protection circuit are in a working state, and all field-effect transistors in the electrostatic discharge protection circuit are in a non-breakdown state, enabling them to work normally. This is beneficial for the electrostatic discharge protection of the integrated circuit and can effectively suppress electrostatic damage to the integrated circuit.

[0093] Based on the above embodiments, in one embodiment of this application, the following continues... Figure 2 As shown, the electrostatic discharge protection circuit further includes a second resistor 15; the method further includes:

[0094] S8: Connect the first end of the second resistor 15 to the first end of the first capacitor 11, and connect the second end to the second end of the first capacitor 11. That is, connect the second resistor 15 in parallel with the first capacitor, so that the second resistor 15 can release the charge accumulated in the first capacitor 11 in time, and prevent the first capacitor 11 from storing too much charge, which would cause the voltage across the first capacitor 11 to be too high and affect the electrostatic protection circuit for the integrated circuit.

[0095] Furthermore, when there are residual positive electrostatic pulses at the power output port and residual negative electrostatic pulses at the ground output port, the second resistor can also be used to discharge the residual positive and negative electrostatic pulses at the power output port and the ground output port, thus preventing the first capacitor from being subjected to multiple electrostatic pulses and preventing the voltage of the first capacitor from becoming too high after being subjected to multiple electrostatic pulses. This helps to ensure the electrostatic protection circuit provides electrostatic protection for the integrated circuit. It should be noted that when the electrostatic protection circuit includes at least two first capacitors, the electrostatic protection circuit also includes at least two second resistors, and the at least two second resistors are connected in parallel with the at least two first capacitors.

[0096] Optionally, in one embodiment of this application, the resistance value of the second resistor is in the range of 10KΩ to 100MΩ, including the endpoint value, but this embodiment of the application does not limit this, and it depends on the specific situation.

[0097] It should be noted that when an electrostatic pulse (ESP) exists inside the integrated circuit, after flowing through the first input port, first output port, or first power output port, it may flow through other ports of the ESP protection circuit. However, due to the low resistance and strong shunt capability of the ESP protection circuit, the intensity of the ESP flowing through these other ports will also be low. Therefore, even if the ESP flows through other ports of the ESP protection circuit, it will not affect the operation of those other ports. Similarly, when an ESP flows into the second input port, second output port, or second power output port of the ESP protection circuit, it may also flow through other ports. Likewise, due to the low resistance and strong shunt capability of the ESP protection circuit, the intensity of the ESP flowing through these other ports will also be low. Therefore, even if the ESP flows through other ports of the ESP protection circuit, it will not affect the operation of those other ports.

[0098] It should also be noted that, in this embodiment of the application, in order not to affect the normal operation of the integrated circuit, the turn-on voltage of the field-effect transistor in the electrostatic discharge (ESD) protection circuit is about 20% higher than the turn-on voltage of the integrated circuit. This ensures that when the integrated circuit is turned on, the field-effect transistor in the ESD protection circuit is in a turned-off state. This prevents the power signal of the integrated circuit from flowing through the second power output port and then exiting from the ground terminal of the ESD protection circuit, thus preventing the integrated circuit from malfunctioning. Furthermore, according to... Figure 1As can be seen, each diode in the electrostatic discharge protection circuit is in reverse connection with the second power output port. This ensures that after the power signal of the integrated circuit flows through the second power output port, the power signal will not flow through the diodes and out of the ground terminal, thus guaranteeing the normal operation of the integrated circuit.

[0099] Optionally, in one embodiment of this application, the first diode is a gate-controlled diode, the second diode is a gate-controlled diode, the third diode is a gate-controlled diode, the fourth diode is a gate-controlled diode, and the fifth diode is a gate-controlled diode. However, this application does not limit this, and it depends on the specific circumstances. In other embodiments of this application, the first diode, the second diode, the third diode, the fourth diode, and the fifth diode can also be commonly used ordinary diodes, depending on the specific circumstances.

[0100] Based on the above embodiments, in one embodiment of this application, the following continues... Figure 1 As shown, the electrostatic discharge protection circuit further includes: a third resistor 50; the method further includes:

[0101] S9: The first end of the third resistor 50 is connected to the gate of the first N-type field-effect transistor 14, and the second end is connected to the ground terminal 20. Since the gate of the first N-type field-effect transistor 14 is connected to the second terminal of the second capacitor 13, the second end of the third resistor 50 is connected to the second terminal of the second capacitor 13 through the gate of the first N-type field-effect transistor 14. After the electrostatic pulse couples with the capacitor, the capacitor will discharge to the gate of the first N-type field-effect transistor, accumulating charge at the gate of the first N-type field-effect transistor, triggering the first N-type field-effect transistor to turn on. However, if too much charge accumulates at the gate of the first N-type field-effect transistor, it will cause damage to the first N-type field-effect transistor. The addition of the third resistor can share some of the electrical energy released by the capacitor, which helps to prevent too much charge from accumulating at the gate of the first N-type field-effect transistor and damaging the first N-type field-effect transistor. This helps to ensure the reliability of the electrostatic protection circuit, so that the electrostatic protection method can reliably reduce the possibility of electrostatic damage to the integrated circuit and ensure the reliability of the integrated circuit.

[0102] Based on the above embodiments, in one embodiment of this application, the following continues... Figure 1 As shown, the integrated circuit further includes a ground port 04, and the ground output port 20 includes a first ground output port 21 and a second ground output port 22; the method further includes:

[0103] S10: Connect the first ground output port 21 to the ground port 04 of the integrated circuit, connect the second ground output port 22 to the first ground output port 21, and ground the second ground output port 22, thereby grounding the ground port 04 of the integrated circuit, enabling the electrostatic discharge circuit to discharge electrostatic pulses from the second ground output port 22. The first ground output port and the ground port of the integrated circuit are connected by a wire bonding, and the first ground output port and the second ground output port are connected by a metal wiring. It should be noted that in this embodiment, the ground output port includes two ground output ports (first ground output port and second ground output port), and the integrated circuit includes one ground port. However, this application is not limited to this. In other embodiments of this application, the electrostatic discharge circuit may also include one ground output port or at least three ground output ports, and the integrated circuit may include at least two ground ports, depending on the specific circumstances.

[0104] It should be noted that, continuing as Figure 1 As shown, the second power output port 112 of the electrostatic discharge (ESD) protection circuit is connected to an external power supply 61, the second input output port 312 is connected to an external input port 62, the second output output port 412 is connected to an external output port 63, and the second ground output port 22 is grounded to ground 64. This ensures that the integrated circuit can be connected to the outside world while being protected by the ESD protection circuit, guaranteeing the normal operation of the integrated circuit. Furthermore, the various output ports of the ESD protection circuit are connected to the various ports of the integrated circuit and the various external ports via wire bonding, but this application does not limit this connection; it depends on the specific circumstances.

[0105] In summary, this application provides a low-cost electrostatic discharge (ESD) protection method, comprising: providing a first chip and distributing an integrated circuit on the first chip, the integrated circuit including a power port; providing a second chip and distributing an ESD protection circuit on the second chip, the ESD protection circuit including a power output port, a first capacitor, and a ground output port, wherein the power output port includes a first power output port and a second power output port, the first power output port being connected to the power port of the integrated circuit, enabling the ESD protection circuit to be connected to the integrated circuit, so that when an ESD pulse flows in from the second power output port, the first capacitor absorbs the ESD pulse, suppressing the ESD pulse from flowing into the integrated circuit, thereby enabling the ESD protection method to protect the integrated circuit from ESD, helping to ensure the reliability of the integrated circuit, and also reducing the cost of using the ESD protection method to protect the integrated circuit. Furthermore, the ESD protection method distributes the integrated circuit and the ESD protection circuit on different chips, thereby avoiding the problem that the substrate material of the chip on which the integrated circuit is located cannot be used to design ESD protection for the integrated circuit, enabling ESD protection for ESD-sensitive novel integrated circuits, thus contributing to the reliability of novel material integrated circuits and promoting the development of novel material integrated circuits.

[0106] The various parts of this manual are described in a combination of parallel and progressive methods. Each part focuses on the differences between the other parts, and the same or similar parts can be referred to each other.

[0107] The features described above regarding the disclosed embodiments can be substituted or combined with each other to enable those skilled in the art to implement or use this application. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein can be implemented in other embodiments without departing from the spirit or scope of this application. Therefore, this application is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A low-cost electrostatic discharge protection method, characterized in that, include: A first chip is provided, and an integrated circuit is disposed on the first chip, wherein the integrated circuit includes a power port; A second chip is provided, on which the electrostatic protection circuit is laid. The first chip is a carbon-based chip, and the second chip is a silicon-based chip. The electrostatic discharge protection circuit includes: a power output port, a first capacitor, a second resistor, and a ground output port. The power output port includes a first power output port and a second power output port. The second power output port is connected to the first power output port through a first terminal of the first capacitor, and the second terminal of the first capacitor is connected to the ground output port. The first terminal of the second resistor is connected to the first terminal of the first capacitor, and the second terminal is connected to the second terminal of the first resistor. The first power output port is connected to the power port of the integrated circuit so that the electrostatic discharge protection circuit can provide electrostatic protection for the integrated circuit.

2. The electrostatic protection method according to claim 1, characterized in that, The capacitance value of the first capacitor ranges from 0.05uF to 50uF, including the terminal values.

3. The electrostatic protection method according to claim 1, characterized in that, The electrostatic discharge protection circuit further includes: a second capacitor and a first N-type field-effect transistor disposed between the second power output port and the first terminal of the first capacitor, wherein the first terminal of the second capacitor is connected to the drain of the first N-type field-effect transistor, the gate of the first N-type field-effect transistor is connected to the second terminal of the second capacitor, the source is connected to the ground output port, and the ground output port is grounded; the method further includes: The second power output port is connected sequentially to the first terminal of the second capacitor, the drain of the first N-type field-effect transistor, and the first terminal of the first capacitor. The electrostatic discharge protection circuit further includes a first diode, and the method further includes: Connect the negative terminal of the first diode to the first power supply output port, and connect the positive terminal to the ground output port.

4. The electrostatic protection method according to claim 3, characterized in that, The integrated circuit further includes an input port, and the electrostatic discharge protection circuit further includes an input output port, a second diode, and a third diode. The input output port includes a first input output port and a second input output port. The second input output port is connected to the first input output port through the positive terminal of the second diode. The negative terminal of the second diode is connected to the first terminal of the second capacitor. The negative terminal of the third diode is connected to the positive terminal of the second diode, and the positive terminal is connected to the ground output port. The electrostatic discharge protection circuit further includes: a first resistor and a second N-type field-effect transistor, wherein the first end of the first resistor is connected to the first input output port, the second end is connected to the positive terminal of the second diode, the drain of the second N-type field-effect transistor is connected to the first end of the first resistor, and the source is connected to the gate of the second N-type field-effect transistor and the ground output port respectively. The method also includes: The first input output port is connected to the input port of the integrated circuit so that the electrostatic discharge protection circuit provides electrostatic protection for the integrated circuit.

5. The electrostatic protection method according to claim 4, characterized in that, The integrated circuit further includes an output port, and the electrostatic discharge protection circuit further includes: an output terminal, a fourth diode, and a fifth diode, wherein the output terminal includes a first output terminal and a second output terminal, the second output terminal is connected to the first output terminal through the positive terminal of the fourth diode, the negative terminal of the fourth diode is connected to the first power supply terminal, the negative terminal of the fifth diode is connected to the positive terminal of the fourth diode, and the positive terminal is connected to the ground terminal; the method further includes: Connect the first output port to the output port of the integrated circuit so that the electrostatic discharge protection circuit can provide electrostatic discharge protection for the integrated circuit.

6. The electrostatic protection method according to claim 5, characterized in that, The first diode is a gate-controlled diode, the second diode is a gate-controlled diode, the third diode is a gate-controlled diode, the fourth diode is a gate-controlled diode, and the fifth diode is a gate-controlled diode.

7. The electrostatic protection method according to claim 3, characterized in that, The electrostatic discharge protection circuit further includes a third resistor; the method further includes: The first end of the third resistor is connected to the gate of the first N-type field-effect transistor, and the second end is connected to the ground terminal.

8. The electrostatic protection method according to claim 1, characterized in that, The integrated circuit further includes a ground port, wherein the ground output port includes a first ground output port and a second ground output port; the method further includes: Connect the first ground output port to the ground port of the integrated circuit, connect the second ground output port to the first ground output port, and ground the second ground output port.

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