Memory device with backside bond pads under memory array

Abstract

This application relates to memory devices with backside bond pads under memory arrays. An apparatus is provided that includes a substrate having a front side and a back side opposite the front side; control circuitry disposed over the front side of the substrate; a memory array disposed over and electrically coupled to the control circuitry; a through-silicon via (TSV) disposed under the memory array, the TSV extending through the substrate from the control circuitry to the back side of the substrate; and a bond pad disposed on the back side of the substrate and electrically coupled to the control circuitry via the TSV.

Description

Technical Field

[0001] This disclosure generally relates to memory devices, and more specifically, to memory devices having a rear-side bonding pad beneath a memory array. Background Technology

[0002] Memory devices, such as NAND devices, include arrays of memory cells and control circuitry (e.g., implemented as complementary metal-oxide-semiconductor (CMOS) circuitry) formed on an active surface of a semiconductor (e.g., silicon) substrate. Such memory devices may include bonding pads through which control and data signals are provided to and from the memory device. Summary of the Invention

[0003] In one aspect, this application provides an apparatus comprising: a substrate having a front side and a rear side opposite to the front side; a control circuit system disposed above the front side of the substrate; a memory array disposed above and electrically coupled to the control circuit system; a through-silicon via (TSV) disposed below the memory array, the TSV extending through the substrate from the control circuit system to the rear side of the substrate; and a bonding pad disposed on the rear side of the substrate and electrically coupled to the control circuit system via the TSV.

[0004] In another aspect, this application provides a method for manufacturing a memory die, the method comprising: forming a through-silicon via (TSV) in a substrate having a front side and a rear side opposite to the front side; forming a control circuit system on the front side of the substrate; forming a memory array over the control circuit system, wherein the memory array is electrically coupled to the control circuit system; and forming a bonding pad on the rear side of the substrate, wherein the bonding pad is electrically coupled to the control circuit system via the TSV.

[0005] In another aspect, this application provides an apparatus comprising: a bonding pad formed on a rear side of a substrate, wherein the substrate has a front side opposite to the rear side; a complementary metal-oxide-semiconductor (CMOS) circuit system disposed above the front side of the substrate and below a memory array; wherein the bonding pad is electrically coupled to the CMOS circuit system via vias that pass through the substrate to the CMOS circuit system but do not pass through a plane containing the memory array. Attached Figure Description

[0006] This disclosure will be more fully understood from the detailed descriptions given below and from the accompanying drawings of various embodiments thereof.

[0007] Figures 1A and 1B are block diagrams illustrating a memory device in which bonding pads are located outside the memory array of the memory die and on the front side of the substrate of the memory array of the memory die.

[0008] Figures 2A and 2B are block diagrams showing a memory device on the front side of a substrate where bonding pads are located above a memory array of memory dies.

[0009] Figure 3A , 3B Figures 3 and 3C are block diagrams illustrating a memory device according to some embodiments of the present disclosure, wherein bonding pads are located on the rear side of the substrate and connected to a control circuitry system of the memory die via TSVs.

[0010] Figure 4 It is according to some embodiments of this disclosure for use Figure 3A A flowchart of the manufacturing process of a memory die.

[0011] Figures 5A-5E This illustrates some embodiments according to the present disclosure. Figure 4 A conceptual diagram of the manufacturing process.

[0012] Figure 6 It is according to some embodiments of this disclosure for use Figure 3A A flowchart of another manufacturing process for memory dies.

[0013] Figures 7A-7E It is shown Figure 6 A conceptual diagram of the manufacturing process. Detailed Implementation

[0014] Memory devices may comprise different combinations and types of non-volatile memory components and / or volatile memory components. An example of a non-volatile memory component is a NAND flash memory. A memory component may comprise one or more arrays of memory cells, such as single-level cells (SLC) or multi-level cells (MLC) (e.g., three-level cells (TLC) or four-level cells (QCC)). In some embodiments, a particular memory component may comprise both an SLC portion and an MLC portion of memory cells. Each memory cell may store one or more data bits (e.g., a data block). Memory devices may further comprise a control circuitry, such as a CMOS circuitry, that provides control and data signals to the memory array and interfaces the memory device with external components. An example control circuitry is an under-array CMOS (CUA) design, where the CMOS is located between the memory array and the substrate. In some cases, the memory device may be a memory die, such as a device with a control circuitry and a memory array typically fabricated on a portion of a silicon or other semiconductor substrate along with many other devices. For example, multiple memory devices can be formed on a single wafer, each memory device having a control circuit system and a memory array, and a single-cutter (“cutting”) process (e.g., by scribing and breaking, mechanical sawing, laser cutting, etc.) can divide the wafer to separate the individual memory devices.

[0015] Various aspects of this disclosure relate to memory dies with reduced coverage area and low-stress pad connections. This can be achieved in the memory die by positioning the pads of each memory die on the back side of the silicon substrate of the memory die and electrically connecting the pads to a CMOS control circuitry system located below the memory array via through-silicon vias (TSVs). This type of memory die assembly does not require additional wafer space for pads outside the coverage area of ​​the array and prevents stress on the memory array when the pads are located above or near the front side of the device of the memory array.

[0016] This contrasts with conventional methods, where bonding pads are located on the front side of the memory device, or near or above the memory array. Figures 1A and 1B are block diagrams illustrating a prior art memory die 100, wherein bonding pads are located outside the memory array 106 of the memory die 100 and on the front side 116 of the substrate 102 of the memory array 106 of the memory die 100. The side view of the memory die 100 in Figure 1A shows the substrate 102, the control circuitry system 104 on the front side 116 of the substrate 102, the memory array 106 above the control circuitry system 104, and the bonding pads 108 connected to the control circuitry system 104 via connectors 110. The bonding pads 108 are positioned on the front side 116 of the substrate 102, occupying a region 112 of the substrate 102. The top view of the memory die 100 in Figure 1B shows the front side 116 of the substrate 102, where the region 112 of the substrate 102 is occupied by the bonding pads 108. Figures 2A and 2B are block diagrams illustrating another prior art memory die 200, wherein bonding pads 208 are located on the front side 216 of a substrate 202 above a memory array 206 of the memory die 200. A side view of the memory die 200 in Figure 2A shows the substrate 202, the control circuitry 204, the memory array 206 above the control circuitry 204, and the bonding pads 208 connected to the control circuitry 204 via connectors 210. The bonding pads 208 are positioned above the memory array 206 on the front side 216 of the substrate 202, which can cause stress on the memory array 206 at point 214 (e.g., when connectors are formed between external components and bonding pads 208). A top view of the memory die 200 in Figure 2B shows the front side 216 of the substrate 202 with a region 212 that would be occupied by bonding pads 108, rather than bonding pads 208, in the configuration of Figures 1A and 1B. Alternatively, the bonding pad 208 is positioned above the memory array 206, thereby exposing the memory array 206 to potential stress and damage.

[0017] Figure 3A , 3B 3C is a block diagram showing a memory die 300 having a bonding pad 308 on the rear side 318 of a substrate 302. Figure 3A The side view of the memory die 300 shows a substrate 302 (with a front side 316 and a rear side 318), a control circuit system 304, a memory array 306 above the control circuit system 304, and a bonding pad 308 on the rear side 318 of the substrate 302.

[0018] In some embodiments, the control circuitry 304 may be a complementary metal-oxide-semiconductor (“CMOS”) circuitry. It will be apparent to those skilled in the art that the control circuitry 304 may receive instructions from a host system and may communicate with the memory array 306, for example, transferring (e.g., writing or erasing) commands and data to or from one or more memory cells, planes, sub-blocks, blocks, or pages of the memory array. Furthermore, the control circuitry 304 may include a memory control unit, circuitry, firmware, integrated circuit, or other components configured to control access across the memory array 306 and provide a translation layer between the host and the memory die 300. In some embodiments, the control circuitry 304 may include row decoders and column decoders to decode address signals. Address signals are received and decoded to access the memory array 306. Input / output (I / O) signals (e.g., commands, addresses, or data) may be provided to the control circuitry 304 via TSV 314 and connector 310. Similarly, control circuitry 304 can output data and status information from memory die 300 via TSV 314 and connector 310. Control circuitry 304 may include address registers used in conjunction with row and column decoders to latch address signals before decoding. Control circuitry 304 may include command registers and control logic to latch incoming commands and control the operation of memory die 300 (e.g., controlling access to memory array 306 in response to commands and generating status information for an external processor). Control circuitry 304 may also include (or communicate with) a cache register that latches incoming or outgoing data to temporarily store data while memory array 306 is busy writing or reading other data. Control circuitry 304 may also include a data register. During write operations, data can be transferred from cache registers to data registers to memory array 306; new data can be latched in cache registers. During a read operation, the control circuitry 304 can transfer data through a cache register to output to an external processor; it also allows new data to be transferred from a data register to a cache register.

[0019] Memory array 306 may include various memory configurations, such as 2D or 3D memory arrays. It will be apparent to those skilled in the art that memory array 306 may include memory cells arranged in rows and columns along access lines (e.g., word lines) and data lines (e.g., bit lines). Access lines and data lines are used to transfer information to and from memory cells. Row decoders and column decoders decode address signals on address lines to determine which memory cell is to be accessed. Sensing amplifier circuitry is used to determine the value of the information read from the memory cell. A two-dimensional (2D) memory array is a structure arranged on the surface of a semiconductor substrate. In other embodiments, a three-dimensional (3D) memory array may be employed, which may include strings of memory cells extending vertically through multiple vertically spaced layers containing corresponding word lines. A semiconductor structure (e.g., a polysilicon structure) may extend adjacent to the strings of memory cells to form channels for the cells of the strings. In some cases, the polysilicon structure may be in the form of vertically extending pillars. In other cases, the strings may be “folded” and thus arranged relative to U-shaped pillars. In other cases, multiple vertical structures can be stacked on top of each other to form a stacked array of memory cell strings.

[0020] The bonding pad 308 is connected to the control circuitry 304 of the memory die 300 via TSV 314 and connector 310. Figure 3B A top view of the memory die 300 shows the front side 316 of the substrate 302 with region 312, which will be occupied by bonding pad 108 instead of bonding pad 308 in the configurations of Figures 1A and 1B. This provides the memory die 300 with a smaller overall die coverage area than the memory die 100. Therefore, in the memory die 300, the memory array 306 extends to each edge of the substrate 302 (or within a threshold distance of each edge of the substrate 302) such that there is not enough space between the memory array 306 and the edge of the substrate 302 to form bonding pads on its front side 316 without overlapping the memory array 306. Figure 3C As shown in the bottom view of the memory die 300, bonding pads 308 are located on the rear side 318 of the substrate 302, thereby allowing the substrate 302 to protect the memory array 306 and control circuitry system 304 from potential stress and damage (e.g., associated with forming interconnects or bonding operations that bring the bonding pads into contact with the bonding pads 308). Furthermore, there are no bonding pads on the front side of the memory die 300. Compared to the memory die 200, this provides a more stable and durable memory die 300.

[0021] As will be apparent to those skilled in the art, although the memory device is shown in this example embodiment using a single bonding pad connected to the control circuitry system via a single TSV, in other embodiments of this disclosure, the memory device may include multiple bonding pads, each connected by a corresponding one of a plurality of TSVs.

[0022] Figure 4 This is a flowchart illustrating an example of a first manufacturing process 400 for a memory die 300 according to some embodiments of the present invention. Although shown in a specific order or sequence, the order of processes 400 may be modified unless otherwise specified. Therefore, it should be understood that the illustrated embodiments are merely examples, and the illustrated processes 400 may be performed in different orders, and some processes 400 may be performed in parallel. Furthermore, one or more processes 400 may be omitted in various embodiments. Therefore, not all processes 400 are required in every embodiment. Other process flows are possible. Figures 5A-5E It is shown Figure 4 The first manufacturing process 400 is shown in the concept diagram 500. Although Figures 5A-5E The formation of a single memory device is shown, but it can be understood that in some cases, many such memory devices can be formed on a single wafer before the wafer is diced to form individual memory dies.

[0023] At block 402, process 400 may form a TSV (e.g., TSV 314) in substrate 506 (e.g., a semiconductor substrate such as silicon, silicon-germanium, etc.). This TSV may be positioned to connect to a control circuitry system of the memory die. In various embodiments, cavities in the substrate may be created using etching or other methods that form or remove semiconductor material, wherein process 400 will form the TSV. Figure 5A As shown, cavity 502 is formed by etching the front side 504 of the substrate. TSV 508 can be formed in cavity 502. At block 404, process 400 can form a control circuit system (e.g., CMOS control circuit system 304) on the front side of the substrate. Figure 5A As further shown, a control circuit system 510 is formed on the front side 504 of the substrate 506, thereby connecting the TSV 508 to the control circuit system 510.

[0024] At block 406, process 400 may form a memory array (e.g., memory array 306) on a memory die above the control circuitry system (e.g., on the substrate-opposite side of the control circuitry system). Figure 5BAs shown, the memory array 512 is formed on the side 514 of the control circuit system 510 opposite to the substrate 506. In some embodiments, forming the memory array may include forming a 3D NAND memory array. In some embodiments, as will be apparent to those skilled in the art, forming a 3D NAND memory array may include a stack of layers forming NAND memory cell structures.

[0025] At frame 408, process 400 attaches the carrier wafer to the side of the memory array opposite the control circuitry. For example... Figure 5B and 5C As indicated by arrow 516, process 400 may include flipping the memory device to mount it on carrier wafer 518, or otherwise adjusting or using alternative manufacturing machinery to operate on the rear side of the memory device. In other embodiments, carrier wafer 518 may be placed on top of memory array 512 without flipping the memory device or altering the manufacturing machinery. Figure 5C As shown, the carrier chip 518 is attached to the side 520 of the memory array 512 opposite to the control circuit system 510.

[0026] At box 410, process 400 exposes the TSV by planarizing the back side of substrate 506. Various processes can be used to remove portions of substrate 506, such as mechanical etching or chemical etching. Figure 5D As shown, the rear side 522 of substrate 506 is planarized to remove portion 524 (as shown). Figure 5D (Removed from the image). The width of portion 524 is sufficient to expose TSV 508 on the rear side 522 of substrate 506.

[0027] At frame 412, process 400 can form a bonding pad (e.g., bonding pad 308) on the rear side of substrate 506 via the exposed TSV. Figure 5E As shown, a bonding pad 526 may be formed on the rear side 522 of the substrate 506, thereby connecting the bonding pad 526 to the TSV 508 and extending through the TSV 508 to the control circuitry system 510. At block 414, process 400 may remove the carrier wafer from the memory device (e.g., by planarizing the carrier wafer from the memory device or removing the adhesive that attaches the carrier wafer to the memory device). Figure 5E As further shown, the carrier chip 518 has been removed from the memory device.

[0028] Figure 6This is a flowchart illustrating an example of a second manufacturing process 600 for a memory die 300 according to some embodiments of the present invention. Although shown in a specific order or sequence, the order of the processes 600 may be modified unless otherwise specified. Therefore, it should be understood that the illustrated embodiments are merely examples, and the illustrated processes 600 may be performed in different orders, and some processes 600 may be performed in parallel. Furthermore, one or more processes 600 may be omitted in various embodiments. Therefore, not all processes 600 are required in every embodiment. Other process flows are possible. Figures 7A-7E It is shown Figure 6 Conceptual diagram 700 for the second manufacturing process 600. Although Figures 7A-7E The formation of a single memory device is shown, but it can be understood that in some cases, many such memory devices can be formed on a single wafer before the wafer is diced to form individual memory dies.

[0029] At frame 602, process 600 may form a control circuit system (e.g., CMOS control circuit system 304) on the front side of the substrate. Figure 7A As shown, the control circuit system 710 is formed on the front side 704 of the substrate 706.

[0030] At block 604, process 600 may form a memory array (e.g., memory array 306) of the memory device above the control circuitry system (e.g., on the side of the control circuitry system opposite to the substrate). Figure 7B As shown, the memory array 712 is formed on the memory die on the side 714 of the control circuit system 710 opposite to the substrate 706.

[0031] At block 606, process 600 can attach a carrier wafer to a memory device on the side of the memory array opposite to the control circuitry system. For example... Figure 7B and 7C As indicated by arrow 716, process 600 may include flipping the memory device to mount it on carrier wafer 718, or otherwise adjusting or using alternative manufacturing machinery to operate on opposite sides of the memory device. In other embodiments, carrier wafer 718 may be placed on top of memory array 712 without flipping the memory device or altering the manufacturing machinery. Figure 7C As shown, the carrier chip 718 is attached to the side 720 of the memory array 712 opposite to the control circuit system 710.

[0032] At frame 608, process 600 can planarize the back side of the substrate to a specified thickness. Various processes can be used to remove portions of the substrate, such as mechanical etching or chemical etching. Figure 7DAs shown, the rear side 722 of the substrate 706 is planarized to remove a portion 724 (as shown). Figure 7D (The portion removed in the original text). The width of the removed portion 724 is sufficient to form a TSV through the remainder of the substrate 706.

[0033] At block 610, process 600 can form a cavity in the substrate. In various embodiments, etching or other methods that form or remove semiconductor material can be used to form the cavity in the substrate. Figure 7E As shown, cavity 702 is formed by etching the rear side 722 of substrate 706.

[0034] At frame 612, process 600 can form a TSV (e.g., TSV 314) through a cavity and form a bonding pad (e.g., bonding pad 308) on the TSV on the back side of the substrate. The TSV can be formed to connect to a control circuitry system of the memory die. Figure 7E As further shown, a TSV 708 may be formed in a cavity 702, and a bonding pad 726 may be formed on the rear side 722 of a substrate 706, thereby connecting the bonding pad 726 to a control circuit system 710 via the TSV 708.

[0035] At box 614, process 600 may remove the carrier wafer from the memory device, for example, by planarizing the carrier wafer from the memory device. Figure 7E As further shown, the carrier chip 718 has been planarized from the memory die (e.g. Figure 7E As shown, the carrier chip 718 has been removed.

[0036] In some implementations, multiple memory devices can be formed on a wafer using process 400 or process 600 before the wafer is diced to form multiple individual memory dies.

[0037] While this document describes non-volatile memory components such as NAND-type flash memory, memory components may be based on any other type of memory, such as volatile memory. In some embodiments, the memory component may be, but is not limited to, random access memory (RAM), read-only memory (ROM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), phase-change memory (PCM), magnetic random access memory (MRAM), NOR flash memory, electrically erasable programmable read-only memory (EEPROM), and cross-point arrays of non-volatile memory cells.

[0038] In the foregoing specification, embodiments of the present disclosure have been described with reference to specific examples. It will be apparent that various modifications can be made to the present disclosure without departing from the broader spirit and scope of the embodiments set forth in the appended claims. Therefore, the specification and drawings should be viewed in an illustrative rather than restrictive sense. Those skilled in the art will understand that the components and blocks shown in the figures described above can be modified in various ways. For example, the order of logic can be rearranged, sub-steps can be executed in parallel, shown logic can be omitted, other logic can be included, and so on. In some embodiments, one or more of the components described above can perform one or more of the processes described below.

[0039] The foregoing figures illustrate several embodiments of the disclosed technology. In this specification, references to "implementation" (e.g., "some embodiments," "various embodiments," "an embodiment," "implementation," etc.) indicate that a particular feature, structure, or characteristic described in connection with an embodiment is included in at least one embodiment of this disclosure. The appearance of these phrases in various places in the specification does not necessarily refer to the same embodiment, nor are they separate or alternative embodiments mutually exclusive with other embodiments. Furthermore, various features are described that may be present in some embodiments but not in others. Similarly, various requirements are described that may be requirements for some embodiments but not for others.

[0040] As used herein, above a threshold means that the value of an item being compared is higher than another specified value, that the item being compared is among a specified number of items with a maximum value, or that the item being compared has a value within a specified top percentage value. As used herein, below a threshold means that the value of an item being compared is lower than another specified value, that the item being compared is among a specified number of items with a minimum value, or that the item being compared has a value within a specified bottom percentage value. As used herein, within a threshold means that the value of an item being compared is between two other specified values, that the item being compared is among a specified number of items in the middle, or that the item being compared has a value within a specified middle percentage range. For example, relative terms such as high or unimportant, when not otherwise defined, can be understood as assigning a value and determining how said value will be compared to an established threshold. For example, the phrase “select fast connection” can be understood as meaning to select a connection with a value above a threshold corresponding to its connection speed.

[0041] As used in this article, the word “or” refers to any possible permutation of a set of items. For example, the phrase “A, B, or C” refers to at least one of A, B, C, or any combination thereof, such as any of the following: A; B; C; A and B; A and C; B and C; A, B, and C; or, for example, A and A; B, B, and C; multiples of any of the items A, A, B, C, and C; etc.

[0042] Although the subject matter has been described in language specific to structural features and / or methodological actions, it should be understood that the subject matter defined in the appended claims is not necessarily limited to the specific features or actions described above. Specific embodiments and implementations have been described herein for illustrative purposes, but various modifications may be made without departing from the scope of the embodiments and implementations. The specific features and actions described above are disclosed as examples of implementing the appended claims. Therefore, the embodiments and implementations are not limited to those specified in the appended claims.

[0043] Any patents, patent applications, and other references mentioned above are incorporated herein by reference. Where necessary, modifications may be made to provide other further embodiments using the systems, functions, and concepts described in the various references above. If any statement or subject matter in the cited documents conflicts with the statement or subject matter of this application, this application shall prevail.

Claims

1. A memory device, comprising: a substrate having a front side and a back side opposite the front side; control circuitry disposed over the front side of the substrate; a memory array disposed over and electrically coupled to the control circuitry; a through-silicon via (TSV) disposed under the memory array, the TSV extending through the substrate from the control circuitry to the back side of the substrate; and a bond pad disposed on the back side of the substrate and electrically coupled to the control circuitry via the TSV, wherein there is no bond pad at a top side of the memory device.

2. The memory device of claim 1, wherein the memory array comprises a not-and (NAND) memory array.

3. The memory device of claim 1, wherein the control circuitry comprises complementary metal-oxide-semiconductor (CMOS) circuitry.

4. The memory device of claim 3, wherein the memory array is disposed over CMOS control circuitry in a below-array CMOS (CUA) configuration.

5. The memory device of claim 1, wherein the memory array extends within a threshold distance of each edge of the substrate, the threshold distance being less than a width of the bond pad.

6. A method for fabricating a memory die, the method comprising: forming a through-silicon via (TSV) in a substrate having a front side and a back side opposite the front side; forming control circuitry on the front side of the substrate; forming a memory array over the control circuitry, wherein the memory array is electrically coupled to the control circuitry; and forming a bond pad on the back side of the substrate, wherein the bond pad is electrically coupled to the control circuitry via the TSV, and wherein there is no bond pad on a top side of the memory array.

7. The method of claim 6, further comprising singulating the memory die from a wafer.

8. The method of claim 6, further comprising attaching a carrier wafer to a top side of the memory die opposite the back side of the substrate prior to forming the bond pad.

9. The method of claim 8, further comprising removing the carrier wafer from the memory die after forming the bond pad.

10. The method of claim 6, further comprising exposing the TSV by planarizing the back side of the substrate.

11. The method of claim 6, wherein the memory array comprises NAND memory cells.

12. The method of claim 6, wherein the control circuitry is complementary metal-oxide-semiconductor (CMOS) circuitry.

13. A memory device, comprising: a bond pad formed on a back side of a substrate, wherein the substrate has a front side opposite the back side; complementary metal-oxide-semiconductor (CMOS) circuitry disposed over the front side of the substrate and under a memory array; wherein the bond pad is electrically coupled to the CMOS circuitry by a via that passes through the substrate to the CMOS circuitry but does not pass through a plane containing the memory array, and wherein there are no bond pads at a top side of the memory device.

14. The memory device of claim 13, wherein the via is a through-silicon via (TSV).

15. The memory device of claim 13, wherein the via is vertically aligned with a memory array and does not penetrate the memory array.

16. The memory device of claim 13, wherein the memory array extends within a threshold distance of each edge of the substrate, such that the threshold distance is less than a width of the bond pad; and wherein the bond pad is vertically aligned with the memory array.

17. The memory device of claim 13, wherein the memory array comprises a NAND memory array.

18. The memory device of claim 13, wherein the via does not extend from the bond pad beyond the CMOS circuitry.

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