Substrate inspection device, substrate inspection system and substrate inspection method

Abstract

A substrate inspection device for inspecting a substrate is provided, comprising: an acquisition unit, which acquires an estimated image of the inspection object substrate after being processed by the substrate processing device based on an image estimation model and a captured image of the inspection object substrate before being processed by the substrate processing device, wherein the image estimation model is generated through machine learning using the captured images of a plurality of substrates before being processed by the substrate processing device and the captured images after being processed; and a judgment unit, which judges whether the inspection object substrate has defects based on the captured image of the inspection object substrate after being processed by the substrate processing device and the estimated image.

Description

Technical Field

[0001] The present disclosure relates to a substrate inspection device, a substrate inspection system, and a substrate inspection method. Background Art

[0002] Patent document 1 discloses a method for inspecting wafers in a substrate processing system, wherein the substrate processing system includes a plurality of processing devices that process the wafers. In this inspection method, the surface of the wafer before being processed by the processing device is photographed to obtain a first substrate image, and feature quantities are extracted from the first substrate image. Next, a reference image corresponding to the feature quantities extracted from the first substrate image is selected from a storage unit that stores a plurality of reference images serving as defect inspection references, wherein the plurality of reference images are set to correspond to feature quantities in different ranges, respectively. Then, the surface of the substrate after being processed by the processing device is photographed to obtain a second substrate image, and the presence or absence of defects in the wafer is determined based on the selected reference image and the second substrate image.

[0003] Prior art literature

[0004] Patent Literature

[0005] Patent Document 1: Japanese Patent Application Laid-Open No. 2016-212008 Summary of the Invention

[0006] Technical problem to be solved by the invention

[0007] The technology disclosed herein aims to further improve the defect detection accuracy in defect inspection performed based on an image obtained by imaging an inspection target substrate.

[0008] Technical means to solve the problem

[0009] One aspect of the present disclosure provides a substrate inspection device for inspecting a substrate, comprising: an acquisition unit, which acquires an estimated image of the inspection object substrate after being processed by the substrate processing device based on an image estimation model and a captured image of the inspection object substrate before being processed by the substrate processing device, wherein the image estimation model is generated through machine learning using the captured images of a plurality of substrates before being processed by the substrate processing device and the captured images after being processed; and a judgment unit, which judges whether the inspection object substrate has defects based on the captured image of the inspection object substrate after being processed by the substrate processing device and the estimated image.

[0010] Effects of the Invention

[0011] According to the present disclosure, it is possible to further improve the defect detection accuracy in defect inspection performed based on an image obtained by imaging an inspection target substrate. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1 This is a diagram schematically showing the general configuration of a substrate inspection system according to this embodiment.

[0013] Figure 2 It is a plan view schematically showing the general structure of each substrate processing system.

[0014] Figure 3 It is a front view schematically showing the general internal structure of each substrate processing system.

[0015] Figure 4 It is a rear view schematically showing the general internal structure of each substrate processing system.

[0016] Figure 5 It is a longitudinal sectional view showing a schematic structure of an inspection imaging device.

[0017] Figure 6 It is a cross-sectional view showing a schematic structure of an inspection imaging device.

[0018] Figure 7 This is a block diagram schematically showing the general configuration of an imaging control device and an overall control device related to substrate inspection.

[0019] Figure 8 This is a conceptual diagram for explaining an example of conventional defect inspection.

[0020] Figure 9 This is a conceptual diagram for explaining an example of defect inspection according to this embodiment.

[0021] Figure 10 This is a graph showing the relationship between the pixel values ​​of the actual captured image and the pixel values ​​of the estimated image for each portion of the image, and the entire wafer is shown.

[0022] Figure 11 This diagram shows the relationship between the pixel values ​​of the actual captured image and the pixel values ​​of the estimated image for each portion of the image, and only the center portion of the wafer is shown.

[0023] Figure 12 This diagram shows the relationship between the pixel values ​​of an actual captured image and the pixel values ​​of other estimated images for each portion of the image, and shows the entire wafer.

[0024] Figure 13 This diagram shows the relationship between the pixel values ​​of an actual captured image and the pixel values ​​of other estimated images for each portion of the image, and only the center portion of the wafer is shown.

[0025] Figure 14 This is a block diagram showing a schematic configuration of another example of the overall control device.

[0026] Figure 15 This is an explanatory diagram showing the state after the planar distribution of pixel values ​​is decomposed into multiple in-plane trend components of pixel values ​​using Zernike polynomials.

[0027] Figure 16 It is an explanatory diagram showing the pixel value of each pixel in the wafer surface.

[0028] Figure 17 This is an explanatory diagram showing the values ​​of each pixel within the wafer surface in the height direction within the wafer surface.

[0029] Figure 18 This is a diagram showing the flow of a process of selecting a pair of captured images for model generation performed by a selection unit.

[0030] Figure 19 This is a diagram for explaining the Mahalanobis distance.

[0031] Figure 20 1 is a block diagram showing a schematic configuration of another example of an overall control device.

[0032] Figure 21 This is a diagram illustrating another example of a method for calculating the Mahalanobis distance. DETAILED DESCRIPTION

[0033] In the manufacturing process of semiconductor devices, a resist coating process is performed on a semiconductor wafer (hereinafter referred to as a "wafer") to form a resist film. This process is followed by an exposure process to expose the resist film to light, and a development process to develop the exposed resist film. This process forms a resist pattern on the wafer. Following the resist pattern formation process, the target layer is etched using the resist pattern as a mask, thereby forming a predetermined pattern on the target layer. Furthermore, during the formation of the resist pattern, a film other than the resist film may be formed beneath the resist film.

[0034] Furthermore, when forming a resist pattern or performing etching using a resist pattern as described above, defect inspection is sometimes performed on the wafer after various processes. This defect inspection includes, for example, checking whether the resist pattern has been properly formed and whether there are foreign objects attached to the wafer. In recent years, images obtained by photographing the surface of the wafer being inspected after processing have sometimes been used for this defect inspection. In this case, defect inspection is performed by comparing the captured image of the wafer being inspected with a reference image serving as a reference for inspection.

[0035] However, in the image captured of the inspected wafer after processing, unevenness (spots) may occur due to the influence of the surface condition of the inspected wafer before processing, that is, the condition of the substrate surface of the inspected wafer. In addition, because the processing environment is inconsistent between wafers, the uneven state described above varies from wafer to wafer. For example, even if a resist film is normally formed on the anti-reflective film of the wafer under the same processing conditions, the unevenness generated in the image captured of the wafer after the resist film is formed will also vary from wafer to wafer. Measures need to be taken to prevent this unevenness from being misjudged as a defect.

[0036] Patent Document 1 discloses selecting a substrate image corresponding to a feature extracted from a first substrate image from a plurality of substrate images, each set to correspond to a feature within a different range and stored in a storage unit, serving as a defect inspection reference. The first substrate image is obtained by photographing the surface of a wafer before processing. In Patent Document 1, the presence or absence of a wafer defect is determined based on the selected substrate image and a second substrate image obtained by photographing the surface of the substrate after processing.

[0037] When the above-mentioned unevenness exists, higher defect detection accuracy may be required compared to defect inspection performed using a substrate image selected as in Patent Document 1.

[0038] Therefore, an object of the technology disclosed herein is to further improve the defect detection accuracy in defect inspection performed based on an image obtained by imaging an inspection target substrate.

[0039] Hereinafter, the substrate inspection apparatus, substrate inspection system, and substrate inspection method of the present embodiment will be described with reference to the accompanying drawings. In this specification and the accompanying drawings, elements having substantially the same functional structure are denoted by the same reference numerals to omit repeated description.

[0040] Figure 1 This is a diagram schematically showing the general configuration of a substrate inspection system according to this embodiment.

[0041] As shown in the figure, the substrate inspection system 1 includes a plurality of substrate processing systems 10 and an overall control device 20. Alternatively, the number of substrate processing systems 10 included in the substrate inspection system 1 may be one.

[0042] Each substrate processing system 10 is used to process a wafer as a substrate. In this example, the substrate processing system 10 performs a process for forming a resist pattern on the wafer.

[0043] Figure 2 It is a plan view schematically showing the general structure of each substrate processing system 10. Figure 3 and Figure 41 and 2 are diagrams schematically showing the internal structure of each substrate processing system 10 , which are a front view and a rear view respectively.

[0044] like Figure 2 As shown, each substrate processing system 10 includes a cassette station 100 and a processing station 101. The cassette station 100 is used to load and unload a cassette C containing multiple wafers W, and the processing station 101 includes multiple processing devices that perform predetermined processing on the wafers W. Each substrate processing system 10 has a structure in which the cassette station 100, the processing station 101, and the interface station 103 are connected as an integrated whole. The interface station 103 transfers wafers W between the interface station 103 and the adjacent exposure device 102 of the processing station 101.

[0045] The cassette station 100 is provided with a cassette placement table 110 . The cassette placement table 110 is provided with a plurality of cassette placement plates 111 for placing the cassette C thereon when the cassette C is loaded in and unloaded from the outside of the substrate processing system 10 .

[0046] The cassette station 100 is equipped with a wafer transport device 113 that is movable along a transport path 112 extending in the X direction. The wafer transport device 113 is also movable in the vertical direction and in a direction around a vertical axis (theta direction), and is capable of transporting wafers W between the cassettes C on each cassette loading plate 111 and a transfer device in the third block G3 of the processing station 101, described later.

[0047] The processing station 101 is provided with a plurality of, for example, four, blocks including various devices, namely, the first block G1 to the fourth block G4. For example, on the front side of the processing station 101 ( Figure 2 A first block G1 is provided on the negative X direction side of the processing station 101. Figure 2 A second block G2 is provided on the positive X direction side (the upper side in the figure). Figure 2 A third block G3 is provided on the negative Y direction side of the processing station 101, and is located on the interface station 103 side ( Figure 2 A fourth block G4 is provided on the positive Y direction side.

[0048] In the first block G1, liquid processing devices as substrate processing devices for processing wafers W using processing liquid are arranged. Specifically, in the first block G1, liquid processing devices such as Figure 3 As shown, for example, a developing apparatus 120 , a lower layer film forming apparatus 121 , an intermediate layer film forming apparatus 122 , and a resist coating apparatus 123 are arranged in this order from the bottom.

[0049] The development processing apparatus 120 performs a development process on the wafer W. Specifically, the development processing apparatus 120 supplies a developer onto the resist film on the wafer W to form a resist pattern.

[0050] The lower film forming apparatus 121 is used to form an underlayer film as a base film for the resist film on the wafer W. Specifically, the lower film forming apparatus 121 applies a material for forming the lower layer film, i.e., an underlayer film material, onto the wafer W to form the lower layer film. The lower layer film is, for example, an SOC (spin-on-carbon) film.

[0051] The interlayer film forming apparatus 122 forms an interlayer film on the lower film of the wafer W and below the resist film. Specifically, the interlayer film forming apparatus 122 coats an interlayer film-forming material, i.e., an interlayer film material, on the lower film of the wafer W to form the interlayer film. The interlayer film is, for example, an SOG (spin-on-glass) film.

[0052] The resist coating apparatus 123 coats a resist liquid on the wafer W to form a resist film. Specifically, the resist coating apparatus 123 coats a resist liquid on the intermediate layer film of the wafer W to form a resist film.

[0053] For example, three of each of the developing apparatus 120, the lower film forming apparatus 121, the intermediate film forming apparatus 122, and the resist coating apparatus 123 are arranged horizontally. The number and arrangement of these developing apparatuses 120, the lower film forming apparatus 121, the intermediate film forming apparatus 122, and the resist coating apparatus 123 can be arbitrarily selected.

[0054] In the development processing unit 120, the lower layer film forming unit 121, the intermediate layer film forming unit 122, and the resist coating unit 123, a predetermined processing liquid is applied to the wafer W by, for example, spin coating. In the spin coating method, for example, the processing liquid is sprayed onto the wafer W from a coating nozzle and the wafer W is rotated to spread the processing liquid on the surface of the wafer W.

[0055] In the second block G2, heat treatment apparatuses 130 are arranged vertically and horizontally. These heat treatment apparatuses 130 are substrate processing apparatuses that perform thermal processes such as heating or cooling the wafers W using heating plates or cooling plates for mounting the wafers W. The number and arrangement of these heat treatment apparatuses 130 can be arbitrarily selected. Furthermore, each of the heat treatment apparatuses 130 can use a known apparatus.

[0056] In the third block G3, multiple transfer devices 140, 141, 142, 143, and 144 are arranged in order from below, and above them, inspection camera devices 145, 146, and 147 are arranged in order from below. Furthermore, in the fourth block G4, multiple transfer devices 150, 151, and 152 are arranged in order from below, and above them, inspection camera devices 153 and 154 are arranged.

[0057] Here, the configuration of the inspection imaging device 145 will be described.

[0058] Figure 5 and Figure 6 These are a longitudinal sectional view and a transverse sectional view respectively showing a schematic configuration of the inspection imaging device 145 .

[0059] like Figure 5 and Figure 6 As shown, the inspection camera device 145 has a housing 200. A mounting table 201 for mounting the wafer W is provided in the housing 200. The mounting table 201 can be rotated and stopped by a rotation drive unit 202 such as a motor. Figure 6 The negative X direction side) extends to the other end side ( Figure 6 The mounting table 201 and the rotation drive unit 202 are provided on the guide rail 203 and can be moved along the guide rail 203 by the drive device 204.

[0060] On the other end side in the housing 200 ( Figure 6 An imaging unit 210 is provided on the side surface (positive X-direction side) of the image sensor. For example, a wide-angle CCD camera is used as the imaging unit 210.

[0061] A half-mirror 211 is provided near the center of the upper portion of the housing 200. The half-mirror 211 is provided at a position opposite to the camera unit 210 in such a state that the mirror surface is tilted 45 degrees upward toward the camera unit 210, from a state in which the mirror surface faces vertically downward. An illuminating device 212 is provided above the half-mirror 211. The half-mirror 211 and the illuminating device 212 are fixed to the upper surface inside the housing 200. The illuminating light from the illuminating device 212 is irradiated downward through the half-mirror 211. Thus, the light reflected by an object located below the illuminating device 212 is further reflected by the half-mirror 211 and captured by the camera unit 210. That is, the camera unit 210 can capture an object located in the irradiation area of ​​the illuminating device 212. In addition, the shooting results of the camera unit 210 are input to the camera control device 251 described later.

[0062] In addition, the configurations of the inspection imaging devices 146 , 147 , 153 , and 154 are the same as the configuration of the inspection imaging device 145 described above.

[0063] Back to use Figures 2 to 4 1. Description of each substrate processing system 10.

[0064] like Figure 2As shown, a wafer transfer area D is formed in the area surrounded by the first to fourth blocks G1 to G4. Multiple wafer transfer devices 160 are located in the wafer transfer area D. Each wafer transfer device 160 includes a transfer arm 160a that is movable in the Y, X, θ, and vertical directions. The wafer transfer devices 160 are capable of moving within the wafer transfer area D, transferring wafers W to desired devices within the surrounding first, second, third, and fourth blocks G1, G2, G3, and G4.

[0065] In addition, if Figure 4 As shown, a shuttle transport device 170 is provided in the wafer transport area D for linearly transporting wafers W between the third block G3 and the fourth block G4 .

[0066] The shuttle device 170 may be used, for example, Figure 4 The shuttle device 170 can move in the Y direction while supporting the wafer W, and transfers the wafer W between the transfer device 142 in the third block G3 and the transfer device 152 in the fourth block G4.

[0067] like Figure 2 As shown, a wafer transport device 180 is provided adjacent to the third block G3 on the positive X-direction side. The wafer transport device 180 includes, for example, a transport arm 180a that is movable in the X-direction, the θ-direction, and the vertical direction. The wafer transport device 180 can move vertically while supporting the wafer W, transporting the wafer W to various transfer devices within the third block G3.

[0068] The interface station 103 is equipped with a wafer transport device 190 and a transfer device 191. The wafer transport device 190 includes, for example, a transport arm 190a that is movable in the Y direction, the θ direction, and the vertical direction. The wafer transport device 190 can, for example, support a wafer W on the transport arm 190a and transport the wafer W between the transfer devices, the transfer device 191, and the exposure device 102 within the fourth block G4.

[0069] Furthermore, the substrate processing system 10 is provided with a transport / process control device 250 and an imaging control device 251 serving as a substrate inspection device.

[0070] The transport / process control device 250 (hereinafter sometimes referred to as the "main control device 250") is, for example, a computer including a CPU, memory, and other components, and has a program storage unit (not shown). This program storage unit stores programs for controlling the operation of the various processing devices, transport devices, and other drive systems described above, and for performing various processes on the wafers W. These programs can also be recorded on a computer-readable storage medium and installed from this storage medium into the main control device 250. Alternatively, part or all of the programs can be implemented using dedicated hardware (circuit boards).

[0071] The imaging control device 251, like the main control device 250, is a computer including a CPU, memory, and the like, and has a program storage unit (not shown). This program storage unit stores a program that controls the operation of the imaging unit and drive system of each inspection imaging device, and controls processing related to substrate inspection. The program can also be recorded on a computer-readable storage medium and installed from the storage medium into the imaging control device 251. Part or all of the program can also be implemented using dedicated hardware (circuit board).

[0072] Back to use Figure 1 1. Description of a substrate inspection system.

[0073] As described above, the substrate inspection system 1 includes the overall control device 20 .

[0074] The overall control device 20 is, for example, a computer including a CPU, memory, etc., and has a program storage unit (not shown). This program storage unit stores a program for generating the image estimation model described later. The program may also be recorded on a computer-readable storage medium and installed from the storage medium into the overall control device 20. Alternatively, part or all of the program may be implemented using dedicated hardware (circuit board).

[0075] Figure 7 This is a block diagram schematically showing the general configuration of the imaging control device 251 and the overall control device 20 related to substrate inspection.

[0076] As shown in the figure, the overall control device 20 includes a storage unit 301 and a model generation unit 302 .

[0077] The storage unit 301 stores various information. The storage unit 301 stores captured images of the wafer W, which are obtained based on the capture results obtained by the imaging unit 210 of the inspection imaging device in each substrate processing system 10. In addition, for ease of understanding, unless otherwise specified, the captured images and the estimated images described below are assumed to be grayscale images. However, these images can also be images of at least any one of the R component, G component, and B component. Each captured image is associated with identification information of the captured wafer W, identification information of the processing device used in processing the captured wafer W, etc.

[0078] The model generation unit 302 generates an image estimation model through machine learning using images of each of the plurality of wafers W captured before and after the required processing by the substrate processing system 10 (hereinafter sometimes referred to as "image pairs captured before and after processing by the substrate processing system 10"). The image estimation model is a model for estimating images of the inspection target wafer W after the required processing by the substrate processing system 10 based on the images captured of the inspection target wafer W before the required processing by the substrate processing system 10. In other words, the image estimation model is a model for generating an estimated image of the inspection target wafer W after the processing based on the images captured of the inspection target wafer W before the processing.

[0079] The machine learning used to generate the image estimation model is, for example, machine learning based on Conditional Generative Adversarial Networks (GAN), more specifically, pix2pix.

[0080] In addition, the image estimation model is a generative network (Generator) that transforms an arbitrary input image to generate a fake image, for example, in a conditional generative adversarial network or pix2pix.

[0081] In conditional generative adversarial networks or pix2pix, a discriminator is used as a neural network in addition to the generative network described above. The discriminator takes as input an arbitrary image and a true image corresponding to the arbitrary image, or an arbitrary image and a false image generated by the generative network based on the arbitrary image, and identifies whether the image input together with the arbitrary image is a true image or a false image.

[0082] Furthermore, in machine learning based on conditional generative adversarial networks or pix2pix, a recognition method is learned for the recognition network so that the above-mentioned recognition can be performed correctly, and an image conversion method is learned for the generation network so that the false image is recognized as a true image in the recognition network.

[0083] In the model generation unit 302 , a pair of captured images before and after processing by the substrate processing system 10 is used as an image pair of the arbitrary image and a true image corresponding to the arbitrary image to be input to the recognition network.

[0084] The image estimation model generated by the model generation unit 302 is sent to the imaging control device 251 of the substrate processing system 10 .

[0085] The imaging control device 251 includes a storage unit 311 , a captured image acquisition unit 312 , an estimated image acquisition unit 313 , and a determination unit 314 .

[0086] The storage unit 311 stores various information. For example, the storage unit 311 stores an image estimation model generated by the model generation unit 302 of the overall control device 20 .

[0087] The captured image acquisition unit 312 acquires a captured image of the wafer W based on the image capturing results of the wafer W captured by the imaging units 210 of the inspection imaging devices 145 , 146 , 147 , 153 , and 154 . Specifically, the captured image acquisition unit 312 performs necessary image processing on the image captured by the imaging unit 210 , thereby generating an image representing the state of the entire surface of the wafer W as the captured image of the wafer W.

[0088] The captured image acquisition unit 312 acquires captured images of the inspection object wafer W before and after the required processing by the substrate processing system 10, and also acquires captured images of the inspection object wafer W before and after the required processing for generating an image estimation model.

[0089] The estimated image acquisition unit 313 generates and acquires an estimated image of the inspection target wafer W after the required processing, based on the captured image of the inspection target wafer W before the substrate processing system 10 performs the required processing, acquired by the captured image acquisition unit 312, and the image estimation model stored in the storage unit 311. Alternatively, the overall control device 20 may generate an estimated image of the inspection target wafer W after the required processing using the image estimation model, and the estimated image acquisition unit 313 may acquire the generated estimated image.

[0090] The determination unit 314 determines whether the inspection target wafer W has defects based on the captured image of the inspection target wafer W after the substrate processing system 10 has undergone the required processing, obtained by the captured image acquisition unit 312. Specifically, the determination unit 314 determines whether the inspection target wafer W has defects based on the captured image of the inspection target wafer W after the required processing, obtained by the captured image acquisition unit 312, and the estimated image of the inspection target wafer W after the required processing, obtained by the estimated image acquisition unit 313. Specifically, the determination unit 314 compares the captured image of the inspection target wafer W after the required processing with the estimated image of the inspection target wafer W after the required processing, and determines whether the inspection target wafer W has defects based on the comparison result. More specifically, the determination unit 314 determines whether the inspection target wafer W has defects based on the difference between the captured image of the inspection target wafer W after the required processing and the estimated image of the inspection target wafer W after the required processing.

[0091] Next, a description will be given of a method for processing wafer W and a method for inspecting wafer W performed in each substrate processing system 10 constructed as described above. In the following description, although the wafer W is photographed at more than three moments, with respect to defect inspections based on the photographed images of the wafer W, only defect inspections based on the photographed images of the wafer W after the resist pattern is formed are performed. In addition, before the following processing of the wafer W and inspection of the wafer W, it is assumed that machine learning of an image estimation model for the wafer W after the resist pattern is formed, which is to be used in the above-mentioned defect inspection, has been completed. This image estimation model is generated, for example, based on photographed images of the wafer W after the resist film of the wafer W is formed (i.e., before the resist pattern is formed) in each substrate processing system 10 and the wafer W after the resist pattern is formed.

[0092] First, a cassette C containing a plurality of wafers W is loaded into the cassette station 100. Then, under the control of the main controller 250, the wafers W in the cassette C are transported to the inspection imaging device 145 in the third block G3. Then, under the control of the imaging control device 251, the imaging unit 210 captures images of the wafers W in their initial state, before various films such as an underlayer film are formed, and the captured image acquisition unit 312 acquires images of the wafers W in this initial state.

[0093] Next, under the control of the main control unit 250 , the wafer W is transported to the lower layer film forming apparatus 121 in the first block G1 , where an underlying film is formed on the wafer W.

[0094] Then, the wafer W is transferred to the heat treatment apparatus 130 for the lower layer film in the second block G2 , and the lower layer film is subjected to a heat treatment.

[0095] Thereafter, the wafer W is conveyed to the inspection imaging device 153. Then, under the control of the imaging control device 251, the imaging unit 210 images the wafer W after the lower layer film is formed, and acquires an image of the wafer W after the lower layer film is formed.

[0096] Next, under the control of the main control unit 250 , the wafer W is transported to the intermediate layer film forming apparatus 122 in the first block G1 , where an intermediate layer film is formed on the lower layer film of the wafer W.

[0097] Then, the wafer W is transferred to the heat treatment apparatus 130 for the intermediate layer in the second block G2 , and the intermediate layer film is subjected to a heat treatment.

[0098] The wafer W is then transferred to the inspection imaging device 146. Under the control of the imaging control device 251, the imaging unit 210 images the wafer W after the intermediate layer film is formed, and the captured image acquisition unit 312 acquires the captured image of the wafer W after the intermediate layer film is formed.

[0099] Next, under the control of the main control device 250 , the wafer W is transported to the resist coating apparatus 123 in the first block G1 , where a resist film is formed on the intermediate layer film on the wafer W.

[0100] Then, the wafer W is transferred to the thermal treatment apparatus 130 for PAB treatment in the second block G2 and subjected to PAB treatment.

[0101] The wafer W is then transferred to the inspection imaging device 153. Under the control of the imaging control device 251, the imaging unit 210 images the wafer W after the resist film is formed, and the captured image acquisition unit 312 acquires the captured image of the wafer W after the resist film is formed.

[0102] Next, under the control of the main controller 250 , the wafer W is transported to the exposure device 102 and exposed to a desired pattern.

[0103] Then, the wafer W is transferred to the thermal treatment apparatus 130 for PEB treatment in the second block G2 and subjected to PEB treatment.

[0104] Next, the wafer W is transferred to the development processing apparatus 120 in the first block G1 and subjected to development processing, thereby forming a resist pattern on the wafer W.

[0105] The wafer W is then transferred to the inspection imaging device 147 . Under the control of the imaging control device 251 , the imaging unit images the wafer W after the resist pattern is formed, and the captured image acquisition unit 312 acquires the captured image of the wafer W after the resist pattern is formed.

[0106] Next, based on the captured image of the wafer W after the resist pattern is formed, acquired by the captured image acquisition unit 312, the presence or absence of defects in the wafer after the resist pattern is formed is determined. Specifically, the estimated image acquisition unit 313 generates an estimated image of the wafer W after the resist film is formed (i.e., before the resist pattern is formed) based on the captured image of the wafer W after the resist film is formed (i.e., before the resist pattern is formed) and a pre-generated image estimation model for the wafer W after the resist pattern is formed. Then, based on the captured image of the wafer W after the resist pattern is formed and the estimated image, the determination unit 314 determines whether the wafer W after the resist pattern is formed (i.e., the inspection target wafer W) has defects.

[0107] In the defect determination, for example, for a wafer W after the resist pattern is formed, the captured image is compared with the estimated image, and the portion where the pixel values ​​of the two images differ by a threshold value is determined to be a defective portion, and the other portion is determined to be a non-defective portion.

[0108] If the image estimation model for the wafer W after resist pattern formation has not yet been generated during the above determination, the presence or absence of defects in the wafer W is determined using the same method as in the prior art. If the estimation model generation has not yet been completed, the image of the wafer W captured after resist film formation and the image captured after resist pattern formation are input to the model generation unit 302 of the overall control device 20 to facilitate machine learning of the model.

[0109] When the above determination is completed, that is, when the defect inspection is completed, the wafer W is returned to the cassette C under the control of the main control device 250 , and the processing of the wafer W is completed. The above processing is also performed on other wafers W.

[0110] As described above, in this embodiment, an image estimation model is used. This image estimation model is generated through machine learning using images of each of a plurality of wafers W taken before the substrate processing system 10 performs the required processing and images taken after the aforementioned required processing. This image estimation model is a model for generating an estimated image of the wafer W after the aforementioned required processing based on the images taken of the wafer W before the substrate processing system 10 performs the required processing. In this embodiment, an estimated image of the inspection target wafer W after the aforementioned required processing is generated and obtained based on the above-mentioned image estimation model and the images taken of the inspection target wafer W before the aforementioned required processing. Then, based on the images actually obtained for the inspection target wafer W after the aforementioned required processing and the above-mentioned estimated images, it is determined whether the inspection target wafer W has defects. That is, based on a reference image that is suitable for each inspection target wafer W and serves as a reference for defect detection, it is determined whether the inspection target wafer has defects. Therefore, the accuracy of defect detection can be improved. Specifically, because the reference image serving as the defect inspection benchmark is an estimated image generated based on the aforementioned image estimation model, the nonuniformity of the captured image and the estimated image (i.e., the reference image) for the desired processed inspection target wafer W is approximately the same. Consequently, the likelihood of nonuniformity being detected as a defect is reduced, thereby improving defect detection accuracy. Specifically, when determining the presence or absence of defects, the comparison of the captured image and the estimated image as described above for the desired processed inspection target wafer W eliminates the possibility of nonuniformity being mistakenly detected as a defect, thereby reducing the aforementioned threshold. Consequently, defects that would otherwise be undetectable using a higher threshold can be detected.

[0111] use Figure 8 and Figure 9 , the effect of defect inspection of this embodiment is further described in detail.

[0112] Figure 8 This is a conceptual diagram for explaining an example of conventional defect inspection. Figure 9This is a conceptual diagram for explaining an example of defect inspection in this embodiment. Figure 8 and Figure 9 In FIG. 1 , the horizontal axis represents the coordinates of each portion along a certain direction on the wafer, and the vertical axis represents the pixel values ​​and the like of the above-mentioned portions. Figure 8 (A) shows an example of the relationship between the captured image Ip of the inspection target wafer W and the average image Ia described later. Figure 8 (B) in the middle represents the difference between the captured image Ip of the inspection target wafer W and the average image Ia described later. Figure 8 The middle (C) shows an example of a defect judgment value Vc described later in conventional defect inspection. Figure 9 (A) shows an example of the relationship between the captured image Ip of the inspection target wafer W and the corresponding estimated image Ie. Figure 9 (B) in the middle shows an example of a defect judgment value V described later in this embodiment.

[0113] In conventional defect inspection, for example, images of a plurality of wafers W after a desired process are obtained, and an average image Ia and a standard deviation image Is are obtained from the images of the plurality of wafers W. The average image Ia is an image using the average value of each pixel in the images of the plurality of wafers W as the pixel value of each pixel, and for example, the average image Ia has a value similar to the image Ip of the wafer W to be inspected. Figure 8 The standard deviation image Is is an image using the standard deviation of each pixel in the captured images of the plurality of wafers W as the pixel value of each pixel.

[0114] In conventional defect inspection, the difference between the captured image Ip of the inspection target wafer W and the average image Ia is calculated. The portion of the difference that has a significant value is as follows: Figure 8 As shown in (B), it includes not only defective parts but also parts caused by unevenness. Therefore, the standard deviation image Is is applied as a variation filter for removing unevenness to generate a defect judgment value Vc. Specifically, for each pixel whose absolute value of the difference pixel value exceeds the absolute value of the pixel value of the standard deviation image Is, the pixel value of the standard deviation image Is is subtracted from the pixel value of the difference to generate the following value: Figure 8 The defect judgment value Vc shown in (C) is shown in FIG. In conventional defect inspection, the portion of the defect judgment value exceeding the threshold value Tc is judged as a defect.

[0115] However, the variation filter for removing unevenness, that is, the standard deviation image Is, is not unique to each wafer W and is not an image that can accurately express unevenness. Figure 8As shown in (C), the portion of the defect judgment value that represents a significant value includes not only the portion caused by defects K1, K2, and K3, but also the portion caused by the unevenness U. To prevent this unevenness U portion from being detected as a defect, conventional defect inspection methods set the threshold Tc for the defect judgment value to a high value. In other words, the detection sensitivity is set to a low level. Consequently, only defects K1 and K2, which appear as large values ​​in the defect judgment value Vc, may be detected, while the defect K3, which appears as a small value in the defect judgment value Vc and should be detected, may not be detected.

[0116] On the other hand, in this embodiment, the captured image Ip of the inspection target wafer W after the processing is required and the estimated image Ie as the defect inspection reference image has, for example, Figure 9 The relationship shown in (A). Then, for example, the difference between each pixel of the captured image Ip of the inspection object wafer W after the required processing and the estimated image Ie is used as the defect judgment value V, and the part of the defect judgment value V that exceeds the threshold T is judged as a defect. As described above, the estimated image Ie used in the defect judgment of this embodiment is generated by machine learning and based on the image estimation model, and is inherent to each wafer W, which reflects the state of the inspection object wafer W before the required processing. Therefore, in the captured image Ip and the estimated image Ie of the inspection object wafer W after the required processing, the unevenness is roughly the same, such as Figure 9 As shown in (B), the portion of the defect judgment value V that exhibits a significant value does not include portions caused by unevenness, but only portions caused by defects K1, K2, and K3. Therefore, even if the threshold T for the defect judgment value V is reduced, uneven portions will not be detected as defects. Therefore, the threshold T can be set to a lower value, that is, the detection sensitivity can be set to a higher value, allowing accurate detection of even defect K3, which appears as a small value in the defect judgment value V.

[0117] The inventors used images of wafer W after resist film formation and images of wafer W after resist pattern formation to actually generate an image estimation model through machine learning. Then, based on the images of a certain inspection target wafer W after resist film formation and the generated image estimation model, an estimated image of the inspection target wafer W after resist pattern formation was generated and compared with the actual images of the inspection target wafer W after resist pattern formation. The results are shown in Figure 10 and Figure 11 . Figure 10 and Figure 11 This is a diagram showing the relationship between the pixel values ​​of the actual captured image and the pixel values ​​of the estimated image for each portion of the image. Figure 10 Represents a diagram involving the entire wafer, Figure 11The diagram shows only the center of the wafer.

[0118] like Figure 10 and Figure 11 As shown in FIG, in each part of the image, the pixel value of the actual captured image and the pixel value of the estimated image are close to each other. Figure 11 As shown, at the center of the wafer, the pixel value of the actual captured image is substantially the same as the pixel value of the estimated image.

[0119] in addition, Figure 10 and Figure 11 The diagram shows the pixel values ​​of the R component, but the inventors have confirmed that the G and B components also exhibit the same trend as that of the R component.

[0120] In the above description, an image estimation model for the inspection target wafer W after resist pattern formation is generated based on a captured image of the wafer W after resist film formation and a captured image of the wafer W after resist pattern formation. Alternatively, an image estimation model for the inspection target wafer W after resist pattern formation may be generated based on a captured image of the wafer W in its initial state before underlying film formation and a captured image of the wafer W after resist pattern formation. Thus, an estimated image of the inspection target wafer W after resist pattern formation can be estimated based on this image estimation model and the captured image of the inspection target wafer W in its initial state, and defect inspection of the inspection target wafer W after resist pattern formation can be performed based on this estimated image.

[0121] The inventors used the captured images of the wafer W in the initial state and the captured images of the wafer W after the resist pattern was formed to actually generate an image estimation model through machine learning. Then, based on the captured images of the initial state of a certain inspection target wafer W and the generated image estimation model, an estimated image of the inspection target wafer W after the resist pattern was formed was generated and compared with the actual captured image of the inspection target wafer W after the resist pattern was formed. The results are shown in Figure 12 and Figure 13 . Figure 12 and Figure 13 This is a diagram showing the relationship between the pixel values ​​of the actual captured image and the pixel values ​​of the estimated image for each portion of the image. Figure 12 Represents a diagram involving the entire wafer, Figure 13 The diagram shows only the center of the wafer.

[0122] like Figure 12 and Figure 13 As shown in FIG, in each part of the image, the pixel value of the actual captured image and the pixel value of the estimated image are close to each other. Figure 13As shown, at the center of the wafer, the pixel value of the actual captured image is substantially the same as the pixel value of the estimated image.

[0123] in addition, Figure 12 and Figure 13 The diagram shows the pixel values ​​of the R component, but the inventors have confirmed that the G and B components also exhibit the same trend as that of the R component.

[0124] Alternatively, an image estimation model for the inspection target wafer W after resist pattern formation can be generated based on a captured image of the wafer W after the lower layer film is formed, a captured image of the wafer W after the intermediate layer film is formed, and a captured image of the wafer W after the resist pattern is formed. Thus, an estimated image of the inspection target wafer W after the resist pattern is formed can be estimated based on this image estimation model and the captured image of the inspection target wafer W after the lower layer film is formed, or the captured image of the wafer W after the intermediate layer film is formed. Defect inspection of the inspection target wafer W after the resist pattern is formed can be performed based on this estimated image. Specifically, if n types of processing are performed and captured images of the inspection target wafer W are acquired before and after each processing, the following captured images can be used for defect inspection and image estimation model generation for the inspection target wafer W after the mth (m≤n)th) type of processing. That is, not only the captured image of wafer W before undergoing the mth processing (in other words, after the (m-1)th processing) can be used, but also the captured image of wafer W before undergoing the (m-1)th processing (in other words, after the (m-2)th processing) can be used.

[0125] Furthermore, in this embodiment, according to Figure 11 and Figure 13 As a result, defect inspection can also be performed based on an image of only the center portion of the wafer, from among the captured and estimated images of the inspection target wafer W after the substrate processing system 10 has undergone the required processing. This further reduces the possibility of misdetecting unevenness as a defect, enabling more accurate defect detection. In this case, for example, an edge filter that excludes the peripheral portion of the wafer W is applied during defect inspection.

[0126] Furthermore, regarding the image estimation model, for example, captured images acquired by the plurality of substrate processing systems 10 included in the substrate inspection system 1 are used to generate an image estimation model that is common among the substrate processing systems.

[0127] Alternatively, an image estimation model of a certain substrate processing system 10 may be generated using only the captured images acquired by the substrate processing system 10. In this way, an image estimation model reflecting the characteristics of the substrate processing system 10 can be generated.

[0128] Furthermore, captured images of wafers W determined to be defective during defect inspection may be excluded from the captured images of wafers W used to generate the image estimation model. This allows for the generation of a more accurate image estimation model.

[0129] Furthermore, although the substrate processing system 10 of this embodiment performs multiple film forming processes (including a resist pattern forming process after a resist film forming process), the substrate inspection method of this embodiment can also be applied to a case where a single film forming process is performed. Furthermore, the substrate inspection method of this embodiment can also be applied to a case where processes other than film forming processes (e.g., etching processes) are performed.

[0130] Figure 14 This is a block diagram showing the schematic configuration of another example of the overall control device, showing a configuration related to substrate inspection.

[0131] Figure 14 The overall control device 20a and Figure 7 The overall control device 20 similarly includes a storage unit 301 and a model generation unit 302. Furthermore, the overall control device 20a includes a selection unit 400 that selects, from among a large number of captured image pairs, a captured image pair for use by the model generation unit 302 in generating an image estimation model, i.e., a captured image pair for model generation. The captured image pair refers to an image pair consisting of a combination of an image of a wafer W before and after processing by the substrate processing system 10.

[0132] The selection unit 400 determines an abnormality level for each captured image pair and selects a captured image pair for model generation based on the abnormality level. The abnormality level is determined using the correlation distribution between the in-plane trend of pixel values ​​in an image of the wafer W before the required processing by the substrate processing system 10 (hereinafter sometimes referred to as the "IN image (input image)") and the in-plane trend of pixel values ​​in an image of the wafer W after processing by the substrate processing system 10 (hereinafter sometimes referred to as the "OUT image (output image)").

[0133] The selection unit 400 includes, for example, a candidate acquisition unit 401 , a coefficient calculation unit 402 , a distance calculation unit 403 , and an extraction unit 404 .

[0134] The candidate acquisition unit 401 acquires a plurality of captured image pairs from the storage unit 301 as candidates for captured image pairs for model generation.

[0135] The coefficient calculation unit 402 uses Zernike polynomials to decompose the planar distribution of pixel values ​​in each captured image of the wafer W included in the captured image pair obtained by the candidate acquisition unit 401 into multiple in-plane tendency components of the pixel values, and calculates the Zernike coefficient of each in-plane tendency component.

[0136] Images captured of wafer W are generally composed of the three primary colors of RGB (red, green, and blue). Therefore, it is possible to determine the in-plane trend component Zi of the pixel value for each of the primary colors R, G, and B. However, the image processing methods differ for each of the three primary colors R, G, and B. Therefore, unless otherwise specified, the following assumes that all primary colors R, G, and B are processed in parallel.

[0137] In the coefficient calculation unit 402, for each captured image of the wafer W included in the captured image pair obtained by the candidate acquisition unit 401, the color of the captured image is first digitized into pixel values ​​on the entire surface of the wafer W, for example, in units of pixels. In this way, the planar distribution of the pixel values ​​within the wafer surface is obtained. Next, in the coefficient calculation unit 402, the planar distribution of the pixel values ​​within the wafer surface is decomposed into a plurality of in-plane trend components Zi (i is an integer greater than 1) of the pixel values. The plurality of in-plane trend components Zi of the pixel values ​​are as follows: Figure 15 As shown, the planar distribution Z of pixel values ​​within the wafer surface is decomposed into multiple components using Zernike polynomials.

[0138] Here, we will explain Zernike polynomials. Zernike polynomials are complex functions primarily used in the field of optics, with two degrees (n, m). Furthermore, they are functions on a unit circle with a radius of 1, and have polar coordinates (r, θ). In optics, these Zernike polynomials are used, for example, to analyze the aberration components of a lens. By using Zernike polynomials to decompose wavefront aberrations, aberration components based on various independent wavefront shapes, such as mountain and saddle shapes, can be obtained.

[0139] Next, use Figure 16 and Figure 17 In this embodiment, a method of obtaining the in-plane trend component Zi of the pixel value using the Zernike polynomial will be described. Figure 16 The plane distribution Z of the pixel value of each pixel P in the wafer W surface is shown, and the numerical value recorded inside each pixel P represents the pixel value of the pixel P. In addition, for the convenience of explanation, Figure 16 and Figure 17 Only a series of pixels P along the X-axis direction is recorded. Figure 16 The planar distribution Z of pixel values ​​shown is shown when the Zernike polynomials are applied, for example, as Figure 17 As shown, the pixel value of each pixel P is represented in the height direction ( Figure 17 As a result, the planar distribution of the pixel values ​​of each pixel P can be regarded as a curve of a prescribed shape drawn in three dimensions. Therefore, by expressing the pixel values ​​of all pixels P in the surface of wafer W in the same manner in the height direction on the surface of wafer W, the distribution of pixel values ​​in the surface of wafer W can be regarded as a three-dimensional circular wavefront. By regarding the distribution of pixel values ​​as a three-dimensional wavefront in this way, the Zernike polynomials can be applied, and the Zernike polynomials can be used to decompose the planar distribution Z of the pixel values ​​in the wafer surface into multiple in-plane trend components Zi of pixel values, such as the inclined components in the up, down, left, and right directions in the wafer surface, and the curved components of convex or concave curvature. The size of each in-plane trend component Zi of the pixel value can be represented by a Zernike coefficient.

[0140] Specifically, the Zernike coefficients representing the in-plane trend component Zi of the pixel value are expressed using polar coordinate arguments (r, θ) and degrees (n, m). The first to ninth Zernike coefficients are given below as an example.

[0141] Z1, n=0, m=0(1)

[0142] Z2, n=1, m=1(r·cosθ)

[0143] Z3, n = 0, m = -1 (r·sinθ)

[0144] Z4, n = 2, m = 0 (2r 2 -1)

[0145] Z5, n = 2, m = 2 (r 2 ·cos2θ)

[0146] Z6, n = 2, m = -2 (r 2 ·sin2θ)

[0147] Z7, n = 3, m = 1 ((3r 3 -2r)·cosθ)

[0148] Z8, n = 3, m = -1 ((3r 3 -2r)·sinθ)

[0149] Z9, n=4, m=0(6r 4 -6r 2 +1)

[0150] ·

[0151] ·

[0152] ·

[0153] For example, the first Zernike coefficient, namely the Zernike coefficient Z1, represents the average value of the pixel values ​​on the wafer surface, the second Zernike coefficient Z2 represents the tilt component of the pixel values ​​on the wafer surface in the left-right direction, the third Zernike coefficient Z3 represents the tilt component of the pixel values ​​on the wafer surface in the front-back direction (a direction orthogonal to the tilt direction of the Zernike coefficient Z2), and the fourth Zernike coefficient represents the curved component of the pixel values ​​that is uniform in the circumferential direction and gradually increases in the radial direction with the center of the wafer as the origin.

[0154] Back to Figure 14 Description.

[0155] The coefficient calculation unit 402 calculates the values ​​of the in-plane trend components Zi of the pixel values ​​obtained by decomposing the planar distribution Z of the pixel values ​​within the wafer surface in the above manner. Specifically, as described above, the magnitude of the in-plane trend components Zi of the pixel values ​​is represented by the Zernike coefficients. Therefore, the values ​​of the in-plane trend components Zi of the pixel values ​​are calculated by calculating the values ​​of the respective Zernike coefficients.

[0156] The distance calculation unit 403 calculates the Mahalanobis distance for each pair of captured images acquired by the candidate acquisition unit 401, based on the correlation distribution between the Zernike coefficients of the IN image and the Zernike coefficients of the OUT image, for each term (each degree) of the Zernike polynomial. The distance calculation unit 403 calculates the Mahalanobis distance MD (see below) between a point representing the captured image pair and the correlation distribution in the space to which the correlation distribution belongs (i.e., the distribution space composed of the Zernike coefficients of the IN image and the Zernike coefficients of the OUT image) for each term of the Zernike polynomial. Figure 19 ).

[0157] The extraction unit 404 determines an abnormality level for each captured image pair acquired by the candidate acquisition unit 401 based on the Mahalanobis distance calculated by the distance calculation unit 403. Then, based on the determined abnormality level, the extraction unit 404 extracts and selects a captured image pair for model generation from the captured image pairs acquired by the candidate acquisition unit 401.

[0158] Next, the selection process of the captured image pair for model generation performed by the selection unit 400 will be described. Figure 18 4 is a diagram showing the flow of a process of selecting a pair of captured images for model generation performed by the selection unit 400 . Figure 19 This is a diagram for explaining the Mahalanobis distance. Figure 20 This is a diagram conceptually showing a method for calculating the abnormality degree.

[0159] First, as shown in the figure, the candidate acquisition unit 401 of the selection unit 400 obtains a plurality of image pairs from the storage unit 301 as candidate image pairs for model generation (step S1). At this time, the candidate acquisition unit 401 excludes images of wafers W that were determined to be "defective" during defect inspection from the candidate image pairs for model generation. The candidate acquisition unit 401 excludes image pairs of wafers W that were determined to be "defective" both when defect inspection was performed based on the IN image and when defect inspection was performed based on the OUT image.

[0160] Next, the coefficient calculation unit 402 performs enhancement processing on each of the captured images (i.e., the IN image and the OUT image) included in the captured image pair obtained by the candidate acquisition unit 401 (step S2). This enhancement processing, for example, enhances the contrast of each captured image. This can, for example, make potential coating unevenness more apparent in an image of a wafer with a coating film formed thereon.

[0161] Next, the coefficient calculation unit 402 uses Zernike polynomials to decompose the planar distribution of pixel values ​​within each enhanced image of the wafer W into multiple in-plane trend components Zi of the pixel values, and calculates the Zernike coefficients for each in-plane trend component (step S3). In other words, the coefficient calculation unit 402 uses Zernike polynomials to approximate the planar distribution of pixel values ​​within each enhanced image of the wafer W (i.e., each enhanced IN image and OUT image) and calculates the coefficients of each term in the approximation, i.e., the Zernike coefficients. The coefficient calculation unit 402 calculates, for example, the Zernike coefficients for the first to sixteenth terms in the Zernike polynomials. The calculation of the Zernike coefficients by the coefficient calculation unit 402 is performed, for example, for each of the RGB images.

[0162] Next, the distance calculation unit 403 calculates the Mahalanobis distance MD for each term of the Zernike polynomial for each pair of captured images acquired by the candidate acquisition unit 401 (step S4). Figure 19 As shown, the Mahalanobis distance MD of each term in the Zernike polynomial calculated here is the Mahalanobis distance between the point P of the captured image pair representing the calculation object in the distribution space K of the Zernike coefficients between the IN image and the OUT image, and the correlation distribution C of the Zernike coefficients of the IN image and the Zernike coefficients of the OUT image.

[0163] The Mahalanobis distance represents the distance between a sample point and a distribution. The Mahalanobis distance MD between a vector y and a distribution with mean μ and covariance ∑ can be calculated using the following formula.

[0164] [Formula 1]

[0165]

[0166] The distance calculation unit 403 calculates the Mahalanobis distance MD of each pair of captured images acquired by the candidate acquisition unit 401 for each of the first to sixteenth terms in the Zernike polynomials.

[0167] Furthermore, the calculation of the Mahalanobis distance of each term in the Zernike polynomial is performed, for example, separately for RGB.

[0168] Furthermore, the Mahalanobis distance calculated for each term of the Zernike polynomial may be divided by the average value of the corresponding term to perform normalization.

[0169] Next, the extraction unit 404 determines the abnormality Ab for each image pair based on the Mahalanobis distance calculated by the distance calculation unit 403 for each term of the Zernike polynomial for each image pair (step S5). For example, the extraction unit 404 determines the abnormality Ab by adding the Mahalanobis distance MD calculated by the distance calculation unit 403 for each term of the Zernike polynomial for each image pair.

[0170] More specifically, for example, the extraction unit 404 may Figure 20 As shown, for each captured image pair, the Mahalanobis distances MD with respect to R calculated by the distance calculation unit 403 for each of the first to sixteenth terms in the Zernike polynomial are all added together. Then, the extraction unit 404 determines the result of the addition (i.e., the sum of the Mahalanobis distances MD) as the abnormality Ab with respect to R of each captured image pair. r Similarly, the extraction unit 404 adds up all the Mahalanobis distances MD with respect to G calculated by the distance calculation unit 403 for each term from the first term to the sixteenth term in the Zernike polynomial for each captured image pair, and determines the sum as the abnormality Ab with respect to G of each captured image pair. g In addition, the extraction unit 404, for example, adds up all the Mahalanobis distances MD with respect to B calculated by the distance calculation unit 403 for each term from the first term to the sixteenth term in the Zernike polynomial for each captured image pair, and determines the sum as the abnormality Ab with respect to B of each captured image pair. b That is, the extraction unit 404 adds up all the Mahalanobis distances MD calculated for each of the first to sixteenth terms in the Zernike polynomials and for each of the RGB colors for each captured image pair.

[0171] Furthermore, when summing the Mahalanobis distances MD calculated by the distance calculation unit 403 for each term of the Zernike polynomial for each pair of captured images, weighting may be applied to each term of the Zernike polynomial. Furthermore, when summing the Mahalanobis distances calculated by the distance calculation unit 403 for each term of the Zernike polynomial and for each RGB color for each pair of captured images, weighting may be applied to each color.

[0172] Next, the extraction unit 404 sets an abnormality determination threshold value Th for the abnormality degree Ab determined by the extraction unit 404 (step S6). For example, the extraction unit 404 calculates the threshold value Th based on the following formula: c In the following formula, Ab Ave The average value of the abnormality Ab determined by the extraction unit 404 is represented by Ab. Std It represents the standard deviation of the abnormality Ab determined by the extraction unit 404 , and c is an integer of 1 to 3, for example.

[0173] Thc=Ab Ave +c×Ab Std

[0174] The extraction unit 404 calculates the threshold value Th c Set as the abnormality judgment threshold Th. In addition, if the calculated threshold Th c If the threshold is too small, in the image pair extraction step for model generation in step S7 described later, more image pairs than necessary may be excluded from the image pairs for model generation. Therefore, the lower limit of the abnormality judgment threshold Th may be set in advance, and the threshold Th calculated based on the above formula may be set as follows: c If the value is lower than the lower limit, the lower limit is set as the abnormality judgment threshold Th. The threshold Th is calculated based on the above formula for RGB. c , and set the abnormality judgment threshold Th. In addition, let the abnormality judgment threshold Th of R, G, and B be Th r Th g Th b .

[0175] Next, the extraction unit 404 extracts and selects image pairs for model generation based on the abnormality degree Ab determined by the extraction unit 404 and the threshold value Th set by the extraction unit 404 (step S7). Specifically, the extraction unit 404 extracts as image pairs for model generation those image pairs obtained by the candidate acquisition unit 401 for which the abnormality degree Ab, obtained by adding the Mahalanobis distance MD, does not exceed the abnormality determination threshold value Th. More specifically, the extraction unit 404 extracts as image pairs for model generation those image pairs that meet all of the following conditions (x1) to (x3).

[0176] (x1)Abnormality Ab of R r ≥Abnormality judgment threshold Th for R r

[0177] (x2)Abnormality Ab of G g ≥Abnormality judgment threshold Th of G g

[0178] (x3) Regarding B's abnormality Ab b ≥Abnormality judgment threshold Th for B b

[0179] As described above, by automatically selecting image pairs suitable for learning the image estimation model from a large number of captured image pairs, the quality of the image estimation model can be ensured, and the accuracy of defect detection using the image estimation model can be improved.

[0180] The method by which the extraction unit 404 extracts the captured image pairs for model generation based on the Mahalanobis distance is not limited to the above-mentioned example. For example, the following method may be adopted.

[0181] That is, the extraction unit 404 sets the Mahalanobis distance MD calculated by the distance calculation unit 403 as the abnormality Ab for each term of the Zernike polynomial for each captured image pair. More specifically, the extraction unit 404 sets the Mahalanobis distance MD with respect to R calculated by the distance calculation unit 403 for each term from the first term to the sixteenth term of the Zernike polynomial as the abnormality Ab with respect to R for each captured image pair. r1 ~Ab r16 Similarly, the extraction unit 404 sets the Mahalanobis distance MD with respect to G calculated by the distance calculation unit 403 for each of the first to sixteenth terms in the Zernike polynomial as the abnormality Ab with respect to G of each captured image pair. g1 ~Ab g16 In addition, the extraction unit 404 sets the Mahalanobis distance MD with respect to B calculated by the distance calculation unit 403 for each of the first to sixteenth terms in the Zernike polynomial as the abnormality Ab with respect to B of each captured image pair. b1 ~Ab b16 .

[0182] Then, the extraction unit 404 sets an abnormality determination threshold value Th for each term of the Zernike polynomial for the abnormality degree Ab set by the extraction unit 404. For example, the extraction unit 404 calculates the threshold value Th for each term from the first term to the sixteenth term in the Zernike polynomial. c The calculation formula in this case can be, for example, the same formula as described above.

[0183] The extraction unit 404 converts the calculated threshold value Th to each of the first to sixteenth terms in the Zernike polynomial. c Set as the abnormality judgment threshold Th. In this example, the lower limit of the abnormality judgment threshold Th can also be set in the same way as above. Calculate the threshold Th for RGB respectively c , and set the abnormality judgment threshold Th. In addition, hereinafter, for each of the first to sixteenth terms in the Zernike polynomial, let the abnormality judgment threshold Th with respect to R be Th r1 ~Th r16 , the abnormality judgment threshold Th of G is Th g1 ~Th g16 , the abnormality judgment threshold Th of B is Th b1 ~Th b16 .

[0184] Then, the extraction unit 404 extracts, from among the image pairs acquired by the candidate acquisition unit 401, image pairs that do not have a term (degree) in the Zernike polynomial for which the abnormality degree Ab exceeds the abnormality determination threshold Th, as image pairs for model generation. More specifically, when n is an integer from 1 to 16, the extraction unit 404 extracts, as image pairs for model generation, image pairs that satisfy all of the following conditions (y1) to (y3).

[0185] (y1) For the nth term in the Zernike polynomial, the anomaly Ab rn ≥Threshold Th rn .

[0186] (y2) For the nth term in the Zernike polynomial, the anomaly Ab gn ≥Threshold Th gn .

[0187] (y3) For the nth term in the Zernike polynomial, the anomaly Ab bn ≥Threshold Th bn .

[0188] In the above example, Mahalanobis distance calculations are performed for all colors and all terms in the Zernike polynomials. However, the Mahalanobis distance calculations may be omitted for some colors or some terms. Information on the colors and terms for which the Mahalanobis distance calculations may be omitted is pre-stored in the storage unit 301.

[0189] Figure 21 This is a diagram illustrating another example of a method for calculating the Mahalanobis distance.

[0190] like Figure 21As shown in FIG, the correlation distribution C of the Zernike coefficients of the IN image and the Zernike coefficients of the OUT image may not be concentrated, and it may be impossible to calculate the appropriate Mahalanobis distance, and it may be impossible to appropriately select the image pair for model generation. In this case, the correlation distribution C can be divided into multiple sub-correlation distributions. For example, the correlation distribution C can be divided into Figure 21 Then, when the distance calculation unit 403 calculates the Mahalanobis distance of the captured image pair, it can calculate the Mahalanobis distance between the sub-correlation distribution to which the captured image pair belongs and the point representing the captured image pair.

[0191] The unit for dividing the sub-correlation distributions of the correlation distribution C is, for example, division by each lot of wafers W, each device, or each transport route, that is, by each through module.

[0192] The embodiments disclosed in the specification are merely illustrative in all respects and should not be considered restrictive. The above embodiments may be omitted, replaced, and modified in various ways without departing from the scope of the technical solution and the concept of the present invention.

[0193] In addition, the following structures also belong to the technical scope of the present disclosure.

[0194] (1) A substrate inspection device for inspecting a substrate, comprising:

[0195] an acquisition unit that acquires an estimated image of the inspection target substrate after being processed by the substrate processing apparatus based on an image estimation model and a captured image of the inspection target substrate before being processed by the substrate processing apparatus, wherein the image estimation model is generated by machine learning using the captured images of each of a plurality of substrates before being processed by the substrate processing apparatus and the captured images after being processed; and

[0196] A determination unit determines whether the inspection target substrate has a defect based on a captured image of the inspection target substrate processed by the substrate processing device and the estimated image.

[0197] In (1) above, an image estimation model is generated through machine learning using captured images of multiple substrates before and after processing. This image estimation model is then used to generate a reference image, which serves as a benchmark for defect inspection, to determine whether the substrate being inspected has defects. Because the reference image, which serves as a benchmark for defect inspection, is an estimated image generated based on the image estimation model, the unevenness (plaque) in the captured image and the reference image after processing of the substrate being inspected is approximately the same. Consequently, the likelihood of unevenness being detected as a defect is reduced, thereby improving defect detection accuracy.

[0198] (2) The substrate inspection apparatus according to (1) above, wherein the acquisition unit generates an estimated image of the inspection target substrate processed by the substrate processing apparatus.

[0199] (3) The substrate inspection device according to (1) or (2) above, wherein the judgment unit judges whether the inspection object substrate has defects based on the difference between the captured image of the inspection object substrate processed by the substrate processing device and the estimated image.

[0200] (4) A substrate inspection device according to any one of (1) to (3) above, wherein the judgment unit judges whether the inspection object substrate has defects based on a captured image of the inspection object substrate after being processed by the substrate processing device and an image of the central portion of the substrate in the estimated image.

[0201] By adopting the above (4), defect inspection can be performed more accurately.

[0202] (5) The substrate inspection device according to any one of (2) to (5) above, wherein the image estimation model is a generative network that transforms an arbitrary input image in a conditional generative adversarial network to generate a false image,

[0203] Machine learning of a recognition method is performed on a recognition network in the conditional generative adversarial network, wherein the recognition network takes an arbitrary image and a true image corresponding to the arbitrary image as input, or takes an arbitrary image and a false image generated based on the arbitrary image as input, and is used to identify whether the image input together with the arbitrary image is the true image or the false image, and the machine learning of the recognition method enables the recognition to be performed correctly.

[0204] Machine learning of an image conversion method is performed on the generation network so that the false image can be identified as the true image in the recognition network.

[0205] (6) A substrate inspection system for inspecting a substrate, comprising:

[0206] a substrate processing device for processing a substrate; and

[0207] control device,

[0208] The control device comprises:

[0209] a generating unit for generating an image estimation model through machine learning using the captured images of each of the plurality of substrates before and after processing by the substrate processing device;

[0210] a generating unit configured to generate an estimated image of the inspection target substrate after being processed by the substrate processing apparatus based on a captured image of the inspection target substrate before being processed by the substrate processing apparatus and the image estimation model; and

[0211] A determination unit determines whether the inspection target substrate has a defect based on a captured image of the inspection target substrate processed by the substrate processing device and the estimated image.

[0212] (7) The substrate inspection system according to (6) above, wherein the image estimation model is a generative network that transforms an arbitrary input image in a conditional generative adversarial network to generate a false image,

[0213] Machine learning of a recognition method is performed on a recognition network in the conditional generative adversarial network, wherein the recognition network takes an arbitrary image and a true image corresponding to the arbitrary image as input, or takes an arbitrary image and a false image generated based on the arbitrary image as input, and is used to identify whether the image input together with the arbitrary image is the true image or the false image, and the machine learning of the recognition method enables the recognition to be performed correctly.

[0214] Machine learning of an image conversion method is performed on the generation network so that the false image can be identified as the true image in the recognition network.

[0215] (8) The substrate inspection system according to (6) or (7) above, further comprising a selection unit that selects an image pair for model generation, the image pair being a captured image pair consisting of a combination of a captured image of the substrate before processing and a captured image of the substrate after processing,

[0216] The selection unit selects the pair of captured images for model generation based on the degree of abnormality, wherein the degree of abnormality is determined by the correlation distribution between the in-plane trend of pixel values ​​in the captured image of the substrate before processing and the in-plane trend of pixel values ​​in the captured image of the substrate after processing.

[0217] (9) The substrate inspection system according to (8) above, wherein the selection unit includes:

[0218] a candidate acquisition unit that acquires a plurality of the captured image pairs as candidates for the captured image pairs used for model generation;

[0219] a coefficient calculation unit for decomposing, for each captured image of the substrate included in the acquired captured image pair, a planar distribution of pixel values ​​in the captured image into a plurality of in-plane trend components of the pixel values ​​using Zernike polynomials, and calculating a Zernike coefficient for each in-plane trend component;

[0220] a distance calculation unit that calculates, for each term of a Zernike polynomial, a Mahalanobis distance between the pair of captured images based on a correlation distribution between a Zernike coefficient in the captured image of the substrate before the processing and a Zernike coefficient in the captured image of the substrate after the processing; and

[0221] An extraction unit determines an abnormality degree for each of the captured image pairs based on the Mahalanobis distance, and extracts the captured image pairs for generating the model from the captured image pairs acquired by the candidate acquisition unit based on the abnormality degree.

[0222] (10) The substrate inspection system according to (9) above, wherein the extraction unit,

[0223] For each of the captured image pairs, the Mahalanobis distances calculated by the distance calculation unit for each term of the Zernike polynomial are added to determine the abnormality degree.

[0224] Then, among the captured image pairs acquired by the acquisition unit, image pairs for which the abnormality degree obtained by adding the Mahalanobis distance does not exceed a threshold value are extracted as the captured image pairs for generating the model.

[0225] (11) The substrate inspection system according to (9) above, wherein the abnormality is a Mahalanobis distance calculated by the distance calculation unit for each term of the Zernike polynomial.

[0226] The extraction unit extracts, from among the captured image pairs, a captured image pair that does not have an item in the Zernike polynomial whose abnormality exceeds a threshold value, as the captured image pair for generating the model.

[0227] (12) A substrate inspection method for inspecting a substrate, comprising:

[0228] a step of obtaining a captured image of the inspection target substrate before being processed by the substrate processing device;

[0229] a step of obtaining a captured image of the inspection target substrate after being processed by a substrate processing device;

[0230] a step of obtaining an estimated image of the inspection target substrate after being processed by the substrate processing apparatus based on an image estimation model and a captured image of the inspection target substrate before being processed by the substrate processing apparatus, wherein the image estimation model is generated by machine learning using the captured images of each of a plurality of substrates before being processed by the substrate processing apparatus and the captured images after being processed;

[0231] A step of determining whether the inspection target substrate has defects based on the captured image of the inspection target substrate processed by the substrate processing device and the estimated image.

[0232] (13) The substrate inspection method according to (12) above, wherein the image estimation model is a generative network that transforms an arbitrary input image in a conditional generative adversarial network to generate a false image,

[0233] Machine learning of a recognition method is performed on a recognition network in the conditional generative adversarial network, wherein the recognition network takes an arbitrary image and a true image corresponding to the arbitrary image as input, or takes an arbitrary image and a false image generated based on the arbitrary image as input, and is used to identify whether the image input together with the arbitrary image is the true image or the false image, and the machine learning of the recognition method enables the recognition to be performed correctly.

[0234] Machine learning of an image conversion method is performed on the generation network so that the false image can be identified as the true image in the recognition network.

[0235] (14) An estimation model of a captured image of a substrate used when inspecting the substrate,

[0236] The estimation model,

[0237] The computer is caused to perform the following functions: based on the captured image of the inspection target substrate before being processed by the substrate processing device, the captured image of the inspection target substrate after being processed by the substrate processing device is estimated;

[0238] The estimation model is generated by machine learning based on a conditional generative adversarial network using images of each of the plurality of substrates before and after processing by the substrate processing device.

[0239] The estimation model is a generative network that transforms an arbitrary input image in the conditional generative adversarial network to generate a fake image.

[0240] In the machine learning based on the conditional generative adversarial network, machine learning of the recognition method is performed on the recognition network, wherein the recognition network takes an arbitrary image and a true image corresponding to the arbitrary image as input, or takes an arbitrary image and the false image generated based on the arbitrary image as input, and is used to identify whether the image input together with the arbitrary image is the true image or the false image, and the recognition can be performed correctly through machine learning; and machine learning of the image conversion method is performed on the generation network, so that the false image can be identified as the true image in the recognition network.

[0241] Description of Reference Numerals

[0242] 1. Substrate inspection system

[0243] 20 Overall control device

[0244] 120 Development processing device

[0245] 121 Lower layer film forming device

[0246] 122 Intermediate layer film forming device

[0247] 123 Resist coating device

[0248] 130 Heat treatment device

[0249] 251 Camera Control Device

[0250] 302 Model Generation Department

[0251] 313 Estimated Image Acquisition Unit

[0252] 314 Judgment Department

[0253] Ie estimated image

[0254] IP Photographic Image

[0255] K1, K2, K3 defects

[0256] W wafer.

Claims

1. A substrate inspection device for inspecting a substrate, comprising: an acquisition unit configured to acquire an estimated image of the inspection target substrate after being processed by the substrate processing apparatus based on an image estimation model and a captured image of the inspection target substrate before being processed by the substrate processing apparatus, wherein the image estimation model is generated by machine learning using the captured images of each of a plurality of substrates before being processed by the substrate processing apparatus and the captured images after being processed; a determination unit configured to determine whether the inspection target substrate has a defect based on a captured image of the inspection target substrate processed by the substrate processing device and the estimated image; a generating unit that generates an image estimation model through machine learning using the captured images of each of a plurality of substrates before and after processing by the substrate processing device; and a selection unit configured to select an image pair for model generation, the image pair being a captured image pair consisting of a combination of a captured image of the substrate before processing and a captured image of the substrate after processing; The selection unit selects the pair of captured images for model generation based on the degree of abnormality, wherein the degree of abnormality is determined by the correlation distribution between the in-plane trend of pixel values ​​in the captured image of the substrate before processing and the in-plane trend of pixel values ​​in the captured image of the substrate after processing.

2. The substrate inspection device according to claim 1, wherein: The image estimation model generates an estimated image of the inspection target substrate processed by the substrate processing device.

3. The substrate inspection device according to claim 1 or 2, wherein: The determination unit determines whether the inspection target substrate has a defect based on a difference between a captured image of the inspection target substrate processed by the substrate processing device and the estimated image.

4. The substrate inspection device according to claim 1 or 2, wherein: The determination unit determines whether the inspection target substrate has a defect based on a captured image of the inspection target substrate processed by the substrate processing device and an image of a central portion of the substrate in the estimated image.

5. The substrate inspection device according to claim 1, wherein: The image estimation model is a generative network that transforms any input image in a conditional generative adversarial network to generate a fake image. Machine learning of a recognition method is performed on a recognition network in the conditional generative adversarial network, wherein the recognition network takes as input an arbitrary image and a captured image corresponding to the arbitrary image and captured after substrate processing, or takes as input an arbitrary image and an estimated image generated based on the arbitrary image, and is used to identify whether the image input together with the arbitrary image is the captured image or the estimated image, and the machine learning of the recognition method enables the recognition to be performed correctly. Machine learning of an image conversion method is performed on the generation network so that the estimated image can be recognized as the captured image in the recognition network.

6. The substrate inspection device according to claim 1, wherein: The selection unit includes: a candidate acquisition unit that acquires a plurality of the captured image pairs as candidates for the captured image pairs used for model generation; a coefficient calculation unit for decomposing, for each captured image of the substrate included in the acquired captured image pair, a planar distribution of pixel values ​​in the captured image into a plurality of in-plane trend components of the pixel values ​​using Zernike polynomials, and calculating a Zernike coefficient for each in-plane trend component; a distance calculation unit that calculates, for each term of a Zernike polynomial, a Mahalanobis distance between the pair of captured images based on a correlation distribution between a Zernike coefficient in the captured image of the substrate before the processing and a Zernike coefficient in the captured image of the substrate after the processing; and An extraction unit determines an abnormality degree for each of the captured image pairs based on the Mahalanobis distance, and extracts the captured image pairs for generating the model from the captured image pairs acquired by the candidate acquisition unit based on the abnormality degree.

7. The substrate inspection device according to claim 6, wherein: The extraction part, For each of the captured image pairs, the Mahalanobis distances calculated by the distance calculation unit for each term of the Zernike polynomial are added to determine the abnormality degree. Then, among the captured image pairs acquired by the candidate acquisition unit, image pairs for which the abnormality degree obtained by adding the Mahalanobis distance does not exceed a threshold value are extracted as the captured image pairs for generating the model.

8. The substrate inspection device according to claim 6, wherein: The abnormality degree is the Mahalanobis distance calculated by the distance calculation unit for each term of the Zernike polynomial. The extraction unit extracts, from among the captured image pairs, a captured image pair that does not have an item in the Zernike polynomial whose abnormality exceeds a threshold value, as the captured image pair for generating the model.

9. A substrate inspection system comprising: The substrate inspection device according to claim 1; and A substrate processing device for processing a substrate.

10. A substrate inspection method for inspecting a substrate, comprising: a step of obtaining an estimated image of the inspection target substrate after being processed by the substrate processing device based on an image estimation model and a captured image of the inspection target substrate before being processed by the substrate processing device, wherein the image estimation model is generated by machine learning using the captured images of each of a plurality of substrates before being processed by the substrate processing device and the captured images after being processed; a step of judging whether the inspection target substrate has defects based on the captured image of the inspection target substrate processed by the substrate processing device and the estimated image; a generating step, wherein an image estimation model is generated by machine learning using the captured images of each of a plurality of substrates before and after processing by the substrate processing device; and a selecting step, wherein an image pair for model generation is selected, the image pair being a captured image pair consisting of a combination of a captured image of the substrate before the treatment and a captured image of the substrate after the treatment; In the selection step, the pair of captured images for model generation is selected based on the degree of abnormality, wherein the degree of abnormality is determined by the correlation distribution between the in-plane trend of the pixel values ​​in the captured image of the substrate before processing and the in-plane trend of the pixel values ​​in the captured image of the substrate after processing.

11. The substrate inspection method according to claim 10, wherein: The image estimation model generates an estimated image of the inspection target substrate processed by the substrate processing device.

12. The substrate inspection method according to claim 10 or 11, wherein: In the judging step, whether the inspection target substrate has a defect is judged based on a difference between a captured image of the inspection target substrate processed by the substrate processing device and the estimated image.

13. The substrate inspection method according to claim 10 or 11, wherein: In the judging step, whether the inspection target substrate has a defect is judged based on the captured image of the inspection target substrate processed by the substrate processing device and the image of the substrate center portion in the estimated image.

14. The substrate inspection method according to claim 10, wherein: The selection step includes: a candidate obtaining step of obtaining a plurality of the captured image pairs as candidates for the captured image pairs for model generation; a coefficient calculation step, wherein, for each captured image of the substrate included in the acquired captured image pair, a planar distribution of pixel values ​​in the captured image is decomposed into a plurality of in-plane trend components of the pixel values ​​using Zernike polynomials, and a Zernike coefficient of each in-plane trend component is calculated; a distance calculating step of calculating, for each term of a Zernike polynomial, a Mahalanobis distance between each pair of captured images based on a correlation distribution between a Zernike coefficient in the captured image of the substrate before the processing and a Zernike coefficient in the captured image of the substrate after the processing; and An extraction step of determining an abnormality degree for each of the captured image pairs based on the Mahalanobis distance, and extracting the captured image pairs for generating the model from the captured image pairs acquired in the candidate acquisition step based on the abnormality degree.

15. A computer program product for causing a computer to execute a process for inspecting a substrate. The process of inspecting the substrate includes the following processes: Based on the image estimation model and the captured image of the inspection target substrate before being processed by the substrate processing device, an estimated image of the inspection target substrate after being processed by the substrate processing device is obtained, wherein: The image estimation model is generated by machine learning using the captured images of each of the plurality of substrates before and after processing by the substrate processing device. determining whether the inspection target substrate has defects based on the captured image of the inspection target substrate processed by the substrate processing device and the estimated image; Using the captured images of each of the plurality of substrates before and after processing by the substrate processing device, an image estimation model is generated through machine learning, An image pair for model generation is selected, the image pair being a captured image pair consisting of a combination of a captured image of the substrate before the treatment and a captured image of the substrate after the treatment, The pair of captured images for model generation is selected based on the degree of abnormality, wherein the degree of abnormality is determined by the correlation distribution between the in-plane trend of the pixel values ​​in the captured image of the substrate before processing and the in-plane trend of the pixel values ​​in the captured image of the substrate after processing.

Images