Negative gate stress operation machine storage device in multiple-pass programming

Abstract

A storage device is provided. The storage device includes: an array of arranged memory cells; a plurality of word lines; and a peripheral circuit configured to perform multi-pass programming on the memory cells of a selected row coupled to a selected word line. The multi-pass programming includes a plurality of programming passes. Each programming pass includes a programming operation and a verification operation. To perform the multi-pass programming, the peripheral circuit is configured to: in a non-final programming pass of the memory cells, between the programming operation and the verification operation, perform a negative gate stress (NGS) operation on the memory cells in the memory cells of the selected row; and simultaneously, perform an NGS operation on the memory cells in the memory cells of an unselected row coupled to an unselected word line among the word lines. The unselected word line is adjacent to the selected word line.

Description

BACKGROUND OF THE INVENTION

[0001] The present disclosure relates to a storage device and an operation method thereof.

[0002] A flash memory is a low-cost, high-density, non-volatile solid-state storage medium that can be electrically erased and reprogrammed. The flash memory includes a NOR flash memory and a NAND flash memory. The flash memory can perform various operations, such as reading, programming (writing), and erasing, to change the threshold voltage of each storage cell to a desired level. For a NAND flash memory, an erase operation can be performed at the block level, a programming operation can be performed at the page level, and a reading operation can be performed at the cell level. SUMMARY OF THE INVENTION

[0003] In one aspect, a storage device includes: an array of storage cells arranged in multiple rows; multiple word lines respectively coupled to the multiple rows of storage cells; and a peripheral circuit coupled to the word lines, the peripheral circuit being configured to perform multi-pass programming on the storage cells of a selected row coupled to a selected word line among the word lines. The multi-pass programming includes multiple programming passes. Each programming pass includes a programming operation and a verification operation. To perform the multi-pass programming, the peripheral circuit is configured to: in a non-final programming pass of the storage cells, between the programming operation and the verification operation, perform a negative gate stress (NGS) operation on the storage cells in the selected row of the storage cells; and simultaneously, perform an NGS operation on the storage cells in the storage cells of an unselected row coupled to an unselected word line among the word lines, the unselected word line being adjacent to the selected word line.

[0004] In another aspect, a method for operating a storage device is provided. The storage device includes an array of storage cells arranged in multiple rows and multiple word lines respectively coupled to the multiple rows of storage cells. The method includes performing multi-pass programming on the storage cells of a selected row coupled to a selected word line among the word lines. The multi-pass programming includes multiple programming passes. Each programming pass includes a programming operation and a verification operation. Performing the multi-pass programming includes: in a non-final programming pass of the storage cells, between the programming operation and the verification operation, performing an NGS operation on the storage cells in the selected row of the storage cells. Performing the multi-pass programming further includes: simultaneously, performing an NGS operation on the storage cells in the storage cells of an unselected row coupled to an unselected word line among the word lines, the unselected word line being adjacent to the selected word line.

[0005] In another aspect, a system includes a storage device configured to store data and a memory controller coupled to the storage device and configured to control the storage device. The system includes a storage device configured to store data. The storage device includes: an array of memory cells arranged in multiple rows; multiple word lines respectively coupled to the multiple rows of memory cells; and a peripheral circuit coupled to the word lines, the peripheral circuit being configured to perform multi-pass programming on the memory cells of a selected row coupled to a selected word line among the word lines. The multi-pass programming includes multiple programming passes. Each programming pass includes a programming operation and a verification operation. To perform the multi-pass programming, the peripheral circuit is configured to: in a non-final programming pass of the memory cells, between the programming operation and the verification operation, perform an NGS operation on the memory cells in the selected row of memory cells. To perform the multi-pass programming, the peripheral circuit is configured to: simultaneously, perform an NGS operation on the memory cells in the unselected rows of memory cells coupled to unselected word lines among the word lines, the unselected word lines being adjacent to the selected word line. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] The drawings incorporated herein and constituting a part of this specification illustrate aspects of the present disclosure and, together with the specification, further serve to explain the principles of the present disclosure and enable a person skilled in the relevant art to make and use the present disclosure.

[0007] Figure 1A A block diagram showing an exemplary system having a storage device in accordance with some aspects of the present disclosure.

[0008] Figure 1B A diagram showing an exemplary memory card having a storage device in accordance with some aspects of the present disclosure.

[0009] Figure 1C A diagram showing an exemplary solid state drive (SSD) having a storage device in accordance with some aspects of the present disclosure.

[0010] Figure 2 A block diagram showing an exemplary storage device including an array of memory cells and a peripheral circuit in accordance with some aspects of the present disclosure.

[0011] Figure 3 A schematic circuit diagram showing an exemplary storage device including a peripheral circuit in accordance with some aspects of the present disclosure.

[0012] Figure 4A A cross-section showing an exemplary memory array device in accordance with some aspects of the present disclosure.

[0013] Figure 4B A top view showing a block in an exemplary memory array device in accordance with some aspects of the present disclosure.

[0014] Figure 5A Shows a scheme for multi - pass programming for operating an exemplary memory device in accordance with some aspects of the present disclosure.

[0015] Figure 5B Shows a programming cycle with NGS operation in accordance with some aspects of the present disclosure.

[0016] Figure 5C Shows a programming cycle without NGS operation in accordance with some aspects of the present disclosure.

[0017] Figure 6A Shows NGS operation on memory cells in a string in an exemplary memory array device in accordance with some aspects of the present disclosure.

[0018] Figure 6B Shows, in accordance with some aspects of the present disclosure, in Figure 6A the voltage waveform applied to the word line coupled to the memory cell in the shown NGS operation.

[0019] Figure 7A Shows an exemplary word line priority order in a memory device in accordance with some aspects of the present disclosure.

[0020] Figure 7B Shows an exemplary voltage waveform applied to the word line coupled to the memory cell and the select gate transistor in an exemplary NGS operation in a non - last programming pass with a word line priority order in accordance with some aspects of the present disclosure.

[0021] Figure 7C Shows an exemplary voltage waveform applied to the word line coupled to the memory cell and the select gate transistor in a known NGS operation in accordance with some aspects of the present disclosure.

[0022] Figure 8A Shows an exemplary saw - tooth order in a memory device in accordance with some aspects of the present disclosure.

[0023] Figure 8B Shows an exemplary voltage waveform applied to the word line coupled to the memory cell and the select gate transistor in an exemplary NGS operation in a non - last programming pass with a saw - tooth order in accordance with some aspects of the present disclosure.

[0024] Figure 9 Shows a flowchart of an exemplary method for performing multi - pass programming on memory cells of a selected row in accordance with some aspects of the present disclosure.

[0025] Aspects of the present disclosure will be described with reference to the accompanying drawings. Detailed Description

[0026] Although specific configurations and arrangements have been discussed, it should be understood that this is done for illustrative purposes only. Thus, other configurations and arrangements may be used without departing from the scope of the present disclosure. Moreover, the present disclosure may be used in a variety of other applications. The functional and structural features described in the present disclosure may be combined, adjusted, and modified with each other in ways not specifically depicted in the drawings such that these combinations, adjustments, and modifications are within the scope of the present disclosure.

[0027] Generally, terms may be understood, at least in part, in light of their use in context. For example, depending at least in part on the context, the term "one or more" as used herein may be used to describe any feature, structure, or characteristic in a singular sense or may be used to describe a combination of features, structures, or characteristics in a plural sense. Similarly, depending at least in part on the context, terms such as "a" or "the" may also be understood to convey a singular usage or to convey a plural usage. Additionally, depending at least in part on the context, the term "based on" may be understood to not necessarily be intended to convey a set of exclusive factors and may instead allow for the existence of additional factors that are not necessarily expressly described.

[0028] It should be readily understood that the meanings of "above", "over", and "on" in the present disclosure should be interpreted in the broadest sense such that "above" not only means directly "on" something, but also includes the meaning of being "on" something with intermediate features or layers therebetween, and "over" or "on" not only means the meaning of being "above" or "over" something, but may also include the meaning of being "above" or "over" something with no intermediate features or layers therebetween (i.e., directly on something).

[0029] In addition, for ease of description, spatial relative terms such as "below", "beneath", "lower", "above", "upper", etc. may be used herein to describe the relationship of one element or feature to another element or feature as shown in the figures. In addition to the orientations described in the figures, the spatial relative terms are also intended to cover different orientations of the device during use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein may be interpreted accordingly.

[0030] As used herein, the term "layer" refers to a portion of material that includes a region having a thickness. The layer can extend over the entire underlying or overlying structure, or can have a scope that is less than the scope of the underlying or overlying structure. Additionally, the layer can be a region of a homogeneous or heterogeneous continuous structure, the thickness of which is less than the thickness of the continuous structure. For example, the layer can be located between the top and bottom surfaces of the continuous structure, or between any pair of horizontal planes at the top and bottom surfaces of the continuous structure. The layer can extend horizontally, vertically, and / or along a tapered surface. A substrate can be a layer, can include one or more layers therein, and / or can have one or more layers thereon, above, and / or below. A layer can include multiple layers. For example, an interconnect layer can include one or more conductors and contact layers (in which interconnect lines and / or via contacts are formed) and one or more dielectric layers.

[0031] Charge trapping materials have been used to retain data in NAND flash memories. For example, charge trapping materials can be used in a charge trapping layer in a NAND memory string (e.g., a memory channel). However, charge trapping devices (e.g., a storage device having a charge trapping layer for data retention) may have reliability issues due to the nature of the charge trapping materials.

[0032] A common problem with charge trapping devices is referred to as the fast initial charge loss (or early retention) problem, which is a fast relaxation behavior in which charges escape from the charge trapping layer shortly after a programming operation. This behavior is thought to be caused by shallow trapped charges and can lead to a threshold voltage drift of the storage cell. The drift of the threshold voltage can cause the programming distribution to deteriorate.

[0033] In a NAND flash memory, the intersections of word lines and strings form multiple storage cells. A block includes multiple fingers, and each finger includes a pair of fingers. Each string is coupled to a bit line. The strings in the fingers are coupled to a drain select gate (DSG). The storage cells store data in the form of a threshold voltage, which represents the lowest voltage at which the storage cell can be turned on. For example, the threshold voltage range of a 2-bit multi-level cell (MLC) NAND flash memory storage cell is divided into four regions. The region where the threshold voltage of the storage cell drops represents the current state of the storage cell, which can be an erased (or ER) state and three higher data states. A programming pass can use a set of increasing programming voltages / pulses applied to the word lines coupled to the storage cells to program the storage cells by setting the threshold voltage of the storage cells to a desired state. Each programming voltage / pulse is applied during a programming operation, followed by a verification operation that uses one or more verification voltages to determine whether the storage cells have been programmed. After all the storage cells have been programmed, the data in the storage cells can be read back in a read operation.

[0034] Multiple-pass programming can be used when programming a memory cell. In multiple-pass programming, multiple programming passes are employed successively. Multiple-pass programming can reduce the neighbor word line interference (NWI), which refers to the increase in the threshold voltage of the memory cells connected to a word line when neighboring (adjacent) memory cells (e.g., in the same string and coupled to other word lines) are programmed. Multiple-pass programming can reduce NWI by programming the memory cells to an intermediate threshold voltage distribution in non-final programming passes and programming the memory cells to a final threshold voltage distribution in the final programming pass.

[0035] As described above, the shallow-trapped charges may cause the programming distribution to deteriorate. To solve the problem of the programming distribution deterioration, negative gate stress (NGS) operations have been used in multiple-pass programming to remove at least some of the shallow-trapped charges and tighten the threshold voltage distribution. However, the NGS operation may reduce the read window budget (RWB), i.e., the threshold voltage window between the erased state and the higher data state required for the read operation of the memory cell, so it is not suitable to enable the NGS operation on the memory cell after the memory cell has passed the verification operation. In the NGS operation, different voltage combinations are applied to the memory cells that pass the verification operation immediately before the NGS operation and the memory cells that do not pass the verification operation immediately before the NGS operation, such that the memory cells that pass the verification operation do not experience the NGS operation and only the memory cells that do not pass the verification operation experience the NGS operation. For example, when programming the memory cells row by row, different voltages are applied to the DSG and bit lines coupled to the memory cells that pass and do not pass the verification operation (e.g., in the same row), such that only the memory cells that do not pass the verification operation experience the NGS operation. The operation of the NAND memory may be complex, and the power consumption of the operation may be undesirably high. Sometimes, the distribution of the threshold voltage of the memory cells that have experienced the NGS operation undesirably narrows, thus affecting the read operation.

[0036] The present disclosure provides a novel NGS scheme for multi-pass programming in a memory device, a memory device, and a system thereof. The NGS scheme is enabled in at least one non-final programming pass of the multi-pass programming to remove shallow trapped charges in memory cells that pass and fail the corresponding verification operation immediately before the NGS operation. Different from the known NGS scheme that is enabled only on the memory cells of the selected row, the novel NGS scheme is enabled on the memory cells of two rows simultaneously. In an example, the novel NGS scheme is enabled in the selected row being programmed and the unselected row that was programmed immediately before the memory cells of the selected row. Depending on the direction in which the word line is programmed, the unselected row can be immediately above or below the selected row. In the word line priority order, the memory cells that pass and fail the corresponding verification operation immediately before the NGS operation in the selected row and the unselected row can both undergo the corresponding NGS operation. In the zigzag order, only the memory cells that have not undergone the final programming pass can undergo the corresponding NGS operation. The NGS operation can further remove the shallow trapped charges in the memory cells that have passed the corresponding verification operation and further narrow the distribution of the threshold voltage, thereby increasing the RWB. In the final programming pass of the multi-pass programming, when the memory cells of the selected row are being programmed, the NGS operation is enabled only on the memory cells that fail the corresponding verification operation immediately before the NGS operation, or the NGS operation is not enabled on any memory cells. Therefore, the NGS operation does not reduce the RWB of the memory cells.

[0037] To enable the NGS operation on the memory cells in the selected row being programmed and the unselected row that has been programmed, the source select gates (SSGs) of all the strings where all the memory cells are located are turned off. If the voltage is applied to the word lines in the word line priority order, the same low voltage can be applied to the DSGs of all the strings where all the memory cells in the selected row and the unselected row are located. Therefore, the DSGs of all the strings are turned off. If the voltage is applied to the word lines in the zigzag order, a low voltage can be applied to the DSG of the selected finger where (i) the final programming pass has been performed on the selected finger and at least one memory cell in the selected row and the unselected row fails the corresponding verification operation, or (ii) the final programming pass has not been performed on these memory cells. At the same time, a high positive voltage can be applied to the DSG of the unselected finger where (i) all the memory cells in the selected row and the unselected row have passed the corresponding verification operation, and (ii) these memory cells have undergone the final programming pass. Together with the bit line voltage applied to the corresponding strings in each finger, the selected string and the unselected string can be selected respectively such that the selected string (i.e., the string having the memory cells to undergo NGS in the selected row and the unselected row) will undergo potential boosting, and the unselected string (i.e., the string having no memory cells to undergo NGS in the selected row and the unselected row) is grounded. A relatively high positive voltage (e.g., higher than V DD)Applied above and below the word lines of the memory cells coupled to the selected and unselected rows. The potential of the strings (i.e., all strings for word line priority order and the selected strings for zigzag order) can be raised. Thus, these strings are all in a floating state and the potential in the strings increases. A low voltage is applied to the word lines of the memory cells coupled to the selected and unselected rows, enabling the NGS operation to be performed in the memory cells of both rows and the strings having a potential boost. This can achieve the "erasure" of the shallow trapped charges, enabling these memory cells to further remove the shallow trapped charges. To avoid a reduction in the RWB of the memory cells, a novel NGS scheme is enabled in non-final programming passes. In some embodiments, since a low voltage such as ground or a negative voltage is applied to the DSG of the strings having a potential boost, power consumption can be reduced.

[0038] Figure 1A FIG. 4 shows a block diagram of an exemplary system 100 having a memory device in accordance with some aspects of the present disclosure. System 100 can be a mobile phone, a desktop computer, a laptop computer, a tablet computer, a vehicle computer, a gaming console, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality (VR) device, an augmented reality (AR) device, or any other suitable electronic device having a storage device therein. As Figure 1A shown, system 100 can include a host 108 and a memory system 102 having one or more memory devices 104 and a memory controller 106. Host 108 can be a processor (e.g., a central processing unit (CPU)) or a system-on-chip (SoC) (e.g., an application processor (AP)) of an electronic device. Host 108 can be configured to send data to or receive data from memory device 104.

[0039] Memory device 104 can be any memory device disclosed herein, such as a NAND flash memory device. Consistent with the scope of the present disclosure, memory controller 106 can control multi-pass programming on memory device 104 such that in non-final programming passes of multi-pass programming, the NGS operation is enabled simultaneously on the memory cells of two rows. Peripheral circuits such as word line drivers can apply corresponding voltages to the DSG of each memory string coupled to the selected word line, and can apply a low voltage or a negative voltage to the selected and unselected word lines to enable the NGS operation on all memory cells coupled to two word lines or on a portion of the memory cells coupled to two word lines during non-final programming passes.

[0040] According to some embodiments, the memory controller 106 is coupled to the storage device 104 and the host 108 and is configured to control the storage device 104. The memory controller 106 can manage data stored in the storage device 104 and communicate with the host 108. In some embodiments, the memory controller 106 is designed to operate in a low duty cycle environment, such as a Secure Digital (SD) card, a Compact Flash (CF) card, a Universal Serial Bus (USB) flash drive, or other media used in electronic devices such as personal computers, digital cameras, mobile phones, etc. In some embodiments, the memory controller 106 is designed to operate in a high duty cycle environment, such as a Solid State Drive (SSD) or an embedded multimedia card (eMMC) used as a data storage device for mobile devices such as smartphones, tablets, laptop computers, etc., and enterprise storage arrays. The memory controller 106 can be configured to control operations of the storage device 104, such as read, erase, and program operations. The memory controller 106 can also be configured to manage various functions related to data stored or to be stored in the storage device 104, including but not limited to bad block management, garbage collection, logical-to-physical address translation, wear leveling. In some embodiments, the memory controller 106 is also configured to process an error correction code (ECC) for data read from or written to the storage device 104. The memory controller 106 can also perform any other suitable functions, such as programming the storage device 104. The memory controller 106 can communicate with external devices (e.g., the host 108) according to a specific communication protocol. For example, the memory controller 106 can communicate with external devices through at least one of various interface protocols, such as the USB protocol, the MMC protocol, the Peripheral Component Interconnect (PCI) protocol, the PCI Express (PCI-E) protocol, the Advanced Technology Attachment (ATA) protocol, the Serial ATA protocol, the Parallel ATA protocol, the Small Computer System Interface (SCSI) protocol, the Enhanced Small Disk Interface (ESDI) protocol, the Integrated Drive Electronics (IDE) protocol, the Firewire protocol, etc.

[0041] The memory controller 106 and one or more storage devices 104 can be integrated into various types of storage devices, e.g., included in the same package, such as included in a Universal Flash Storage (UFS) package or an eMMC package. That is, the memory system 102 can be implemented and packaged into different types of end electronic products. In as Figure 1BIn one example shown, the memory controller 106 and a single storage device 104 may be integrated into a memory card 112. The memory card 112 may include a PC card (PCMCIA, Personal Computer Memory Card International Association), a CF card, a Smart Media (SM) card, a Memory Stick, a Multimedia Card (MMC, RS-MMC, MMCmicro), an SD card (SD, miniSD, microSD, SDHC), a UFS, etc. The memory card 112 may also include a memory card connector 114 that couples the memory card 112 to a host (e.g., Figure 1A the host 108 in Figure 1C ). In another example shown in Figure 1A , the memory controller 106 and multiple storage devices 104 may be integrated into an SSD 116. The SSD 116 may also include an SSD connector 118 that couples the SSD 116 to a host (e.g.,

[0042] Figure 2 the host 108 in Figure 3 ). In some embodiments, the storage capacity and / or operating speed of the SSD 116 is greater than that of the memory card 112. Figure 2 and Figure 3 . For ease of illustration, some components in Figure 2 are described together. The peripheral circuit 302 may include

[0043] the page buffer 204, the column decoder / bit line driver 206, the row decoder / word line driver 208, the voltage generator 210, the control logic unit 212, the register 214, and the interface 216 in Figure 3As shown, the memory cell array 202 can be a NAND flash memory cell array, where the memory cells 306 are provided in the form of an array of NAND memory strings 308, and each NAND memory string 308 extends vertically above a substrate (not shown). In some embodiments, each NAND memory string 308 includes a plurality of memory cells 306 coupled in series and vertically stacked. Each memory cell 306 can hold a continuous analog value, such as a voltage or a charge, depending on the number of electrons trapped within the region of the memory cell 306. Each memory cell 306 can be a floating-gate type of memory cell including a floating-gate transistor, or a charge-trapping type of memory cell including a charge-trapping transistor.

[0044] In some embodiments, each memory cell 306 is a single-level cell (SLC) having two possible storage states and thus can store one bit of data. For example, a first storage state "0" can correspond to a first voltage range, and a second storage state "1" can correspond to a second voltage range. In some embodiments, each memory cell 306 is a multi-level cell (MLC) capable of storing more than one data bit with more than four storage states. For example, an MLC can store two bits per cell, three bits per cell (also referred to as a triple-level cell (TLC)), or four bits per cell (also referred to as a quad-level cell (QLC)). Each MLC can be programmed to assume a range of possible nominal storage values. In one example, if each MLC stores two bits of data, the MLC can be programmed from an erased state to assume one of three possible programmed levels by writing one of three possible nominal storage values to the cell. A fourth nominal storage value can be used for the erased state.

[0045] As Figure 3As shown, each NAND memory string 308 can include an SSG 310 at its source extreme and a DSG 312 at its drain extreme. The SSG 310 and DSG 312 are the gate electrodes of the SSG transistor and DSG transistor respectively, and can be configured to activate the selected NAND memory string 308 (a column of the array) during read and program operations. In some embodiments, the SSGs 310 of the NAND memory strings 308 in the same block 304 are coupled to, for example, ground through the same source line (SL) 314 (e.g., a common SL). According to some embodiments, the DSG 312 of each NAND memory string 308 is coupled to a corresponding bit line 316, and data can be read from the corresponding bit line 316 via an output bus (not shown). In some embodiments, each NAND memory string 308 is configured to be selected or deselected by applying a select voltage (e.g., higher than the threshold voltage of the transistor having the DSG 312) or a deselect voltage (e.g., 0V) to the corresponding DSG 312 through one or more DSG lines 313, and / or by applying a select voltage (e.g., higher than the threshold voltage of the transistor having the SSG 310) or a deselect voltage (e.g., 0V) to the corresponding SSG 310 through one or more SSG lines 315.

[0046] As Figure 3 shown, the NAND memory strings 308 can be organized into multiple blocks 304, and each block 304 can have a common source line 314. In some embodiments, each block 304 is a basic data unit for an erase operation, i.e., all the memory cells 306 on the same block 304 are erased simultaneously. The memory cells 306 of adjacent NAND memory strings 308 can be coupled by a word line 318, and the word line 318 selects which row of memory cells 306 is subject to read and program operations. In some embodiments, each word line 318 is coupled to a page 320 of the memory cells 306, and the page 320 is a basic data unit for a program operation. The size (in bits) of a page 320 can correspond to the number of NAND memory strings 308 coupled by the word line 318 in a block 304. Each word line 318 can include multiple control gates (gate electrodes) at each memory cell 306 in the corresponding page 320, and can include a gate line for coupling the control gates.

[0047] The peripheral circuit 302 can be coupled to the memory cell array 202 via bit lines 316, word lines 318, source lines 314, SSG lines 315, and DSG lines 313. The peripheral circuit 302 can apply voltages on the bit lines 316, word lines 318, source lines 314, SSG lines 315, and DSG lines 313 to perform multi-pass programming including the proposed NGS scheme in non-final programming passes. As described above, the peripheral circuit 302 can include any suitable circuitry for facilitating the operation of the memory cell array 202 by applying voltage signals and / or current signals to each target memory cell 306 via the bit lines 316 and sensing voltage signals and / or current signals from each target memory cell 306 via the word lines 318, source lines 314, SSG lines 315, and DSG lines 313. The peripheral circuit 302 can include various types of peripheral circuits formed using MOS technology.

[0048] Figure 4A A cross-section of an exemplary memory cell array 202 in accordance with some aspects of the present disclosure is shown. As Figure 4A shown, the memory cell array 202 includes NAND memory strings 410, which can be an example of the NAND memory strings 308 in Figure 3 and extend vertically above the substrate 402. The substrate 402 can include silicon (e.g., single-crystalline silicon), silicon germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon-on-insulator (SOI), germanium-on-insulator (GOI), or any other suitable material. Note that in Figure 4A the x, y, and z axes are included to further illustrate the spatial relationship of the components in the memory cell array 202. The substrate 402 includes two lateral surfaces (e.g., a top surface and a bottom surface) that extend laterally in the x direction (i.e., the lateral direction). As used herein, when a substrate (e.g., the substrate 402) is in the lowest plane of a semiconductor structure (e.g., the memory cell array 202) in the z direction (i.e., the vertical direction or the depth direction), whether a component of the semiconductor structure is "on", "above", or "below" another component in the z direction is determined relative to the substrate of the semiconductor structure. Throughout the present disclosure, the same concept for describing spatial relationships is applied.

[0049] As Figure 4AAs shown, the NAND memory string 410 extends vertically through the memory stack layer 404 having interleaved gate conductive layers 406 and gate-to-gate dielectric layers 408 over the substrate 402. The gate conductive layers 406 and the gate-to-gate dielectric layers 408 in the memory stack layer 404 may alternate in the vertical direction. Each gate conductive layer 406 may include a conductive material including, but not limited to, tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polysilicon, doped silicon, silicide, or any combination thereof. In some embodiments, each gate conductive layer 406 includes a metal layer, such as a tungsten layer. In some embodiments, each gate conductive layer 406 includes a doped polysilicon layer. Each gate conductive layer 406 may include a control gate surrounding a memory cell (e.g., Figure 3 the memory cell 306 in Figure 3 ), a DSG (e.g., Figure 3 the DSG 312 in Figure 3 ), or an SSG (e.g., Figure 3 the SSG 310 in Figure 3 ), and may extend laterally as a DSG line (e.g., Figure 3 the DSG line 313 in Figure 3 ) at the top of the memory stack layer 404, an SSG line (e.g., Figure 3 the SSG line 315 in Figure 3 ) at the bottom of the memory stack layer 404, or a word line (e.g., Figure 3 the word line 318 in Figure 3 ) between the DSG line and the SSG line.

[0050] As Figure 4A shown, the NAND memory string 410 includes a channel structure 412 that extends vertically through the memory stack layer 404. In some embodiments, the channel structure 412 includes a channel hole filled with a semiconductor material (e.g., as a semiconductor channel 420) and a dielectric material (e.g., as a memory film 418). In some embodiments, the semiconductor channel 420 includes silicon, such as amorphous silicon, polysilicon, or single-crystalline silicon. In some embodiments, the memory film 418 is a composite dielectric layer including a tunneling layer 426, a storage layer 424 (also referred to as a "charge trapping / storage layer"), and a blocking layer 422. The channel structure 412 may have a cylindrical shape (e.g., a columnar shape). According to some embodiments, the semiconductor channel 420, the tunneling layer 426, the storage layer 424, and the blocking layer 422 are arranged radially from the center of the column toward the outer surface of the column in this order. The tunneling layer 426 may include silicon oxide, silicon oxynitride, or any combination thereof. The storage layer 424 may include silicon nitride, silicon oxynitride, silicon, or any combination thereof. The blocking layer 422 may include silicon oxide, silicon oxynitride, a high dielectric constant (high-k) dielectric, or any combination thereof. In one example, the memory film 418 may include a composite layer of silicon oxide / silicon oxynitride / silicon oxide (ONO).

[0051] In some embodiments, the NAND memory string 410 further includes a semiconductor plug 414 in a lower portion (e.g., at the lower end) of the NAND memory string 410. The semiconductor plug 414 may include a semiconductor material such as single-crystalline silicon, which epitaxially grows from the substrate 402 in any suitable direction. The semiconductor plug 414 may be used as a part of the channel of the source select transistor of the NAND memory string 410 (e.g., Figure 3 the source select transistor having the SSG 310 in Figure 3 ). In some embodiments, the NAND memory string 410 further includes a channel plug 416 in an upper portion (e.g., at the upper end) of the NAND memory string 410. In some embodiments, the channel plug 416 may be used as the channel of the drain select transistor of the NAND memory string 410 (e.g., Figure 3 the drain select transistor having the DSG 312 in

[0052] Figure 4B ). As used herein, when the substrate 402 is in the lowest plane of the memory cell array 202, the upper end of a component (e.g., the channel structure 412) is the end that is farther from the substrate 402 in the z direction, and the lower end of a component (e.g., the channel structure 412) is the end that is closer to the substrate 402 in the z direction.

[0052] Figure 4B A top view of a portion of the memory cell array 202 according to some embodiments is shown, which includes a block 434, and a plurality of NAND memory strings 410 are located in the block 434. Multiple passes of programming may be performed to program the threshold voltages of the memory cells in the block 434 to higher data states. The block 434 may be Figure 3 an example of the block 304 in the memory cell array 202 shown. As Figure 4B shown, in the xy plane, the block 434 is located between a pair of gate line slots (GLS) 432 in the memory cell array 202. One or more (e.g., a pair of) GLSs 432 may further divide the block 434 into a plurality of finger portions 436A and 436B. Source contact (not shown) structures may be located in each GLS 432 and electrically coupled to the source line 314. The DSG cut 428 may be located in the upper portion of the block 434 and divide the block 434 into a pair of finger portions 436A and 436B. Each finger portion 436A / 436B may include a plurality of NAND memory strings 410 arranged in the x direction and the y direction. In some embodiments, the source contact structures each include an insulating spacer and a conductive material in the insulating spacer. The insulating spacer may include a suitable dielectric material, such as silicon oxide, and the conductive material may include W, Co, Al, Cu, polysilicon, silicide, etc. In some embodiments, the DSG cut 428 extends in the x direction and includes a suitable dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof.

[0053] In some embodiments, the same voltage is applied to the DSG (e.g., DSG 312) of the NAND memory strings 410 in the same finger via a DSG line (e.g., DSG line 313). In some embodiments, the DSG of the NAND memory strings 410 in each finger can be separately controlled by applying corresponding voltages via the respective DSG lines. During a programming pass, the memory cells (e.g., memory cell 306) coupled to the same word line (e.g., word line 318) in block 434 can be simultaneously applied with the same programming voltage / pulse and verification voltage. In some embodiments, the same voltage is applied to the SSG (e.g., SSG 310) of the NAND memory strings 410 in block 434 via an SSG line (e.g., SSG line 315). In some embodiments, each NAND memory string 410 is applied with a corresponding voltage via a respective bit line (e.g., bit line 316). To perform multiple-pass programming on the NAND memory strings 410 in block 434, the control logic unit 212 can control each peripheral circuit 302 to apply corresponding voltages. Details are shown below.

[0054] Return reference Figure 2 , the page buffer 204 can be configured to read data from the memory cell array 202 and program data into the memory cell array 202 according to the control of the control logic unit 212. In one example, the page buffer 204 can store a page of programming data (write data) in a page 320 to be programmed into the memory cell array 202. In another example, the page buffer 204 also performs a verification operation to ensure that the data has been correctly programmed into the memory cells 306 coupled to the selected word line 318.

[0055] The row decoder / word line driver 208 can be configured to be controlled by the control logic unit 212. The row decoder / word line driver 208 can select / deselect the blocks 304 of the memory cell array 202 and the word lines 318 (pages 320) of the selected blocks 304. The row decoder / word line driver 208 can also be configured to drive the selected word lines 318 with word line voltages generated from the voltage generator 210. The row decoder / word line driver 208 can also be configured to select the fingers of the blocks 304. The voltage generator 210 can be configured to be controlled by the control logic unit 212 and generate word line voltages (e.g., read voltage, programming voltage, pass voltage, local voltage, and verification voltage) to be supplied to the memory cell array 202. The column decoder / bit line driver 206 can be configured to be controlled by the control logic unit 212 and select one or more NAND memory strings 308 by applying bit line voltages generated from the voltage generator 210. For example, the column decoder / bit line driver 206 can apply column signals for selecting a set of N-bit data to be output in a read operation from the page buffer 204.

[0056] The control logic unit 212 may be coupled to or disposed in each peripheral circuit 302 and is configured to control the operation of the peripheral circuit 302. For example, the control logic unit 212 may control the peripheral circuit 302 to perform multi-pass programming, which includes the disclosed NGS scheme in non-final programming passes. The register 214 may be coupled to the control logic unit 212 and includes status registers, command registers, and address registers for storing status information, command operation codes (OP codes), and command addresses for controlling the operation of each peripheral circuit 302. The interface 216 may be coupled to the control logic unit 212 and serves as a control buffer to buffer control commands received from a host (not shown) and forward them to the control logic unit 212, as well as buffer status information received from the control logic unit 212 and forward it to the host. The interface 216 may also be coupled to the memory controller 106 and serves as an I / O interface and data buffer to buffer programming data received from the memory controller 106 and forward it to the control logic unit 212.

[0057] Figure 5A An exemplary multi-pass programming 500 applied to a selected word line (e.g., word line 318) of block 304 (or block 434) is shown in accordance with some embodiments. Figure 5B An exemplary programming loop 506 including NGS operations in a non-final programming pass 502 of the multi-pass programming 500 is shown in accordance with some embodiments. Figure 5C An exemplary programming loop 508 without NGS operations in a final programming pass 504 of the multi-pass programming 500 is shown in accordance with some embodiments.

[0058] Figure 5AShows an example of the voltage applied to a memory cell coupled to a selected word line in a multi-pass programming 500 according to an embodiment of the present disclosure. The multi-pass programming 500 may include one or more non-final pass programming 502 and a final programming pass 504. For example, the multi-pass programming 500 may be a two-pass programming including a first / non-final programming pass 502 and a second / final programming pass 504. Each programming pass may include one or more programming cycles. For example, the non-final programming pass 502 may include a plurality of programming cycles 506, and the final programming pass 504 may include a plurality of programming cycles 508. Each programming cycle 506 / 508 may include a programming voltage / pulse applied by a programming operation, and one or more verification voltages applied by a verification operation. The programming operation may apply a programming voltage on the selected word line to program the memory cells in the selected word line to a data state. In some embodiments, the amplitude of the programming voltage is gradually increased using a fixed or variable step size in one or more programming cycles of the programming pass. In some embodiments, in incremental step pulse programming (ISPP), the programming voltage starts at an initial level and steps up in each successive programming cycle until the programming pass is completed. The verification operation may apply one or more verification voltages on the selected word line to test whether the threshold voltage of the memory cells in the selected word line has been programmed to the desired data state. It should be noted that the actual amplitudes of the programming voltage and the verification voltage are not limited by the embodiments of the present disclosure. Although the programming voltage in the programming pass 504 is shown to be higher than the programming voltage in the programming pass 502 in Figure 5A , depending on the operation, the programming voltage in the programming pass 504 may also be less than or equal to the programming voltage in the programming pass 502.

[0059] Figure 5B Shows an example of the voltage applied to a selected word line in the programming cycle 506 according to an embodiment of the present disclosure. In some embodiments, the programming cycle 506 includes a programming operation 510, an NGS operation 512 after the programming operation 510, and a verification operation 514 after the NGS operation 512. In the programming operation 510, a programming voltage V PGM1 may be applied on the selected word line so that the threshold voltage of the memory cell coupled to the selected word line is assigned to a higher data state. By applying a low voltage V L on the selected word line, the NGS operation 512 can then be enabled on all memory cells coupled to the selected word line. The details of the NGS operation 512 are described below in Figure 6A and Figure 6B . In some embodiments, the verification operation 514 is performed after the NGS operation 512 to test whether the threshold voltage of the memory cells assigned to the higher data state reaches the verification voltage V R1 (e.g., an intermediate verification voltage), as shown in Figure 5Bas shown

[0060] Figure 5C illustrates an example of the voltage applied to a selected word line in programming cycle 508 according to an embodiment of the present disclosure. In some embodiments, programming cycle 508 includes a programming operation 520 and a verification operation 524 after the programming operation 520. According to some embodiments, no NGS operation is performed in any programming cycle 508. In some embodiments, as Figure 5C shown, the NGS operation is prohibited on all memory cells in programming cycle 508. In programming operation 520, a programming voltage V PGM2 can be applied to the selected word line to cause the threshold voltages of the memory cells coupled to the selected word line to be assigned to a higher data state and / or have a narrower distribution. In some embodiments, a verification operation 524 is performed after the programming operation 520 to test whether the threshold voltages of the memory cells assigned to the higher data state reach a verification voltage V R2 (e.g., a final verification voltage), as Figure 5C shown. In some embodiments, although not shown, the NGS operation is selectively enabled only on the memory cells coupled to the selected word line and that have not passed the corresponding verification operation immediately before the NGS operation.

[0061] The non-final programming pass 502 may or may not be the first programming pass in the multi-pass programming 500. If the non-final programming pass 502 is not the first programming pass, the memory cells coupled to the selected word line may include the memory cells that have passed the corresponding verification operation before the non-final programming pass 502, and the memory cells that have not passed the corresponding verification operation before the non-final programming pass 502. If the non-final programming pass 502 is the first programming pass, all the memory cells coupled to the selected word line may be regarded as not having passed the corresponding verification operation before the non-final programming pass 502. According to the present disclosure, all the memory cells coupled to the selected word line may undergo the NGS operation in the non-final programming pass 502. However, in known multi-pass programming, in the non-final programming pass 502, only the memory cells that have not passed the corresponding verification operation before the non-final programming pass 502 are selected to undergo the corresponding NGS operation, while the NGS operation is prohibited in the memory cells that have passed the corresponding verification operation before the non-final programming pass 502.

[0062] Figure 6A illustrates a memory string 600 in an exemplary NGS operation according to some embodiments of the present disclosure. Figure 6B illustrates an example of the voltage applied to a selected word line in programming cycle 506 according to some embodiments of the present disclosure. For ease of illustration, Figure 6A and Figure 6B are described together.

[0063] AsFigure 6A As shown, the memory string 600 may include, for example, a plurality of memory cells arranged in the z - direction at respective cell depths. Each memory cell may be coupled to a respective word line. For ease of illustration, memory cell 602 is coupled to a selected word line 610 (e.g., 318), memory cell 603 is coupled to an unselected word line 611 adjacent to the selected word line 610, and the other memory cells 608 are all coupled to an unselected word line 612. The memory string 600 may also include a DSG transistor 604 at the upper end and an SSG transistor 606 at the lower end. The DSG transistor 604 has a DSG (e.g., 312) coupled to a DSG line 614, and the SSG transistor 606 has an SSG (e.g., 310) coupled to an SSG line 616. The DSG, SSG, selected word line 610, DSG line 614, and SSG line 616 may be Figure 3 respective examples of the DSG 312, SSG 310, selected word line 318, DSG line 313, and SSG line 315 shown.

[0064] For each programming pass 502 and 504, the word lines 612, 611, and 610 in the same block (e.g., block 304) may be sequentially applied corresponding voltages in the z - direction (e.g., in the direction from the SSG transistor 606 to the DSG transistor 604 and vice versa), from bottom to top or from top to bottom. In the example, the word lines 612, 611, and 610 are programmed from bottom to top in the z - direction, and the word line 611 is located directly below the word line 610. In some embodiments, the memory cell 603 is programmed before the memory cell 602, although the multi - pass programming may not be completed in the memory cell 603 before starting the multi - pass programming in the memory cell 602. When performing a programming cycle 506 on the word line 610, the programming operation 510 may include applying a programming voltage V PGM1 to the word line driver of (e.g., Figure 2 208 in). The threshold voltage of the memory cell (e.g., memory cell 602) coupled to the word line 610 may be programmed to a higher data state. After the programming operation 510, an NGS operation 512 may be enabled on some or all of the memory cells (e.g., memory cell 602) coupled to the word line 610 (details are provided below). The NGS operation 512 may include a word line driver that applies a low voltage V L to the word line 610, and a high voltage V P to the word line 612. The low voltage V L may be V SS / GND or a negative voltage applied to the memory cell (e.g., memory cell 602) coupled to the word line 610. The high voltage V Pcan be a positive voltage high enough to keep the memory cell 608 turned on during the NGS operation 512. In some embodiments, V P is higher than V DD . After the NGS operation 512, a verify operation 514 can be performed on the memory cells (e.g., memory cell 602) coupled to the word line 610. The verify operation 514 can include a word line driver that applies a verify voltage V R1 on the word line 610 to test whether the threshold voltage of any memory cell coupled to the word line 610 has been successfully programmed to a higher data state.

[0065] The NGS operation 512 can be used as a "shallow etch" to remove at least some of the shallow trapped charges in all of the memory cells (e.g., memory cell 602) coupled to the word line 610. Specifically, to enable the NGS operation 512 on the memory cell 602, the memory string 600 in which the memory cell 602 is located is configured to be in a "floating" state and subjected to a potential boost, where the potential of the memory string 600 increases. In the present disclosure, to set the memory string 600 to the "floating" state, both the DSG transistor 604 and the SSG transistor 606 are turned off. Specifically, the value of V L is low enough to ensure that the value of the voltage on the DSG line 614 minus the voltage on the bit line (e.g., 316) is lower than the threshold voltage of the DSG transistor 604. Thus, the DSG transistor 604 is turned off for both memory cells that have passed and failed the verify operation. In this way, the NGS operation can be enabled on both memory cells that have passed and failed the verify operation. Different from known NGS operations that are only enabled on memory cells coupled to a selected word line and that have failed the corresponding verify operation, when programming the word line 610 in the programming loop 506, the NGS operation 512 is enabled on all memory cells coupled to the selected word line (e.g., word line 610).

[0066] In the present disclosure, the NGS operation 512 can be enabled on both the memory cells 602 and 603 simultaneously. That is, although the memory cell 603 can be programmed before the memory cell 602 and / or the memory cell 603 can undergo the corresponding NGS operation before the memory cell 602, when the NGS operation 512 is enabled on the memory cell 602, the memory cell 603 may also undergo the corresponding NGS operation (e.g., 512) simultaneously with the memory cell 602. In some embodiments, a low voltage V LSince the storage string 600 is in a "floating" state, the memory cell 603 can also undergo a shallow etch to further remove at least some of the shallowly trapped charge in the memory cell 603. In some embodiments, at least all of the memory cells that are coupled to the word lines 610 and 611 and are in the same finger simultaneously undergo the NGS operation.

[0067] Return reference Figure 4B , by way of example, the storage string 600 can be located in the finger 436B. In some embodiments, the same voltage is applied to the DSG transistors of all of the NAND storage strings 410 in the same finger (e.g., 436A or 436B). The memory cell 602 may or may not pass the corresponding verification operation immediately prior to the NGS operation 512. If the memory cell 602 passes the verification operation, then in some embodiments, in order to enable the NGS operation 512 on the memory cells 602 and 603, the storage string 600 is set to "floating" by applying a turn-off voltage to the DSG transistor 604 via the DSG line 614 of the corresponding finger, applying a cut-off voltage to the SSG transistor 606 via the SSG line 616 of the corresponding finger, and applying a low voltage to the bit line (not shown) coupled to the storage string 600. If the memory cell 602 does not pass the verification operation, then in some embodiments, in order to enable the NGS operation 512 on the memory cells 602 and 603, the storage string 600 is set to "floating" by applying a turn-off voltage to the DSG transistor 604 via the DSG line 614 of the corresponding finger, applying a cut-off voltage to the SSG transistor 606 via the SSG line 616 of the corresponding finger, and applying a high voltage to the bit line (not shown) coupled to the storage string 600. That is, when the word line 610 is selected for programming, even if the finger 436B includes a memory cell that is coupled to the word line 610 and does not pass the corresponding verification operation immediately prior to the NGS operation 512, the DSG transistors 604 of all of the storage strings in the finger 436B are turned off to enable the NGS operation 512 in at least some of the memory cells (e.g., including the memory cells 602 and 603) that are coupled to the word lines 610 and 611. In some embodiments, the turn-off voltage includes a low voltage or a negative voltage, and the turn-on voltage includes a positive voltage. In some embodiments, the turn-off voltage is V SS / GND, and the turn-on voltage is V DD . At the same time, the low voltage V L can be applied to the memory cells 602 and 603 via the word lines 610 and 611, respectively, and the high voltage V P can be applied to the memory cell 608 via the word line 612. In some embodiments, the low voltage V L includes one of V SS and a negative voltage, and the high voltage V P includes a voltage higher than VDD a positive voltage.

[0068] As Figure 6A and Figure 4B shown, memory cells 602 and 603 are in the same memory string 600 and the same finger 436B. For memory cells in different fingers, depending on the programming order, the voltage applied to the DSG transistors of the finger can vary. Figure 7A - Figure 7C shows an exemplary waveform of the word line priority order and the voltages employed in the word line priority order. Figure 8A , Figure 8B and Figure 7C shows an exemplary waveform of the zigzag order and the voltages employed in the zigzag order.

[0069] Figure 7A shows the word line priority order in which the non-last programming pass 502 and the last programming pass 504 are performed. Figure 7B shows an exemplary waveform of the voltages applied to certain elements of the memory string 600 in the NGS operation 512 in the programming cycle 506 according to some embodiments. Figure 7C shows the waveform of the voltages applied to certain elements of the memory string 600 in the NGS operation in the programming cycle 508 according to some embodiments. In various embodiments, Figure 7B the voltages shown in Figure 7C are applied in the non-last programming pass, and Figure 5C the voltages shown in

[0070] As Figure 7A shown, the word line priority order includes an order in which the memory cells in adjacent fingers of a single row are programmed sequentially (e.g., one after another), and the memory cells of adjacent rows are programmed in a staggered manner. In Figure 7AIn it, "finger portion 0" - "finger portion 5" represent six finger portions arranged in a storage device. Finger portion 0 and finger portion 1 may be examples of finger portions 436A and 436B of a memory cell array, respectively. "WL#" represents the serial number of a word line. For example, WL0 represents the word line at the bottom (e.g., the 0th word line, immediately above the SSG), WL1 represents the word line immediately above the 0th word line (e.g., the 1st word line), WL2 represents the word line immediately above the 1st word line (e.g., the 2nd word line),..., WL64 represents the word line at the top (e.g., the 63rd word line, immediately below the DSG). In some embodiments, the word lines are programmed from the 0th word line to the 1st word line. As an example, multi-pass programming is two-pass programming having a first pass programming (e.g., non-final programming pass) and a second pass programming (e.g., final programming pass). The memory cells in finger portions 0–finger portion 6 all undergo a corresponding first pass programming and a corresponding second pass programming. In Figure 7A it, "the 1st" represents the serial number of the first pass programming, and "the 2nd" represents the serial number of the second pass programming.

[0071] In some embodiments, the memory cells of the 0th row (i.e., the memory cells coupled to the 0th word line) are sequentially programmed from finger portion 0 to finger portion 5 to undergo the first pass programming (e.g., 502). The order in which the finger portions are programmed is shown as serial numbers 0-5. Then, the memory cells of the 1st row (i.e., the memory cells coupled to the 1st word line) are sequentially programmed from finger portion 0 to finger portion 5 to undergo the first pass programming. The order in which the finger portions are programmed is shown as serial numbers 6-11. Then, the memory cells of the 1st row are sequentially programmed from finger portion 0 to finger portion 5 to undergo the second pass programming (e.g., 504). The order in which the finger portions are programmed is shown as serial numbers 12-17. Then, the memory cells of the 2nd row (i.e., the memory cells coupled to the 2nd word line) are sequentially programmed from finger portion 0 to finger portion 5 to undergo the first pass programming (e.g., 502). The order in which the finger portions are programmed is shown as serial numbers 18-23. Then, the memory cells of the 1st row are sequentially programmed from finger portion 0 to finger portion 5 to undergo the second pass programming. The order in which the finger portions are programmed is shown as serial numbers 24-29. Then, the memory cells of the 3rd row (i.e., the memory cells coupled to the 3rd word line) are sequentially programmed from finger portion 0 to finger portion 5 to undergo the first pass programming. The order in which the finger portions are programmed is shown as serial numbers 30-35. Then, the memory cells of the 2nd row are sequentially programmed from finger portion 0 to finger portion 5 to undergo the second pass programming. The order in which the finger portions are programmed is shown as serial numbers 36-41. As described above, the memory cells coupled to the remaining word lines can be repeatedly programmed in the word line priority order until the memory cells coupled to the 63rd word line undergo the second pass programming.

[0072] As an example, the second word line can be a selected word line, similar to 610, and among finger portions 0 to 5, the memory cells coupled to the second word line can be the memory cells of the selected row. The first word line can be an unselected word line similar to 611. When the memory cells of the selected row are undergoing the first pass of programming, all the memory cells in the row coupled to the first word line have undergone the first pass of programming but not the second pass of programming. For example, the memory cell in finger portion 0 and coupled to the second word line may first undergo the first pass of programming (sequence number 18), the memory cell in finger portion 1 and coupled to the second word line may then undergo the first pass of programming (sequence number 19), the memory cell in finger portion 0 and coupled to the first word line may then undergo the second pass of programming (sequence number 24), the memory cell in finger portion 1 and coupled to the first word line may then undergo the second pass of programming (sequence number 25), the memory cell in finger portion 0 and coupled to the second word line may then undergo the second pass of programming (sequence number 36), and the memory cell in finger portion 1 and coupled to the second word line may then undergo the second pass of programming (sequence number 37). That is, when the memory cells of the selected row are undergoing the first pass of programming, the memory cells of the unselected row immediately below the selected row have not undergone the second pass of programming. In some embodiments, when the memory cells coupled to the second word line are undergoing the NGS operation, the memory cells coupled to the first word line also undergo the NGS simultaneously.

[0073] Figure 7B and Figure 7C shows the voltage waveforms applied to the DSG line 614 and word lines 610, 611, and 612 during the first pass of programming and the second pass of programming. The NGS operation can be enabled in stages 700 and 701 respectively. In some embodiments, in stages 700 / 701, the DSG line 614 and word lines 610, 611, and 612 rise from an initial voltage to corresponding voltages such that the NGS operation can be enabled. WLn represents the selected word line being programmed. WLn+1 represents the word line immediately above WLn in the z direction. WL(above) represents all the other word lines above WLn+1. WLn-1 represents the word line immediately below WLn in the z direction, for example, the unselected word line according to the example in Figure 6A The DSG(sel) represents the voltage waveform applied to the DSG of the finger portion having a memory cell that is coupled to WLn and has not passed the corresponding verification operation immediately before the NGS operation. The DSG(unsel) represents the voltage waveform applied to the DSG of the finger portion having a memory cell that is coupled to WLn and has all passed the corresponding verification operation immediately before the NGS operation.

[0074] As Figure 7BAs shown, in stage 700, WLn (e.g., 610) is programmed and a low voltage is applied. The DSG line 614 can be applied with a low voltage so that the DSG transistors of all the memory strings in the finger can be turned off. In some embodiments, the DSG transistors of all the fingers (e.g., finger 0 - finger 5) coupled to WLn are turned off. In some embodiments, the low voltage is V SS / GND. At the same time, high voltages are applied to the other word lines 612 (e.g., WL (above), WLn + 1, WL (below)) above and below WLn and WLn - 1. In some embodiments, the other word lines are applied with a positive voltage of V P . In some embodiments, V P is higher than V DD .

[0075] Different from the NGS operation 512, the NGS operation shown in Figure 7C can be enabled only on the memory cells coupled to WLn and not passing through the corresponding verification operation immediately before the NGS operation. For example, if the memory cell 602 does not pass the verification operation, a voltage V DSG_P_L can be applied to the DSG line 614; and if the memory cell 602 passes the verification operation, a voltage V DSG_P_L can be applied to the DSG line 614. In some embodiments, both V DSG_P_L and V DSG_P_H are positive voltages, and V DSG_P_H is higher than V DSG_P_L . As described above, in the NGS operation, a high voltage, such as V DD , can be applied to the bit line of the memory string of the memory cell coupled to WLn and not passing through the verification operation; and a low voltage, such as V SS , can be applied to the bit line of the memory string of the memory cell in the selected word line and all passing through the verification operation. The value of V DSG_P_L minus V DD is lower than the threshold voltage of the DSG transistor, so that the DSG transistor is turned off, thereby enabling the NGS operation on the memory cell coupled to the word line 610 and not passing through the corresponding verification operation. The value of V DSG_P_H minus V DD is higher than the threshold voltage of the DSG transistor, so that the DSG transistor is turned on, thereby prohibiting the NGS operation on the memory cell coupled to the word line 610 and passing through the corresponding verification operation.

[0076] Figure 8A shows the sawtooth order in which the non - last programming pass 502 and the last programming pass 504 are executed. Figure 8BAn exemplary waveform of the voltage applied to certain elements of a memory string 600 during an NGS operation 512 in a programming cycle 506 according to some embodiments is shown. The NGS operation in programming cycle 508 may include the same voltage waveform as that shown in Figure 7C and will not be described in detail again herein. In various embodiments, Figure 8B the voltage shown in is applied during a non-final programming pass, and Figure 7C the voltage shown in may be applied during a non-final programming pass or a final programming pass. In some embodiments, the NGS operation is prohibited in programming cycle 508, return to reference Figure 5C and the related description.

[0077] As Figure 8A shown, the zigzag order includes an order in which the memory cells in adjacent rows are programmed sequentially (e.g., one after another). In some embodiments, the memory cells of row 0 (i.e., the memory cells coupled to the 0th word line) are programmed sequentially from finger 0 to finger 5 to undergo a first programming pass (e.g., 502). The order in which the fingers are programmed is shown as sequence numbers 0-5. The memory cells of row 1 in finger 0 (i.e., the memory cells coupled to the 1st word line and in finger 0) then undergo a first programming pass. The memory cells of row 0 in finger 1 (i.e., the memory cells coupled to the 0th word line and in finger 1) then undergo a second programming pass. The memory cells of row 1 in finger 1 (i.e., the memory cells coupled to the 1st word line and in finger 1) then undergo a first programming pass. The memory cells of row 0 in finger 2 (i.e., the memory cells coupled to the 0th word line and in finger 2) then undergo a second programming pass. The order in which the fingers are programmed is shown as sequence numbers 6-9. As described above, the remaining memory cells may be programmed repeatedly in the zigzag priority order until the memory cells coupled to the 63rd word line undergo a second programming pass.

[0078] As an example, the second word line may be a selected word line, similar to 610, and the memory cells in finger 0 to finger 5 coupled to the second word line may be the memory cells of the selected row. The first word line may be an unselected word line, similar to 611. When the memory cells in the selected row in a finger are undergoing the first pass of programming, the memory cells in the unselected rows in the other fingers that have been programmed before this finger have undergone the second pass of programming. For example, the memory cell in finger 0 and coupled to the second word line may first undergo the first pass of programming (sequence number 18), the memory cell in finger 0 and coupled to the first word line may then undergo the second pass of programming (sequence number 19), the memory cell in finger 0 and coupled to the second word line may then undergo the first pass of programming (sequence number 20), and the memory cell in finger 2 and coupled to the first word line may then undergo the second pass of programming (sequence number 21), the memory cell in finger 0 and coupled to the second word line may then undergo the second pass of programming (sequence number 31), and the memory cell in finger 1 and coupled to the second word line may then undergo the second pass of programming (sequence number 33). That is, when the memory cells of the selected row are undergoing the first pass of programming, the memory cells in the unselected row immediately below the selected row may or may not have undergone the second pass of programming. In some embodiments, when the memory cells in a selected row and in a finger (e.g., finger 1) are undergoing the first pass of programming, the memory cells in the unselected rows in another finger (e.g., finger 0) that has been programmed before this finger may have undergone the second pass of programming. The memory cells in the unselected rows in the remaining fingers (e.g., fingers 2-5) have not undergone the second pass of programming. Therefore, the memory cells in the unselected rows that have undergone the second pass of programming may not undergo the NGS operation simultaneously with the memory cells in the selected row.

[0079] In some embodiments, for the memory cells in the selected row and the unselected row, only the memory cells in the selected fingers may undergo the NGS operation simultaneously. The selected fingers may include the fingers having memory cells that have not passed the corresponding verification operation of the NGS operation in the selected row and the unselected row. In some embodiments, the selected fingers may further include the fingers having memory cells that have not undergone the second pass of programming in the selected row and the unselected row. The memory cells in the selected row and the unselected row in the unselected fingers may not undergo the NGS operation simultaneously. In some embodiments, the unselected fingers include the fingers having memory cells that have undergone the second pass of programming in the selected row and the unselected row. In some embodiments, in the unselected fingers, all the memory cells in the selected row and the unselected row have passed the corresponding verification operation before the NGS operation.

[0080] As an example, when coupled to the second word line and the memory cells in finger 1 are undergoing the first pass of programming, finger 1 can be the selected finger. The memory cells coupled to the first word line and in finger 0 have undergone the second pass of programming. Finger 0 can be the unselected finger. In some embodiments, if all the memory cells in finger 0 and coupled to the first and second word lines pass the verification operation, then finger 0 is the unselected finger. If at least one of the memory cells in finger 0 and coupled to the first and second word lines fails the verification operation, then finger 0 is the selected finger. In some embodiments, fingers 2 - 5 can all be selected fingers.

[0081] Different from the NGS operation 512, it can be enabled only on the memory cells coupled to WLn and WLn - 1 and in the selected finger Figure 8B the NGS operation shown in. The NGS operation can be performed in stage 800. Alternatively, for example, if the memory cell 602 is in the selected finger, a V SS voltage can be applied to the DSG line 614; and if the memory cell 602 is in the unselected finger, a V DSG_P_H voltage can be applied to the DSG line 614. In some embodiments, V DSG_P_H is a positive voltage higher than V DD . As described above, in the NGS operation, a high voltage, such as V DD , can be applied to the bit line of the memory string having a memory cell coupled to WLn and failing the verification operation; and a low voltage, such as V SS , can be applied to the bit line of the memory string having a memory cell in the selected word line and all passing the verification operation. The value of V SS minus V DD is lower than the threshold voltage of the DSG transistor to turn off the DSG transistor, thereby enabling the NGS operation on the memory cells coupled to the word lines 610 and 611 and in the selected finger. The value of V DSG_P_H minus V DD is higher than the threshold voltage of the DSG transistor to turn on the DSG transistor, thereby prohibiting the NGS operation on the memory cells coupled to the word lines 610 and 611 and in the unselected finger.

[0082] Figure 9 is a flowchart of an exemplary method 900 for operating a memory device according to some embodiments of the present disclosure. Figure 9 Examples of the memory devices depicted in Figure 1A include the memory device 104 depicted in Figure 3 , Figure 5A - 5C , Figure 6A ,Figure 6B , Figure 7A - 7C , Figure 8A and Figure 8B are described by the operations shown in Figure 9 . It should be understood that the operations shown in method 900 are not exhaustive, and other operations may be performed before, after, or between any of the shown operations. Additionally, some operations may be performed simultaneously, or in a different order than Figure 9 shown. In some embodiments, method 900 is performed by the peripheral circuit 302. Specifically, a word line driver (e.g., 208) may be configured to apply voltages on the word lines, DSG lines, and SSG lines, and a bit line driver (e.g., 206) may be configured to apply voltages on the bit lines.

[0083] Referring Figure 9 , method 900 begins at operation 902, where a non-final programming pass is performed on the memory cells of a selected row coupled to a selected word line. The non-final programming pass includes one or more programming cycles. At least one of the programming cycles includes a programming operation, an NGS operation after the programming operation, and a verification operation after the NGS operation. The NGS operation may be performed on the memory cells of the selected row and the memory cells of unselected rows adjacent to the selected row.

[0084] Returning to reference Figure 5A - 5C , Figure 6A , Figure 6B , Figure 7A - 7C , Figure 8A and Figure 8B , a non-final programming pass, such as 502, may be performed on the memory cells of a selected row coupled to a selected word line (e.g., 610 / WLn). The non-final programming pass may include one or more programming cycles, such as 506. At least one of the programming cycles includes a programming operation (e.g., 510), an NGS operation (e.g., 512) after the programming operation, and a verification operation (e.g., 514) after the NGS operation. The programming operation is first performed by applying a programming voltage / pulse (e.g., V PGM1 ) on the selected word line. The NGS operation may be enabled on some or all of the memory cells in the selected row in one or more programming cycles 506 (e.g., each programming cycle 506). At the same time, the NGS operation may also be enabled on some or all of the memory cells in unselected rows adjacent to the selected row. To enable the NGS operation, corresponding voltages are applied to the DSG (e.g., 614) in some fingers including the memory cells coupled to the selected word line and unselected word lines, as Figure 7B and Figure 8A shown. For the word line priority order, a low voltage, such as V SS , is applied to the DSG of all fingers. For the zigzag order, a low voltage, such as VSS and the DSG high voltage for the unselected finger, e.g., V DSG_P_H . High voltages (e.g., V DD ) and low voltages (V SS ) are applied to the bit lines of the memory strings having memory cells that have not passed the verification operation and have passed the verification operation, respectively. A low voltage, e.g., V SS , is applied to the SSG (e.g., 616) in the finger. At the same time, a low voltage (GND or negative voltage) is applied to the selected word line and the unselected word line, and a positive voltage is applied to the word lines above and below the selected word line and the unselected word line, as shown in Figure 6B , Figure 7B and Figure 8A . For the word line priority order, all memory cells coupled to the selected word line and the unselected word line can simultaneously undergo the NGS operation. For the zigzag order, only the memory cells coupled to the selected word line and the unselected word line and in the selected finger can simultaneously undergo the NGS operation. A verification operation can be performed on the memory cells coupled to the selected word line after the NGS operation by applying one or more verification voltages (e.g., V R1 ) to the selected word line.

[0085] In some embodiments, the NGS operation is enabled in each programming cycle of the non-final programming pass. In some embodiments, if the programming cycle is the first programming cycle, e.g., before any verification operation is performed, each memory cell coupled to the selected word line is considered a memory cell that has not passed the corresponding verification operation before the NGS operation.

[0086] Returning to reference Figure 9 , method 900 proceeds to operation 904, where a final programming pass is performed on the selected word line. The final programming pass includes one or more programming cycles. The programming cycle may not include any NGS operations, or may include NGS operations enabled only on the memory cells that have not passed the corresponding verification operation immediately preceding the NGS operation.

[0087] Returning to reference Figure 5A - 5C , Figure 6A , Figure 6B , Figure 7A - 7C , Figure 8A and Figure 8B, the final programming pass, e.g., 504, can be performed on a selected word line such as 610 / WLn. The final programming pass can include one or more programming cycles, e.g., 508. Different from the programming cycles in non-final programming passes, the programming cycles may not include any NGS operations on any memory cells, or may include NGS operations enabled only on memory cells that fail the corresponding verification operation immediately before the NGS operation. In some embodiments, NGS operations are not enabled on memory cells that pass the verification operation. In some embodiments, NGS operations are prohibited between a programming operation (e.g., 520) and a subsequent verification operation (524), as Figure 5C shown. In some embodiments, NGS operations are enabled between a programming operation and a subsequent verification operation only on memory cells coupled to the selected word line and that fail the corresponding verification operation immediately before the NGS operation. NGS operations can be enabled in one or more programming cycles 508. The programming operation and the verification operation can refer to Figure 5C 's description and are not described in detail again herein. To prohibit NGS operations on memory cells coupled to the selected word line and passing the verification operation, a low positive voltage (e.g., V DSG_P_L ) is applied to the DSG (e.g., 614) in the finger including these memory cells, as Figure 7C shown. To enable NGS operations on memory cells coupled to the selected word line and that fail the verification operation, a high positive voltage (e.g., V DSG_P_H ) is applied to the DSG (e.g., 614) in the finger including these memory cells, as Figure 7C shown. A high voltage (e.g., V DD ) and a low voltage (e.g., V SS ) are applied to the bit lines of the memory strings having memory cells that fail and pass the verification operation, respectively. The SSG (e.g., 616) in the finger is applied with a low voltage and turned off. At the same time, a low voltage (e.g., GND or a negative voltage) is applied to the selected word line, and a positive voltage is applied to the word lines above and below the selected word line, as Figure 6B , Figure 7B and Figure 8A shown. Verification operations can be performed on the memory cells coupled to the selected word line after the NGS operation by applying one or more verification voltages (e.g., V R2 ) to the selected word line. In some embodiments, operation 904 is performed by the peripheral circuit 302. It should be noted that in various embodiments, verification operations (e.g., 514 and / or 524) may not be performed in all programming cycles.

[0088] Some aspects of the present disclosure provide a storage device. The storage device includes: an array of memory cells arranged in multiple rows; multiple word lines respectively coupled to the multiple rows of memory cells; and a peripheral circuit coupled to the word lines, the peripheral circuit being configured to perform multi-pass programming on the memory cells of a selected row coupled to a selected word line among the word lines. The multi-pass programming includes a plurality of programming passes. Each programming pass includes a programming operation and a verification operation. To perform the multi-pass programming, the peripheral circuit is configured to: in a non-final programming pass of the memory cells, between the programming operation and the verification operation, perform an NGS operation on the memory cells in the memory cells of the selected row; and simultaneously, perform an NGS operation on the memory cells in the memory cells of an unselected row coupled to an unselected word line among the word lines. The unselected word line is adjacent to the selected word line.

[0089] In some embodiments, the peripheral circuit includes a word line driver coupled to the multiple word lines. To perform the NGS operation on the memory cells of the selected row and the unselected row, the word line driver is configured to apply one of a negative voltage or a GND voltage on the selected word line and the unselected word line, respectively.

[0090] In some embodiments, to perform the NGS operation on the memory cells of the selected row and the unselected row, the word line driver is further configured to apply a positive voltage on the remaining word lines.

[0091] In some embodiments, the storage device further includes multiple bit lines. The array of memory cells includes multiple strings coupled to the multiple bit lines. Each string includes an SSG transistor. The memory cells in the selected row are respectively in the multiple strings. To perform the corresponding NGS operation on the memory cells of the selected row and the memory cells of the unselected row, the peripheral circuit is further configured to turn off the SSG transistor of each string.

[0092] In some embodiments, in response to the memory cells of the row having a memory cell that fails the corresponding verification operation immediately before the NGS operation, the bit line voltage is a positive voltage. In some embodiments, in response to the memory cells of the row including a memory cell that passes the corresponding verification operation immediately before the NGS operation, the bit line voltage is a GND voltage.

[0093] In some embodiments, the multiple strings are arranged in multiple fingers, and the multi-pass programming includes an order. The order includes performing a non-final programming pass on the first memory cell of the selected row in the first finger of the fingers, immediately after the non-final programming pass on the first memory cell, performing a non-final programming pass on the second memory cell of the selected row in the second finger of the fingers, and immediately after the non-final programming pass on the second memory cell, performing a final programming pass on the third memory cell of the unselected row in the first finger.

[0094] In some embodiments, NGS operations are performed on each memory cell in the selected and unselected rows.

[0095] In some embodiments, each string includes a DSG transistor. In some embodiments, in order to perform corresponding NGS operations on the memory cells of the selected and unselected rows, the peripheral circuit is further configured to turn off the DSG transistors of each string in the plurality of fingers.

[0096] In some embodiments, the peripheral circuit includes a bit line driver coupled to a plurality of bit lines, and the word line driver is coupled to the DSG transistor via a DSG line. In some embodiments, in order to turn off the DSG transistors of the first and second strings, the bit line driver is configured to apply a bit line voltage on each string respectively. In some embodiments, the word line driver is configured to apply a DSG voltage on the DSG transistors of each string via the DSG line respectively, and the value of the DSG voltage minus the bit line voltage is lower than the threshold voltage of the DSG transistor.

[0097] In some embodiments, the DSG voltage is the GND voltage.

[0098] In some embodiments, a plurality of strings are arranged in a plurality of fingers, and the multi-pass programming includes an order. The order includes performing a non-final programming pass on the first memory cell of the selected row in the first finger of the fingers, immediately after the non-final programming pass on the first memory cell, performing a final programming pass on the second memory cell of the unselected row in the first finger, and immediately after the final programming pass on the second memory cell, performing a non-final programming pass on the third memory cell of the selected row in the second finger of the fingers.

[0099] In some embodiments, in the selected and unselected rows, in response to (i) no final programming pass being performed or (ii) a final programming pass being performed and the selected finger including at least one memory cell that has not passed the corresponding verification operation, NGS operations are performed on the memory cells in the selected finger. In some embodiments, in response to (i) a final programming pass being performed and (ii) all memory cells having passed the corresponding verification operation, NGS operations are prohibited on the memory cells in the unselected finger.

[0100] In some embodiments, each string includes a DSG transistor. In some embodiments, in order to perform corresponding NGS operations on the memory cells of the selected and unselected rows, the peripheral circuit is further configured to: turn off the DSG transistors of the strings in the selected finger in response to no final programming pass being performed on the selected finger; and turn on the DSG transistors of the strings in the unselected finger in response to a final programming pass being performed on the unselected finger.

[0101] In some embodiments, the peripheral circuit includes a bit-line driver coupled to a plurality of bit lines, and a word-line driver is coupled to the DSG transistors via DSG lines. In some embodiments, the bit-line driver is configured to apply a bit-line voltage on the corresponding bit lines of each string. In some embodiments, the word-line driver is configured to apply a DSG voltage on the DSG transistors of each string via the DSG lines. In some embodiments, in order to turn off the DSG transistors of each string, the value of the DSG voltage minus the bit-line voltage is lower than the threshold voltage of the DSG transistors. In some embodiments, in order to turn on the DSG transistors of each string, the value of the DSG voltage minus the bit-line voltage is higher than the threshold voltage of the DSG transistors.

[0102] In some embodiments, the DSG voltage applied on the selected finger is the GND voltage, and the DSG voltage applied on the unselected finger is a positive voltage.

[0103] In some embodiments, the peripheral circuit includes SSG lines coupled to the SSG transistors of each string and a source driver coupled to the SSG lines. In some embodiments, the source driver is configured to apply the GND voltage on the SSG lines.

[0104] In some embodiments, in order to perform multi-pass programming, the peripheral circuit is configured to: in the last programming pass, in response to one of the memory cells in the selected row or the unselected row passing the corresponding verification operation immediately before the last programming pass, prohibit the corresponding NGS operation on the one of the memory cells. In some embodiments, in order to perform multi-pass programming, the peripheral circuit is configured to: in the last programming pass, in response to another one of the memory cells in the selected row or the unselected row not passing the corresponding verification operation immediately before the last programming pass, perform the corresponding NGS operation on the another one of the memory cells.

[0105] In some embodiments, in order to perform multi-pass programming, the peripheral circuit is configured to: in the last programming pass, prohibit the corresponding NGS on each of the memory cells in the selected row and the unselected row.

[0106] In some embodiments, the NGS operation is performed between the corresponding programming operation and the corresponding verification operation.

[0107] In some embodiments, the non-last programming pass includes a plurality of programming operations and a plurality of verification operations. The NGS operation is performed after each programming operation and before the corresponding verification operation.

[0108] In some embodiments, the memory device is a 3D NAND flash memory device.

[0109] Some aspects of the present disclosure provide a method for operating a memory device, the memory device including an array of memory cells arranged in multiple rows and multiple word lines respectively coupled to the multiple rows of memory cells. The method includes performing multi-pass programming on the memory cells of a selected row coupled to a selected word line among the word lines. The multi-pass programming includes a plurality of programming passes. Each programming pass includes a programming operation and a verification operation. Performing the multi-pass programming includes: in a non-final programming pass of the memory cells, between the programming operation and the verification operation, performing an NGS operation on the memory cells in the selected row of memory cells. Performing the multi-pass programming further includes: simultaneously, performing an NGS operation on the memory cells in the non-selected rows of memory cells coupled to non-selected word lines among the word lines, the non-selected word lines being adjacent to the selected word line.

[0110] In some embodiments, performing the NGS operation on the memory cells of the selected row and the non-selected row includes applying one of a negative voltage or a GND voltage on the selected word line and the non-selected word line respectively.

[0111] In some embodiments, performing the NGS operation on the memory cells of the selected row and the non-selected row further includes applying a positive voltage on the remaining word lines.

[0112] In some embodiments, the memory device includes multiple bit lines, and the array of memory cells includes multiple strings coupled to the multiple bit lines. Each string includes an SSG transistor. The memory cells in the selected row are respectively in the multiple strings. In some embodiments, performing the corresponding NGS operation on the memory cells of the selected row and the non-selected row includes turning off the SSG transistor of each string.

[0113] In some embodiments, the method further includes: in response to the memory cells of the row having memory cells that have not passed the corresponding verification operation immediately before the NGS operation, applying a positive voltage as the bit line voltage. In some embodiments, the method further includes: in response to the memory cells of the row including memory cells that have passed the corresponding verification operation immediately before the NGS operation, applying a GND voltage as the bit line voltage.

[0114] In some embodiments, the multiple strings are arranged in multiple fingers, and the multi-pass programming includes an order. The order includes performing a non-final programming pass on the first memory cells of the selected row in the first finger among the fingers, immediately after the non-final programming pass on the first memory cells, performing a non-final programming pass on the second memory cells of the selected row in the second finger among the fingers, and immediately after the non-final programming pass on the second memory cells, performing a final programming pass on the third memory cells of the non-selected row in the first finger.

[0115] In some embodiments, the method includes performing an NGS operation on each memory cell in the selected and non-selected rows.

[0116] In some embodiments, each string includes a DSG transistor. In some embodiments, performing a corresponding NGS operation on the memory cells of the selected row and the unselected row includes turning off the DSG transistors of each string in the plurality of fingers.

[0117] In some embodiments, the method includes applying a bit line voltage to each string respectively. In some embodiments, the method further includes applying a DSG voltage to the DSG transistors on each string via DSG lines respectively. The value obtained by subtracting the bit line voltage from the DSG voltage is lower than the threshold voltage of the DSG transistor.

[0118] In some embodiments, the DSG voltage is the GND voltage.

[0119] In some embodiments, a plurality of strings are arranged in a plurality of fingers, and the multi-pass programming includes an order. The order includes performing a non-final programming pass on the first memory cell of the selected row in the first finger among the fingers, immediately after the non-final programming pass on the first memory cell, performing a final programming pass on the second memory cell of the unselected row in the first finger, and immediately after the final programming pass on the second memory cell, performing a non-final programming pass on the third memory cell of the selected row in the second finger among the fingers.

[0120] In some embodiments, the method further includes: in the selected row and the unselected row, in response to (i) no final programming pass being performed or (ii) a final programming pass being performed and the selected finger including at least one memory cell that has not passed the corresponding verification operation, performing an NGS operation on the memory cells in the selected finger. In some embodiments, the method further includes: in the selected row and the unselected row, in response to (i) a final programming pass being performed and (ii) all memory cells having passed the corresponding verification operation, prohibiting the NGS operation on the memory cells in the unselected finger.

[0121] In some embodiments, each string includes a DSG transistor. In some embodiments, performing a corresponding NGS operation on the memory cells of the selected row and the unselected row includes: turning off the DSG transistors of the strings in the selected finger in response to no final programming pass being performed on the selected finger. In some embodiments, performing a corresponding NGS operation on the memory cells of the selected row and the unselected row further includes: turning on the DSG transistors of the strings in the unselected finger in response to a final programming pass being performed on the unselected finger.

[0122] In some embodiments, the method includes applying a bit line voltage to corresponding bit lines in each string. In some embodiments, the method further includes applying a DSG voltage to DSG transistors in each string via a DSG line. In some embodiments, the method further includes turning off the DSG transistors of each string when the value of the DSG voltage minus the bit line voltage is lower than the threshold voltage of the DSG transistors. In some embodiments, the method further includes turning on the DSG transistors of each string when the value of the DSG voltage minus the bit line voltage is higher than the threshold voltage of the DSG transistors.

[0123] In some embodiments, the method includes: applying a GND voltage as the DSG voltage to a selected finger and applying a positive voltage as the DSG voltage to an unselected finger.

[0124] In some embodiments, the memory device includes an SSG line coupled to SSG transistors of each string, and the method includes applying a GND voltage to the SSG line.

[0125] In some embodiments, performing multi-pass programming includes: in a last programming pass, in response to one of the memory cells in a selected row or an unselected row passing a corresponding verification operation immediately before the last programming pass, prohibiting a corresponding NGS operation on the one of the memory cells. In some embodiments, performing multi-pass programming includes: in a last programming pass, in response to another one of the memory cells in a selected row or an unselected row failing a corresponding verification operation immediately before the last programming pass, performing a corresponding NGS operation on the another one of the memory cells.

[0126] In some embodiments, performing multi-pass programming includes: in a last programming pass, prohibiting a corresponding NGS on each of the memory cells in the selected row and the unselected row.

[0127] In some embodiments, the method includes performing an NGS operation between a corresponding programming operation and a corresponding verification operation.

[0128] In some embodiments, a non-last programming pass includes a plurality of programming operations and a plurality of verification operations, and the method includes: performing an NGS operation after each programming operation and before a corresponding verification operation.

[0129] Some aspects of the present disclosure also provide a system. The system includes a storage device configured to store data and a memory controller coupled to the storage device and configured to control the storage device. The storage device includes: an array of memory cells arranged in multiple rows; multiple word lines respectively coupled to the multiple rows of memory cells; and a peripheral circuit coupled to the word lines, the peripheral circuit being configured to perform multiple-pass programming on the memory cells of a selected row coupled to a selected word line among the word lines. The multiple-pass programming includes multiple programming passes. Each programming pass includes a programming operation and a verification operation. To perform the multiple-pass programming, the peripheral circuit is configured to: in a non-last programming pass of the memory cells, between the programming operation and the verification operation, perform an NGS operation on the memory cells in the selected row of the memory cells. To perform the multiple-pass programming, the peripheral circuit is configured to: simultaneously, perform an NGS operation on the memory cells in the unselected rows of the memory cells coupled to unselected word lines among the word lines, the unselected word lines being adjacent to the selected word line.

[0130] In some embodiments, the system further includes a host coupled to the memory controller and configured to send or receive data.

[0131] In some embodiments, the storage device is a 3D NAND flash storage device.

[0132] In some embodiments, the peripheral circuit includes a word line driver coupled to the multiple word lines, and wherein, to perform the NGS operation on the memory cells of the selected row and the unselected rows, the word line driver is configured to apply one of a negative voltage or a ground (GND) voltage on the selected word line and the unselected word lines, respectively.

[0133] In some embodiments, to perform the multiple-pass programming, the peripheral circuit is configured to: in the last programming pass, in response to one of the memory cells in the selected row or the unselected rows passing the corresponding verification operation immediately before the last programming pass, prohibit the corresponding NGS operation on the one of the memory cells. In some embodiments, to perform the multiple-pass programming, the peripheral circuit is configured to: in response to another of the memory cells in the selected row or the unselected rows not passing the corresponding verification operation immediately before the last programming pass, perform the corresponding NGS operation on the another of the memory cells.

[0134] The foregoing description of specific embodiments can be readily modified and / or adapted for various applications. Accordingly, such adaptations and modifications are intended to be within the meaning and scope of equivalents of the disclosed embodiments, based on the teachings and guidance presented herein.

[0135] The breadth and scope of the present disclosure should not be limited by any of the above exemplary embodiments, but should be defined only in accordance with the appended claims and their equivalents.

Claims

1. A memory device, comprising: An array of memory cells arranged in multiple rows; Multiple word lines respectively coupled to the multiple rows of the memory cells; And A peripheral circuit coupled to the word lines, the peripheral circuit being configured to perform multi-pass programming on the memory cells of a selected row coupled to a selected word line among the word lines, the multi-pass programming including a plurality of programming passes, each programming pass including a programming operation and a verification operation, wherein, in order to perform the multi-pass programming, the peripheral circuit is configured to: in a non-final programming pass of the memory cells, Between the programming operation and the verification operation, perform a negative gate stress (NGS) operation on the memory cells in the selected row of the memory cells; and Simultaneously, perform an NGS operation on the memory cells in the non-selected rows of the memory cells coupled to the non-selected word lines among the word lines, the non-selected word lines being adjacent to the selected word line, Wherein the NGS operation includes applying a first voltage to the word line coupled to the memory cell on which the NGS operation will be performed, and applying a second voltage to other word lines, the second voltage being higher than the first voltage.

2. The storage device according to claim 1, wherein, The peripheral circuit includes a word line driver coupled to the multiple word lines, and wherein, in order to perform the NGS operation on the memory cells of the selected row and the non-selected row, the word line driver is configured to apply either a negative voltage or a ground (GND) voltage on the selected word line and the non-selected word line respectively.

3. The memory device according to claim 2, wherein, In order to perform the NGS operation on the memory cells of the selected row and the non-selected row, the word line driver is further configured to apply a positive voltage on the remaining word lines.

4. The memory device according to any one of claims 1-3, further comprising multiple bit lines, wherein: The array of memory cells includes multiple strings coupled to the multiple bit lines, each string including a source select gate (SSG) transistor; The memory cells in the selected row are respectively in the multiple strings; and In order to perform corresponding NGS operations on the memory cells of the selected row and the non-selected row, the peripheral circuit is further configured to turn off the SSG transistor of each string.

5. The memory device according to claim 4, wherein, In response to the memory cells of the row including memory cells that did not pass the corresponding verification operation immediately before the NGS operation, the bit line voltage is a positive voltage; and In response to the memory cells of the row including memory cells that passed the corresponding verification operation immediately before the NGS operation, the bit line voltage is a GND voltage.

6. The memory device according to claim 5, wherein, The multiple strings are arranged in multiple fingers, and the multi-pass programming includes an order, the order including: Performing the non-final programming pass on the first memory cell of the selected row in the first finger of the fingers; Immediately after the non-final programming pass on the first memory cell, performing the non-final programming pass on the second memory cell of the selected row in the second finger of the fingers, and After the non-final programming pass on the second storage unit, a final programming pass is performed on the third storage unit of the unselected rows in the first finger.

7. The memory device according to claim 6, wherein, The NGS operation is performed on each storage unit in the selected rows and the unselected rows.

8. The memory device according to claim 6 or 7, wherein each of the strings includes a drain select gate (DSG) transistor; and to perform the respective NGS operations on the storage units of the selected rows and the unselected rows, the peripheral circuit is further configured to turn off the DSG transistors of each of the strings in the plurality of fingers.

9. The storage device according to claim 8, wherein, The peripheral circuit includes a bit line driver coupled to the plurality of bit lines, and the word line driver is coupled to the DSG transistors via DSG lines, and wherein, to turn off the DSG transistors of the first string and the second string in the plurality of strings, the bit line driver is configured to apply a bit line voltage on each of the strings respectively; and the word line driver is configured to apply a DSG voltage on the DSG transistors on each of the strings via the DSG lines, and the value obtained by subtracting the bit line voltage from the DSG voltage is lower than the threshold voltage of the DSG transistors.

10. The storage device according to claim 9, wherein, The DSG voltage is the GND voltage.

11. The memory device according to claim 5, wherein, The plurality of strings are arranged in a plurality of fingers, and the multi-pass programming includes an order, the order including: performing the non-final programming pass on the first storage unit of the selected rows in the first finger of the fingers; immediately after the non-final programming pass on the first storage unit, performing the final programming pass on the second storage unit of the unselected rows in the first finger; and immediately after the final programming pass on the second storage unit, performing the non-final programming pass on the third storage unit of the selected rows in the second finger of the fingers.

12. The storage device according to claim 11, wherein, In the selected rows and the unselected rows, in response to (i) not performing the final programming pass or (ii) performing the final programming pass and the selected finger including at least one storage unit that fails the corresponding verification operation, performing the NGS operation on the storage units in the selected finger; and in response to (i) performing the final programming pass and (ii) all the storage units passing the corresponding verification operation, prohibiting the NGS operation on the storage units in the unselected finger.

13. The storage device according to claim 11 or 12, wherein each of the strings includes a drain select gate (DSG) transistor; and to perform the respective NGS operations on the storage units of the selected rows and the unselected rows, the peripheral circuit is further configured to: turn off the DSG transistors of the strings in the selected finger in response to not performing the final programming pass on the selected finger; and turn on the DSG transistors of the strings in the unselected finger in response to performing the final programming pass on the unselected finger.

14. The memory device according to claim 13, wherein: The peripheral circuit includes a bit line driver coupled to the plurality of bit lines, and the word line driver is coupled to the DSG transistor via a DSG line; The bit line driver is configured to apply a bit line voltage to the corresponding bit line of each of the strings; The word line driver is configured to apply a DSG voltage to the DSG transistor of each of the strings via the DSG line; To turn off the DSG transistor of each of the strings, the value of the DSG voltage minus the bit line voltage is lower than the threshold voltage of the DSG transistor; and To turn on the DSG transistor of each of the strings, the value of the DSG voltage minus the bit line voltage is higher than the threshold voltage of the DSG transistor.

15. The memory device according to claim 14, wherein: The DSG voltage applied to the selected finger is the GND voltage; and The DSG voltage applied to the unselected finger is a positive voltage.

16. The memory device according to any one of claims 4 - 15, wherein, The peripheral circuit includes an SSG line coupled to the SSG transistor of each of the strings and a source driver coupled to the SSG line, and wherein the source driver is configured to: Apply a GND voltage to the SSG line.

17. The memory device according to any one of claims 1-16, wherein, To perform the multi-pass programming, the peripheral circuit is configured to: in the last programming pass: In response to one of the memory cells in the selected row or the unselected row passing the corresponding verification operation immediately before the last programming pass, prohibit the corresponding NGS operation on the one of the memory cells; In response to the other of the memory cells in the selected row or the unselected row not passing the corresponding verification operation immediately before the last programming pass, perform the corresponding NGS operation on the other of the memory cells.

18. The memory device according to any one of claims 1-17, wherein, To perform the multi-pass programming, the peripheral circuit is configured to: in the last programming pass, prohibit the corresponding NGS on each of the memory cells in the memory cells of the selected row and the unselected row.

19. The memory device according to any one of claims 1-18, wherein, Perform the NGS operation between the corresponding programming operation and the corresponding verification operation.

20. The memory device according to claim 19, wherein, The non-last programming pass includes a plurality of programming operations and a plurality of verification operations, and the NGS operation is performed after each of the programming operations and before the corresponding verification operation.

21. The memory device according to any one of claims 1-20, wherein, The memory device is a three-dimensional (3D) NAND flash memory device.

22. A method for operating a memory device, the memory device including an array of memory cells arranged in multiple rows and a plurality of word lines respectively coupled to the multiple rows of the memory cells, the method including: Performing multi-pass programming on the memory cells of a selected row of the word lines coupled to the selected word line, the multi-pass programming including a plurality of programming passes, each of the programming passes including a programming operation and a verification operation, wherein performing the multi-pass programming includes: In a non-last programming pass of the memory cells, between the programming operation and the verification operation, performing a negative gate stress (NGS) operation on the memory cells in the memory cells of the selected row; and Meanwhile, an NGS operation is performed on the memory cells in the unselected rows of the unselected word lines coupled to the word lines, where the unselected word lines are adjacent to the selected word line. Wherein, the NGS operation includes applying a first voltage to the word line coupled to the memory cell on which the NGS operation will be performed, and applying a second voltage to other word lines, the second voltage being higher than the first voltage.

23. The method according to claim 22, wherein, Performing the NGS operation on the memory cells of the selected row and the unselected row includes applying one of a negative voltage or a ground (GND) voltage to the selected word line and the unselected word line, respectively.

24. The method according to claim 23, wherein Performing the NGS operation on the memory cells of the selected row and the unselected row further includes applying a positive voltage to the remaining word lines.

25. The method according to any one of claims 22-24, wherein, The memory device includes a plurality of bit lines, and an array of the memory cells includes a plurality of strings coupled to the plurality of bit lines, each of the strings including a source select gate (SSG) transistor; the memory cells in the selected row are respectively in the plurality of strings; and Performing corresponding NGS operations on the memory cells of the selected row and the unselected row includes turning off the SSG transistors of each of the strings.

26. The method according to claim 25, further comprising: In response to the memory cells of the row including memory cells that did not pass the corresponding verification operation immediately before the NGS operation, applying a positive voltage as the bit line voltage, and In response to the memory cells of the row including memory cells that passed the corresponding verification operation immediately before the NGS operation, applying a GND voltage as the bit line voltage.

27. The method according to claim 26, wherein, The plurality of strings are arranged in a plurality of fingers, and the multi-pass programming includes an order, the order including: Performing the non-final programming pass on the first memory cell of the selected row in the first finger of the fingers; Immediately after the non-final programming pass on the first memory cell, performing the non-final programming pass on the second memory cell of the selected row in the second finger of the fingers, and After the non-final programming pass on the second memory cell, performing the final programming pass on the third memory cell of the unselected row in the first finger.

28. The method according to claim 27 further comprises: Performing the NGS operation on each memory cell in the selected row and the unselected row.

29. The method according to claim 27 or 28, wherein, Each of the strings includes a drain select gate (DSG) transistor; and Performing the corresponding NGS operations on the memory cells of the selected row and the unselected row includes turning off the DSG transistors of each of the strings in the plurality of fingers.

30. The method according to claim 29, comprising: Applying a bit line voltage to each of the strings, respectively; And Applying a DSG voltage to the DSG transistors on each of the strings via the DSG lines, a value obtained by subtracting the bit line voltage from the DSG voltage being lower than a threshold voltage of the DSG transistors.

31. The method according to claim 30, wherein The DSG voltage is a GND voltage.

32. The method according to claim 26, wherein, The plurality of strings are arranged in a plurality of fingers, and the multi-pass programming includes an order, the order including: Perform the non-final programming pass on the first storage cells of the selected row in the first finger of the fingers; Immediately after the non-final programming pass on the first storage cells, perform the final programming pass on the second storage cells of the unselected rows in the first finger; and Immediately after the final programming pass on the second storage cells, perform the non-final programming pass on the third storage cells of the selected row in the second finger of the fingers.

33. The method according to claim 32, comprising: In the selected row and the unselected rows, In response to (i) not performing the final programming pass or (ii) performing the final programming pass and the selected finger including at least one storage cell that has not passed the corresponding verification operation, perform the NGS operation on the storage cells in the selected finger; and In response to (i) performing the final programming pass and (ii) the storage cells all passing the corresponding verification operation, prohibit the NGS operation on the storage cells in the unselected finger.

34. The method according to claim 32 or 33, wherein, The strings each include a drain select gate (DSG) transistor; and Performing the corresponding NGS operation on the storage cells of the selected row and the unselected rows includes: Turning off the DSG transistors of the strings in the selected finger in response to not performing the final programming pass on the selected finger; and Turning on the DSG transistors of the strings in the unselected finger in response to performing the final programming pass on the unselected finger.

35. The method according to claim 34, including: Applying a bit line voltage on the corresponding bit line of each of the strings; Applying a DSG voltage on the DSG transistor of each of the strings via the DSG line; Turning off the DSG transistors of each of the strings, where the value of the DSG voltage minus the bit line voltage is lower than the threshold voltage of the DSG transistor; And Turning on the DSG transistors of each of the strings, where the value of the DSG voltage minus the bit line voltage is higher than the threshold voltage of the DSG transistor.

36. The method according to claim 35, including: Applying a GND voltage on the selected finger as the DSG voltage; And Applying a positive voltage on the unselected finger as the DSG voltage.

37. The method according to any one of claims 25-36, the memory device including an SSG line coupled to the SSG transistor of each of the strings, and the method including: Applying a GND voltage on the SSG line.

38. The method according to any one of claims 22-37, wherein, Performing the multi-pass programming includes: in the final programming pass: Prohibiting the corresponding NGS operation on one of the storage cells in response to one of the storage cells in the selected row or the unselected rows passing the corresponding verification operation immediately before the final programming pass; and Performing the corresponding NGS operation on the other of the storage cells in response to the other of the storage cells in the selected row or the unselected rows not passing the corresponding verification operation immediately before the final programming pass.

39. The method according to any one of claims 22-38, wherein Performing the multi-pass programming includes: in the last programming pass, inhibiting a corresponding NGS on each of the memory cells in the memory cells of the selected row and the unselected row.

40. The method according to any one of claims 22-39, including performing the NGS operation between a corresponding programming operation and a corresponding verification operation.

41. The method according to claim 40, wherein, The non-last programming pass includes a plurality of programming operations and a plurality of verification operations, and the method includes: performing the NGS operation after each of the programming operations and before a corresponding verification operation.

42. A system, comprising: A memory device configured to store data, the memory device including: An array of memory cells arranged in multiple rows; A plurality of word lines respectively coupled to the multiple rows of the memory cells; and A peripheral circuit coupled to the word lines, the peripheral circuit being configured to perform multi-pass programming on the memory cells of a selected row coupled to a selected word line among the word lines, the multi-pass programming including a plurality of programming passes, each of the programming passes including a programming operation and a verification operation, wherein, to perform the multi-pass programming, the peripheral circuit is configured to: in a non-last programming pass of the memory cells, Between the programming operation and the verification operation, perform a negative gate stress (NGS) operation on the memory cells in the memory cells of the selected row; and At the same time, perform an NGS operation on the memory cells in the memory cells of an unselected row coupled to an unselected word line among the word lines, the unselected word line being adjacent to the selected word line, Wherein the NGS operation includes applying a first voltage to a word line coupled to the memory cell on which the NGS operation is to be performed, and applying a second voltage to other word lines, the second voltage being higher than the first voltage; and A memory controller coupled to the memory device and configured to control the memory device.

43. The system according to claim 42, further comprising a host coupled to the memory controller, the host being configured to send or receive the data.

44. The system according to claim 42 or 43, wherein The memory device is a three-dimensional (3D) NAND flash memory device.

45. The system according to any one of claims 42-44, wherein, The peripheral circuit includes a word line driver coupled to the plurality of word lines, and wherein, to perform the NGS operation on the memory cells of the selected row and the unselected row, the word line driver is configured to apply either a negative voltage or a ground (GND) voltage on the selected word line and the unselected word line, respectively.

46. The system according to any one of claims 42-45, to perform the multi-pass programming, the peripheral circuit is configured to: in the last programming pass: In response to one of the memory cells in the selected row or the unselected row passing a corresponding verification operation immediately before the last programming pass, inhibiting a corresponding NGS operation on the one of the memory cells; and In response to another of the memory cells in the selected row or the unselected row not passing a corresponding verification operation immediately before the last programming pass, performing a corresponding NGS operation on the another of the memory cells.

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