Amplifier equipped with a conversion circuit that reduces the inherent time constant

Abstract

This invention relates to an amplifier for converting a differential input signal into a single-ended output signal. Specifically, this invention relates to an amplifier with a reduced inherent time constant of the conversion. The invention provides an amplifier including a conversion circuit for converting a differential input signal into a single-ended output signal. The conversion circuit includes: an input section for receiving the differential input signal; and an output section including an output port for providing the single-ended output signal, wherein the output section includes a capacitor element for reducing the inherent time constant of the conversion circuit.

Description

Technical Field

[0001] This invention relates to an amplifier for converting a differential input signal into a single-ended output signal. More particularly, it relates to an amplifier with a reduced inherent time constant for the conversion. The invention also relates to a method for operating such an amplifier. Background Technology

[0002] In transmitters (e.g., for optical communications), high-speed digital sources generate differential signals. Meanwhile, electro-optic modulators typically require single-ended input signals. For this purpose, driver amplifiers are used to convert the differential input to a single-ended output.

[0003] A key requirement for increasing the data rate of electro-optic transmitters is bandwidth. The wider the bandwidth, the higher the data rate. Users are interested in schemes that allow for wide-bandwidth differential inputs to single-ended output driver amplifiers in order to maximize the data rate of the electro-optic transmitter.

[0004] Figure 10 A typical differential input to single-ended output driver amplifier scheme used in the prior art is shown. This scheme consists of three blocks: a differential input to differential output block, a differential input to single-ended output block, and a single-ended input to single-ended output block. Each of these three blocks can consist of one or more internal gain stages. The differential input to single-ended output block is implemented using a differential pair with two inputs (Vin+ and Vin-) and only one output (Vout). The differential pair (in its simplest form) consists of two identical transistors (Q1 and Q2), a current source (IS), two identical load resistors (RD), and a bias voltage (VD). Figure 10 The two capacitors CDS in the diagram are not components of the differential pair; they refer to the inherent output parasitic capacitances of the two transistors. Figure 10 These two capacitors are shown because they are important for estimating the differential input-to-single-ended output voltage gain (AV) of the differential pair, as shown in the following equation:

[0005]

[0006] Where ω is the angular frequency, g m It is the transconductance of the transistor. According to equation (1), the bandwidth of the differential input to single-ended output driver amplifier in the prior art can be estimated, that is, the angular frequency at which the voltage gain is 3dB lower than the direct current (DC) value, which is expressed by the following equation:

[0007]

[0008] Figure 11 Typical voltage gain versus frequency behavior is shown, with the 3dB bandwidth also highlighted in the figure.

[0009] By considering equation (2), it can be noted that the bandwidth of a conventional differential input to single-ended output driver amplifier is essentially limited by the parasitic capacitor CDS, which depends on the size of the transistors (Q1 and Q2). The smaller the transistor size, the smaller the parasitic capacitor CDS, and the smaller the gain and linearity of the differential pair.

[0010] In summary, the solutions proposed in the prior art can only achieve limited bandwidth in practical designs due to trade-offs between gain and linearity. Therefore, an amplifier that can overcome these shortcomings is needed. Summary of the Invention

[0011] In view of the above problems and disadvantages, the embodiments of the present invention aim to improve conventional amplifiers.

[0012] The object of this invention is to realize a differential input to single-ended output driver amplifier with optimal wide bandwidth. For example, this aspect is beneficial for transmitters used in optical communications, where the wideband driver amplifier is used to boost the level of a high-speed digital source to ensure adequate power supply and proper driving of the electro-optic modulator.

[0013] Specifically, the objective of this invention is achieved through a differential-to-single-ended conversion circuit, which includes components connected to the closed output path of the circuit, the components being used to reduce the inherent time constant of the circuit. These components may be capacitors added to the differential-to-single-ended conversion circuit (e.g., differential pairs converting differential inputs to single-ended outputs). The resulting conversion function ensures a wide bandwidth can be achieved without affecting other critical performance values ​​of the amplifier. For example, the capacitance of the selected capacitor should be greater than the parasitic capacitance of the differential-to-single-ended conversion circuit.

[0014] The object of this invention is achieved by the solutions provided in the appended independent claims. Advantageous implementations of the invention are further defined in the dependent claims.

[0015] According to a first aspect, the present invention provides an amplifier including a conversion circuit for converting a differential input signal into a single-ended output signal. The conversion circuit includes: an input portion for receiving the differential input signal; and an output portion including an output port for providing the single-ended output signal, wherein the output portion includes a capacitor element for reducing the inherent time constant of the conversion circuit.

[0016] This is beneficial because it provides a differential input-to-single-ended output driver amplifier with optimal bandwidth.

[0017] In one implementation of the first aspect, the input portion is connected to the output portion via a first node and the output port, wherein the capacitor element is connected to the first node.

[0018] Specifically, the capacitor element is connected to a path opposite to the path that includes the output port.

[0019] This ensures that the capacitor element reduces the time constant.

[0020] In another implementation of the first aspect, the capacitance of the capacitor element is greater than the output parasitic capacitance of the input portion.

[0021] In another implementation of the first aspect, the capacitance of the capacitor element is greater than 4 / 3 times the output parasitic capacitance of the input portion.

[0022] Specifically, the capacitance of the capacitor element is 2.6 to 3.0 times the output parasitic capacitance of the input section, for example, 2.7 to 2.9 times the output parasitic capacitance of the input section.

[0023] Specifically, the capacitance of the capacitor element is substantially 2.8 times the output parasitic capacitance of the input section.

[0024] In another implementation of the first aspect, the capacitor element is connected to the closed output path of the conversion circuit.

[0025] In another implementation of the first aspect, the input portion includes a first input port, a second input port, a first transistor, a second transistor, and a current supply port, wherein the first transistor is connected to the output portion, the first input port, and the current supply port, and the second transistor is connected to the output portion, the second input port, and the current supply port.

[0026] Specifically, the current supply port includes a current source and / or a resistor. Specifically, the current source and / or the resistor may also be connected to ground potential.

[0027] In another implementation of the first aspect, the output parasitic capacitance of the input portion is based on the output parasitic capacitance of the first transistor and / or the output parasitic capacitance of the second transistor.

[0028] Specifically, the output parasitic capacitance of the input section is equal to the output parasitic capacitance of the first transistor and / or the output parasitic capacitance of the second transistor.

[0029] In another implementation of the first aspect, the output portion further includes a first resistor, a second resistor, and a voltage supply port, wherein the first resistor is connected to the input portion, the voltage supply port, and the second resistor, and the second resistor is connected to the input portion.

[0030] Specifically, the voltage supply port can be connected to a voltage source. Specifically, the voltage source can be connected to ground potential.

[0031] In another implementation of the first aspect, the first resistor of the output portion is connected to the first transistor of the input portion, and the second resistor of the output portion is connected to the second transistor of the input portion.

[0032] In another implementation of the first aspect, the output port is connected to the second resistor, and the capacitor element is connected to the first resistor.

[0033] In another implementation of the first aspect, the output port is connected to the first resistor, and the capacitive element is connected to the second resistor.

[0034] In another implementation of the first aspect, the capacitor element includes a stub or interdigitated capacitor, specifically, the stub includes a distributed stub.

[0035] In another implementation of the first aspect, the capacitor element is also connected to ground potential.

[0036] In another implementation of the first aspect, the capacitor element is also connected to the voltage supply port.

[0037] According to a second aspect, the present invention provides a method for operating an amplifier, the method comprising the steps of: an input portion of a conversion circuit of the amplifier receiving a differential input signal; the conversion circuit converting the differential input signal into a single-ended output signal; a capacitive element in the output portion reducing the inherent time constant of the conversion circuit; and the output portion of the conversion circuit providing the single-ended output signal.

[0038] In one implementation of the second aspect, the input portion is connected to the output portion via a first node and the output port, wherein the capacitor element is connected to the first node.

[0039] Specifically, the capacitor element is connected to a path opposite to the path that includes the output port.

[0040] In another implementation of the second aspect, the capacitance of the capacitor element is greater than the output parasitic capacitance of the input portion.

[0041] In another implementation of the second aspect, the capacitance of the capacitor element is greater than 4 / 3 times the output parasitic capacitance of the input portion.

[0042] Specifically, the capacitance of the capacitor element is 2.6 to 3.0 times the output parasitic capacitance of the input section, for example, 2.7 to 2.9 times the output parasitic capacitance of the input section.

[0043] Specifically, the capacitance of the capacitor element is substantially 2.8 times the output parasitic capacitance of the input section.

[0044] In another implementation of the second aspect, the capacitor element is connected to the closed output path of the conversion circuit.

[0045] In another implementation of the second aspect, the input section includes a first input port, a second input port, a first transistor, a second transistor, and a current supply port, wherein the first transistor is connected to the output section, the first input port, and the current supply port, and the second transistor is connected to the output section, the second input port, and the current supply port.

[0046] Specifically, the current supply port includes a current source and / or a resistor. Specifically, the current source and / or the resistor may also be connected to ground potential.

[0047] In another implementation of the second aspect, the output parasitic capacitance of the input portion is based on the output parasitic capacitance of the first transistor and / or the output parasitic capacitance of the second transistor.

[0048] Specifically, the output parasitic capacitance of the input section is equal to the output parasitic capacitance of the first transistor and / or the output parasitic capacitance of the second transistor.

[0049] In another implementation of the second aspect, the output section further includes a first resistor, a second resistor, and a voltage supply port, wherein the first resistor is connected to the input section, the voltage supply port, and the second resistor, and the second resistor is connected to the input section.

[0050] Specifically, the voltage supply port can be connected to a voltage source. Specifically, the voltage source can be connected to ground potential.

[0051] In another implementation of the second aspect, the first resistor of the output section is connected to the first transistor of the input section, and the second resistor of the output section is connected to the second transistor of the input section.

[0052] In another implementation of the second aspect, the output port is connected to the second resistor, and the capacitor element is connected to the first resistor.

[0053] In another implementation of the second aspect, the output port is connected to the first resistor, and the capacitor element is connected to the second resistor.

[0054] In another implementation of the second aspect, the capacitor element includes a stub or interdigitated capacitor, specifically, the stub includes a distributed stub.

[0055] In another implementation of the second aspect, the capacitor element is also connected to ground potential.

[0056] In another implementation of the second aspect, the capacitor element is also connected to the voltage supply port.

[0057] The method described according to the second aspect and its implementation can achieve the same advantages as the amplifier described according to the first aspect and its corresponding implementation.

[0058] It should be noted that all devices, elements, units, and modules described in this application can be implemented by software or hardware elements or any combination thereof. All steps performed by the various entities described in this application and the functions described to be performed by the various entities are intended to indicate that the respective entities are used to perform the corresponding steps and functions. Although the specific functions or steps performed by external entities are not reflected in the detailed description of the specific elements of the entities performing the specific steps or functions in the following description of specific embodiments, those skilled in the art will understand that these methods and functions can be implemented by corresponding hardware or software elements or any combination thereof. Attached Figure Description

[0059] The following detailed description of specific embodiments, in conjunction with the accompanying drawings, illustrates various aspects and implementations of the present invention.

[0060] Figure 1 An amplifier provided in an embodiment of the present invention is shown;

[0061] Figure 2 The amplifier provided in the embodiments of the present invention is shown in more detail;

[0062] Figure 3An example comparing the voltage gain of the solution provided in this embodiment of the invention with that of the prior art is shown;

[0063] Figure 4 A schematic diagram of another amplifier provided in an embodiment of the present invention is shown;

[0064] Figure 5 A schematic diagram of another amplifier provided in an embodiment of the present invention is shown;

[0065] Figure 6 A schematic diagram of another amplifier provided in an embodiment of the present invention is shown;

[0066] Figure 7 A schematic diagram of another amplifier provided in an embodiment of the present invention is shown;

[0067] Figure 8 A schematic diagram of another amplifier provided in an embodiment of the present invention is shown;

[0068] Figure 9 A schematic diagram of the method provided in an embodiment of the present invention is shown;

[0069] Figure 10 A schematic diagram of an amplifier provided by the prior art is shown;

[0070] Figure 11 An example of voltage gain versus frequency for a differential input to single-ended output driver amplifier provided by the prior art is shown. Detailed Implementation

[0071] Figure 1 An amplifier 100 according to an embodiment of the present invention is shown. The amplifier 100 includes a conversion circuit 101 for converting differential input signals 102a and 102b into a single-ended output signal 103. Therefore, the conversion circuit 101 includes: an input section 104 for receiving the differential input signals 102a and 102b; and an output section 105 including an output port 106 for providing the single-ended output signal 103. The output section 105 includes a capacitor element 107 for reducing the inherent time constant of the conversion circuit 101.

[0072] Figure 2 The amplifier 100 provided in an embodiment of the present invention is shown in more detail. Figure 2 The amplifier 100 shown has the same Figure 1 The amplifier shown in the figure has the same features and functions.

[0073] like Figure 2As shown, in the differential input to single-ended output differential pair of the amplifier 100 (including first node 201, first input port 202 and second input port 203, first transistor Q1 and second transistor Q2, first resistor RD1 and second resistor RD2, output port 106, current supply port 204 and voltage supply port 205), another capacitor element 107 (e.g., capacitor C1) is added to the closed output path of the differential input to single-ended output differential pair. The closed output path includes resistor RD1, the drain-source terminal of transistor Q1, the source-drain terminal of transistor Q2, and resistor RD2.

[0074] The differential input-to-single-ended output voltage gain of the differential pair provided in this embodiment of the invention can be expressed by the following equation:

[0075]

[0076] Among them, R D =R D1 =R D2 C DS =C DS1 =C DS2 In other words, equation (3) can also be expressed by the following formula:

[0077]

[0078] By comparing the voltage gain of the proposed scheme (Equation 3) with that of the prior art scheme (Equation 1), it can be noted that if C1 > 4 / 3·C DS Therefore, the proposed solution has a 3dB bandwidth that is wider than the existing technical solution.

[0079] Figure 2 The two capacitors CDS1 and CDS2 are not components of the differential pair; they refer to the inherent output parasitic capacitances of the two transistors Q1 and Q2, respectively.

[0080] In order to better illustrate the advantages of the embodiments of the present invention, given that Figure 3 The differential input-to-single-ended output differential pair designed according to an embodiment of the present invention is compared with a differential pair designed according to a prior art solution. For this comparison, the same transistors (Q1 and Q2), the same load resistors (RD1, RD2), the same current source (IS), and the same bias voltage (VD) are used in both cases. Furthermore, the capacitor C1 is selected to be 2.8 times the CDS for the comparison (this is an optional feature of the embodiments of the present invention; other ratios can also be used to achieve the desired effect). Figure 3A comparison of the voltage gains obtained in the two cases is shown, where the solid line represents the voltage gain of the solution provided by the embodiments of the present invention, and the dashed line represents the voltage gain of the prior art solution. It can be noted that, considering the same transistors, load resistors, and bias current and voltage—that is, the same DC gain, linearity, and power consumption—the solution provided by the embodiments of the present invention achieves a wider bandwidth compared to the prior art solution.

[0081] Figure 4 A schematic diagram of an amplifier 100 provided in an embodiment of the present invention is shown. Figure 4 The amplifier 100 shown includes the same features as described above. Figure 1 and Figure 2 It has the same features and functions as the amplifier 100 shown in the figure.

[0082] Figure 4 The embodiment of amplifier 100 shown includes a differential pair (transistor Q1, transistor Q2, first resistor RD1, second resistor RD2, voltage source VD and current source IS), capacitor C1 107, differential inputs (Vin+ and Vin- located at the first input port 202 and the second input port 203, respectively) and a single-ended output 106 (providing Vout).

[0083] The transistors Q1 and Q2 can have the same size. However, they can also have different sizes. The resistors RD1 and RD2 can have the same value. However, they can also have different values. The value of the capacitor C1 is chosen to optimize the bandwidth of the driver amplifier. For example, Figure 4 The embodiments shown are the simplest way to fully incorporate the invention in monolithic microwave integrated circuit technology.

[0084] Figure 5 An alternative embodiment of the invention is shown, wherein the output voltage Vout and capacitor C1 are inverted at node 107.

[0085] Figure 6 Another alternative embodiment of the invention is shown, wherein capacitor C1 107 is implemented by distributed stubs.

[0086] Figure 7 Another alternative embodiment of the invention is shown, wherein capacitor C1 107 is implemented by an interdigitated capacitor.

[0087] Figure 8 Another alternative embodiment of the invention is shown, wherein capacitor C1 107 is connected to the bias voltage supply VD instead of ground.

[0088] Figure 9A schematic diagram of a method 900 for operating an amplifier 100 (e.g., for an optical communication device) is shown. The method 900 includes a first step: an input portion 104 of a conversion circuit 101 of the amplifier 100 receives (901) differential input signals 102a, 102b. The method 900 includes a further step: the conversion circuit 101 converts (902) the differential input signals 102a, 102b into a single-ended output signal 103. The method 900 includes a further step: a capacitor element 107 of an output portion 105 reduces (903) the inherent time constant of the conversion circuit 101. The method 900 further includes the step of: the output portion 105 of the conversion circuit 101 providing (904) the single-ended output signal 103.

[0089] Embodiments of the invention have been described in conjunction with different examples and implementations. However, based on a study of the drawings, the invention, and the independent claims, those skilled in the art will be able to understand and implement other variations when carrying out the claimed invention. In the claims and the description, the word "comprising" does not exclude other elements or steps, and the indefinite article "a" does not exclude a plurality. A single element or other unit may fulfill the function of several entities or items listed in the claims. Listing measures in different dependent claims does not imply that combinations of these measures cannot be used in advantageous implementations.

Claims

1. An amplifier (100), characterized in that, include: A conversion circuit (101) is used to convert differential input signals (102a, 102b) into single-ended output signals (103). The conversion circuit (101) includes: an input section (104) for receiving the differential input signals (102a, 102b); and an output section (105) including an output port (106) for providing the single-ended output signal (103). The output section (105) includes a capacitor element (107) for reducing the inherent time constant of the conversion circuit (101); The input section (104) is connected to the output section (105) via a first node (201) and the output port (106), wherein the capacitor element (107) is connected to the first node (201), and the capacitance of the capacitor element (107) is greater than the output parasitic capacitance of the input section (104).

2. The amplifier (100) according to claim 1, characterized in that, The capacitance of the capacitor element (107) is greater than 4 / 3 times the output parasitic capacitance of the input section (104).

3. The amplifier (100) according to claim 1, characterized in that, The capacitor element (107) is connected to the closed output path of the conversion circuit (101).

4. The amplifier (100) according to claim 1, characterized in that, The input section (104) includes a first input port (202), a second input port (203), a first transistor (Q1), a second transistor (Q2), and a current supply port (204), wherein the first transistor (Q1) is connected to the output section (105), the first input port (202), and the current supply port (204), and the second transistor (Q2) is connected to the output section (105), the second input port (203), and the current supply port (204).

5. The amplifier (100) according to claim 4, characterized in that, The output parasitic capacitance of the input section (104) is based on the output parasitic capacitance (CDS1) of the first transistor (Q1) and / or the output parasitic capacitance (CDS2) of the second transistor (Q2).

6. The amplifier (100) according to claim 1, characterized in that, The output section (105) further includes a first resistor (RD1), a second resistor (RD2) and a voltage supply port (205), wherein the first resistor (RD1) is connected to the input section (104), the voltage supply port (205) and the second resistor (RD2), and the second resistor (RD2) is connected to the input section (104).

7. The amplifier (100) according to claim 6, characterized in that, The first resistor (RD1) of the output section (105) is connected to the first transistor (Q1) of the input section (104), and the second resistor (RD2) of the output section (105) is connected to the second transistor (Q2) of the input section (104).

8. The amplifier (100) according to claim 6 or 7, characterized in that, The output port (106) is connected to the second resistor (RD2), and the capacitor element (107) is connected to the first resistor (RD1).

9. The amplifier (100) according to claim 6 or 8, characterized in that, The output port (106) is connected to the first resistor (RD1), and the capacitor element (107) is connected to the second resistor (RD2).

10. The amplifier (100) according to claim 1, characterized in that, The capacitor element (107) includes a stub or interdigitated capacitor, specifically, the stub includes a distributed stub.

11. The amplifier (100) according to claim 1, characterized in that, The capacitor element (107) is also connected to ground potential.

12. The amplifier (100) according to claim 1, characterized in that, The capacitor element (107) is also connected to the voltage supply port (205).

13. A method (900) for operating an amplifier (100), characterized in that, The method (900) includes the following steps: The input section (104) of the conversion circuit (101) of the amplifier (100) receives (901) differential input signals (102a, 102b). The conversion circuit (101) converts (902) the differential input signals (102a, 102b) into single-ended output signals (103). The capacitor element (107) of the output section (105) reduces (903) the inherent time constant of the conversion circuit (101); the input section (104) is connected to the output section (105) through a first node (201) and an output port (106), wherein the capacitor element (107) is connected to the first node (201); the capacitance of the capacitor element (107) is greater than the output parasitic capacitance of the input section (104); The output portion (105) of the conversion circuit (101) provides (904) the single-ended output signal (103).

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