Maximum allowed block size for BDPCM mode

Abstract

A device for decoding video data may be configured to: receive a syntax element indicating a maximum block size for a transform skip mode; determine a maximum block size for a block-based delta pulse code modulation (BDPCM) mode based on the syntax element; and decode a block of video data based on the determined maximum block size for the BDPCM mode.

Description

[0001] This application claims priority to U.S. patent application No. 16 / 905,100 filed on June 18, 2020, which claims priority to U.S. Provisional Patent Application No. 62 / 863,734 filed on June 19, 2019, and the entire contents of each application are incorporated herein by reference. Technical Field

[0002] The present disclosure relates to video encoding and video decoding. Background Art

[0003] Digital video capabilities may be incorporated into a wide variety of devices, including digital televisions, digital direct broadcast systems, wireless broadcast systems, personal digital assistants (PDAs), laptop or desktop computers, tablet computers, electronic book readers, digital cameras, digital recording devices, digital media players, video game devices, video game consoles, cellular or satellite wireless telephones, so-called "smart phones", video teleconferencing equipment, video streaming equipment, and the like. Digital video devices implement video coding techniques, such as those described in the standards specified by MPEG-2, MPEG-4, ITU-T H.263, ITU-T H.264 / MPEG-4 Part 10, Advanced Video Coding (AVC), ITU-T H.265 / High Efficiency Video Coding (HEVC), and extensions of these standards. Video devices may more efficiently send, receive, encode, decode, and / or store digital video information by implementing these video coding techniques.

[0004] Video coding techniques include spatial (intra-frame) prediction and / or temporal (inter-frame) prediction to reduce or eliminate redundancy inherent in video sequences. For block-based video coding, a video segment (e.g., a video picture or a portion of a video picture) may be divided into video blocks, which may also be referred to as coding tree units (CTUs), coding units (CUs), and / or coding nodes. Video blocks in an intra-coded (I) segment of a picture are encoded using spatial prediction relative to reference samples in neighboring blocks in the same picture. Video blocks in an inter-coded (P or B) segment of a picture may use spatial prediction relative to reference samples in neighboring blocks in the same picture, or temporal prediction relative to reference samples in other reference pictures. Pictures may be referred to as frames, and reference pictures may be referred to as reference frames. Summary of the invention

[0005] The present disclosure describes techniques related to block-based incremental pulse code modulation (BDPCM) modes, residual BDPCM modes, and transform skip modes. More specifically, the present disclosure describes techniques that can be used to align the maximum block size for BDPCM mode and residual BDPCM mode with the maximum block size for transform skip mode in the following manner: based on the maximum block size for transform skip mode, the maximum block size for BDPCM or residual BDPCM mode is determined. By aligning the maximum block size for BDPCM mode and residual BDPCM mode with the maximum block size for transform skip mode in this manner, the techniques of the present disclosure can simplify various aspects of BDPCM mode and residual BDPCM mode signaling, and can prevent inconsistent bitstreams.

[0006] According to an example, a method for decoding video data includes: receiving a syntax element indicating a maximum block size for a transform skip mode; determining a maximum block size for a BDPCM mode based on the syntax element; and decoding a block of video data based on the determined maximum block size for the BDPCM mode.

[0007] According to another example, a method for encoding video data includes: determining a maximum block size for a transform skip mode; determining a maximum block size for a BDPCM mode based on the maximum block size for the transform skip mode; and encoding a video data block based on the determined maximum block size for the BDPCM mode.

[0008] According to another example, a device for decoding video data includes: a memory configured to store video data, and one or more processors configured to perform the following operations: receiving a syntax element indicating a maximum block size for a transform skip mode; determining a maximum block size for a BDPCM mode based on the syntax element; and decoding a block of video data based on the determined maximum block size for the BDPCM mode.

[0009] According to another example, a device for encoding video data includes: a memory configured to store video data, and one or more processors configured to perform the following operations: determine a maximum block size for a transform skip mode; determine a maximum block size for a BDPCM mode based on the maximum block size for the transform skip mode; and encode a block of video data based on the determined maximum block size for the BDPCM mode.

[0010] According to another example, a computer-readable storage medium stores instructions that, when executed by one or more processors, cause the one or more processors to perform the following operations: receive a syntax element indicating a maximum block size for a transform skip mode; determine a maximum block size for a BDPCM mode based on the syntax element; and decode a video data block based on the determined maximum block size for the BDPCM mode.

[0011] According to another example, a computer-readable storage medium stores instructions that, when executed by one or more processors, cause the one or more processors to perform the following operations: determine a maximum block size for a transform skip mode; determine a maximum block size for a BDPCM mode based on the maximum block size for the transform skip mode; and encode a video data block based on the determined maximum block size for the BDPCM mode.

[0012] According to another example, a device for decoding video data includes: a unit for receiving a syntax element for indicating a maximum block size of a transform skip mode; a unit for determining a maximum block size for a BDPCM mode based on the syntax element; and a unit for decoding a video data block based on the determined maximum block size for the BDPCM mode.

[0013] According to another example, a device for encoding video data includes: a unit for determining a maximum block size for a transform skip mode; a unit for determining a maximum block size for a BDPCM mode based on the maximum block size for the transform skip mode; and a unit for encoding a video data block based on the determined maximum block size for the BDPCM mode.

[0014] The details of one or more examples are set forth in the accompanying drawings and the description below. Other features, objects, and advantages will be apparent from the description and drawings, and from the claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 is a block diagram illustrating an example video encoding and decoding system that may perform the techniques of this disclosure.

[0016] Figure 2A and Figure 2B is a conceptual diagram illustrating an exemplary quadtree binary tree (QTBT) structure and a corresponding coding tree unit (CTU).

[0017] Figure 3 is a block diagram illustrating an example video encoder that may perform the techniques of this disclosure.

[0018] Figure 4 is a block diagram illustrating an example video decoder that may perform the techniques of this disclosure.

[0019] Figure 5 is a flow chart illustrating an exemplary process performed by a video encoder.

[0020] Figure 6 is a flow chart illustrating an exemplary process performed by a video decoder.

[0021] Figure 7 is a flow chart illustrating an example process performed by a video encoder, in accordance with one or more techniques of this disclosure.

[0022] Figure 8 is a flow chart illustrating an example process performed by a video decoder, in accordance with one or more techniques of this disclosure. DETAILED DESCRIPTION

[0023] Video decoding (e.g., video encoding and / or video decoding) typically involves predicting a block of video data based on decoded video data blocks in the same picture (e.g., intra-frame prediction), or predicting a block of video data based on decoded video data blocks in different pictures (e.g., inter-frame prediction). Examples of intra-frame prediction modes include various directional modes, as well as planar modes and DC modes. The block-based incremental pulse code modulation (BDPCM) mode and the residual domain BDPCM (RDPCM) mode described in more detail below are also types of intra-frame prediction modes. In some cases, the video encoder also calculates residual data by comparing the predicted block with the original block. Therefore, the residual data represents the difference between the predicted block and the original block. In order to reduce the number of bits required to signal the residual data, the video encoder can transform and quantize the residual data and signal the transformed and quantized residual data in the encoded bitstream.

[0024] The video decoder decodes the residual data and adds the residual data to the prediction block to produce a reconstructed video block that more closely matches the original video block than the prediction block alone. The compression achieved by the transform and quantization process may be lossy, meaning that the transform and quantization process may introduce distortion in the decoded video data. Due to the losses introduced by the transform and quantization of the residual data, the first reconstructed block may have distortion or artifacts. One common type of artifact or distortion is called blocking, in which the boundaries of the blocks used to decode the video data are visible.

[0025] To further improve the quality of the decoded video, the video decoder may perform one or more filtering operations on the reconstructed video blocks. Examples of these filtering operations include: deblocking filtering, sample adaptive offset (SAO) filtering, and adaptive loop filtering (ALF). The parameters for these filtering operations may be determined by the video encoder and explicitly signaled in the coded video bitstream, or may be implicitly determined by the video decoder without explicitly signaling these parameters in the coded video bitstream.

[0026] In some decoding scenarios, the video encoder may encode a block of video data in a transform skip mode in which the above-mentioned transform process is not performed (i.e., the transform process is skipped). BDPCM mode and residual BDPCM mode are examples of modes that utilize transform skip, although transform skip can also be used in other modes and other encoding scenarios. For blocks encoded in transform skip mode, the residual data is not transformed but is still quantized. Therefore, transform skip coefficients generally correspond to quantized representations of residual values, while transform coefficients generally correspond to residual values ​​of a block that have been quantized and transformed to generate transform coefficients. As used in the present disclosure, the term "coefficient" may refer to a transform coefficient or a transform skip coefficient, and may or may not be quantized.

[0027] The present disclosure describes techniques related to BDPCM mode, residual BDPCM mode, and transform skip mode. Specifically, the present disclosure describes techniques that can be used to align the maximum block size for BDPCM mode and residual BDPCM mode with the maximum block size for transform skip mode by performing the following operations: determining the maximum block size for BDPCM or residual BDPCM mode based on the maximum block size for transform skip mode. By aligning the maximum block size for BDPCM mode and residual BDPCM mode with the maximum block size for transform skip mode in this manner, the techniques of the present disclosure can simplify various aspects of BDPCM mode and residual BDPCM mode signaling, and can prevent inconsistent bitstreams.

[0028] The present disclosure may use the term incremental pulse code modulation (DPCM) mode to refer generally to BDPCM mode or RDPCM mode. In addition, the term BDPCM mode may also be considered to include RDPCM mode as a type of BDPCM mode. In addition, it should be noted that the abbreviation RDPCM refers to any one of residual BDPCM, residual domain BDPCM, and quantized residual domain BDPCM, which are all alternative names for RDPCM.

[0029] The technology of the present disclosure can be applied to any existing video codec (e.g., the High Efficiency Video Coding (HEVC) standard, the Versatile Video Coding (VVC) currently under development), or become an efficient coding tool in future video coding standards.

[0030] Figure 1 1 is a block diagram illustrating an exemplary video encoding and decoding system 100 that can perform the techniques of the present disclosure. The techniques of the present disclosure are generally directed to the decoding (encoding and / or decoding) of video data. Generally, video data includes any data used to process video. Therefore, video data can include original, unencoded video, encoded video, decoded (e.g., reconstructed) video, and video metadata (e.g., signaling data).

[0031] like Figure 1 As shown in , in this example, system 100 includes source device 102, which provides encoded video data to be decoded and displayed by destination device 116. Specifically, source device 102 provides video data to destination device 116 via computer-readable medium 110. Source device 102 and destination device 116 can both be any of a wide range of devices, including desktop computers, notebook (e.g., laptop) computers, tablet computers, set-top boxes, telephone handsets (e.g., smart phones), televisions, cameras, display devices, digital media players, video game consoles, video streaming devices, etc. In some cases, source device 102 and destination device 116 can be equipped for wireless communication and can therefore be referred to as wireless communication devices.

[0032] exist Figure 1 In the example of the present invention, the source device 102 includes a video source 104, a memory 106, a video encoder 200, and an output interface 108. The destination device 116 includes an input interface 122, a video decoder 300, a memory 120, and a display device 118. According to the present disclosure, the video encoder 200 of the source device 102 and the video decoder 300 of the destination device 116 can be configured to apply the technology described in the present disclosure. Therefore, the source device 102 represents an example of a video encoding device, and the destination device 116 represents an example of a video decoding device. In other examples, the source device and the destination device may include other components or arrangements. For example, the source device 102 may receive video data from an external video source such as an external camera. Similarly, the destination device 116 may be docked with an external display device instead of including an integrated display device.

[0033] like Figure 1The system 100 shown in is only an example. In general, any digital video encoding and / or decoding device can perform the techniques described in the present disclosure. The source device 102 and the destination device 116 are only examples of such decoding devices, wherein the source device 102 generates encoded video data for transmission to the destination device 116. The present disclosure refers to a "decoding" device as a device that performs decoding (encoding and / or decoding) of data. Therefore, the video encoder 200 and the video decoder 300 represent examples of decoding devices (specifically, video encoders and video decoders), respectively. In some examples, the devices 102 and 116 can operate in a substantially symmetrical manner so that each of the devices 102 and 116 includes a video encoding and decoding component. Therefore, the system 100 can support one-way or two-way video transmission between the source device 102 and the destination device 116, for example, for video streaming, video playback, video broadcasting, or video telephony.

[0034] Typically, the video source 104 represents a source of video data (i.e., original, unencoded video data) and provides a continuous sequence of pictures of the video data (also referred to as "frames") to the video encoder 200, wherein the video encoder 200 encodes the data of the pictures. The video source 104 of the source device 102 may include a video capture device (e.g., a camera), a video archive containing previously captured original video, and / or a video feed interface for receiving video from a video content provider. As another alternative, the video source 104 may generate computer graphics-based data as a source video, or a combination of real-time video, archived video, and computer-generated video. In each case, the video encoder 200 encodes captured, pre-captured, or computer-generated video data. The video encoder 200 may rearrange the images from the order in which they are received (sometimes referred to as "display order") to a decoding order for decoding. The video encoder 200 may generate a bitstream including encoded video data. Source device 102 may then output the encoded video data onto computer-readable medium 110 via output interface 108 for receipt and / or retrieval by, for example, input interface 122 of destination device 116 .

[0035] The memory 106 of the source device 102 and the memory 120 of the destination device 116 represent general purpose memories. In some examples, the memories 106, 120 can store raw video data, for example, raw video from the video source 104 and raw decoded video data from the video decoder 300. Additionally or alternatively, the memories 106, 120 can store software instructions that can be executed by, for example, the video encoder 200 and the video decoder 300, respectively. Although shown separately from the video encoder 200 and the video decoder 300 in this example, it should be understood that the video encoder 200 and the video decoder 300 can also include internal memory to achieve functionally similar or equivalent purposes. In addition, the memories 106, 120 can store encoded video data (e.g., output from the video encoder 200 and input to the video decoder 300). In some examples, a portion of the memories 106, 120 can be allocated as one or more video buffers, for example, for storing raw, decoded and / or encoded video data.

[0036] The computer-readable medium 110 may represent any type of medium or device capable of transmitting the encoded video data from the source device 102 to the destination device 116. In one example, the computer-readable medium 110 represents a communication medium for enabling the source device 102 to send the encoded video data directly to the destination device 116 in real time, for example, via a radio frequency network or a computer-based network. The output interface 108 may modulate the transmission signal including the encoded video data, and the input interface 122 may demodulate the received transmission signal according to a communication standard such as a wireless communication protocol. The communication medium may include any wireless or wired communication medium, such as a radio frequency (RF) spectrum or one or more physical transmission lines. The communication medium may form part of a packet-based network such as a local area network, a wide area network, or a global network (e.g., the Internet). The communication medium may include a router, a switch, a base station, or any other device that facilitates communication from the source device 102 to the destination device 116.

[0037] In some examples, source device 102 may output the encoded data from output interface 108 to storage device 112. Similarly, destination device 116 may access the encoded data from storage device 112 via input interface 122. Storage device 112 may include any of a variety of distributed or locally accessed data storage media (e.g., hard drive, Blu-ray disc, DVD, CD-ROM, flash memory, volatile or non-volatile memory) or any other suitable digital storage media for storing encoded video data.

[0038] In some examples, source device 102 may output the encoded video data to file server 114 or another intermediate storage device that may store the encoded video data generated by source device 102. Destination device 116 may access the stored video data from file server 114 via streaming or downloading.

[0039] The file server 114 may be any type of server device capable of storing encoded video data and sending the encoded video data to the destination device 116. The file server 114 may represent a network server (e.g., for a website), a server configured to provide a file transfer protocol service (e.g., a file transfer protocol (FTP) or a file transfer protocol over unidirectional transport (FLUTE) protocol), a content delivery network (CDN) device, a hypertext transfer protocol (HTTP) server, a multimedia broadcast multicast service (MBMS) or an enhanced MBMS (eMBMS) server, and / or a network attached storage (NAS) device. Additionally or alternatively, the file server 114 may implement one or more HTTP streaming protocols such as Dynamic Adaptive Streaming over HTTP (DASH), HTTP Real-Time Streaming (HLS), Real-Time Streaming Protocol (RTSP), HTTP Dynamic Streaming, and the like.

[0040] The destination device 116 may access the encoded video data from the file server 114 through any standard data connection, including an Internet connection. This may include a wireless channel (e.g., a Wi-Fi connection), a wired connection (e.g., a digital subscriber line (DSL), a cable modem, etc.), or a combination of both, suitable for accessing encoded video data already stored on the file server 114. The input interface 122 may be configured to operate according to any one or more of the various protocols discussed above to retrieve or receive media data from the file server 114, or to operate according to other such protocols for retrieving media data.

[0041] Output interface 108 and input interface 122 may represent wireless transmitters / receivers, modems, wired network components (e.g., Ethernet cards), wireless communication components that operate according to any of the various IEEE 802.11 standards, or other physical components. In examples where output interface 108 and input interface 122 include wireless components, output interface 108 and input interface 122 may be configured to transmit data, such as encoded video data, according to cellular communication standards such as 4G, 4G-LTE (Long Term Evolution), Advanced LTE, 5G, etc. In some examples where output interface 108 includes a wireless transmitter, output interface 108 and input interface 122 may be configured to transmit data, such as encoded video data, according to other wireless standards such as the IEEE 802.11 specification, the IEEE 802.15 specification (e.g., ZigBeeTM ), Bluetooth TM standards, etc., to transmit data such as encoded video data. In some examples, source device 102 and / or destination device 116 may include respective system-on-chip (SoC) devices. For example, source device 102 may include an SoC device to perform functions attributed to video encoder 200 and / or output interface 108, while destination device 116 may include an SoC device to perform functions attributed to video decoder 300 and / or input interface 122.

[0042] The techniques of the present disclosure may be applied to video encoding to support any of a variety of multimedia applications, such as over-the-air television broadcasting, cable television transmission, satellite television transmission, Internet streaming video transmission (e.g., Dynamic Adaptive Streaming over HTTP (DASH), digital video encoded onto a data storage medium), decoding of digital video stored on a data storage medium, or other applications.

[0043] The input interface 122 of the destination device 116 receives the encoded video bitstream from the computer-readable medium 110 (e.g., the storage device 112, the file server 114, etc.). The encoded video bitstream may include signaling information defined by the video encoder 200 and used by the video decoder 300, such as syntax elements with values ​​describing characteristics and processing of video blocks or other decoding units (e.g., slices, pictures, groups of pictures, sequences, etc.). The display device 118 displays decoded pictures of the decoded video data to a user. The display device 118 may represent any of a variety of display devices, such as a cathode ray tube (CRT), a liquid crystal display (LCD), a plasma display, an organic light emitting diode (OLED) display, or another type of display device.

[0044] Although not in Figure 1 , but in some examples, the video encoder 200 and the video decoder 300 may be integrated with an audio encoder and / or an audio decoder, respectively, and may include appropriate MUX-DEMUX units or other hardware and / or software to process a multiplexed stream including both audio and video in a common data stream. If applicable, the MUX-DEMUX unit may conform to the ITU H.223 multiplexer protocol or other protocols (e.g., User Datagram Protocol (UDP)).

[0045] The video encoder 200 and the video decoder 300 can each be implemented as any of a variety of suitable encoder and / or decoder circuits, such as one or more microprocessors, digital signal processors (DSPs), application specific integrated circuits (ASICs), field programmable gate arrays (FPGAs), discrete logic, software, hardware, firmware, or any combination thereof. When these techniques are partially implemented in software, the device can store instructions for the software in an appropriate non-temporary computer-readable medium and use one or more processors to execute these instructions in hardware to perform the techniques of the present disclosure. Each of the video encoder 200 and the video decoder 300 can be included in one or more encoders or decoders, any of which can be integrated as part of a combined encoder / decoder (CODEC) in the corresponding device. The device including the video encoder 200 and / or the video decoder 300 can include an integrated circuit, a microprocessor, and / or a wireless communication device (e.g., a cellular phone).

[0046] The video encoder 200 and the video decoder 300 may operate according to video coding standards, including ITU-T H.261, ISO / IEC MPEG-1 video, ITU-T H.262 or ISO / IEC MPEG-2 video, ITU-T H.263, ISO / IEC MPEG-4 video, and ITU-T H.264 (also known as ISO / IEC MPEG-4 AVC), including its scalable video coding (SVC) and multi-view video coding (MVC) extensions.

[0047] In addition, the Joint Collaborative Team on Video Coding (JCT-VC) and the Joint Collaborative Team on 3D Video Coding Extensions Development (JCT-3V) of the ITU-T Video Coding Experts Group (VCEG) and the ISO / IEC Moving Picture Experts Group (MPEG) recently developed a new video coding standard, High Efficiency Video Coding (HEVC) or ITU-T H.265, including its range extension, multi-view extension (MV-HEVC), and scalable extension (SHVC).

[0048] Alternatively or additionally, the video encoder 200 and the video decoder 300 may operate according to other proprietary or industry standards such as the Joint Exploration Experimental Model (JEM) or ITU-T H.266 (also known as Versatile Video Coding (VVC)). A recent draft of the VVC standard is described in the following document: Bross, et al. "Versatile Video Coding (Draft 5)," 14th Meeting of the Joint Video Experts Group (JVET) of ITU-T SG 16WP 3 and ISO / IEC JTC 1 / SC 29 / WG 11: JVET-N1001-v8, March 19-27, 2019, Geneva, Switzerland (hereinafter referred to as "VVC Draft 5"). However, the technology of the present disclosure is not limited to any particular coding standard.

[0049] Typically, the video encoder 200 and the video decoder 300 can perform block-based encoding of the picture. The term "block" generally refers to a structure that includes data to be processed (e.g., encoding, decoding, or other methods used in the encoding and / or decoding process). For example, a block may include a two-dimensional matrix of samples of luminance and / or chrominance data. Typically, the video encoder 200 and the video decoder 300 can decode video data represented in YUV (e.g., Y, Cb, Cr) format. That is, instead of decoding the red, green, and blue (RGB) data of the samples of the picture, the video encoder 200 and the video decoder 300 can decode the luminance and chrominance components, where the chrominance components may include red and blue chrominance components. In some examples, the video encoder 200 converts the received RGB format data into a YUV representation before encoding, and the video decoder 300 converts the YUV representation into an RGB format. Alternatively, pre-processing and post-processing units (not shown) can perform these conversions.

[0050] The present disclosure may generally relate to the decoding (e.g., encoding and decoding) of a picture to include the process of encoding or decoding data of a picture. Similarly, the present disclosure may relate to the decoding of blocks of a picture to include the process of encoding or decoding data of these blocks (e.g., prediction and / or residual coding). A coded video bitstream generally includes a series of values ​​for syntax elements, where these syntax elements represent decoding decisions (e.g., decoding modes) and the division of a picture into blocks. Therefore, references to decoding a picture or a block should generally be understood as the decoded values ​​of the syntax elements used to form the picture or block.

[0051] HEVC defines various blocks, including coding units (CUs), prediction units (PUs), and transform units (TUs). According to HEVC, a video decoder (e.g., video encoder 200) divides a coding tree unit (CTU) into CUs according to a quadtree structure. That is, the video decoder divides the CTU and CU into four equal, non-overlapping squares, and each node of the quadtree has zero or four child nodes. A node without child nodes may be referred to as a "leaf node", and the CU of such a leaf node may include one or more PUs and / or one or more TUs. The video decoder may further partition the PU and TU. For example, in HEVC, a residual quadtree (RQT) represents the partitioning of a TU. In HEVC, a PU represents inter-frame prediction data, and a TU represents residual data. An intra-predicted CU includes intra-frame prediction information (e.g., an intra-frame mode indication).

[0052] As another example, the video encoder 200 and the video decoder 300 may be configured to operate according to JEM or VVC. According to JEM or VVC, a video decoder (e.g., video encoder 200) divides a picture into a plurality of coding tree units (CTUs). The video encoder 200 may divide the CTU according to a tree structure such as a quadtree-binary tree (QTBT) structure or a multi-type tree (MTT) structure. The QTBT structure eliminates the concept of multiple partition types, such as the separation between CU, PU, ​​and TU of HEVC. The QTBT structure includes two levels: a first level divided according to quadtree partitioning and a second level divided according to binary tree partitioning. The root node of the QTBT structure corresponds to the CTU. The leaf nodes of the binary tree correspond to coding units (CUs).

[0053] In the MTT partition structure, blocks can be partitioned using quadtree (QT) partitioning, binary tree (BT) partitioning, and one or more types of ternary tree (TT) partitioning. Ternary tree partitioning is a partitioning of a block into three sub-blocks. In some examples, ternary tree partitioning divides a block into three sub-blocks without dividing the original block through the center. The partitioning types in MTT (e.g., QT, BT, and TT) can be symmetric or asymmetric.

[0054] In some examples, the video encoder 200 and the video decoder 300 may use a single QTBT or MTT structure to represent each of the luma and chroma components, while in other examples, the video encoder 200 and the video decoder 300 may use two or more QTBT or MTT structures, such as one QTBT / MTT structure for the luma component and another QTBT / MTT structure for the two chroma components (or two QTBT / MTT structures for corresponding chroma components).

[0055] The video encoder 200 and the video decoder 300 may be configured to use quadtree partitioning, QTBT partitioning, MTT partitioning, or other partitioning structures per HEVC. For ease of illustration, a description of the techniques of the present disclosure is given with respect to QTBT partitioning. However, it should be understood that the techniques of the present disclosure may also be applied to video decoders configured to use quadtree partitioning or other types of partitioning.

[0056] The present disclosure may use "NxN" and "N by N" interchangeably to refer to the sample size of a block (e.g., a CU or other video block) in the vertical and horizontal dimensions, such as 16x16 samples or 16 by 16 samples. Typically, a 16x16 CU will have 16 samples in the vertical direction (y=16) and 16 samples in the horizontal direction (x=16). Likewise, an NxN CU typically has N samples in the vertical direction and N samples in the horizontal direction, where N represents a non-negative integer value. The samples in a CU may be arranged in rows and columns. In addition, a CU does not necessarily have the same number of samples in the horizontal direction as in the vertical direction. For example, a CU may include NxM samples, where M is not necessarily equal to N.

[0057] The video encoder 200 encodes video data for a CU representing prediction and / or residual information and other information. The prediction information indicates how the CU will be predicted in order to form a prediction block for the CU. The residual information typically represents the sample-by-sample difference between the samples of the CU before encoding and the prediction block.

[0058] In order to predict a CU, the video encoder 200 can generally form a prediction block for the CU by inter-frame prediction or intra-frame prediction. Inter-frame prediction generally refers to predicting a CU from data of a previously encoded picture, while intra-frame prediction generally refers to predicting a CU from previously encoded data of the same picture. In order to perform inter-frame prediction, the video encoder 200 can use one or more motion vectors to generate a prediction block. The video encoder 200 can generally perform a motion search to identify a reference block that closely matches the CU, for example, in terms of the difference between the CU and the reference block. The video encoder 200 can use the sum of absolute differences (SAD), the sum of square differences (SSD), the mean absolute difference (MAD), the mean square difference (MSD) or other such difference calculations to calculate a difference metric to determine whether the reference block closely matches the current CU. In some examples, the video encoder 200 can use unidirectional prediction or bidirectional prediction to predict the current CU.

[0059] Some examples of JEM and VVC also provide an affine motion compensation mode, which can be considered an inter-frame prediction mode. In the affine motion compensation mode, the video encoder 200 can determine two or more motion vectors representing non-translational motion, such as reduction or enlargement, rotation, perspective motion, or other irregular motion types.

[0060] To perform intra prediction, the video encoder 200 can select an intra prediction mode to generate a prediction block. Certain examples of JEM and VVC provide 67 intra prediction modes, including various directional modes as well as planar modes and DC modes. Typically, the video encoder 200 selects an intra prediction mode that describes the neighboring samples relative to the current block (e.g., the block of the CU) and predicts the samples of the current block from the neighboring samples. Assuming that the video encoder 200 decodes the CTU and CU in a raster scan order (from left to right, from top to bottom), these samples can typically be above, above left, or to the left of the current block in the same picture as the current block.

[0061] The video encoder 200 encodes data representing the prediction mode of the current block. For example, for inter-frame prediction mode, the video encoder 200 can encode data indicating which mode of various available inter-frame prediction modes is used, and motion information of the corresponding mode. For unidirectional or bidirectional inter-frame prediction, for example, the video encoder 200 can encode the motion vector using advanced motion vector prediction (AMVP) or merge mode. The video encoder 200 can use a similar mode to encode the motion vector of the affine motion compensation mode.

[0062] After a prediction such as intra prediction or inter prediction of a block, the video encoder 200 may calculate residual data for the block. The residual data (e.g., a residual block) represents the sample-by-sample difference between the block and a prediction block for the block formed using a corresponding prediction mode. The video encoder 200 may apply one or more transforms to the residual block to produce transformed data in a transform domain rather than a sample domain. For example, the video encoder 200 may apply a discrete cosine transform (DCT), an integer transform, a wavelet transform, or a conceptually similar transform to the residual video data. In addition, the video encoder 200 may apply a secondary transform after the first transform, such as a mode-dependent non-separable secondary transform (MDNSST), a signal-dependent transform, a Karhunen-Loeve transform (KLT), and the like. After applying the one or more transforms, the video encoder 200 generates transform coefficients.

[0063] Although the above describes an example of performing a transform, in some examples, the transform may be skipped. For example, the video encoder 200 may implement a transform skip mode in which the transform operation is skipped. In the example of skipping the transform, the video encoder 200 may output coefficients corresponding to the residual values ​​instead of transform coefficients. For example, the coefficients corresponding to the residual values ​​may correspond to the quantized residual values. In the following description, the term "coefficient" should be interpreted as including coefficients corresponding to the residual values ​​or transform coefficients generated according to the transform result.

[0064] As described above, the video encoder 200 may perform quantization of transform coefficients, or, in the case of a transform skip, quantization of residual values. Quantization generally refers to a process in which coefficients are quantized to possibly reduce the amount of data used to represent the coefficients, thereby providing further compression. By performing a quantization process, the video encoder 200 may reduce the bit depth associated with some or all of these coefficients. For example, the video encoder 200 may round an n-bit value to an m-bit value during quantization, where n is greater than m. In some examples, to perform quantization, the video encoder 200 may perform a bitwise right shift of the value to be quantized.

[0065] After quantization, the video encoder 200 can scan the coefficients to generate a one-dimensional vector according to the two-dimensional matrix including the quantized coefficients. For the transform coefficients, the scan can be designed to place the coefficients with higher energy (and therefore lower frequency) in front of the vector and the transform coefficients with lower energy (and therefore higher frequency) in the back of the vector. For transform skip coefficients, the same or different scans can be used. In some examples, the video encoder 200 can scan the quantized coefficients using a predefined scan order to generate a serialized vector, and then entropy encode the quantized coefficients of the vector. In other examples, the video encoder 200 can perform adaptive scanning. After scanning the quantized coefficients to form a one-dimensional vector, the video encoder 200 can entropy encode the one-dimensional vector, for example, according to context adaptive binary arithmetic coding (CABAC). The video encoder 200 can also entropy encode the value of the syntax element, which describes the metadata associated with the encoded video data for use by the video decoder 300 when decoding the video data.

[0066] To perform CABAC, the video encoder 200 may assign context within a context model to a symbol to be transmitted. For example, the context may relate to whether the neighboring values ​​of the symbol are zero values. The probability determination may be based on the context assigned to the symbol.

[0067] The video encoder 200 may also generate syntax data (e.g., block-based syntax data, picture-based syntax data, and sequence-based syntax data) for the video decoder 300, for example, in a picture header, a block header, a slice header, or other syntax data (e.g., a sequence parameter set (SPS), a picture parameter set (PPS), or a video parameter set (VPS). The video decoder 300 may similarly decode such syntax data to determine how to decode the corresponding video data.

[0068] In this way, the video encoder 200 can generate a bitstream including the encoded video data, for example, syntax elements for describing the division of a picture into blocks (e.g., CUs), and syntax elements for prediction and / or residual information of these blocks. Finally, the video decoder 300 can receive the bitstream and decode the encoded video data.

[0069] In general, the video decoder 300 performs a process that is reciprocal to the process performed by the video encoder 200 to decode the encoded video data of the bitstream. For example, the video decoder 300 may decode the values ​​of the syntax elements of the bitstream using CABAC in a manner substantially similar to the CABAC encoding process of the video encoder 200 (although reciprocal). The syntax elements may define partitioning information for partitioning a picture into CTUs, and partitioning each CTU according to a corresponding partitioning structure (such as a QTBT structure) to define CUs of the CTUs. These syntax elements may further specify prediction and residual information for a block (e.g., CU) of video data.

[0070] The residual information may be represented by, for example, quantized transform coefficients, quantized transform skip coefficients, or unquantized transform skip coefficients. The video decoder 300 may inverse quantize and inverse transform the quantized coefficients of the block (if decoded in transform mode) to reproduce a residual block for the block. The video decoder 300 uses the signaled prediction mode (intra-frame or inter-frame prediction) and related prediction information (e.g., motion information for inter-frame prediction) to form a prediction block for the block. The video decoder 300 may then combine the prediction block and the residual block (on a sample-by-sample basis) to reproduce the original block. The video decoder 300 may perform other processing, such as performing a deblocking process to reduce visual artifacts along the boundaries of the blocks.

[0071] As described in further detail below, the video encoder 200 may be configured to determine a maximum block size for a transform skip mode, and based on the maximum block size for the transform skip mode, determine a maximum block size for the BDPCM mode. The video encoder 200 may generate a syntax element indicating the maximum block size for the transform skip mode for inclusion in a sequence parameter set syntax structure of the video data. The video decoder 300 may be configured to receive a syntax element indicating the maximum block size for the transform skip mode, and based on the syntax element, determine the maximum block size for the BDPCM mode. By aligning the maximum block size for the BDPCM mode and the residual BDPCM mode with the maximum block size for the transform skip mode in this manner, the techniques of the present disclosure (as implemented by the video encoder 200 and the video decoder 300) may simplify various aspects of the BDPCM mode and the residual BDPCM mode signaling, and may prevent inconsistent bitstreams.

[0072] The present disclosure generally relates to "signaling" certain information (e.g., syntax elements). The term "signaling" may generally refer to transmitting values ​​for syntax elements and / or other data used to decode encoded video data. That is, the video encoder 200 may signal values ​​for syntax elements in a bitstream. Generally, signaling refers to generating values ​​in a bitstream. As described above, the source device 102 may transmit the bitstream to the destination device 116 in substantially real time or in non-real time, such as may occur when storing syntax elements to the storage device 112 for later retrieval by the destination device 116.

[0073] Figure 2A and Figure 2B is a conceptual diagram showing an exemplary quadtree binary tree (QTBT) structure 130 and a corresponding coding tree unit (CTU) 132. Solid lines represent quadtree partitioning, while dashed lines represent binary tree partitioning. In each partition (i.e., non-leaf) node of the binary tree, a flag is signaled to indicate which partition type (i.e., horizontal or vertical) is used, in which case 0 indicates horizontal partitioning and 1 indicates vertical partitioning. For quadtree partitioning, since the quadtree node partitions a block horizontally and vertically into 4 sub-blocks of equal size, there is no need to indicate the partition type. Therefore, the video encoder 200 can encode the syntax elements (e.g., partition information) of the region tree level (i.e., solid line) of the QTBT structure 130 and the syntax elements (e.g., partition information) of the prediction tree level (i.e., dashed line) of the QTBT structure 130, and the video decoder 300 can decode it. The video encoder 200 may encode video data (eg, prediction and transform data) of a CU represented by a terminal leaf node of the QTBT structure 130 , and the video decoder 300 may decode it.

[0074] Generally speaking, Figure 2B The CTU 132 may be associated with parameters that specify the size of the block corresponding to the nodes of the first and second level QTBT structures 130. These parameters may include the CTU size (which represents the size of the CTU 132 in samples), the minimum quadtree size (MinQTSize, which represents the minimum allowed quadtree leaf node size), the maximum binary tree size (MaxBTSize, which represents the maximum allowed binary tree root node size), the maximum binary tree depth (MaxBTDepth, which represents the maximum allowed binary tree depth), and the minimum binary tree size (MinBTSize, which represents the minimum allowed binary tree leaf node size).

[0075] The root node of the QTBT structure corresponding to the CTU may have four child nodes at the first level of the QTBT structure, and each child node may be divided according to the quadtree partitioning. That is, the nodes of the first level are leaf nodes (without child nodes) or have four child nodes. The example of the QTBT structure 130 represents such a node, for example, including a parent node and a child node with a solid line for branching. If the nodes of the first level are not larger than the maximum allowed binary tree root node size (MaxBTSize), the nodes may be further divided by the corresponding binary tree. The binary tree partitioning of a node may be iterated until the node generated by the partitioning reaches the minimum allowed binary tree leaf node size (MinBTSize) or the maximum allowed binary tree depth (MaxBTDepth). The example of the QTBT structure 130 represents such a node as having a dotted line for branching. The binary tree leaf node is called a coding unit (CU), which is used for prediction (e.g., intra-frame or inter-frame prediction) and transformation without any further partitioning. As described above, a CU may also be referred to as a "video block" or "block".

[0076] In an example of a QTBT partitioning structure, the CTU size is set to 128x128 (luminance sample and two corresponding 64x64 chrominance samples), MinQTSize is set to 16x16, MaxBTSize is set to 64x64, MinBTSize (for both width and height) is set to 4, and MaxBTDepth is set to 4. First, quadtree partitioning is applied to the CTU to generate quadtree leaf nodes. The size of the quadtree leaf node can be from 16x16 (i.e., MinQTSize) to 128x128 (i.e., CTU size). If the quadtree leaf node is 128x128, since the size exceeds MaxBTSize (i.e., 64x64 in this example), the quadtree leaf node will not be further split by the binary tree. Otherwise, the quadtree leaf node will be further divided by the binary tree. Therefore, the quadtree leaf node is also the root node of the binary tree, and the depth of the binary tree is 0. When the depth of the binary tree reaches MaxBTDepth (4 in this example), no further splitting is allowed. A binary tree node with a width equal to MinBTSize (4 in this example) means that no further horizontal splitting is allowed. Similarly, a binary tree node with a height equal to MinBTSize means that no further vertical splitting is allowed for the binary tree node. As described above, the leaf nodes of the binary tree are called CUs and are further processed according to prediction and transformation without further division.

[0077] The video encoder 200 and the video decoder 300 can be configured to decode the block in a transform skip mode. The transform skip mode skips the transform process of the residual signal before the quantization step at the encoder end, and skips the inverse transform step after the dequantization step at the decoder end. For each transform block, the transform skip mode may be applied or not. The video decoder 300 can determine whether to apply the transform skip to the current block by predefined rules for both the encoder and the decoder or by parsing information from the bitstream. In the current VVC design, for some modes such as residual BDPCM, transform skip is implicitly used, so no flag is required in the bitstream. For other modes where transform skip can be applied, the video encoder 200 has the freedom to choose from several candidate transforms including the transform skip mode. In this case, when the transform block has a non-zero decoding block flag (CBF), a flag is required to indicate whether the current block should use the transform skip mode. When the CBF is zero, there is no residual information decoded for the corresponding transform block.

[0078] The video encoder 200 and the video decoder 300 can be configured to encode the block in BDPCM mode. The BDPCM mode predicts rows or columns line by line using reconstructed samples. That is, the video encoder 200 and the video decoder 300 can predict the first line of the block (i.e., the first row or first column of the block), for example, based on the reconstructed lines in the adjacent blocks, as in typical intra-frame prediction. However, the video encoder 200 and the video decoder 300 can predict the second line of the block based on the samples reconstructed for the first line, which means that the video encoder 200 and the video decoder 300 predict the second line of the block based on the samples predicted for the first line plus the residual value for the first line. Then, the video encoder 200 and the video decoder 300 can predict the third row of the block based on the samples reconstructed for the second line, and so on. The BDPCM direction notified by the signal indicates whether the vertical prediction direction or the horizontal prediction direction is used. The reference pixels used are unfiltered samples. The prediction error is quantized in the spatial domain. The pixels are reconstructed by adding the dequantized prediction error to the prediction.

[0079] As an additional or alternative to BDPCM, the video encoder 200 and the video decoder 300 can be configured to decode the video block in RDPCM mode, where the RDPCM mode is currently included in VVC Draft 5. The signaling and prediction direction used are the same as BDPCM. In RDPCM, similar to intra-frame prediction, the video encoder 200 and the video decoder 300 first perform intra-frame prediction on the entire block by copying samples of adjacent blocks according to the prediction direction (e.g., horizontal or vertical prediction). The residual is quantized, and the difference between the quantized residual and the predictor (horizontal or vertical) quantization value is decoded. That is, for the first line of the block, the video encoder 200 and the video decoder 300 receive a residual value representing the difference between the sample predicted for the first line and the corresponding original sample. However, for the second line of the block, the video encoder 200 and the video decoder 300 use the residual value for the first line as a predictor for the residual value for the second line. Therefore, the video encoder 200 and the video decoder 300 signal the residual for the samples of the second line as the difference between the residual values ​​for the neighboring samples in the first line and the residual values ​​for the samples in the second line. The video encoder 200 and the video decoder 300 signal the residual for the samples of the third line as the difference between the residual values ​​for the neighboring samples in the second line and the residual values ​​for the samples in the third line, and so on.

[0080] The benefit of this scheme is that the video encoder 200 and the video decoder 300 can perform inverse DPCM on the fly during coefficient parsing by simply adding the predictor when parsing the coefficients, or the video decoder 300 can perform inverse DPCM after parsing. The process of splitting 4xN and Nx4 blocks into 2 parallel processing blocks can be eliminated.

[0081] The 14th JVET meeting approved residual domain BDPCM. In VVC, the maximum block size for BDPCM / RDPCM is 32x32. BDPCM mode always uses transform skip (TS). The maximum size of TS is signaled in the PPS RBSP and is defined as follows:

[0082] log2_transform_skip_max_size_minus2 specifies the maximum block size for transform skipping, which should be in the range of 0 to 3.

[0083] If not present, the value of log2_transform_skip_max_size_minus2 is inferred to be equal to 0.

[0084] Set the variable MaxTsSize equal to 1 << (log2_transform_skip_max_size_minus2+2).

[0085] Since the BDPCM mode and the RDPCM mode always use transform skip, the present disclosure proposes a technique for aligning the design of the BDPCM mode and the RDPCM mode with the design of the transform skip mode.

[0086] According to an exemplary technique of the present disclosure, the design of the prediction mode using transform skip can be aligned with the transform skip (TS) design. For example, in VVC draft 5, the maximum TS block size is signaled in the PPS. According to the technology of the present disclosure, the video encoder 200 and the video decoder 300 can be configured to set the maximum block size for BDPCM (or RDPCM) equal to the maximum TS size, which can be equal to:

[0087] 1<<(log2_transform_skip_max_size_minus2+2)).

[0088] In addition, the existence of the RDPCM mode flag may depend on the maximum allowed TS size. In this example, the maximum TS size may be set to a value signaled to the video decoder 300 from the video encoder 200 at the sequence level, the picture level, the slice level. For example, the value may be signaled in an SPS, a PPS, or a slice header (SH). In some examples, the RDPCM mode flag may specify the direction for the RDPCM mode. In other examples, the RDPCM mode flag may additionally or alternatively specify whether the RDPCM mode is used for a specific block.

[0089] According to another example technique of the present disclosure, the maximum block size of BDPCM (or RDPCM) may be signaled separately from the TS. In one example, the maximum block size for BDPCM or RDPCM may be pre-defined by the video encoder 200 and the video decoder 300, or set to a value signaled from the video encoder 200 to the video decoder 300 at a sequence level, a picture level, or a slice level. For example, the value may be signaled in an SPS, a PPS, or a SH.

[0090] According to another example technique of the present disclosure, the video encoder 200 and the video decoder 300 may signal the maximum block size for BDPCM or RDPCM as the difference between the maximum block size for BDPCM or RDPCM and the maximum block size for TS. The difference may be represented by the syntax element log2_diff_max_BDPCM_max_TS. In this example, the video encoder 200 and the video decoder 300 may be configured to set the maximum block size for BDPCM or RDPCM to be equal to

[0091] 1<<(log2_transform_skip_max_size_minus2+2-log2_diff_max_BDPCM_max_TS). In another example, the video encoder 200 may be configured to signal the value of log2_diff_max_BDPCM_max_TS. In this example, the video encoder 200 and the video decoder 300 may be configured to set the maximum block size for BDPCM or RDPCM equal to

[0092] 1<<(log2_transform_skip_max_size_minus2+2+log2_diff_max_BDPCM_max_TS). In another example, the video encoder 200 may be configured to signal the sign and value of log2_diff_max_BDPCM_max_TS. In this example, the video encoder 200 and the video decoder 300 may be configured to set the maximum size for BDPCM or RDPCM equal to

[0093] 1<<(log2_transform_skip_max_size_minus2+2+sign*log2_diff_max_BDPCM_max_TS). In another example, the video encoder 200 may signal the maximum block size of BDPCM or RDPCM to the video decoder 300 at a sequence level, a picture level, or a slice level. For example, the maximum block size may be signaled in an SPS, a PPS, or a SH.

[0094] According to another example technique of the present disclosure, the techniques of the present disclosure can be extended to any prediction mode using transform skipping.In addition, as an alternative to or in addition to the maximum block size, the techniques of the present disclosure can also be used to signal the minimum block size.

[0095] Figure 3 is a block diagram illustrating an exemplary video encoder 200 that may perform the techniques of this disclosure. Figure 3 For ease of explanation, it should not be considered as limiting the techniques widely illustrated and described in the present disclosure. For ease of explanation, the present disclosure describes the video encoder 200 in the context of video coding standards such as the HEVC video coding standard and the developing H.266 / VVC video coding standard. However, the techniques of the present disclosure are not limited to these video coding standards and are generally applicable to video encoding and decoding.

[0096] exist Figure 3In the example of , the video encoder 200 includes a video data memory 230, a mode selection unit 202, a residual generation unit 204, a transform processing unit 206, a quantization unit 208, an inverse quantization unit 210, an inverse transform processing unit 212, a reconstruction unit 214, a filtering unit 216, a decoded picture buffer (DPB) 218, and an entropy coding unit 220. Any one or all of the video data memory 230, the mode selection unit 202, the residual generation unit 204, the transform processing unit 206, the quantization unit 208, the inverse quantization unit 210, the inverse transform processing unit 212, the reconstruction unit 214, the filtering unit 216, the DPB 218, and the entropy coding unit 220 may be implemented in one or more processors or in processing circuits. In addition, the video encoder 200 may include additional or alternative processors or processing circuits to perform these functions and other functions.

[0097] The video data memory 230 may store video data to be encoded by the components of the video encoder 200. The video encoder 200 may receive video data from, for example, the video source 104 ( Figure 1 ) receives the video data stored in the video data memory 230. DPB218 can act as a reference picture memory, which stores reference video data for use when the video encoder 200 predicts subsequent video data. Video data memory 230 and DPB 218 can be formed by any one of a variety of storage devices (e.g., dynamic random access memory (DRAM) (including synchronous DRAM (SDRAM)), magnetoresistive RAM (MRAM), resistive RAM (RRAM) or other types of storage devices). Video data memory 230 and DPB 218 can be provided by the same storage device or different storage devices. In various examples, video data memory 230 can be on the chip with other components of the video encoder 200, as shown, or off the chip relative to those components.

[0098] In the present disclosure, references to the video data memory 230 should not be interpreted as limited to memory inside the video encoder 200 (unless specifically described as such), nor should they be interpreted as limited to memory outside the video encoder 200 (unless specifically described as such). Rather, references to the video data memory 230 should be understood as a reference memory storing video data, where the video encoder 200 receives the video data (e.g., video data of a current block to be encoded) for encoding. Figure 1 The memory 106 may also provide temporary storage for outputs from the various units of the video encoder 200 .

[0099] Shows Figure 3The various units of the video encoder 200 are provided to help understand the operations performed by the video encoder 200. These units can be implemented as fixed-function circuits, programmable circuits, or a combination thereof. Fixed-function circuits refer to circuits that provide specific functions and are pre-set on the operations that can be performed. Programmable circuits refer to circuits that can be programmed to perform various tasks and provide flexible functions in the operations that can be performed. For example, a programmable circuit can execute software or firmware that causes the programmable circuit to operate in a manner defined by the instructions of the software or firmware. Fixed-function circuits can execute software instructions (e.g., for receiving parameters or outputting parameters), but the type of operation performed by the fixed-function circuit is generally immutable. In some examples, one or more of these units may be different circuit blocks (fixed function or programmable), and in some examples, the one or more units may be integrated circuits.

[0100] The video encoder 200 may include an arithmetic logic unit (ALU), an elementary function unit (EFU), a digital circuit, an analog circuit, and / or a programmable core formed by a programmable circuit. In an example where the operation of the video encoder 200 is performed using software executed by a programmable circuit, the memory 106 ( Figure 1 ) may store object code for software received and executed by the video encoder 200, or another memory (not shown) in the video encoder 200 may store such instructions.

[0101] The video data memory 230 is configured to store received video data. The video encoder 200 may retrieve pictures of video data from the video data memory 230 and provide the video data to the residual generation unit 204 and the mode selection unit 202. The video data in the video data memory 230 may be original video data to be encoded.

[0102] The mode selection unit 202 includes a motion estimation unit 222, a motion compensation unit 224, and an intra prediction unit 226. The mode selection unit 202 may include other functional units to perform video prediction according to other prediction modes. For example, the mode selection unit 202 may include a palette unit, an intra-block copy unit (which may be part of the motion estimation unit 222 and / or the motion compensation unit 224), an affine unit, a linear model (LM) unit, and the like.

[0103] The mode selection unit 202 typically coordinates multiple encoding passes to test combinations of encoding parameters and final rate-distortion values ​​for such combinations. The encoding parameters may include: CTU to CU partitioning, prediction mode for CU, transform type for residual data of CU, quantization parameter for residual data of CU, etc. The mode selection unit 202 may ultimately select a combination of encoding parameters that has a better rate-distortion value than other tested combinations.

[0104] The video encoder 200 may divide the picture retrieved from the video data memory 230 into a series of CTUs and encapsulate one or more CTUs in a segment. The mode selection unit 202 may divide the CTUs of the picture according to a tree structure (e.g., the QTBT structure or quadtree structure of HEVC described above). As described above, the video encoder 200 may form one or more CUs by dividing the CTUs according to the tree structure. Such CUs may also be generally referred to as "video blocks" or "blocks".

[0105] Typically, the mode selection unit 202 also controls its components (e.g., the motion estimation unit 222, the motion compensation unit 224, and the intra prediction unit 226) to generate a prediction block for the current block (e.g., the current CU, or in HEVC, the overlapping portion of the PU and TU). For inter prediction of the current block, the motion estimation unit 222 can perform a motion search to identify one or more closely matching reference blocks in one or more reference pictures (e.g., one or more previously encoded pictures stored in the DPB 218). Specifically, the motion estimation unit 222 can calculate a value indicating how similar the potential reference block is to the current block, for example, based on the sum of absolute differences (SAD), the sum of squared differences (SSD), the mean absolute difference (MAD), the mean squared difference (MSD), etc. The motion estimation unit 222 can generally perform these calculations using the sample-by-sample differences between the current block and the reference block being considered. The motion estimation unit 222 can identify the reference block having the minimum value produced by these calculations, which indicates the reference block that most closely matches the current block.

[0106] The motion estimation unit 222 may form one or more motion vectors (MVs) that define the position of a reference block in a reference picture relative to a current block in a current picture. The motion estimation unit 222 may then provide the motion vectors to the motion compensation unit 224. For example, for unidirectional inter prediction, the motion estimation unit 222 may provide a single motion vector, and for bidirectional inter prediction, the motion estimation unit 222 may provide two motion vectors. The motion compensation unit 224 may then use the motion vectors to generate a prediction block. For example, the motion compensation unit 224 may use the motion vectors to retrieve data for the reference block. As another example, if the motion vector has fractional sampling accuracy, the motion compensation unit 224 may interpolate the values ​​for the prediction block according to one or more interpolation filters. In addition, for bidirectional inter prediction, the motion compensation unit 224 may retrieve data for two reference blocks identified by corresponding motion vectors, for example, by sample-by-sample averaging or weighted averaging, and combine the retrieved data.

[0107] As another example, for intra prediction or intra prediction decoding, the intra prediction unit 226 can generate a prediction block based on samples adjacent to the current block. For example, for directional mode, the intra prediction unit 226 can generally mathematically combine the values ​​of adjacent samples and fill these calculated values ​​along a defined direction on the current block to produce a prediction block. As another example, for DC mode, the intra prediction unit 226 can calculate the average value of adjacent samples to the current block and generate a prediction block to include the resulting average value for each sample of the prediction block. As another example, the intra prediction unit 226 can generate a prediction block, for example, using BDPCM and RDPCM as described above.

[0108] The mode selection unit 202 provides the prediction block to the residual generation unit 204. The residual generation unit 204 receives the original uncoded version of the current block from the video data memory 230 and receives the prediction block from the mode selection unit 202. The residual generation unit 204 calculates the sample-by-sample difference between the current block and the prediction block. The resulting sample-by-sample difference defines a residual block for the current block. In some examples, the residual generation unit 204 may also determine the difference between the sample values ​​in the residual block to generate the residual block using residual differential pulse code modulation (RDPCM). In some examples, the residual generation unit 204 may be formed using one or more subtractor circuits that perform binary subtraction.

[0109] In the example where the mode selection unit 202 divides the CU into PUs, each PU may be associated with a luma prediction unit and a corresponding chroma prediction unit. The video encoder 200 and the video decoder 300 may support PUs of various sizes. As described above, the size of the CU may refer to the size of the luma coding block of the CU, and the size of the PU may refer to the size of the luma prediction unit of the PU. Assuming that the size of a particular CU is 2Nx2N, the video encoder 200 may support PU sizes of 2Nx2N or NxN for intra-frame prediction, and support symmetric PU sizes of 2Nx2N, 2NxN, Nx2N, NxN, etc. for inter-frame prediction. The video encoder 200 and the video decoder 300 may also support asymmetric partitioning of PU sizes of 2NxnU, 2NxnD, nLx2N, and nRx2N for inter-frame prediction.

[0110] In an example where the mode selection unit does not further divide the CU into PUs, each CU may be associated with a luma coding block and a corresponding chroma coding block. As described above, the size of a CU may refer to the size of the luma coding block of the CU. The video encoder 200 and the video decoder 300 may support a CU size of 2Nx2N, 2NxN, or Nx2N.

[0111] For other video coding techniques (e.g., intra-block copy mode coding, affine mode coding, and linear model (LM) mode coding, to name a few), the mode selection unit 202 generates a prediction block for the current block being encoded via various units associated with the coding technique. In some examples (e.g., palette mode coding), the mode selection unit 202 may not generate a prediction block, but instead generate syntax elements that indicate how to reconstruct the block based on the selected palette. In such a mode, the mode selection unit 202 may provide these syntax elements to the entropy coding unit 220 for encoding.

[0112] As described above, the residual generation unit 204 receives video data of a current block and a corresponding prediction block. Then, the residual generation unit 204 generates a residual block for the current block. To generate the residual block, the residual generation unit 204 calculates the sample-by-sample difference between the prediction block and the current block.

[0113] The transform processing unit 206 may apply one or more transforms to the residual block to generate a block of transform coefficients (referred to herein as a "transform coefficient block"). The transform processing unit 206 may apply various transforms to the residual block to form a transform coefficient block. For example, the transform processing unit 206 may apply a discrete cosine transform (DCT), a directional transform, a Karhunen-Loeve transform (KLT), or a conceptually similar transform to the residual block. In some examples, the transform processing unit 206 may perform multiple transforms on the residual block, for example, a primary transform and a secondary transform, such as a rotation transform. In some examples, the transform processing unit 206 does not apply a transform to the residual block. In other words, the residual block is decoded using a transform skip mode. For a video data block decoded in a transform skip mode, the transform processing unit 206 may be treated as a pass-through unit that does not change the residual block. However, the present disclosure refers to the elements in the transform skip block as "coefficients" rather than the residual values ​​after passing through the transform processing unit 206 as "coefficients".

[0114] The quantization unit 208 may quantize the coefficients in the coefficient block to produce a quantized coefficient block. The quantization unit 208 may quantize the coefficients of the coefficient block according to a quantization parameter (QP) value associated with the current block. The video encoder 200 (e.g., via the mode selection unit 202) may adjust the degree of quantization applied to the coefficient block associated with the current block by adjusting the QP value associated with the CU. Quantization may result in a loss of information, and therefore, the accuracy of the quantized coefficients may be lower than the accuracy of the original coefficients.

[0115] The inverse quantization unit 210 and the inverse transform processing unit 212 may apply inverse quantization and inverse transform to the quantized coefficient block, respectively, to reconstruct the residual block according to the coefficient block. For a video data block decoded in a transform skip mode, the inverse transform processing unit 212 may be regarded as a pass-through unit that does not change the dequantized coefficient block. The reconstruction unit 214 may generate a reconstructed block corresponding to the current block (although it may have a certain degree of distortion) based on the reconstructed residual block and the prediction block generated by the mode selection unit 202. For example, the reconstruction unit 214 may add samples of the reconstructed residual block to corresponding samples in the prediction block generated by the mode selection unit 202 to generate a reconstructed block.

[0116] Filtering unit 216 may perform one or more filtering operations on the reconstructed blocks. For example, filtering unit 216 may perform a deblocking operation to reduce blocking artifacts along the edges of the CU. In some examples, the operations of filtering unit 216 may be skipped.

[0117] The video encoder 200 stores the reconstructed blocks in the DPB 218. For example, in an example where the operation of the filtering unit 216 is not performed, the reconstruction unit 214 can store the reconstructed blocks in the DPB 218. In an example where the operation of the filtering unit 216 is performed, the filtering unit 216 can store the filtered reconstructed blocks in the DPB 218. The motion estimation unit 222 and the motion compensation unit 224 can retrieve a reference picture from the DPB 218, which is formed by the reconstructed (and possibly filtered) blocks, to perform inter-frame prediction on subsequently encoded pictures. In addition, the intra-frame prediction unit 226 can use the reconstructed blocks in the DPB 218 of the current picture to perform intra-frame prediction on other blocks in the current picture.

[0118] In general, the entropy coding unit 220 may entropy code syntax elements received from other functional components of the video encoder 200. For example, the entropy coding unit 220 may entropy code the quantized coefficient blocks from the quantization unit 208. As another example, the entropy coding unit 220 may entropy code the prediction syntax elements (e.g., motion information for inter-frame prediction or intra-frame mode information for intra-frame prediction) from the mode selection unit 202. The entropy coding unit 220 may perform one or more entropy coding operations on syntax elements as another example of video data to generate entropy-coded data. For example, the entropy coding unit 220 may perform a context-adaptive variable length coding (CAVLC) operation, a CABAC operation, a variable-to-variable (V2V) length coding operation, a syntax-based context-adaptive binary arithmetic coding (SBAC) operation, a probability interval partitioning entropy (PIPE) coding operation, an exponential Grunb coding operation, or another type of entropy coding operation on the data. In some examples, the entropy coding unit 220 may operate in a bypass mode where the syntax elements are not context-coded.

[0119] The video encoder 200 may output a bitstream including entropy-encoded syntax elements required for reconstructing blocks of a slice or picture. Specifically, the entropy encoding unit 220 may output a bitstream.

[0120] The operations described above are described with respect to blocks. Such descriptions should be understood as operations for luma coding blocks and / or chroma coding blocks. As described above, in some examples, the luma coding blocks and chroma coding blocks are the luma and chroma components of a CU. In some examples, the luma coding blocks and chroma coding blocks are the luma and chroma components of a PU.

[0121] In some examples, operations performed for luma coding blocks do not need to be repeated for chroma coding blocks. As one example, operations for identifying a motion vector (MV) and reference picture for a luma coding block do not need to be repeated to identify an MV and reference picture for a chroma block. Instead, the MV for the luma coding block may be scaled to determine the MV for the chroma block, and the reference picture may be the same. As another example, the intra prediction process may be the same for luma coding blocks and chroma coding blocks.

[0122] The video encoder 200 represents an example of a device configured to encode video data, the device including a memory configured to store the video data, and one or more processing units implemented in a circuit and configured to perform the following operations: determine a maximum block size for transform skipping, and determine a maximum size for BDPCM or RDPCM mode based on the maximum block size for transform skipping. In other examples, the video encoder 200 can determine the maximum size for BDPCM or RDPCM mode based on the second syntax element alone, or use the maximum size for BDPCM or RDPCM mode defined in the CODEC being executed by the video encoder 200.

[0123] Figure 4 is a block diagram illustrating an exemplary video decoder 300 that can perform the techniques of this disclosure. Figure 4 For the purpose of explanation, it should not be considered as limiting the techniques widely illustrated and described in this disclosure. For the purpose of explanation, this disclosure describes a video decoder 300 according to the techniques of JEM, VVC and HEVC. However, the techniques of this disclosure can be performed by a video encoding device configured to implement other video encoding standards.

[0124] exist Figure 4 In the example of , the video decoder 300 includes a coded picture buffer (CPB) memory 320, an entropy decoding unit 302, a prediction processing unit 304, an inverse quantization unit 306, an inverse transform processing unit 308, a reconstruction unit 310, a filtering unit 312, and a decoded picture buffer (DPB) 314. Any one or all of the CPB memory 320, the entropy decoding unit 302, the prediction processing unit 304, the inverse quantization unit 306, the inverse transform processing unit 308, the reconstruction unit 310, the filtering unit 312, and the DPB 314 may be implemented in one or more processors or in processing circuits. In addition, the video decoder 300 may include additional or alternative processors or processing circuits to perform these functions and other functions.

[0125] The prediction processing unit 304 includes a motion compensation unit 316 and an intra prediction unit 318. The prediction processing unit 304 may include other units for performing predictions according to other prediction modes. For example, the prediction processing unit 304 may include a palette unit, an intra-block copy unit (which may form part of the motion compensation unit 316), an affine unit, a linear model (LM) unit, etc. In other examples, the video decoder 300 may include more, fewer, or different functional components.

[0126] CPB memory 320 may store video data (e.g., an encoded video bitstream) to be decoded by components of video decoder 300. For example, the video bitstream may be obtained from computer readable medium 110 ( Figure 1 ) to obtain video data stored in the CPB memory 320. The CPB memory 320 may include a CPB that stores encoded video data (e.g., syntax elements) from an encoded video bitstream. Moreover, the CPB memory 320 may store video data other than syntax elements of encoded pictures, for example, temporary data representing outputs from various units of the video decoder 300. The DPB 314 typically stores decoded pictures, and the video decoder 300 may output and / or use the decoded pictures as reference video data when decoding subsequent data or pictures of the encoded video bitstream. The CPB memory 320 and the DPB 314 may be formed by any of a variety of storage devices such as DRAM (including SDRAM), MRAM, RRAM, or other types of storage devices. The CPB memory 320 and the DPB 314 may be provided by the same storage device or different storage devices. In various examples, the CPB memory 320 may be on-chip with other components of the video decoder 300, or off-chip relative to those components.

[0127] Additionally or alternatively, in some examples, video decoder 300 may retrieve the video from memory 120 ( Figure 1 ) When some or all of the functions of video decoder 300 are implemented using software executed by processing circuits of video decoder 300, memory 120 may additionally or alternatively store instructions to be executed by video decoder 300.

[0128] Shows Figure 4 The various units are described to help understand the operations performed by the video decoder 300. These units may be implemented as fixed function circuits, programmable circuits, or a combination thereof. Figure 3 , fixed-function circuits refer to circuits that provide specific functions and are pre-set in the operations that can be performed. Programmable circuits refer to circuits that can be programmed to perform various tasks and provide flexible functions in the operations that can be performed. For example, a programmable circuit can execute software or firmware that causes the programmable circuit to operate in a manner defined by the instructions of the software or firmware. Fixed-function circuits can execute software instructions (e.g., for receiving parameters or outputting parameters), but the types of operations performed by fixed-function circuits are generally immutable. In some examples, one or more of these units may be different circuit blocks (fixed-function or programmable), and in some examples, the one or more units may be integrated circuits.

[0129] The video decoder 300 may include an ALU, an EFU, a digital circuit, an analog circuit, and / or a programmable core formed by a programmable circuit. In an example where the operation of the video decoder 300 is performed by software executed on a programmable circuit, an on-chip or off-chip memory may store instructions (e.g., object code) of the software received and executed by the video decoder 300.

[0130] The entropy decoding unit 302 may receive the encoded video data from the CPB and entropy decode the encoded video data to reproduce the syntax elements. The prediction processing unit 304, the inverse quantization unit 306, the inverse transform processing unit 308, the reconstruction unit 310, and the filtering unit 312 may generate decoded video data based on the syntax elements extracted from the bitstream.

[0131] Typically, the video decoder 300 reconstructs a picture on a block-by-block basis. The video decoder 300 may perform a reconstruction operation on each block individually (wherein a block currently being reconstructed (ie, decoded) may be referred to as a "current block").

[0132] The entropy decoding unit 302 may entropy decode syntax elements defining quantized coefficients of the quantized coefficient block, as well as transform information such as a quantization parameter (QP) and / or a transform mode indication. The inverse quantization unit 306 may use the QP associated with the quantized coefficient block to determine a degree of quantization, and likewise, determine a degree of inverse quantization for the inverse quantization unit 306 to apply. For example, the inverse quantization unit 306 may perform a bitwise left shift operation to inverse quantize the quantized coefficients. The inverse quantization unit 306 may thereby form a coefficient block including the coefficients.

[0133] After the inverse quantization unit 306 forms the coefficient block, the inverse transform processing unit 308 may apply one or more inverse transforms to the coefficient block to generate a residual block associated with the current block. For example, the inverse transform processing unit 308 may apply an inverse DCT, an inverse integer transform, an inverse Karhunen-Loeve transform (KLT), an inverse rotational transform, an inverse directional transform, or another inverse transform to the coefficient block. For blocks decoded in transform skip mode, the inverse transform processing unit 308 may be treated as a pass-through unit that does not change the dequantized coefficient block.

[0134] In addition, prediction processing unit 304 generates a prediction block based on the prediction information syntax element entropy decoded by entropy decoding unit 302. For example, if the prediction information syntax element indicates that the current block is inter-predicted, motion compensation unit 316 can generate a prediction block. In this case, the prediction information syntax element can indicate a reference picture in DPB 314 from which the reference block is retrieved, and a motion vector that identifies the position of the reference block in the reference picture relative to the current block in the current picture. Motion compensation unit 316 can generally generate a prediction block in the same manner as described for motion compensation unit 224 ( Figure 3 ) to perform inter-frame prediction processing in a manner substantially similar to that described herein.

[0135] As another example, if the prediction information syntax element indicates that the current block is intra-predicted, the intra-prediction unit 318 can generate a prediction block according to the intra-prediction mode indicated by the prediction information syntax element. The intra-prediction unit 318 can generate the prediction block using, for example, BDPCM and RDPCM as described above. Again, the intra-prediction unit 318 can generally use the same method as described for the intra-prediction unit 226 ( Figure 3 The intra prediction process is performed in a manner substantially similar to that described in the foregoing description. The intra prediction unit 318 may retrieve data of neighboring samples of the current block from the DPB 314.

[0136] The reconstruction unit 310 may reconstruct the current block using the prediction block and the residual block. For example, the reconstruction unit 310 may add samples of the residual block to corresponding samples of the prediction block to reconstruct the current block.

[0137] The filtering unit 312 may perform one or more filtering operations on the reconstructed block. For example, the filtering unit 312 may perform a deblocking operation to reduce blocking artifacts along the edges of the reconstructed block. The operations of the filtering unit 312 may not necessarily be performed in all examples.

[0138] The video decoder 300 may store the reconstructed blocks in the DPB 314. As described above, the DPB 314 may provide reference information to the prediction processing unit 304, such as samples of the current picture for intra-frame prediction and previously decoded pictures for subsequent motion compensation. In addition, the video decoder 300 may output decoded pictures from the DPB 314 for subsequent use in, for example, Figure 1 The display device is presented on a display device such as display device 118.

[0139] In this manner, the video decoder 300 represents an example of a video decoding device that includes a memory configured to store video data and includes one or more processing units implemented in a circuit and configured to perform the following operations: receiving a syntax element indicating a maximum block size for transform skipping, and determining the maximum size for BDPCM or RDPCM mode based on the syntax element. In other examples, the video decoder 300 may receive a second syntax element separate from the first syntax element, and determine the maximum size for BDPCM or RDPCM mode based on the second syntax element. In other examples, the maximum size for BDPCM or RDPCM mode may be defined in the CODEC being executed by the video decoder 300.

[0140] In this way, the video decoder 300 represents an example of a video decoding device that includes a memory configured to store video data, and includes one or more processing units implemented in a circuit and configured to perform the following operations: receiving a syntax element indicating a maximum block size for transform skipping, and processing the syntax element according to any of the techniques described in the present disclosure. For example, the video decoder 300 can determine the maximum size for BDPCM mode based on the syntax element. In order to determine the maximum size for BDPCM mode based on the syntax element, the video decoder 300 can, for example, determine the maximum size for BDPCM mode to be equal to the maximum block size for transform skipping. As part of determining the maximum size for BDPCM mode based on the syntax element, the video decoder 300 can receive a difference value and determine the maximum size for BDPCM mode based on the maximum block size for transform skipping and the difference value. For example, the video decoder 300 can receive the syntax element as part of an SPS, PPS, or slice header.

[0141] The video decoder 300 may additionally or alternatively be configured to determine the maximum size for the RDPCM mode based on the syntax elements. To determine the maximum size for the RDPCM mode based on the syntax elements, the video decoder 300 may, for example, determine the maximum size for the RDPCM mode to be equal to the maximum block size for transform skip. As part of determining the maximum size for the RDPCM mode based on the syntax elements, the video decoder 300 may, for example, receive a difference value and determine the maximum size for the RDPCM mode based on the maximum block size for transform skip and the difference value.

[0142] In some instances, the video decoder 300 may be configured to receive a second syntax element separate from the first syntax element, and determine the maximum size for the BDPCM mode based on the second syntax element. In some instances, the video decoder 300 may be configured to receive a second syntax element separate from the first syntax element, and determine the maximum size for the RDPCM mode based on the second syntax element. The video decoder 300 may also be configured to set the maximum size for the BDPCM mode to a value defined in the CODEC and / or to set the maximum size for the RDPCM mode to a value defined in the CODEC.

[0143] The video decoder 300 may also be configured to determine the maximum block size for transform skipping, and based on the maximum block size for transform skipping, determine whether there is an RDPCM mode flag in the bitstream including the encoded representation of the video data. The video decoder 300 may also be configured to determine the maximum block size for transform skipping, and based on the maximum block size for transform skipping, determine whether there is a BDPCM mode flag in the bitstream including the encoded representation of the video data. In some examples, the BDPCM mode flag may specify the direction for the BDPCM mode. In other examples, the BDPCM mode flag may additionally or alternatively specify whether the BDPCM mode is used for a specific block.

[0144] Figure 5 2 is a flowchart illustrating an example method for encoding a current block. The current block may include a current CU. Although relative to the video encoder 200 ( Figure 1 and Figure 3 ), but it should be understood that other devices may be configured to perform the same Figure 5 Similar approach.

[0145] In this example, the video encoder 200 initially predicts the current block (350). For example, the video encoder 200 may use BDPCM or RDPCM as described above to form a prediction block for the current block. The video encoder 200 may then calculate a residual block for the current block (352). In order to calculate the residual block, the video encoder 200 may calculate the difference between the original uncoded block and the prediction block of the current block. Subsequently, the video encoder 200 may transform and / or quantize the coefficients of the residual block (354). Next, the video encoder 200 may scan the quantized coefficients of the residual block (356). During or after the scan, the video encoder 200 may entropy encode the coefficients (358). For example, the video encoder 200 may encode the coefficients using CAVLC or CABAC. The video encoder 200 may then output the entropy encoded data of the block (360).

[0146] Figure 6 3 is a flowchart illustrating an example method for decoding a current block of video data. The current block may include a current CU. Although with respect to the video decoder 300 ( Figure 1 and Figure 4 ), but it should be understood that other devices may be configured to perform the same Figure 6 Similar approach.

[0147] The video decoder 300 may receive entropy coded data of a current block, for example, entropy coded prediction information and entropy coded data of coefficients of a residual block corresponding to the current block (370). The video decoder 300 may entropy decode the entropy coded data to determine the prediction information of the current block and reproduce the coefficients of the residual block (372). The video decoder 300 may predict the current block (374), for example, using an intra-frame or inter-frame prediction mode as indicated by the prediction information for the current block, to calculate a prediction block for the current block. For example, the video decoder 300 may predict the block using BDPCM or RDPCM as described above. The video decoder 300 may then inverse scan the reproduced coefficients (376) to create a block of quantized coefficients. The video decoder 300 may then inverse quantize and / or inverse transform the coefficients to generate a residual block (378). The video decoder 300 may ultimately decode the current block (380) by combining the prediction block and the residual block.

[0148] Figure 7 2 is a flowchart illustrating an example method for encoding a current block. The current block may include a current CU. Although relative to the video encoder 200 ( Figure 1 and Figure 3 ), but it should be understood that other devices may be configured to perform the same Figure 7 Similar approach.

[0149] The video encoder 200 determines the maximum block size for the transform skip mode (402). The video encoder 200 determines the maximum block size for the BDPCM mode based on the maximum block size for the transform skip mode (404). In order to determine the maximum block size for the BDPCM mode, the video encoder 200 can, for example, determine the maximum block size for the BDPCM mode to be equal to the maximum block size for the transform skip mode. For example, the BDPCM mode can be an RDPCM mode or other types of BDPCM modes. The value of the maximum block size for the BDPCM mode can be, for example, one or both of the following: the maximum block width of a block decoded in the BDPCM mode, or the maximum block height of a block decoded in the BDPCM mode.

[0150] The video encoder 200 encodes the block of video data based on the determined maximum block size for the BDPCM mode (406). As part of encoding the block of video data, the video encoder 200 may generate a syntax element (e.g., log2_transform_skip_max_size_minus2) for inclusion in a sequence parameter set syntax structure for the video data, wherein the syntax element indicates the maximum block size for the transform skip mode. The syntax element may, for example, have a value equal to X, where X is an integer value in the range of 0 to 3 (inclusive). The maximum block size for the BDPCM mode may be equal to 1<<(X+2), where << represents a left shift operation.

[0151] As part of encoding a block of video data, the video encoder 200 may also determine whether to include a BDPCM mode flag in a bitstream of the encoded video data for the block based on the maximum block size for transforming the skip mode. For example, the video encoder 200 may include a BDPCM mode flag in a bitstream of the encoded video data in response to the size of the block of video data being less than or equal to the maximum block size for the BDPCM mode. The video encoder 200 may also output a bitstream of the encoded video data for storage or transmission.

[0152] Figure 8 3 is a flowchart illustrating an example method for decoding a current block of video data. The current block may include a current CU. Although with respect to the video decoder 300 ( Figure 1 and Figure 4 ), but it should be understood that other devices may be configured to perform the same Figure 8 Similar approach.

[0153] The video decoder 300 receives a syntax element indicating a maximum block size for a transform skip mode (eg, log2_transform_skip_max_size_minus2) (410). For example, the syntax element may be part of an SPS.

[0154] The video decoder 300 determines the maximum block size for the BDPCM mode based on the syntax element (412). For example, the BDPCM mode may be an RDPCM mode or another type of BDPCM mode. The value of the maximum block size for the BDPCM mode may be, for example, one or both of the following: the maximum block width of a block decoded in the BDPCM mode, or the maximum block height of a block decoded in the BDPCM mode.

[0155] To determine the maximum block size for the BDPCM mode based on the syntax element, the video decoder 300 may, for example, determine the maximum block size for the BDPCM mode to be equal to the maximum block size for the transform skip mode. To determine the maximum block size for the BDPCM mode based on the syntax element, the video decoder 300 may, for example, determine the maximum block size for the BDPCM mode based on the syntax element by setting the value of the maximum block size for the BDPCM to be equal to 1<<(X+2), where << represents a left shift operation and X represents an integer value in the range of 0 to 3 (including the end value).

[0156] The video decoder 300 decodes the video data block based on the determined maximum block size for the BDPCM mode (414). As part of decoding the video data block, the video decoder 300 can determine, for example, based on syntax elements, the maximum block size for the transform skip mode, and determine whether a BDPCM mode flag is present in a bitstream including an encoded representation of the video data based on the maximum block size for the transform skip mode. For example, in response to the size of the video data block being less than or equal to the maximum block size for the BDPCM mode, the video decoder 300 can determine that a BDPCM mode flag is present for the video data block.

[0157] It should be appreciated that, according to examples, certain actions or events of any of the techniques described herein may be performed in a different order, may be added, combined, or omitted entirely (e.g., not all described actions or events are required to implement the technique). In addition, in some examples, actions or events may be performed concurrently rather than sequentially, such as through multithreading, interrupt processing, or multiple processors.

[0158] In one or more examples, the functions described may be implemented using hardware, software, firmware, or any combination thereof. When implemented using software, the functions may be stored on a computer-readable medium or transmitted as one or more instructions or codes on a computer-readable medium and executed by a hardware-based processing unit. A computer-readable medium may include a computer-readable storage medium, which corresponds to a tangible medium such as a data storage medium or a communication medium, wherein the communication medium includes any medium that facilitates, for example, transmitting a computer program from one place to another according to a communication protocol. In this manner, a computer-readable medium may generally correspond to: (1) a non-temporary tangible computer-readable storage medium; or (2) a communication medium such as a signal or carrier waveform. A data storage medium may be any available medium that one or more computers or one or more processors can access to obtain instructions, codes, and / or data structures for implementing the techniques described in the present disclosure. A computer program product may include a computer-readable medium.

[0159] By way of example, but not limitation, such computer-readable storage media may include RAM, ROM, EEPROM, CD-ROM or other optical disk storage, disk storage or other magnetic storage devices, flash memory or any other medium capable of storing desired program code in the form of instructions or data structures and capable of being accessed by a computer. In addition, any connection may be appropriately referred to as a computer-readable medium. For example, if the instruction is transmitted from a website, server or other remote source using a coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL) or wireless technologies such as infrared, wireless and microwave, then the coaxial cable, fiber optic cable, twisted pair, DSL or wireless technologies such as infrared, wireless and microwave are included in the definition of the medium. However, it should be understood that computer-readable storage media and data storage media do not include connections, carrier waveforms, signals or other temporary media, but are directed to non-temporary tangible storage media. As used herein, disks and optical disks include compact disks CD, laser optical disks, optical disks, digital versatile disks (DVD), floppy disks and blue-ray disks, wherein disks usually reproduce data magnetically, while optical disks reproduce data optically using lasers. The above combinations should also be included within the protection scope of computer-readable media.

[0160] Instructions may be performed by one or more processors such as one or more digital signal processors (DSPs), general-purpose microprocessors, application specific integrated circuits (ASICs), field programmable gate arrays (FPGAs), or other equivalent integrated or discrete logic circuits. Therefore, as used herein, the terms "processor" and "processing circuit" may refer to any of the aforementioned structures or any other structures suitable for implementing the techniques described herein. In addition, in some aspects, the functions described herein may be provided in dedicated hardware and / or software modules configured to implement encoding and decoding, or incorporated into a combined codec. In addition, these techniques may be fully implemented in one or more circuits or logic elements.

[0161] The techniques of the present disclosure may be implemented using a variety of devices or apparatuses, including the use of a wireless handheld device, an integrated circuit (IC), or a set of ICs (e.g., a chipset). Various components, modules, or units are described in the present disclosure to emphasize the functional aspects of the devices configured to perform the disclosed techniques, but do not necessarily need to be implemented by different hardware units. Instead, as described above, the various units may be combined in a codec hardware unit, or provided by a collection of cooperating hardware units (which include one or more processors as described above) in combination with appropriate software and / or firmware.

Claims

1. A method for decoding video data, the method comprising: Receiving a syntax element in a bitstream as part of a sequence parameter set syntax structure for a picture, wherein the syntax element indicates a maximum block size for both a transform skip mode and a block-based delta pulse code modulation (BDPCM) mode; Based on the syntax element, determining a maximum block size for the BDPCM mode, wherein the maximum block size is limited to a range of [4, 32]; determining, based on the syntax element, a maximum block size for the transform skip mode; based on the determined maximum block size for the transform skip mode, in response to a size of a first block being less than or equal to the maximum block size for the BDPCM mode, determining that a BDPCM mode flag is present in the bitstream for the first block, and decoding the BDPCM mode flag from the bitstream; Based on the BDPCM mode flag, determining that the first block of the picture is decoded using the BDPCM mode; decoding the first block based on the determined maximum block size for the BDPCM mode; determining that a second block of the picture is decoded using the transform skip mode; decoding the second block based on the determined maximum block size for the transform skip mode; and A decoded version of the picture is output.

2. The method according to claim 1, wherein: Determining a maximum block size for the BDPCM mode based on the syntax element includes determining the maximum block size for the BDPCM mode to be equal to a maximum block size for the transform skip mode.

3. The method according to claim 1, wherein: The syntax element has a value equal to X, where X is an integer value in the range [0,3], and where the maximum block size for the BDPCM mode is equal to 1<<(X+2), where << represents a left shift operation.

4. The method according to claim 3, wherein: The maximum block size for the BDPCM mode includes a maximum block width for the BDPCM mode.

5. The method according to claim 3, wherein: The maximum block size for the BDPCM mode includes a maximum block height for the BDPCM mode.

6. The method according to claim 1, wherein: The BDPCM mode includes a residual domain BDPCM (RDPCM) mode.

7. A method for encoding video data, the method comprising: For a first block of a picture, determining a maximum block size for a transform skip mode, wherein the maximum block size is limited to a range of [4, 32]; For a second block of the picture, determining a maximum block size for a block-based delta pulse code modulation (BDPCM) mode based on the maximum block size for the transform skip mode; In response to a size of the second block being less than or equal to a maximum block size for the BDPCM mode based on a maximum block size for the transform skip mode, including a BDPCM mode flag in a bitstream of the encoded video data; and Based on the determined maximum block size for the BDPCM mode, encoding the second block comprises generating a syntax element for inclusion in a sequence parameter set syntax structure applied to the picture, the syntax element indicating the maximum block size for both the transform skip mode and the BDPCM mode.

8. The method according to claim 7, wherein: Determining a maximum block size for the BDPCM mode includes determining the maximum block size for the BDPCM mode to be equal to a maximum block size for the transform skip mode.

9. The method according to claim 7, wherein: The syntax element has a value equal to X, where X is an integer value in the range [0,3], and where the maximum block size for the BDPCM mode is equal to 1<<(X+2), where << represents a left shift operation.

10. The method according to claim 9, wherein: The maximum block size for the BDPCM mode includes a maximum block width for the BDPCM mode.

11. The method according to claim 9, wherein: The maximum block size for the BDPCM mode includes a maximum block height for the BDPCM mode.

12. The method according to claim 7, wherein: The BDPCM mode includes a residual domain BDPCM (RDPCM) mode.

13. A device for decoding video data, the device comprising: a memory configured to store video data; as well as One or more processors configured to: Receiving a syntax element in a bitstream as part of a sequence parameter set syntax structure for a picture, wherein the syntax element indicates a maximum block size for both a transform skip mode and a block-based delta pulse code modulation (BDPCM) mode; Based on the syntax element, determining a maximum block size for the BDPCM mode, wherein the maximum block size is limited to a range of [4, 32]; determining, based on the syntax element, a maximum block size for the transform skip mode; based on the determined maximum block size for the transform skip mode, in response to a size of a first block being less than or equal to the maximum block size for the BDPCM mode, determining that a BDPCM mode flag is present in the bitstream for the first block, and decoding the BDPCM mode flag from the bitstream; Based on the BDPCM mode flag, determining that the first block of the picture is decoded using the BDPCM mode; decoding the first block based on the determined maximum block size for the BDPCM mode; determining that a second block of the picture is decoded using the transform skip mode; decoding the second block based on the determined maximum block size for the transform skip mode; and A decoded version of the picture is output.

14. The device according to claim 13, wherein: To determine the maximum block size for the BDPCM mode based on the syntax element, the one or more processors are further configured to determine the maximum block size for the BDPCM mode to be equal to a maximum block size for the transform skip mode.

15. The apparatus according to claim 13, wherein: The syntax element has a value equal to X, where X is an integer value in the range [0,3], and where the maximum block size for the BDPCM mode is equal to 1<<(X+2), where << represents a left shift operation.

16. The device according to claim 15, wherein: The maximum block size for the BDPCM mode includes a maximum block width for the BDPCM mode.

17. The apparatus according to claim 15, wherein: The maximum block size for the BDPCM mode includes a maximum block height for the BDPCM mode.

18. The apparatus of claim 13, wherein: The BDPCM mode includes a residual domain BDPCM (RDPCM) mode.

19. The apparatus of claim 13, wherein: The apparatus comprises a wireless communication device, the apparatus further comprising at least one of: a receiver configured to receive an encoded representation of the video data, or a display configured to display a decoded version of the picture.

20. The apparatus of claim 19, wherein: The wireless communication device comprises a telephone handset and wherein the receiver is configured to demodulate a signal comprising the encoded representation of the video data in accordance with a wireless communication standard.

21. A device for encoding video data, the device comprising: a memory configured to store video data; as well as One or more processors configured to: For a first block of a picture, determining a maximum block size for a transform skip mode, wherein the maximum block size is limited to a range of [4, 32]; For a second block of the picture, determining a maximum block size for a block-based delta pulse code modulation (BDPCM) mode based on the maximum block size for the transform skip mode; In response to a size of the second block being less than or equal to a maximum block size for the BDPCM mode based on a maximum block size for the transform skip mode, including a BDPCM mode flag in a bitstream of the encoded video data; and Based on the determined maximum block size for the BDPCM mode, encoding the second block comprises generating a syntax element for inclusion in a sequence parameter set syntax structure applied to the picture, the syntax element indicating the maximum block size for both the transform skip mode and the BDPCM mode.

22. The apparatus according to claim 21, wherein To determine the maximum block size for the BDPCM mode, the one or more processors are further configured to determine the maximum block size for the BDPCM mode to be equal to a maximum block size for the transform skip mode.

23. The apparatus of claim 21, wherein: The syntax element has a value equal to X, where X is an integer value in the range [0,3], and where the maximum block size for the BDPCM mode is equal to 1<<(X+2), where << represents a left shift operation.

24. The apparatus of claim 23, wherein: The maximum block size for the BDPCM mode includes a maximum block width for the BDPCM mode.

25. The apparatus of claim 23, wherein: The maximum block size for the BDPCM mode includes a maximum block height for the BDPCM mode.

26. The apparatus of claim 21, wherein: The BDPCM mode includes a residual domain BDPCM (RDPCM) mode.

27. The apparatus of claim 21, further comprising: A camera is configured to capture the video data.

28. A non-transitory computer-readable storage medium storing instructions, which, when executed by one or more processors, cause the one or more processors to perform the following operations: The syntax element is received in a bitstream as part of a sequence parameter set syntax structure for a picture, wherein The syntax element indicates a maximum block size for both transform skip mode and block-based delta pulse code modulation (BDPCM) mode; Based on the syntax element, determining a maximum block size for the BDPCM mode, wherein the maximum block size is limited to a range of [4, 32]; determining, based on the syntax element, a maximum block size for the transform skip mode; based on the determined maximum block size for the transform skip mode, in response to a size of a first block being less than or equal to the maximum block size for the BDPCM mode, determining that a BDPCM mode flag is present in the bitstream for the first block, and decoding the BDPCM mode flag from the bitstream; Based on the BDPCM mode flag, determining that the first block of the picture is decoded using the BDPCM mode; decoding the first block based on the determined maximum block size for the BDPCM mode; determining that a second block of the picture is decoded using the transform skip mode; decoding the second block based on the determined maximum block size for the transform skip mode; and A decoded version of the picture is output.

29. An apparatus for decoding video data, the apparatus comprising: means for receiving in a bitstream a syntax element as part of a sequence parameter set syntax structure for a picture, wherein the syntax element indicates a maximum block size for both a transform skip mode and a block-based delta pulse code modulation (BDPCM) mode; means for determining a maximum block size for the BDPCM mode based on the syntax element, wherein the maximum block size is limited to a range of [4, 32]; means for determining a maximum block size for the transform skip mode based on the syntax element; means for determining, based on the determined maximum block size for the transform skip mode, that a BDPCM mode flag is present in the bitstream for the first block in response to the size of the first block being less than or equal to the maximum block size for the BDPCM mode, and means for decoding the BDPCM mode flag from the bitstream; A unit for determining, based on the BDPCM mode flag, that the first block of the picture is decoded using the BDPCM mode; means for decoding the first block based on the determined maximum block size for the BDPCM mode; means for determining that a second block of the picture is to be coded using the transform skip mode; means for decoding the second block based on the determined maximum block size for the transform skip mode; and Means for outputting a decoded version of the picture.

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