Electronic device and method for monitoring output signal of driver

Abstract

An electronic device and a method for monitoring a driver's output signal are provided. The electronic device includes: a driver connected to a pin, receiving an input signal, and outputting an output signal to the pin in response to the input signal; a core circuit that transmits the input signal to the driver; and a monitoring circuit that receives the input signal and an output signal and detects a stagnation voltage state of the output signal based on the input and output signals. The monitoring circuit includes: a first detection circuit that detects a stagnation voltage state when the input and output signals are logically incorrect; a second detection circuit that detects a stagnation voltage state when the input and output signals are logically correct and the output signal is at a low level; and a third detection circuit that detects a stagnation voltage state when the input and output signals are logically correct and the output signal is at a high level.

Description

[0001] This application claims priority from Korean Patent Application No. 10-2020-0093284 filed on July 27, 2020, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0002] Embodiments of the inventive concept described herein relate to an electronic device, and more particularly, to an electronic device that detects a stagnation voltage state of an output driver, and to a method of monitoring the stagnation voltage state. Background Art

[0003] An electronic device, such as a semiconductor chip (or package), is configured to communicate with an external device. The electronic device may include signal lines to receive signals from the external device and transmit signals to the external device. The voltage level of one or more of these signal lines may become stuck or frozen due to errors in manufacturing the electronic device or due to a gradual defect in the electronic device. As used herein, a "stuck voltage state" refers to a situation in which the voltage level of a given signal line is improperly fixed due to coupling with a power supply voltage VDD or a ground voltage VSS. Summary of the Invention

[0004] According to one exemplary embodiment, an electronic device includes: a driver connected to a pin, receiving an input signal, and outputting an output signal to the pin in response to the input signal; a core circuit transmitting the input signal to the driver; and a monitoring circuit receiving the input signal and an output signal and detecting a stagnant voltage state of the output signal based on the input and output signals. The monitoring circuit includes: a first detection circuit for detecting the stagnant voltage state when the input and output signals are logically incorrect; a second detection circuit for detecting the stagnant voltage state when the input and output signals are logically correct and the output signal is at a low level; and a third detection circuit for detecting the stagnant voltage state when the input and output signals are logically correct and the output signal is at a high level.

[0005] According to one exemplary embodiment, an electronic device includes a power management integrated circuit (PMIC) that generates a second voltage from a first voltage received externally and outputs the second voltage; and a processor that receives the second voltage from the PMIC and accesses the PMIC via a general-purpose input / output (GIO). The PMIC includes a driver associated with the GIO that outputs an output signal in response to an input signal; and a monitoring circuit that receives the input signal and the output signal and detects a stagnant voltage state of the output signal based on the input signal and the output signal.

[0006] According to an exemplary embodiment, a method of monitoring an output signal of a driver includes: comparing an input signal and an output signal of the driver, and detecting a stagnant voltage state in response to the input signal and the output signal being logically incorrect; and adjusting a voltage of an output node when the input signal and the output signal are logically correct, and detecting the stagnant voltage state in response to the voltage of the output node not changing. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] The above and other objects and features of the inventive concept will become apparent from the following detailed description with reference to the accompanying drawings.

[0008] Figure 1 An example of a system including an electronic device according to an embodiment of the inventive concept is shown.

[0009] Figure 2 is a flowchart for reference in describing an example of an operating method of an electronic device according to an embodiment of the inventive concept.

[0010] Figure 3 is a flowchart for reference when describing an example of performing a logic check.

[0011] Figure 4 A system including components for performing logic checking according to an embodiment of the inventive concept is shown.

[0012] Figure 5 is a flowchart for reference when describing an example of performing a change check of an output signal.

[0013] Figure 6 is a flowchart for reference when describing an example of performing a logic low check of an output signal.

[0014] Figure 7 A system including components for performing a logic low check of an output signal according to an embodiment of the inventive concept is illustrated.

[0015] Figure 8 An example of a reference voltage generator is shown.

[0016] Figure 9 It shows Figure 7 An example timing diagram of the signals of the monitoring circuit.

[0017] Figure 10 An example of a range of the first reference voltage is shown.

[0018] Figure 11 is a flowchart for reference when describing an example of performing a logic high check of an output signal.

[0019] Figure 12A system including components for performing a logic high check of an output signal according to an embodiment of the inventive concept is illustrated.

[0020] Figure 13 It shows Figure 12 An example timing diagram of the signals of the monitoring circuit.

[0021] Figure 14 An example of a range of the second reference voltage is shown.

[0022] Figure 15 A system including components for performing logic checking and logic low and logic high checking of an output signal according to an embodiment of the inventive concept is shown.

[0023] Figure 16 An example of a reference voltage generator is shown.

[0024] Figure 17 An example is shown in which a plurality of comparators are used for change detection of an output signal.

[0025] Figure 18 A system including components for performing logic checking according to an embodiment of the inventive concept is shown.

[0026] Figure 19 A system including components for performing a logic low check of an output signal according to an embodiment of the inventive concept is illustrated.

[0027] Figure 20 It shows Figure 19 An example timing diagram of the signals of the monitoring circuit.

[0028] Figure 21 A system including components for performing a logic high check of an output signal according to an embodiment of the inventive concept is illustrated.

[0029] Figure 22 It shows Figure 21 An example timing diagram of the signals of the monitoring circuit.

[0030] Figure 23 A system including components for performing logic checking and logic low and logic high checking of an output signal according to an embodiment of the inventive concept is shown.

[0031] Figure 24 An electronic device including an electronic device that performs DC-to-DC conversion according to an embodiment of the inventive concept is illustrated. DETAILED DESCRIPTION

[0032] Figure 1 An example of a system 100 including electronic devices 110 and 120 according to an embodiment of the inventive concept is shown. Figure 1, the first electronic device 110 and the second electronic device 120 can exchange signals.

[0033] The first electronic device 110 may include a core circuit 111, a driver 112, a monitoring circuit 113, a first pin 114, a receiver 115, and a second pin 116. The core circuit 111 may perform operations intended according to design and may exchange signals with the second electronic device 120.

[0034] The driver 112 may receive an input signal IN from the core circuit 111 . The driver 112 may generate an output signal OUT from the input signal IN. The driver 112 may transmit the output signal OUT to the second electronic device 120 through the first pin 114 .

[0035] The monitoring circuit 113 may receive an input signal IN and an output signal OUT. Based on the input signal IN and the output signal OUT, the monitoring circuit 113 may detect a stagnation voltage state of the output signal OUT. The stagnation voltage state may indicate that the output signal OUT is fixed to the power supply voltage VDD due to the connection of the output node of the output signal OUT to the power supply node, or to the ground voltage VSS due to the connection of the output node of the output signal OUT to the ground node. When the stagnation voltage state is detected, the monitoring circuit 113 may activate a check signal CHK. In response to the activation of the check signal CHK, the core circuit 111 may determine whether the stagnation voltage state has been detected.

[0036] The receiver 115 may receive the transmission signal TS from the second electronic device 120 through the second pin 116. The receiver 115 may provide the received transmission signal TS to the core circuit 111.

[0037] The second electronic device 120 may include a core circuit 121, a driver 122, a monitoring circuit 123, a first pin 124, a receiver 125, and a second pin 126. The operations of the components of the second electronic device 120 may be the same as those of the components of the first electronic device 110. Therefore, additional description will be omitted to avoid redundancy.

[0038] Conventional electronic device pin testing is performed using dedicated test equipment, such as automatic test equipment (ATE), or using built-in self-test (BIST) logic. Testing using ATE or BIST logic is limited in that pin testing is performed before the system is activated or only during initialization operations.

[0039] The monitoring circuit 113 according to an embodiment of the inventive concept can perform a pin test while the first electronic device 110 or the second electronic device 120 is operating while the operation of the first electronic device 110 or the second electronic device 120 is suspended. After the pin test is completed, the operation of the first electronic device 110 and the second electronic device 120 can be resumed.

[0040] While the pin test is being performed, the logic level (e.g., logic low or logic high) of the pin is maintained without modification. Therefore, the pins of the first electronic device 110 and the second electronic device 120 can be tested without affecting the operation of the first electronic device 110 and the second electronic device 120.

[0041] For example, one of the first electronic device 110 and the second electronic device 120 may be a power management integrated circuit (PMIC), and the other of the first electronic device 110 and the second electronic device 120 may be an application processor (AP). The drivers 112 and 122 and the receivers 115 and 125 may be general purpose input / output (GPIO).

[0042] The system 100 including the first electronic device 110 and the second electronic device 120 may be an in-vehicle infotainment system. The monitoring circuits 113 and 123 may comply with automotive safety integrity level (ASIL) or ISO26262.

[0043] Although the terms of first pins 114 and 124 and second pins 116 and 126 may be used, the components through which each of the first electronic device 110 and the second electronic device 120 exchanges signals with the outside may be modified or applied by one of various components such as pins, pads (or referred to as "pads" or "solder pads") and solder balls.

[0044] In addition, although Figure 1 The example is shown in which the driver 112 or 122 and the receiver 115 or 125 of the first electronic device 110 or the second electronic device 120 are connected to different pins, but the driver 112 or 122 and the receiver 115 or 125 of the first electronic device 110 or the second electronic device 120 may share one pin.

[0045] Figure 2 An example of an operating method of the first electronic device 110 or the second electronic device 120 according to an embodiment of the inventive concept is shown, for example, a method of monitoring an output signal of a driver. Figure 1 and Figure 2In operation S110, the first electronic device 110 or the second electronic device 120 may perform a logic check. The logic check may check whether the logic level of the input signal IN and the logic level of the output signal OUT are logically correct. When the logic level of the input signal IN and the logic level of the output signal OUT are logically correct, operation S130 is performed.

[0046] In operation S130, the first electronic device 110 or the second electronic device 120 may perform a change check on the output signal OUT. The change check on the output signal OUT may detect whether the level of the output signal OUT has actually changed when the level of the output signal OUT is changed according to the test procedure. If the output signal OUT changes, the first electronic device 110 or the second electronic device 120 may determine that a stagnant voltage state has not occurred in operation S150, and may complete the above monitoring process.

[0047] When it is determined in operation S120 that the logic level of the input signal IN and the logic level of the output signal OUT are logically incorrect or when it is determined in operation S140 that the output signal OUT does not change, operation S160 is performed. In operation S160, the first electronic device 110 or the second electronic device 120 may determine that a stagnant voltage state occurs and may perform an operation planned to be performed when a stagnant voltage state occurs.

[0048] For example, in response to the occurrence of a stagnant voltage state, the first electronic device 110 or the second electronic device 120 may be powered off. Alternatively, in response to the occurrence of a stagnant voltage state, the first electronic device 110 or the second electronic device 120 may notify an external device of the occurrence of the stagnant voltage state, or may enter a sleep mode. To support rechecking of the stagnant voltage state, the first electronic device 110 or the second electronic device 120 may be powered on or awakened under the control of an external device in the power-off state or in the sleep mode, and may perform the monitoring process again.

[0049] For example, Figure 2 The monitoring method may be performed upon initialization or startup of the first electronic device 110 or the second electronic device 120. The first electronic device 110 or the second electronic device 120 may set the input signal IN to logic low and / or logic high, and may perform a logic check and a change check of the output signal OUT.

[0050] Figure 2The monitoring method can be executed during operation of the first electronic device 110 or the second electronic device 120. The first electronic device 110 or the second electronic device 120 can set the input signal IN to logic low and / or logic high, and can perform a logic check and a change check of the output signal OUT. Alternatively, the first electronic device 110 or the second electronic device 120 can perform a logic check on the current input signal IN and a change check on the output signal OUT.

[0051] For example, the first electronic device 110 or the second electronic device 120 may have a normal mode and a test mode. In the normal mode, the first electronic device 110 or the second electronic device 120 may perform normal operations according to design purposes. In the test mode, the first electronic device 110 or the second electronic device 120 may monitor the stagnation voltage state of the first pin 114 or 124 by using the monitoring circuit 113 or 123.

[0052] Figure 3 An example of performing a logic check is shown. Figure 1 and Figure 3 In operation S210, the monitoring circuit 113 or 123 may receive an input signal IN and an output signal OUT. In operation S220, the monitoring circuit 113 or 123 may determine whether the logic level of the input signal IN and the logic level of the output signal OUT are different.

[0053] In response to the logic level of the input signal IN being different from the logic level of the output signal OUT, the monitoring circuit 113 or 123 may complete a logic check in operation S230. In response to the logic level of the input signal IN being the same as the logic level of the output signal OUT, the monitoring circuit 113 or 123 may activate the check signal CHK to report a stagnant voltage state in operation S240.

[0054] For example, the drivers 112 and 122 may operate in an inversion driving scheme. For example, each of the drivers 112 and 122 may invert the logic level of the input signal IN to output the output signal OUT. When the drivers 112 and 122 operate in a non-inversion scheme (e.g., when each of the drivers 112 and 122 outputs the logic level of the input signal IN as the logic level of the output signal OUT), the condition in operation S220 may be modified to determine whether the logic level of the input signal IN and the logic level of the output signal OUT are the same.

[0055] Figure 4 A system 200 is shown that includes components for performing logic checks. Figure 1 and Figure 4, the system 200 may include a first electronic device 210 and a second electronic device 220. The first pin 214 of the first electronic device 210 may be connected to the second pin 226 of the second electronic device 220. The first electronic device 210 and the second electronic device 220 may be connected to Figure 1 The first electronic device 110 and the second electronic device 120 correspond to each other.

[0056] The driver 212 may include a first driving transistor DT1. An input signal IN may be applied to a gate of the first driving transistor DT1. In response to the input signal IN, the first driving transistor DT1 may connect an output node from which an output signal OUT is output to a ground node to which a ground voltage VSS is applied.

[0057] The output node of the output signal OUT can be connected to a power supply node supplied with a power supply voltage VDD through a first resistor R1. The first resistor R1 that supplies the power supply voltage VDD to the output node can be provided at one of a first position 201 within the first electronic device 210, a second position 202 between the first electronic device 210 and the second electronic device 220, and a third position 203 within the second electronic device 220. An example is shown in which the first resistor R1 is provided at the first position 201.

[0058] When the input signal IN is set to a logic low (e.g., a ground voltage VSS), the first drive transistor DT1 may be turned off. Therefore, the output signal OUT may be set to the power supply voltage VDD (i.e., a logic high). When the input signal IN is set to a logic high (e.g., a power supply voltage VDD), the first drive transistor DT1 may be turned on. Therefore, the output signal OUT may be set to the ground voltage VSS (i.e., a logic low). The driver 212 may operate in an open drain scheme. The driver 212 of the open drain scheme may be used when the power supply voltage VDD of the first electronic device 210 and the power supply voltage VDD of the second electronic device 220 are different.

[0059] The monitoring circuit 213 may include a controller 230 and a first detector 240. The first detector 240 may perform an exclusive OR (XOR) operation on the input signal IN and the output signal OUT. When the input signal IN and the output signal OUT are the same, the first detector 240 may activate the first check signal CHK1 to a low level. The controller 230 may activate the check signal CHK in response to the activation of the first check signal CHK1.

[0060] For example, the first detector 240 may be referred to as a "first detection circuit," which checks the logic correctness of the input signal IN and the output signal OUT to output a first check signal CHK1. For example, the controller 230 may activate the first detector 240 in the test mode and deactivate the first detector 240 in the normal mode.

[0061] Figure 5 An example of performing a change check on the output signal OUT is shown. Figure 1 and Figure 5 In operation S310, the monitoring circuit 113 or 123 may perform a logic low check of the output signal OUT. Then, the monitoring circuit 113 or 123 may change (eg, increase) the level of the output signal OUT.

[0062] When it is determined in operation S320 that the output signal OUT changes, operation S330 may be performed. In operation S330, the monitoring circuit 113 or 123 may perform a logic high check of the output signal OUT. The monitoring circuit 113 or 123 may set the input signal IN so that the output signal OUT is converted to a logic high (e.g., the input signal IN may be set to a logic low). Then, the monitoring circuit 113 or 123 may change the level of the output signal OUT (e.g., reduce it).

[0063] When it is determined in operation S340 that the output signal OUT changes, operation S350 may be performed. In operation S350, the monitoring circuit 113 or 123 may complete a change check of the output signal OUT.

[0064] When it is determined in operation S320 that the output signal OUT does not change or when it is determined in operation S340 that the output signal OUT does not change, in operation S360 the monitoring circuit 113 or 123 may activate the check signal CHK to notify the core circuit 111 or 121 that a stagnation voltage state is detected.

[0065] Figure 6 An example of performing a logic low check of the output signal OUT is shown. Figure 1 and Figure 6 In operation S410 , the monitoring circuit 113 or 123 may set the input signal IN so that the output signal OUT is converted to logic low (eg, the input signal IN may be set to logic high).

[0066] In operation S420 , the monitoring circuit 113 or 123 may ramp up the output signal OUT. For example, the monitoring circuit 113 or 123 may ramp up the output signal OUT within a range in which the logic level of the output signal OUT does not change.

[0067] In operation S430 , the monitoring circuit 113 or 123 may determine whether the output signal OUT changes. In response to the output signal OUT changing, in operation S440 , the monitoring circuit 113 or 123 may complete a logic low check of the output signal OUT.

[0068] In response to the output signal OUT not changing, in operation S450, the monitoring circuit 113 or 123 may activate the check signal CHK to notify the core circuit 111 or 121 that a stagnation voltage state has been detected. For example, the monitoring circuit 113 or 123 may activate the check signal CHK in response to the output signal OUT not changing during a given time (e.g., during a check time).

[0069] Figure 7 A system 300 is shown that includes components for performing a logic low check of an output signal OUT. Figure 1 and Figure 7 , the system 300 may include a first electronic device 310 and a second electronic device 320. The first pin 314 of the first electronic device 310 may be connected to the second pin 326 of the second electronic device 320. The first electronic device 310 and the second electronic device 320 may be connected to Figure 1 The first electronic device 110 and the second electronic device 120 correspond to each other.

[0070] The first resistor R1 may be provided at one of a first position 301 within the first electronic device 310, a second position 302 between the first electronic device 310 and the second electronic device 320, and a third position 303 within the second electronic device 320. An example is shown where the first resistor R1 is provided at the first position 301.

[0071] The driver 312 may include a first driving transistor DT1. A second signal S2 may be applied to a gate of the first driving transistor DT1. In response to the second signal S2, the first driving transistor DT1 may selectively connect an output node from which an output signal OUT is output to a ground node to which a ground voltage VSS is applied.

[0072] The monitoring circuit 313 may include a controller 330, a second detector 340, a reference voltage generator 350, and a comparator 360. The second detector 340, the reference voltage generator 350, and the comparator 360 may be referred to as a "second detection circuit" that performs a logic low check of the output signal OUT to output a second check signal CHK2.

[0073] The second detector 340 may include a first gate G1, a second gate G2, a third gate G3, a fourth gate G4, a first transistor T1, a second transistor T2, a first inverter IV1, a second inverter IV2, a first delay unit D1, a second delay unit D2, and a third delay unit D3.

[0074] The first delay unit D1 may receive a first test signal Tm1. The first delay unit D1 may delay and output the first test signal Tm1. The second delay unit D2 may delay the output of the first delay unit D1 and output the delayed output to the first inverter IV1. The first inverter IV1 may invert and output the output of the second delay unit D2. The first gate G1 may perform an AND operation on the second check signal CHK2 and the input signal IN.

[0075] The third delay unit D3 can delay and output the output of the first gate G1. The second inverter IV2 can invert and output the output of the third delay unit D3. The second gate G2 can perform an AND operation on the input signal IN and the output of the first inverter IV1. The third gate G3 can perform an OR operation on the output of the first gate G1 and the output of the second gate G2. The output of the third gate G3 can be provided as the second signal S2 to the gate of the first drive transistor DT1.

[0076] The fourth gate G4 can perform an AND operation on the output of the first delay unit D1 and the output of the second inverter IV2. The output of the fourth gate G4 can be provided as a first signal S1 to the gate of the first transistor T1. The first transistor T1 and the second transistor T2 can be connected in series between the output node of the output signal OUT and the ground node of the ground voltage VSS. The gate voltage Vt from the controller 330 can be provided to the gate of the second transistor T2.

[0077] The reference voltage generator 350 may generate a first reference voltage Vref1. The comparator 360 may compare the first reference voltage Vref1 with the output signal OUT. When the voltage of the output signal OUT is greater than the first reference voltage Vref1, the comparator 360 may activate the second check signal CHK2 to a high level. For example, the reference voltage generator 350 or the comparator 360 may be activated in a test mode and deactivated in a normal mode.

[0078] In the test mode, the controller 330 may apply a gate voltage Vt to the second transistor T2 and may activate the first test signal Tm1. When the second check signal CHK2 transitions to a high level during the test time, the controller 330 may determine that a stagnation voltage state has not been detected. When the second check signal CHK2 does not transition to a high level during the test time, the controller 330 may determine that a stagnation voltage state has been detected. In response to the second check signal CHK2 not being activated during the test time, the controller 330 may activate the check signal CHK to notify the core circuit 111 or 121 that a stagnation voltage state has been detected.

[0079] Figure 8 An example of a reference voltage generator 350 is shown. Figure 1 、 Figure 7 and Figure 8 The reference voltage generator 350 may include a first reference resistor Rref1 and a first reference current source Iref1 connected in series between a power supply node of the power supply voltage VDD and a ground node of the ground voltage VSS. A voltage at a node between the first reference resistor Rref1 and the first reference current source Iref1 may serve as the first reference voltage Vref1.

[0080] When the first resistor R1 is Figure 7 When positioned at the first position 301 within the first electronic device 310 as shown in FIG, the reference voltage generator 350 may have Figure 8 The configuration shown in FIG. The first resistor R1 and the first reference resistor Rref1 can be manufactured by the same process. The process variable of the first reference resistor Rref1 can offset the process variable applied to the first resistor R1. Therefore, the first reference voltage Vref1 can be unaffected by the process variable.

[0081] For example, when the first resistor R1 is disposed at the second position 302 outside the first electronic device 310, the bandgap reference voltage generator may be used as the reference voltage generator 350. The first reference voltage Vref1 may be a bandgap reference voltage or a voltage generated from (e.g., increased or decreased from) the bandgap reference voltage.

[0082] For example, a switch can be added to deactivate the reference voltage generator 350 in normal mode to reduce power consumption. The switch can be provided between the power supply node and the first reference resistor Rref1, between the first reference resistor Rref1 and the first reference current source Iref1, or between the first reference current source Iref1 and the ground node. The switch can be controlled by the first test signal Tm1.

[0083] Figure 9 It shows Figure 7 The timing diagram of the signal of the monitoring circuit 313. Figure 1 、 Figure 7 and Figure 9 In the first phase P1, the controller 330 may enter the first mode M1 as a test mode. The controller 330 may activate the first test signal Tm1 to a high level. To check the logic low of the output signal OUT, the input signal IN may be set to a high level. The controller 330 may control the gate voltage Vt to a conduction level in the early stage of the first mode M1. This conduction level may be a level sufficient to turn on the second transistor T2.

[0084] In the early stage of the first mode M1, the input signal IN can be at a high level and the second check signal CHK2 can be at a low level. Therefore, the output of the first gate G1 can be at a low level, and the output of the second inverter IV2 can be at a high level. As the first test signal Tm1 transitions to a high level, the output of the first delay unit D1 can be set to a high level after the delay of the first delay unit D1. Therefore, in the second stage P2, as all inputs of the fourth gate G4 are set to a high level, the first signal S1 can be set to a high level.

[0085] The first transistor T1 is turned on by the first signal S1, and the second transistor T2 is turned on by the gate voltage Vt. Therefore, the output node of the output signal OUT can be connected to the ground node through the first transistor T1 and the second transistor T2, and the output signal OUT maintains the ground level.

[0086] After the output of the first delay unit D1 transitions to a high level and the delay of the second delay unit D2 elapses, the output of the second delay unit D2 can transition to a high level. The output of the first inverter IV1 is set to a low level, and the output of the second gate G2 is set to a low level. Because the outputs of the first gate G1 and the second gate G2 are set to a low level, in the third phase P3, the second signal S2, which is the output of the third gate G3, is set to a low level. Therefore, the first drive transistor DT1 is turned off.

[0087] From the first phase P1 to the third phase P3, the controller 330 may turn on the first transistor T1 and the second transistor T2 before turning off the first driving transistor DT1, thereby preventing the logic level of the output signal OUT from changing. For the purpose of checking the output signal OUT, the controller 330 may turn off the first driving transistor DT1 and connect the first transistor T1 and the second transistor T2 to the output node.

[0088] After the first driving transistor DT1 is turned off, the controller 330 may gradually reduce the level of the gate voltage Vt. As the gate voltage Vt decreases, the amount of the first current I1 may decrease in the fourth phase P4. As the amount of the first current I1 decreases, the level of the output signal OUT may increase due to the power supply voltage VDD applied to the power supply node connected to the first resistor R1.

[0089] When the voltage of the output signal OUT reaches the first reference voltage Vref1, in the fifth phase P5, the comparator 360 may activate the second check signal CHK2 to a high level. As the second check signal CHK2 transitions to a high level, the output of the first gate G1 may be set to a high level, and the second signal S2, which is the output of the third gate G3, transitions to a high level. As a result, the first drive transistor DT1 is turned on, and the level of the output signal OUT drops to the ground voltage VSS.

[0090] When the second check signal CHK2 transitions to a high level, the controller 330 may set the first test signal Tm1 to a low level. After the first test signal Tm1 is set to a low level and the delay of the first delay unit D1 elapses, in the sixth phase P6, the first signal S1, which is the output of the fourth gate G4, transitions to a low level. Alternatively, after the output of the first gate G1 transitions to a high level and the delay of the third delay unit D3 elapses, in the sixth phase P6, the first signal S1, which is the output of the fourth gate G4, transitions to a low level. As a result, the first transistor T1 is turned off.

[0091] In the case where the output signal OUT is stagnant at the ground node, even if the amount of the first current I1 decreases in the fourth phase P4 and the fifth phase P5, the level of the output signal OUT does not increase but may be maintained at the ground voltage VSS. When the second check signal CHK2 does not transition to a high level during the first check time tCHK1, the controller 330 may activate the check signal CHK to report a stagnant voltage state.

[0092] After the first check time tCHK1 has passed, the controller 330 may complete the logic low check of the output signal OUT in the seventh phase P7. For example, in response to the second check signal CHK2 being set to a high level, the controller 330 may complete the logic low check of the sixth phase P6 early.

[0093] The controller 330 may also perform any other checks or enter the second mode M2, which is the normal mode. In the second mode M2, which is the normal mode, the input signal IN can switch between a high level and a low level. Because the first test signal Tm1 is at a low level, the output of the first inverter IV1 can be at a high level. When the input signal IN is at a high level, the output of the second gate G2 can be at a high level; when the input signal IN is at a low level, the output of the second gate G2 can be at a low level.

[0094] Similarly, when the output of the second gate G2 is at a high level, the second signal S2 may be at a high level; when the output of the second gate G2 is at a low level, the second signal S2 may be at a low level. In the second mode M2, the second signal S2 may follow the input signal IN. Therefore, the first drive transistor DT1 may operate in response to the input signal IN.

[0095] Figure 10 An example of a range RVref1 of the first reference voltage Vref1 is shown. Figure 10 In the figure, the horizontal axis represents time "T" and the vertical axis represents voltage "V". Figure 1 、 Figure 7 and Figure 10 The low voltage VL may be the highest level recognized as a low level by the receiver 115 or 125 of the first electronic device 110 or the second electronic device 120. When the voltage of the transmission signal TS is equal to or less than the low voltage VL, the receiver 115 or 125 may determine that the transmission signal TS is at a low level.

[0096] The high voltage VH may be the lowest level recognized as a high level by the receiver 115 or 125. When the voltage of the transmission signal TS is equal to or greater than the high voltage VH, the receiver 115 or 125 may determine that the transmission signal TS is at a high level.

[0097] The first reference voltage Vref1 may be limited to a range from the ground voltage VSS to the low voltage VL. Therefore, even if the monitoring circuit 113 or 123 of one of the first electronic device 110 or the second electronic device 120 performs a check while changing the output signal OUT, the receiver 125 or 115 of the other electronic device 120 or 110 does not sense the change in the transmission signal TS. That is, according to an embodiment of the inventive concept, the monitoring of the output signal OUT does not affect the communication between the first electronic device 110 and the second electronic device 120.

[0098] Figure 11 An example of performing a logic high check of the output signal OUT is shown. Figure 1 and Figure 11In operation S510 , the monitoring circuit 113 or 123 may set the input signal IN so that the output signal OUT is converted to logic high (eg, the input signal IN may be set to logic low).

[0099] In operation S520 , the monitoring circuit 113 or 123 may ramp down the output signal OUT. For example, the monitoring circuit 113 or 123 may ramp down the output signal OUT within a range in which the logic level of the output signal OUT does not change.

[0100] In operation S530 , the monitoring circuit 113 or 123 may determine whether the output signal OUT changes. In response to the output signal OUT changing, in operation S540 , the monitoring circuit 113 or 123 may complete a logic high check of the output signal OUT.

[0101] In response to the output signal OUT not changing, in operation S550, the monitoring circuit 113 or 123 may activate the check signal CHK to notify the core circuit 111 or 121 that a stagnation voltage state has been detected. For example, the monitoring circuit 113 or 123 may activate the check signal CHK in response to the output signal OUT not changing during a given time (e.g., during a check time).

[0102] Figure 12 A system 400 is shown that includes components for performing a logic high check of an output signal OUT. Figure 1 and Figure 12 , the system 400 may include a first electronic device 410 and a second electronic device 420. The first pin 414 of the first electronic device 410 may be connected to the second pin 426 of the second electronic device 420. The first electronic device 410 and the second electronic device 420 may be connected to Figure 1 The first electronic device 110 and the second electronic device 120 correspond to each other.

[0103] The first resistor R1 may be disposed at one of a first position 401 within the first electronic device 410, a second position 402 between the first electronic device 410 and the second electronic device 420, and a third position 403 within the second electronic device 420. An example is shown where the first resistor R1 is disposed at the first position 401.

[0104] The driver 412 may include a first driving transistor DT1. An input signal IN may be applied to a gate of the first driving transistor DT1. In response to the input signal IN, the first driving transistor DT1 may selectively connect an output node from which an output signal OUT is output to a ground node to which a ground voltage VSS is applied.

[0105] The monitoring circuit 413 may include a controller 430, a third detector 440, a reference voltage generator 450, and a comparator 460. The third detector 440, the reference voltage generator 450, and the comparator 460 may be referred to as a "third detection circuit" that performs a logic high check of the output signal OUT to output a third check signal CHK3.

[0106] The third detector 440 may include a first current source ID1 and a third transistor T3 connected in series between an output node of the output signal OUT and a ground node of the ground voltage VSS. A second test signal Tm2 from the controller 430 may be applied to the gate of the third transistor T3. The first current source ID1 may be a variable current source that varies the amount of current under the control of the controller 430.

[0107] The reference voltage generator 450 may generate a second reference voltage Vref2. The reference voltage generator 450 may be implemented as a reference voltage generator. Figure 8 For example, the reference voltage generator 450 may generate the second reference voltage Vref2 by using the second reference resistor Rref2 and the second reference current source Iref2 instead of the first reference resistor Rref1 and the first reference current source Iref1.

[0108] The comparator 460 can compare the second reference voltage Vref2 with the output signal OUT. When the voltage of the output signal OUT is less than the second reference voltage Vref2, the comparator 460 can activate the third check signal CHK3 to a high level. For example, the reference voltage generator 450 or the comparator 460 can be activated in the test mode and can be deactivated in the normal mode.

[0109] The controller 430 may activate the second test signal Tm2 in the test mode. When the third check signal CHK3 transitions to a high level during the test time, the controller 430 may determine that a stagnation voltage state is not detected. When the third check signal CHK3 does not transition to a high level during the test time, the controller 430 may determine that a stagnation voltage state is detected. In response to the third check signal CHK3 not being activated during the test time, the controller 430 may activate the check signal CHK to notify the core circuit 111 or 121 that a stagnation voltage state is detected.

[0110] Figure 13 It shows Figure 12 The timing diagram of the signal of the monitoring circuit 413. Figure 1 、 Figure 12 and Figure 13In the first phase P1, the controller 430 may enter the third mode M3 as a test mode. The controller 430 may activate the second test signal Tm2 to a high level. For a logic high check of the output signal OUT, the input signal IN may be set to a low level.

[0111] As the second test signal Tm2 transitions to a high level, the third transistor T3 may be turned on. The controller 430 may gradually increase the current of the first current source ID1. As the current of the first current source ID1 gradually increases, the second current I2 may gradually increase. As the second current I2 gradually increases, the level of the output signal OUT may gradually decrease.

[0112] When the voltage of the output signal OUT reaches the second reference voltage Vref2, in the second phase P2, the comparator 460 may deactivate the first current source ID1 and activate the third check signal CHK3 to a high level. When the third check signal CHK3 transitions to a high level, the controller 430 may deactivate the second test signal Tm2 to a low level. As a result, the level of the output signal OUT may rise to the power supply voltage VDD.

[0113] In the case where the output signal OUT is stagnant at the power supply node, even if the amount of the second current I2 increases in the first phase P1 and the second phase P2, the level of the output signal OUT does not decrease and can be maintained at the power supply voltage VDD. When the third check signal CHK3 does not transition to a high level during the second check time tCHK2, the controller 430 may activate the check signal CHK to report a stagnant voltage state.

[0114] After the second check time tCHK2 has passed, in the third phase P3, the controller 430 may complete the logic high check of the output signal OUT. For example, in response to the third check signal CHK3 being set to a high level, the controller 430 may complete the logic high check of the second phase P2 early.

[0115] The controller 430 may also perform any other checks or may enter the second mode M2 ​​as the normal mode. In the second mode M2 ​​as the normal mode, the input signal IN may switch between a high level and a low level. In the second mode M2, the first drive transistor DT1 may drive the output signal OUT in response to the input signal IN.

[0116] Figure 14 An example of a range RVref2 of the second reference voltage Vref2 is shown. Figure 14 In the figure, the horizontal axis represents time "T" and the vertical axis represents voltage "V". Figure 1 、 Figure 12 and Figure 14, the second reference voltage Vref2 can be limited to a range from the power supply voltage VDD to the high voltage VH. Therefore, even if the monitoring circuit 113 or 123 of one electronic device 110 or 120 performs a check while changing the output signal OUT, the receiver 125 or 115 of the other electronic device 120 or 110 does not sense the change in the transmission signal TS. That is, according to an embodiment of the inventive concept, the monitoring of the output signal OUT does not affect the communication between the first electronic device 110 and the second electronic device 120.

[0117] Figure 15 A system 500 is shown that includes components for performing logic checks and logic low and logic high checks of an output signal OUT. Figure 1 and Figure 15 , the system 500 may include a first electronic device 510 and a second electronic device 520. The first pin 514 of the first electronic device 510 may be connected to the second pin 526 of the second electronic device 520. The first electronic device 510 and the second electronic device 520 may be connected to Figure 1 The first electronic device 110 and the second electronic device 120 correspond to each other.

[0118] The first resistor R1 may be disposed at one of a first position 501 within the first electronic device 510, a second position 502 between the first electronic device 510 and the second electronic device 520, and a third position 503 within the second electronic device 520. An example is shown where the first resistor R1 is disposed at the first position 501.

[0119] The driver 512 may include a first drive transistor DT1. A second signal S2 from the monitoring circuit 513 may be applied to the gate of the first drive transistor DT1. In response to the second signal S2, the first drive transistor DT1 may selectively connect an output node from which the output signal OUT is output to a ground node to which a ground voltage VSS is applied.

[0120] The monitoring circuit 513 may include a first detector 240 that performs a logic check, a second detector 340 that performs a logic low check of the output signal OUT, and a third detector 440 that performs a logic high check of the output signal OUT.

[0121] The first detector 240 may perform an exclusive OR operation on the input signal IN and the output signal OUT. The first detector 240 may provide a first check signal CHK1 to the controller 530. When the first check signal CHK1 is at a low level, the controller 530 may determine that the input signal IN and the output signal OUT are logically incorrect.

[0122] The second detector 340 may receive the input signal IN and the first test signal Tm1, may output the second signal S2, and may be connected to the output node of the output signal OUT. The configuration and operation of the second detector 340 are similar to those of the reference Figures 6 to 10 The configuration and operation of the third detector 440 are the same as those described in the reference. The third detector 440 can receive the second test signal Tm2 and can be connected to the output node of the output signal OUT. The configuration and operation of the third detector 440 are the same as those described in the reference. Figures 11 to 14 The configuration and operation described are the same.

[0123] The reference voltage generator 550 may output a first reference voltage Vref1 and a second reference voltage Vref2. The first comparator 360 may compare the first reference voltage Vref1 with the output signal OUT and may output the comparison result as a second check signal CHK2. The second comparator 460 may compare the second reference voltage Vref2 with the output signal OUT and may output the comparison result as a third check signal CHK3.

[0124] The controller 530 may detect a stagnation voltage state based on the first, second, and third check signals CHK1, CHK2, and CHK3. When the stagnation voltage state is detected, the controller 530 may activate the check signal CHK to notify the core circuit 111 or 121 of the detection of the stagnation voltage state.

[0125] Figure 16 An example of a reference voltage generator 550 is shown. Figure 1 、 Figure 15 and Figure 16 , the reference voltage generator 550 may include a third reference resistor Rref3 , a fourth reference resistor Rref4 , and a third reference current source Iref3 connected in series between a power supply node of the power supply voltage VDD and a ground node of the ground voltage VSS.

[0126] A voltage of a node between the third reference resistor Rref3 and the fourth reference resistor Rref4 may be used as a second reference voltage Vref2 . A voltage of a node between the fourth reference resistor Rref4 and the third reference current source Iref3 may be used as a first reference voltage Vref1 .

[0127] For example, when the first resistor R1 is Figure 7 When the reference voltage generator 550 is positioned at the first position 501 in the first electronic device 310 as shown in FIG. Figure 16The configuration shown in FIG. The first resistor R1, the third reference resistor Rref3, and the fourth reference resistor Rref4 can be manufactured using the same process. The process variables of the third reference resistor Rref3 and the fourth reference resistor Rref4 can offset the process variables applied to the first resistor R1. Therefore, the first reference voltage Vref1 and the second reference voltage Vref2 can be unaffected by the process variables.

[0128] For example, when the first resistor R1 is provided at the second position 502 outside the first electronic device 510, the bandgap reference voltage generator may be used as the reference voltage generator 550. The first reference voltage Vref1 and the second reference voltage Vref2 may be the bandgap reference voltage or voltages generated from (e.g., increased or decreased from) the bandgap reference voltage.

[0129] For example, a switch can be added to deactivate the reference voltage generator 550 in normal mode to reduce power consumption. The switch can be provided between the power supply node and the third reference resistor Rref3, between the third reference resistor Rref3 and the fourth reference resistor Rref4, between the fourth reference resistor Rref4 and the third reference current source Iref3, or between the third reference current source Iref3 and the ground node. The switch can be activated by the controller 530 in test mode.

[0130] Figure 17 The example of using a plurality of comparators 360a, 360b, 460a and 460b for checking the change of the output signal OUT is shown. The reference voltage generator 550 and the comparators 360 and 460 can be used. Figure 17 The voltage generator 550a and the comparators 360a, 360b, 460a and 460b are replaced.

[0131] Reference Figure 1 、 Figure 15 and Figure 17 The 1a-th comparator 360a may compare the 1a-th reference voltage Vref1a with the output signal OUT. When the voltage of the output signal OUT is greater than the 1a-th reference voltage Vref1a, the 1a-th comparator 360a may activate the 2a-th check signal CHK2a to a high level. The 1b-th comparator 360b may compare the 1b-th reference voltage Vref1b with the output signal OUT. When the voltage of the output signal OUT is greater than the 1b-th reference voltage Vref1b, the 1b-th comparator 360b may activate the 2b-th check signal CHK2b to a high level.

[0132] The 1a-th comparator 360a may be used to perform a logic low check of the output signal OUT. When the 2a-th check signal CHK2a remains at a low level during a specific check time in the test mode, the controller 530 may detect a stagnation voltage state and may activate the check signal CHK to logic high.

[0133] The 1b-th comparator 360b can be used to determine the level of the output signal OUT. When the output signal OUT is at a low level in the test mode, the 1b-th comparator 360b can compare the level of the output signal OUT with the level of the 1b-th reference voltage Vref1b. For example, the 1b-th reference voltage Vref1b can be less than or greater than the 1a-th reference voltage Vref1a. Two or more comparators and two or more different reference voltages can be used to determine the voltage of the low level of the output signal OUT.

[0134] The 2a-th comparator 460a may compare the 2a-th reference voltage Vref2a with the output signal OUT. When the voltage of the output signal OUT is less than the 2a-th reference voltage Vref2a, the 2a-th comparator 460a may activate the 3a-th check signal CHK3a to a high level. The 2b-th comparator 460b may compare the 2b-th reference voltage Vref2b with the output signal OUT. When the voltage of the output signal OUT is less than the 2b-th reference voltage Vref2b, the 2b-th comparator 460b may activate the 3b-th check signal CHK3b to a high level.

[0135] The 2ath comparator 460a may be used to perform a logic high check of the output signal OUT. When the 3ath check signal CHK3a remains at a low level during a specific check time in the test mode, the controller 530 may detect a stagnation voltage state and may activate the check signal CHK to logic high.

[0136] The 2b-th comparator 460b can be used to determine the level of the output signal OUT. When the output signal OUT is at a high level in the test mode, the 2b-th comparator 460b can compare the level of the output signal OUT with the level of the 2b-th reference voltage Vref2b. For example, the 2b-th reference voltage Vref2b can be less than or greater than the 2a-th reference voltage Vref2a. Two or more comparators and two or more different reference voltages can be used to determine the voltage of the high level of the output signal OUT.

[0137] like Figure 16 As shown in , the number of reference voltages generated by the voltage generator 550a can be increased by increasing the number of reference resistors.

[0138] Figure 18A system 600 is shown including components for performing logic checks. Figure 1 and Figure 18 , the system 600 may include a first electronic device 610 and a second electronic device 620. The first pin 614 of the first electronic device 610 may be connected to the second pin 626 of the second electronic device 620. The first electronic device 610 and the second electronic device 620 may be connected to Figure 1 The first electronic device 110 and the second electronic device 120 correspond to each other.

[0139] The driver 612 may include a second driver transistor DT2 and a third driver transistor DT3 connected in series between a power supply node of a power supply voltage VDD and a ground node of a ground voltage VSS. An input signal IN may be applied to the gate of the second driver transistor DT2 and the gate of the third driver transistor DT3. The voltage at the node between the second driver transistor DT2 and the third driver transistor DT3 may be an output voltage. The second driver transistor DT2 and the third driver transistor DT3 may constitute an inverter. When the input signal IN is at a high level, the driver 612 may connect the output node of the output signal OUT to the ground node using the third driver transistor DT3. When the input signal IN is at a low level, the driver 612 may connect the output node of the output signal OUT to the power supply node using the second driver transistor DT2.

[0140] The monitoring circuit 613 may include a controller 630 and a fourth detector 640. The fourth detector 640 may perform an exclusive OR operation on the input signal IN and the output signal OUT. When the input signal IN and the output signal OUT are the same, the fourth detector 640 may activate the fourth check signal CHK4 to a low level. The controller 630 may activate the check signal CHK in response to the activation of the fourth check signal CHK4.

[0141] For example, the fourth detector 640 may be referred to as a "first detection circuit" that checks the logic correctness of the input signal IN and the output signal OUT to output the fourth check signal CHK4. For example, the controller 630 may activate the fourth detector 640 in the test mode and may deactivate the fourth detector 640 in the normal mode.

[0142] Figure 19 A system 700 is shown that includes components for performing a logic low check of an output signal OUT. Figure 1 and Figure 19 , the system 700 may include a first electronic device 710 and a second electronic device 720. The first pin 714 of the first electronic device 710 may be connected to the second pin 726 of the second electronic device 720. The first electronic device 710 and the second electronic device 720 may be connected to Figure 1The first electronic device 110 and the second electronic device 120 correspond to each other.

[0143] The driver 712 may include a second driving transistor DT2 and a third driving transistor DT3. An input signal IN may be applied to a gate of the second driving transistor DT2, and an output of the sixth gate G6 may be applied to a gate of the third driving transistor DT3.

[0144] The monitoring circuit 713 may include a controller 730, a fifth detector 740, a reference voltage generator 750, and a comparator 760. The fifth detector 740, the reference voltage generator 750, and the comparator 760 may be referred to as a "second detection circuit" that performs a logic low check of the output signal OUT to output a fifth check signal CHK5.

[0145] The fifth detector 740 may include a fifth gate G5, a sixth gate G6, a fourth delay unit D4, a third inverter IV3, a fifth transistor T5, a sixth transistor T6, a second resistor R2, and a second current source ID2. The second current source ID2 may be a variable current source that varies the amount of current under the control of the controller 730.

[0146] The fifth gate G5 can calculate the AND value of the input signal IN and the third test signal Tm3 from the controller 730. The fifth gate G5 can output the calculated result as the third signal S3. The third signal S3 is applied to the gate of the sixth transistor T6. The fourth delay unit D4 can delay and output the third signal S3. The third inverter IV3 can invert the output of the fourth delay unit D4 to output the fourth signal S4.

[0147] The fourth signal S4 may be applied to the gate of the fifth transistor T5. The sixth gate G6 may calculate an AND value of the fourth signal S4 and the input signal IN. The output of the sixth gate G6 may be provided as the fifth signal S5 to the gate of the third driving transistor DT3.

[0148] The node between the fifth transistor T5 and the sixth transistor T6 can be connected to the output node of the output signal OUT. The second current source ID2 can be connected between the power supply node to which the power supply voltage VDD is applied and the fifth transistor T5. The second resistor R2 can be connected between the sixth transistor T6 and the ground node.

[0149] The reference voltage generator 750 may generate a third reference voltage Vref3. The comparator 760 may compare the third reference voltage Vref3 with the output signal OUT. When the voltage of the output signal OUT is greater than the third reference voltage Vref3, the comparator 760 may activate the fifth check signal CHK5 to a high level. For example, the reference voltage generator 750 or the comparator 760 may be activated in the test mode and deactivated in the normal mode.

[0150] The controller 730 may activate the third test signal Tm3 in the test mode. When the fifth check signal CHK5 transitions to a high level during the test time, the controller 730 may determine that a stagnation voltage state is not detected. When the fifth check signal CHK5 does not transition to a high level during the test time, the controller 730 may determine that a stagnation voltage state is detected. In response to the fifth check signal CHK5 not being activated during the test time, the controller 730 may activate the check signal CHK to notify the core circuit 111 or 121 that a stagnation voltage state is detected.

[0151] Figure 20 It shows Figure 19 The timing diagram of the signal of the monitoring circuit 713. Figure 1 、 Figure 19 and Figure 20 In the first phase P1, the controller 730 may enter the fourth mode M4 as a test mode. The controller 730 may activate the third test signal Tm3 to a high level. For a logic low check of the output signal OUT, the input signal IN may be set to a high level.

[0152] In the first phase P1, the input signal IN can be at a high level, and the third test signal Tm3 can be at a high level. Therefore, the output of the fifth gate G5 is converted to a high level, and the sixth transistor T6 is turned on. The sixth transistor T6 can connect the output node to the ground node.

[0153] After the delay time of the fourth delay unit D4 has elapsed, in the second phase P2, the fourth signal S4 may transition to a low level. As the fourth signal S4 transitions to a low level, the fifth transistor T5 may be turned on. The fifth signal S5 may transition to a low level, turning off the third driver transistor DT3. In other words, the driver 712 is deactivated.

[0154] The controller 730 may gradually increase the current of the second current source ID2. As the current of the second current source ID2 gradually increases, the third current I3 may gradually increase. As the third current I3 gradually increases, the voltage of the output signal OUT may gradually increase.

[0155] When the voltage of the output signal OUT reaches the third reference voltage Vref3, in the third phase P3, the comparator 760 may activate the fifth check signal CHK5 to a high level. When the fifth check signal CHK5 transitions to a high level, the controller 730 may set the third test signal Tm3 to a low level. When the third test signal Tm3 is set to a low level, the controller 730 may deactivate the second current source ID2. Therefore, the voltage of the output node of the output signal OUT may be set to the ground voltage VSS via the sixth transistor T6. When the third signal S3 transitions to a low level, the sixth transistor T6 is turned off.

[0156] After the delay of the fourth delay unit D4, in the fourth phase P4, the fourth signal S4 may be converted to a high level. Therefore, the fifth transistor T5 is turned off. The fifth signal S5 is converted to a high level, and the third driving transistor DT3 is turned on. In other words, the driver 712 is activated.

[0157] In the case where the output signal OUT is stagnant at the ground node, even if the amount of the third current I3 increases in the second phase P2 and the third phase P3, the level of the output signal OUT does not increase and may be maintained at the ground voltage VSS. When the fifth check signal CHK5 does not transition to a high level during the third check time tCHK3, the controller 730 may activate the check signal CHK to report a stagnant voltage state.

[0158] After the third check time tCHK3 has passed, in the fifth phase P5, the controller 730 may complete the logic low check of the output signal OUT. For example, in response to the fifth check signal CHK5 being set to a high level, the controller 730 may complete the logic low check of the output signal OUT early in the fourth phase P4.

[0159] The controller 730 may also perform any other checks or may enter the second mode M2, which is the normal mode. In the second mode M2, which is the normal mode, the input signal IN may switch between a high level and a low level. Because the third test signal Tm3 is at a low level, the fourth signal S4 may be at a high level. When the input signal IN is at a high level, the fifth signal S5 may be at a high level; when the input signal IN is at a low level, the fifth signal S5 may be at a low level. In the second mode M2, the fifth signal S5 may follow the input signal IN. Therefore, the second drive transistor DT2 and the third drive transistor DT3 may operate in response to the input signal IN.

[0160] Figure 21 A system 800 is shown that includes components for performing a logic high check of an output signal OUT. Figure 1 and Figure 21, the system 800 may include a first electronic device 810 and a second electronic device 820. The first pin 814 of the first electronic device 810 may be connected to the second pin 826 of the second electronic device 820. The first electronic device 810 and the second electronic device 820 may be connected to Figure 1 The first electronic device 110 and the second electronic device 120 correspond to each other.

[0161] The driver 812 may include a second driving transistor DT2 and a third driving transistor DT3. A seventh signal S7 as an output of a seventh gate G7 may be applied to the gate of the second driving transistor DT2, and an input signal IN may be applied to the gate of the third driving transistor DT3.

[0162] The monitoring circuit 813 may include a controller 830, a sixth detector 840, a reference voltage generator 850, and a comparator 860. The sixth detector 840, the reference voltage generator 850, and the comparator 860 may be referred to as a "third detection circuit," which performs a logic high check of the output signal OUT to output a sixth check signal CHK6.

[0163] The sixth detector 840 may include a seventh gate G7, a fifth delay unit D5, a fourth inverter IV4, a seventh transistor T7, an eighth transistor T8, a third resistor R3, and a third current source ID3. The third current source ID3 may be a variable current source that varies the amount of current under the control of the controller 830.

[0164] The fourth test signal Tm4 from the controller 830 may be applied to the gate of the eighth transistor T8. The fourth inverter IV4 may invert the fourth test signal Tm4 from the controller 830 and output the inverted version of the fourth test signal Tm4 to the gate of the seventh transistor T7. The node between the seventh transistor T7 and the eighth transistor T8 may be connected to the output node of the output signal OUT.

[0165] The third resistor R3 may be connected between the seventh transistor T7 and the power supply node. The third current source ID3 may be connected between the eighth transistor T8 and the ground node. The fifth delay unit D5 may delay the fourth test signal Tm4 and may output the delayed fourth test signal Tm4 as the sixth signal S6. The seventh gate G7 may output the seventh signal S7 as a result of performing an OR operation on the input signal IN and the sixth signal S6. The seventh signal S7 may be applied to the gate of the second drive transistor DT2.

[0166] The reference voltage generator 850 may generate a fourth reference voltage Vref4. The comparator 860 may compare the fourth reference voltage Vref4 with the output signal OUT. When the voltage of the output signal OUT is less than the fourth reference voltage Vref4, the comparator 860 may activate the sixth check signal CHK6 to a high level. For example, the reference voltage generator 850 or the comparator 860 may be activated in the test mode and deactivated in the normal mode.

[0167] The controller 830 may activate the fourth test signal Tm4 in the test mode. When the sixth check signal CHK6 transitions to a high level during the test time, the controller 830 may determine that a stagnation voltage state is not detected. When the sixth check signal CHK6 does not transition to a high level during the test time, the controller 830 may determine that a stagnation voltage state is detected. In response to the sixth check signal CHK6 not being activated during the test time, the controller 830 may activate the check signal CHK to notify the core circuit 111 or 121 that a stagnation voltage state is detected.

[0168] Figure 22 It shows Figure 21 The timing diagram of the signal of the monitoring circuit 813. Figure 1 、 Figure 21 and Figure 22 In the first phase P1, the controller 830 may enter the fifth mode M5 as a test mode. The controller 830 may activate the fourth test signal Tm4 to a high level. For a logic high check of the output signal OUT, the input signal IN may be set to a low level.

[0169] As the fourth test signal Tm4 transitions to a high level, the seventh transistor T7 and the eighth transistor T8 are turned on. The seventh transistor T7 can supply the power supply voltage VDD to the output node of the output signal OUT. The eighth transistor T8 can connect the third current source ID3 to the output node.

[0170] After the delay time of the fifth delay unit D5 has elapsed, in the second phase P2, the sixth signal S6 transitions to a high level. Therefore, the seventh signal S7 is set to a high level. The second driver transistor DT2 and the third driver transistor DT3 are turned off, and the driver 812 is deactivated. The controller 830 may gradually increase the current of the third current source ID3. As the current of the third current source ID3 gradually increases, the amount of the fourth current I4 may gradually increase. As the amount of the fourth current I4 gradually increases, the level of the output signal OUT may gradually decrease.

[0171] When the voltage of the output signal OUT reaches the fourth reference voltage Vref4, in the third phase P3, the comparator 860 may activate the sixth check signal CHK6 to a high level. When the sixth check signal CHK6 transitions to a high level, the controller 830 may deactivate the third current source ID3 and may deactivate the fourth test signal Tm4 to a low level. As the fourth test signal Tm4 is set to a low level, the seventh transistor T7 and the eighth transistor T8 are turned off.

[0172] After the delay time of the fifth delay unit D5 has elapsed, in the fourth phase P4, the sixth signal S6 transitions to a low level, and the seventh signal S7 transitions to a low level. As the seventh signal S7 transitions to a low level, the third driving transistor DT3 is turned on. That is, the driver 812 may be activated.

[0173] In the case where the output signal OUT is stagnant at the power supply node, even if the amount of the fourth current I4 increases in the second phase P2 and the third phase P3, the level of the output signal OUT does not decrease and can be maintained at the power supply voltage VDD. When the sixth check signal CHK6 does not transition to a high level during the fourth check time tCHK4, the controller 830 may activate the check signal CHK to report a stagnant voltage state.

[0174] After the fourth check time tCHK4 has passed, in the fifth phase P5, the controller 830 may complete the logic high check of the output signal OUT. For example, in response to the sixth check signal CHK6 being set to a high level, the controller 830 may complete the logic high check of the output signal OUT early in the fourth phase P4.

[0175] The controller 830 may also perform any other checks or may enter the second mode M2 ​​as a normal mode. In the second mode M2 ​​as the normal mode, the input signal IN may switch between a high level and a low level. In the second mode M2, the seventh signal S7 may follow the input signal IN. Therefore, the second drive transistor DT2 and the third drive transistor DT3 may drive the output signal OUT in response to the input signal IN.

[0176] Figure 23 A system 900 is shown that includes components for performing logic checks and logic low and logic high checks of an output signal OUT. Figure 1 and Figure 23 , the system 900 may include a first electronic device 910 and a second electronic device 920. The first pin 914 of the first electronic device 910 may be connected to the second pin 926 of the second electronic device 920. The first electronic device 910 and the second electronic device 920 may be connected to Figure 1 The first electronic device 110 and the second electronic device 120 correspond to each other.

[0177] The driver 912 may include a second driving transistor DT2 and a third driving transistor DT3. The fifth signal S5 as the output of the fifth detector 740 may be applied to the gate of the third driving transistor DT3, and the seventh signal S7 as the output of the sixth detector 840 may be applied to the gate of the second driving transistor DT2.

[0178] The monitoring circuit 913 may include a fourth detector 640 that performs a logic check, a fifth detector 740 that performs a logic low check of the output signal OUT, and a sixth detector 840 that performs a logic high check of the output signal OUT.

[0179] The fourth detector 640 may perform an exclusive OR operation on the input signal IN and the output signal OUT. The fourth detector 640 may provide a fourth check signal CHK4 to the controller 930. When the fourth check signal CHK4 is at a low level, the controller 930 may determine that the input signal IN and the output signal OUT are logically incorrect.

[0180] The fifth detector 740 may receive the input signal IN and the third test signal Tm3, may output a fifth signal S5, and may be connected to an output node of the output signal OUT. The configuration and operation of the fifth detector 740 are similar to those of the reference signal OUT. Figure 19 and Figure 20 The configuration and operation of the sixth detector 840 are the same as those described above. The sixth detector 840 can receive the input signal IN and the fourth test signal Tm4, can output the seventh signal S7, and can be connected to the output node of the output signal OUT. The configuration and operation of the sixth detector 840 are the same as those described above. Figure 21 and Figure 22 The configuration and operation described are the same.

[0181] The reference voltage generator 950 may output a third reference voltage Vref3 and a fourth reference voltage Vref4. The first comparator 760 may compare the third reference voltage Vref3 with the output signal OUT and may output the comparison result as a fifth check signal CHK5. The second comparator 860 may compare the fourth reference voltage Vref4 with the output signal OUT and may output the comparison result as a sixth check signal CHK6.

[0182] The controller 930 may detect a stagnation voltage state based on the fourth, fifth, and sixth check signals CHK4, CHK5, and CHK6. When a stagnation voltage state is detected, the controller 930 may activate the check signal CHK to notify the core circuit 111 or 121 of the detection of the stagnation voltage state.

[0183] For example, as referenced Figure 17As described above, in addition to detecting the stagnant voltage state, the monitoring circuit 913 may also be configured to determine the low level and / or high level voltage of the output signal OUT.

[0184] Figure 24 is a block diagram illustrating an electronic device 1000 including a first electronic device 110 or a second electronic device 120 that performs DC to DC conversion according to the inventive concept. Figure 24 , the electronic device 1000 may include a main processor 1100, a touch panel 1200, a touch driver integrated circuit (TDI) 1202, a display panel 1300, a display driver integrated circuit (DDI) 1302, a system memory 1400, a storage device 1500, an audio processor 1600, a communication block 1700, an image processor 1800, and a user interface 1900. In an exemplary embodiment, the electronic device 1000 may be one of various electronic devices such as a personal computer, a laptop computer, a workstation, a portable communication terminal, a personal digital assistant (PDA), a portable media player (PMP), a digital camera, a smart phone, a tablet computer, and a wearable device.

[0185] The main processor 1100 may control the overall operation of the electronic device 1000. The main processor 1100 may control / manage the operations of the components of the electronic device 1000. The main processor 1100 may process various operations for the purpose of operating the electronic device 1000. The touch panel 1200 may be configured to sense touch input from a user under the control of the touch driver integrated circuit 1202. The display panel 1300 may be configured to display image information under the control of the display driver integrated circuit 1302.

[0186] The system memory 1400 may store data used for the operation of the electronic device 1000. For example, the system memory 1400 may include a volatile memory such as a static random access memory (SRAM), a dynamic RAM (DRAM), or a synchronous DRAM (SDRAM) and / or a nonvolatile memory such as a phase change RAM (PRAM), a magnetoresistive RAM (MRAM), a resistive RAM (ReRAM), or a ferroelectric RAM (FRAM).

[0187] The storage device 1500 can store data regardless of whether power is supplied. For example, the storage device 1500 can include at least one of various non-volatile memories such as flash memory, PRAM, MRAM, ReRAM, and FRAM. For example, the storage device 1500 can include embedded memory and / or removable memory of the electronic device 1000.

[0188] The audio processor 1600 can process an audio signal by using an audio signal processor 1610. The audio processor 1600 can receive audio input through a microphone 1620 and / or provide audio output through a speaker 1630. The communication block 1700 can exchange signals with an external device / system through an antenna 1710. The transceiver 1720 and the modem (MODEM) 1730 of the communication block 1700 can process signals exchanged with an external device / system based on at least one of the following various wireless communication protocols: Long Term Evolution (LTE), Worldwide Interoperability for Microwave Access (WiMax), Global System for Mobile Communications (GSM), Code Division Multiple Access (CDMA), Bluetooth, Near Field Communication (NFC), Wireless Fidelity (Wi-Fi), and Radio Frequency Identification (RFID).

[0189] The image processor 1800 may receive light through the lens 1810. The image device 1820 and the image signal processor (ISP) 1830 included in the image processor 1800 may generate image information about an external object based on the received light. The user interface 1900 may include an interface capable of exchanging information with a user in addition to the touch panel 1200, the display panel 1300, the audio processor 1600, and the image processor 1800. The user interface 1900 may include a keyboard, a mouse, a printer, a projector, various sensors, a human body communication device, etc.

[0190] The electronic device 1000 may further include a power management IC (PMIC) 1010 and a battery 1020. The power management IC 1010 may generate internal power from power supplied from the battery 1020, and may provide the internal power to the main processor 1100, the touch panel 1200, the touch driver integrated circuit (TDI) 1202, the display panel 1300, the display driver integrated circuit (DDI) 1302, the system memory 1400, the storage device 1500, the audio processor 1600, the communication block 1700, the image processor 1800, and the user interface 1900.

[0191] Each component of electronic device 1000 may include a safety monitoring device SM. Furthermore, the safety monitoring device SM may be connected to each channel between components of electronic device 1000. To detect a stagnant voltage state, the safety monitoring device SM may include a monitoring circuit 113 or 123 according to an embodiment of the inventive concept. Electronic device 1000 may be implemented as an in-vehicle infotainment system. The safety monitoring device SM may be implemented based on ISO 26262 or ASIL.

[0192] In the above embodiments, components according to the inventive concept are described using the terms "first," "second," "third," etc. However, the terms "first," "second," "third," etc. may be used to distinguish components from one another and do not limit the inventive concept. For example, the terms "first," "second," "third," etc. do not refer to any form of order or numerical meaning.

[0193] In the above embodiments, the components of the embodiments according to the inventive concept are described using blocks. The blocks can be implemented using various hardware devices (such as integrated circuits, application specific ICs (ASICs), field programmable gate arrays (FPGAs), and complex programmable logic devices (CPLDs)), firmware driven in the hardware devices, software (such as applications), or a combination of hardware devices and software. In addition, the blocks may include circuits implemented using semiconductor elements in integrated circuits or circuits registered as intellectual property (IP).

[0194] According to the inventive concept, whether the output of a driver of an output signal is in a stagnation voltage state is detected based on an input signal and an output signal of the driver.

[0195] While the inventive concept has been described with reference to exemplary embodiments thereof, it will be apparent to those skilled in the art that various changes and modifications can be made thereto without departing from the spirit and scope of the inventive concept as set forth in the appended claims.

Claims

1. An electronic device comprising: a driver connected to the pin and configured to receive an input signal and output an output signal to the pin in response to the input signal; a core circuit configured to transmit an input signal to a driver; as well as a monitoring circuit configured to receive an input signal and an output signal and detect a stagnant voltage state of the output signal based on the input signal and the output signal, Among them, the monitoring circuit includes: a first detection circuit configured to detect a stagnant voltage state when the input signal and the output signal are logically incorrect; a second detection circuit configured to detect a stagnation voltage state when the input signal and the output signal are logically correct and when the output signal is at a low level; and a third detection circuit configured to detect a stagnation voltage state when the input signal and the output signal are logically correct and when the output signal is at a high level, Therein, while the pin test is performed by the monitoring circuit, the logic level of the pin is maintained without modification.

2. The electronic device according to claim 1, wherein The first detection circuit includes: The XOR gate is configured to detect a stagnant voltage state in response to the logic level of the input signal and the logic level of the output signal being the same.

3. The electronic device according to claim 1, wherein The second detection circuit deactivates the driver and causes current to flow out of the driver's output node. The second detection circuit gradually reduces the amount of current flowing out of the output node of the driver, and In response to the voltage of the output node being greater than the reference voltage, the second detection circuit detects that the output node is not stagnant to the ground voltage.

4. The electronic device according to claim 3, wherein: In response to the voltage of the output node remaining below the reference voltage, the second detection circuit detects that the output node is stagnant to the ground voltage.

5. The electronic device according to claim 3, wherein: The reference voltage is lower than a maximum voltage at which an external device connected to the pin recognizes the logic level of an output signal as a low level. The electronic device according to claim 3 , wherein: In response to the voltage of the output node being greater than a second reference voltage different from the reference voltage, the second detection circuit detects a level of the voltage of the output node.

7. The electronic device according to claim 3, wherein: In response to the voltage of the output node being greater than the reference voltage, the second detection circuit activates the driver, and the second detection circuit is deactivated.

8. The electronic device according to claim 1, wherein The third detection circuit deactivates the driver and causes current to flow out of the driver's output node. The third detection circuit gradually increases the amount of current flowing out of the output node of the driver, and In response to the voltage of the output node being less than the reference voltage, the third detection circuit detects that the output node has not stagnated to the power supply voltage.

9. The electronic device according to claim 8, wherein: In response to the voltage of the output node remaining above the reference voltage, the third detection circuit detects that the output node is stagnant to the power supply voltage.

10. The electronic device according to claim 8, wherein The reference voltage is greater than a minimum voltage at which an external device connected to the pin recognizes a logic level of an output signal as a high level.

11. The electronic device according to claim 8, wherein: In response to the voltage of the output node being less than a second reference voltage different from the reference voltage, the third detection circuit detects a level of the voltage of the output node.

12. The electronic device according to claim 8, wherein In response to the voltage of the output node being less than the reference voltage, the third detection circuit activates the driver, and the third detection circuit is deactivated.

13. The electronic device according to claim 1, wherein The second detection circuit deactivates the driver and supplies current to the output node of the driver, wherein the second detection circuit gradually increases the amount of current supplied to the output node of the driver, and In response to the voltage of the output node being greater than the reference voltage, the second detection circuit detects that the output node is not stagnant at the ground voltage.

14. The electronic device according to claim 1, wherein In response to detecting a stagnant voltage condition, powering off the electronic device is performed.

15. The electronic device according to claim 1, wherein The core circuit generates a second voltage from a first voltage received from the outside, and performs power management so that the second voltage is output, and Among them, the driver is associated with the general input / output.

16. An electronic device comprising: a power management integrated circuit configured to generate a second voltage from a first voltage received from an external source and output the second voltage; as well as a processor configured to receive a second voltage from a power management integrated circuit and access the power management integrated circuit through a general purpose input / output, Among them, the power management integrated circuit includes: a driver associated with the general purpose input / output and configured to output an output signal in response to an input signal; and a monitoring circuit configured to receive an input signal and an output signal and detect a stagnant voltage state of the output signal based on the input signal and the output signal, Therein, while the pin test is being performed by the monitoring circuit, the logic levels of the general purpose inputs / outputs are maintained without modification.

17. The electronic device according to claim 16, wherein: The monitoring circuit supports the Automotive Safety Integrity Level.

18. The electronic device according to claim 16, wherein: The electronic device is implemented by an in-vehicle infotainment system.

19. A method for monitoring an output signal of a driver, comprising: comparing an input signal and an output signal of the driver and detecting a stagnant voltage condition in response to the input signal and the output signal being logically incorrect; as well as The voltage of the output node is regulated when the input signal and the output signal are logically correct, and a stagnant voltage state is detected in response to the voltage of the output node not changing.

20. The method according to claim 19, wherein The steps of regulating the voltage of the output node when the input signal and the output signal are logically correct and detecting a stagnant voltage state in response to the voltage of the output node not changing include: When the output signal is at a logic low level, the voltage of the output node is increased; When the output signal is at a logic high level, reducing the voltage of the output node; and When increasing or decreasing the voltage of the output node, the logic level of the pin connected to the output node is maintained.

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