Technology and application of fast calculation of modular operations using Mersenne numbers or Fermat numbers

Abstract

The present invention discloses a technique and application for quickly calculating modular operations using Mersenne numbers or Fermat numbers. Various embodiments include a modular operation generator associated with a cache memory in a computer-based system. The modular operation generator generates a first sum by performing addition and / or subtraction operations on an input address. A first part of the first sum is applied to a lookup table that generates a correction value. The correction value is then added to a second part of the first sum to generate a second sum. The second sum is adjusted to be less than a divisor as needed. The adjusted second sum forms a residual value, which identifies a cache memory slice, and the input data value corresponding to the input address is stored in the cache memory slice. By generating the residual value in this manner, the cache memory can effectively distribute the input data value between the cache memory slices even if the number of memory slices is not a power of 2.

Description

[0001] Fields of various embodiments

[0002] Various embodiments relate generally to computer processing architecture and, more particularly, to techniques and applications for rapidly computing modular operations via Mersenne or Fermat numbers.

[0003] Related technical notes

[0004] Modulo operations, also referred to herein as "modulo operations," have various applications in computer-based systems. After dividing a first operand (referred to herein as the "dividend") by a second operand (referred to herein as the "divisor"), a value representing the difference, referred to herein as the "residual value," is generated. In this regard, 7 modulo 6 generates a value of 1, 7 modulo 7 generates a value of 0, 7 modulo 8 generates a value of 7, and so on. In one example application, modulo operations may be used to direct received data items to certain portions of cache memory in a computer system. Typically, cache memory is divided into a set of cache memory slices. Modulo operations are applied to two operands to determine the cache memory slice to be used to store, retrieve, or read a particular received data item. The dividend of the modulo operation is the cache memory slice of the received data item to be stored in the cache. The divisor of the modulo operation is the number of slices in the cache memory. The value generated by the modulo operation identifies the number of the cache memory slice to store, retrieve, or read the received data item from. This technique more or less evenly distributes the received data items among the cache memory slices.

[0005] The total number of cache slices is usually a power of 2, such as 8 or 16. In this case, the value of the modulo operation is the value represented by the last "x" bits of the received data item address, where "x" is a power of 2 corresponding to the number of cache slices. 3 =8 cache memory slices, the value generated by the modulo operation is the value represented by the last 3 bits of the address of the received data item. Similarly, if the cache memory is divided into 2 4 =16 cache memory slices, the value generated by the modulo operation is the value represented by the last 4 bits of the address of the received data item.

[0006] In some cases, the number of cache memory slices is not a power of 2. In one example, one of the cache memory slices in a cache memory manufactured from 16 cache memory slices may fail during the manufacturing process, for example, due to a manufacturing defect or later when the cache memory is installed in a computer system. By using modulo 15 operations to distribute data items among the remaining 15 cache memory slices, the cache can still be operated, albeit with reduced performance. In another example, a cache memory can be manufactured with 17 cache memory slices, so that if a cache memory slice fails, the cache memory will still have 16 cache memory slices. However, if all 17 cache memory slices are operational, modulo 17 operations can be used to distribute data items among the 17 cache memory slices.

[0007] A potential disadvantage of the above method for allocating data items in a cache memory is that the modular operation is significantly more complicated when the divisor is not a power of 2. Such modular operations typically involve executing multiple loops, wherein the multiple loops can be executed sequentially or concurrently. One loop sums the number of digits of the dividend, also referred to herein as "coefficients." The second loop repeatedly subtracts the divisor from the sum until the result is less than the divisor. When the divisor is a power of 2, the process of repeating the subtraction may take longer than performing the modular operation. In addition, as the value of the coefficient of the dividend increases, the time required to perform the modular operation also increases. This increase in the time required to perform the modular operation correspondingly increases the time between receiving the data item and storing the data item in the cache memory. As a result, when the number of functional slices in the cache memory is not a power of 2, the performance of the cache memory may be significantly reduced.

[0008] As previously stated, what is needed in the art is a more efficient technique for performing modular operations in computer-based systems. Summary of the invention

[0009] Various embodiments of the present disclosure set forth a computer-implemented method for performing a modular operation in a computer-based system. The method includes performing a first set of summations on input values ​​associated with the modular operation to generate a first sum. The method also includes accessing a correction value associated with a first portion of the first sum. The method also includes performing a second set of summations on the correction value and a second portion of the first sum to generate a second sum. The method also includes generating a result of the modular operation based on the second sum.

[0010] Other embodiments include, but are not limited to, systems implementing one or more aspects of the disclosed technology and one or more computer-readable media including instructions for performing one or more aspects of the disclosed technology.

[0011] At least one technical advantage of the disclosed technology over the prior art is that, using the disclosed technology, divisor operations involving non-powers of 2 are performed in a shorter time relative to modulo operations involving divisor operations that are powers of 2. In addition, regardless of the value of the dividend, as long as the divisor is not a power of 2, the modulo operation is performed in the same time. As a result, operations involving modulo operations, such as allocating data items between slices in a cache, can be performed more efficiently than in the prior art. More specifically, the performance of a cache memory including 15 slices or 17 slices can have the same or nearly the same performance as a cache memory including 16 slices. These advantages represent one or more technical improvements over prior art methods. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] In order that the manner in which the above-mentioned features of various embodiments may be understood in detail, the inventive concept briefly summarized above may be described in more detail by reference to various embodiments, some of which are shown in the accompanying drawings. However, it should be noted that the drawings only show typical embodiments of the inventive concept and therefore should not be considered in any way to limit the scope, and there are other equally effective embodiments.

[0013] Figure 1 is a block diagram of a computer system configured to implement one or more aspects of various embodiments;

[0014] Figure 2 According to various embodiments, the Figure 1 A block diagram of a parallel processing unit (PPU) in a parallel processing subsystem of FIG.

[0015] Figure 3 According to various embodiments, the Figure 2 A block diagram of a general processing cluster in a parallel processing unit of;

[0016] Figure 4 According to various embodiments, it can be configured to implement Figure 2 A conceptual diagram of a modulo-15 operation generator of a parallel processing unit;

[0017] Figure 5 According to various embodiments, it can be configured to implement Figure 2 A conceptual diagram of a modulo-17 operation generator of a parallel processing unit;

[0018] Figure 6A-6B The invention describes various embodiments Figure 2 A conceptual diagram of a modulo 3 / 15 operation generator that the parallel processing unit may be configured to implement;

[0019] Figure 7According to various embodiments, Figure 2 A flowchart of the method steps for performing modular operations with a parallel processing unit.

[0020] Detailed description

[0021] In the following description, numerous specific details are set forth to provide a more thorough understanding of various embodiments. However, it will be apparent to one skilled in the art that the inventive concept may be practiced without one or more of these specific details.

[0022] System Overview

[0023] Figure 1 1 is a block diagram of a computer system 100 configured to implement one or more aspects of various embodiments. As shown, computer system 100 includes, but is not limited to, a central processing unit (CPU) 102 and a system memory 104 coupled to a parallel processing subsystem 112 via a memory bridge 105 and a communication path 113. Memory bridge 105 is also coupled to an I / O (input / output) bridge 107 via a communication path 106, and I / O bridge 107 is in turn coupled to a switch 116.

[0024] In one embodiment, I / O bridge 107 is configured to receive user input information from an optional input device 508, such as a keyboard or mouse, and forward the input information to CPU 102 for processing via communication path 106 and memory bridge 105. In one embodiment, switch 116 is configured to provide connections between I / O bridge 107 and other components of computer system 100, such as network adapter 118 and various add-in cards 120 and 121.

[0025] As shown, I / O bridge 107 is coupled to system disk 114, which can be configured to store content and applications and data for use by CPU 102 and parallel processing subsystem 112. In general, system disk 114 provides non-volatile storage for applications and data, and can include fixed or removable hard disk drives, flash memory devices, and CD-ROM (Compact Disc Read Only Memory), DVD-ROM (Digital Versatile Disc-ROM), Blu-ray, HD-DVD (High Definition DVD) or other magnetic, optical or solid state storage devices. Finally, although not explicitly shown, other components such as universal serial bus or other port connections, optical disk drives, digital versatile disk drives, film recording devices, etc. can also be connected to I / O bridge 107.

[0026] In various embodiments, memory bridge 105 may be a northbridge chip, and I / O bridge 107 may be a southbridge chip. Additionally, communication paths 106 and 113, as well as other communication paths within computer system 100, may be implemented using any technically suitable protocol, including but not limited to AGP (Accelerated Graphics Port), HyperTransport, or any other bus or point communication protocol known in the art.

[0027] In some embodiments, parallel processing subsystem 112 includes a graphics subsystem that transmits pixels to optional display device 110, which can be any conventional cathode ray tube, liquid crystal display, light emitting diode display, etc. In such embodiments, parallel processing subsystem 112 includes circuits optimized for graphics and video processing, including, for example, video output circuits. Figure 2 As shown, such circuitry may be incorporated across one or more parallel processing units (PPUs) included within parallel processing subsystem 112. In other embodiments, parallel processing subsystem 112 includes circuitry optimized for general purpose and / or computational processing. Again, such circuitry may be incorporated into one or more PPUs included within parallel processing subsystem 112, which are configured to perform such general purpose and / or computational operations. In other embodiments, one or more PPUs included in parallel processing subsystem 112 may be configured to perform graphics processing, general purpose processing, and computational processing operations. System memory 104 includes at least one device driver configured to manage processing operations of one or more PPUs within parallel processing subsystem 112.

[0028] In various embodiments, the parallel processing subsystem 112 may be coupled to Figure 1 The parallel processing subsystem 112 may be integrated with one or more other components of the CPU 102 to form a single system. For example, the parallel processing subsystem 112 may be integrated with the CPU 102 and other connecting circuits on a single chip to form a system on a chip (SoC).

[0029] It should be understood that the system shown herein is illustrative and that variations and modifications are possible. The connection topology, including the number and arrangement of bridges, the number of CPUs 102, and the number of parallel processing subsystems 112, may be modified as desired. For example, in some embodiments, system memory 104 may be connected to CPU 102 directly rather than through memory bridge 105, and other devices will communicate with system memory 104 through memory bridge 105 and CPU 102. In other embodiments, parallel processing subsystem 112 may connect it to I / O bridge 107 or directly to CPU 102 rather than to memory bridge 105. In other embodiments, I / O bridge 107 and memory bridge 105 may be integrated into a single chip rather than existing in the form of one or more discrete devices. Finally, in some embodiments, there may be no parallel processing subsystems 112. Figure 1 For example, switch 116 could be omitted, and network adapter 118 and add-in cards 120 , 121 would connect directly to I / O bridge 107 .

[0030] Figure 2 According to various embodiments, the Figure 1 1. Although Figure 2 One PPU 202 is depicted, but as described above, the parallel processing subsystem 112 may include any number of PPUs 202. As shown, the PPU 202 is coupled to a local parallel processing (PP) memory 204. The PPU 202 and the PP memory 204 may be implemented using one or more integrated circuit devices (e.g., a programmable processor, an application specific integrated circuit (ASIC), or a memory device) or in any other technically feasible manner.

[0031] In some embodiments, PPU 202 includes a graphics processing unit (GPU) that can be configured to implement a graphics rendering pipeline to perform various operations related to generating pixel data based on graphics data provided by CPU 102 and / or system memory 104. When processing graphics data, PP memory 204 can be used as a graphics memory to store one or more conventional frame buffers and, if necessary, one or more other rendering targets. Among them, PP memory 204 can be used to store and update pixel data, and transmit the final pixel data or display frame to an optional display device 110 for display. In some embodiments, PPU 202 can also be configured for general processing and computing operations. In some embodiments, computer system 100 can be a server machine in a cloud computing environment.

[0032] In operation, CPU 102 is the main processor of computer system 100, which controls and coordinates the operation of other system components. In particular, CPU 102 issues commands that control the operation of PPU 202. In some embodiments, CPU 102 writes a command stream for PPU 202 to a data structure (in a memory) that can be located in system memory 104, PP memory 204, or other storage location accessible to both CPU 102 and PPU 202. Figure 1 or Figure 2 The push buffer 202 may be used to execute commands asynchronously with respect to the operation of the CPU 102. In an embodiment where multiple push buffers are generated, the application may specify an execution priority for each push buffer through the device driver 103 to control the scheduling of different push buffers.

[0033] As shown, PPU 202 includes an I / O (input / output) unit 205 that communicates with the rest of computer system 100 via communication path 113 and memory bridge 105. I / O unit 205 generates data packets (or other signals) for transmission on communication path 113, and also receives all incoming data packets (or other signals) from communication path 113, thereby directing the incoming packets to the appropriate components of PPU 202. For example, commands related to processing tasks can be directed to host interface 206, while commands related to memory operations (e.g., reads or writes from PP memory 204) are directed to crossbar unit 210. Host interface 206 reads each push buffer and sends the command stream stored in the push buffer to front end 212.

[0034] As above combined Figure 1 As described above, the connection of PPU 202 to the rest of computer system 100 may vary. In some embodiments, parallel processing subsystem 112 including at least one PPU 202 is implemented as an add-in card that can be inserted into an expansion slot of computer system 100. In other embodiments, PPU 202 may be integrated on a single chip with a bus bridge (e.g., memory bridge 105 or I / O bridge 107). Likewise, in other embodiments, some or all elements of PPU 202 may be included with CPU 102 in a single integrated circuit or system on a chip (SoC).

[0035] In one operation, the front end 212 sends the processing tasks received from the host interface 206 to the work distribution unit (not shown) within the task / work unit 207. The work distribution unit receives a pointer to the encoded processing task as task metadata (TMD) and stores it in memory. The pointer to the TMD is contained in a command stream, which is stored as a command queue and received by the front end unit 212 from the host interface 206. The processing task that can be encoded as a TMD also includes an index associated with the data to be processed as a state parameter and command that defines how to process the data. For example, the state parameter and command can define a program to be executed on the data. The task / work unit 207 receives tasks from the front end 212 and ensures that the GPC 208 is configured to a valid state before starting the processing task specified by each TMD. A priority can be specified for each TMD, which is used to schedule the execution of the processing task. The processing task can also be received from the processing cluster array 230. Optionally, the TMD may include a parameter that controls whether the TMD is added to the head or tail of a list of processing tasks (or a list of pointers to processing tasks), thereby providing another level of control over execution priority.

[0036] PPU 202 conveniently implements a highly parallel processing architecture based on a processing cluster array 230, which includes a set of C general processing clusters (GPCs) 208, where C ≥ 1. Each GPC 208 is capable of executing a large number of concurrent threads (e.g., hundreds or thousands), where each thread is an instance of a program. In various applications, different GPCs 208 can be assigned to process different types of programs or to perform different types of calculations. The allocation of GPCs 208 can vary depending on the workload generated by each type of program or calculation.

[0037] The memory interface 214 includes a set of D partition units 215, where D ≥ 1. Each partition unit 215 is coupled to one or more dynamic random access memories (DRAMs) 220 residing within the PPM memory 204. In one embodiment, the number of partition units 215 is equal to the number of DRAMs 220, and each partition unit 215 is coupled to a different DRAM 220. In other embodiments, the number of partition units 215 may be different from the number of DRAMs 220. It will be appreciated by those of ordinary skill in the art that the DRAMs 220 may be replaced with any other technically suitable storage device. In operation, various rendering targets, such as texture maps and frame buffers, may be stored on the DRAMs 220, thereby allowing the partition units 215 to write portions of each rendering target in parallel to efficiently use the available bandwidth of the PP memory 204.

[0038] A given GPC 208 may process data to be written to any DRAM 220 in PP memory 204. Crossbar unit 210 is configured to route the output of each GPC 208 to the input partition unit 215 of any GPC 208 or to any other GPC 208 for further processing. GPCs 208 communicate with memory interface 214 via crossbar unit 210 to read or write to the various DRAMs 220. In one embodiment, crossbar unit 210 has connections to I / O unit 205 in addition to connections to PP memory 204 via memory interface 214, thereby enabling processing cores in different GPCs 208 to communicate with system memory 104 or other memory that is not local to PPU 202. In Figure 2 In the embodiment of FIG. 2 , the crossbar unit 210 is directly connected to the I / O unit 205. The crossbar unit 210 can use virtual channels to separate the traffic flows between the GPCs 208 and the partition units 215.

[0039] Again, the GPCs 208 may be programmed to perform processing tasks associated with a wide variety of applications, including, but not limited to, linear and nonlinear data transformations, filtering of video and / or audio data, modeling operations (e.g., applying physical laws that determine the position, velocity, and other properties of an object), image rendering operations (e.g., tessellation shader, vertex shader, geometry shader, and / or pixel / fragment shader programs), general computational operations, etc. In operation, the PPU 202 is configured to transfer data from the system memory 104 and / or the PP memory 204 to one or more on-chip memory units, process the data, and write the resulting data back to the system memory 104 and / or the PP memory 204. The resulting data may then be accessed by other system components, including the CPU 102, another PPU 202 in the parallel processing subsystem 112, or another parallel processing subsystem 112 in the computer system 100.

[0040] As described above, any number of PPUs 202 may be included in the parallel processing subsystem 112. For example, multiple PPUs 202 may be provided on a single plug-in card, or multiple plug-in cards may be connected to the communication path 113, or one or more of the PPUs 202 may be integrated into a bridge chip. The PPUs 202 in a multi-PPU system may be the same or different from each other. For example, different PPUs 202 may have different numbers of processing cores and / or different numbers of PP memories 204. In implementations where there are multiple PPUs 202, these PPUs may run in parallel to process data at a higher throughput than a single PPU could process. Systems containing one or more PPUs 202 may be implemented in a variety of configurations and forms, including but not limited to desktops, laptops, handheld personal computers or other handheld devices, servers, workstations, game consoles, embedded systems, and the like.

[0041] Figure 3 According to various embodiments, the Figure 2 A block diagram of a general processing cluster (GPC) 208 in a parallel processing unit (PPU) 202 of a processor. In operation, GPC 208 can be configured to execute a large number of threads in parallel to perform graphics, general processing and / or computing operations. As used herein, "thread" refers to an instance of a specific program executed on a specific set of input data. In some embodiments, single instruction multiple data (SIMD) instruction issuance technology is used to support the parallel execution of a large number of threads without providing multiple independent instruction units. In other embodiments, single instruction multiple thread (SIMT) technology is used to support the parallel execution of a large number of generally synchronized threads by using a general instruction unit configured to issue instructions to a group of processing engines in GPC 208. Under an execution mechanism in which all processing engines generally execute the same instructions, SIMT execution allows different threads to more easily follow different execution paths through a given program. It will be understood by those of ordinary skill in the art that the SIMD processing scheme represents a functional subset of the SIMT processing scheme.

[0042] The operation of GPC 208 is controlled by pipeline manager 305, which distributes processing tasks received from a work distribution unit (not shown) within task / work unit 207 to one or more streaming multiprocessors (SMs) 310. Pipeline manager 305 may also be configured to control work distribution crossbar 330 by specifying the destination of processed data output by SM 310.

[0043] In one embodiment, the GPC 208 includes a group of M SMs 310, where M ≥ 1. Furthermore, each SM 310 includes a group of function execution units (not shown), such as execution units and load-store units. Processing operations for any function execution unit can be pipelined, which enables a new instruction to be issued for execution before the previous instruction has completed execution. Any combination of function execution units within a given SM 310 can be provided. In various embodiments, the function execution units can be configured to support a variety of different operations, including integer and floating point arithmetic (e.g., addition and multiplication), comparison operations, Boolean operations (AND, OR, XOR), bit-shifts, and various algebraic functions (e.g., planar interpolation and trigonometric functions, exponential functions and logarithmic functions, etc.). Advantageously, the same function execution unit can be configured to perform different operations.

[0044] In operation, each SM 310 is configured to process one or more thread groups. As used herein, a "thread group" or "thread bundle" refers to a group of threads that execute the same program simultaneously on different input data, and a thread in the group is assigned to a different execution unit within the SM 310. The number of threads included may be less than the number of execution units in the SM 310, in which case some executions may be idle during the cycle processing the thread group. The thread group may also include more threads than the number of execution units in the SM 310, in which case processing can be performed in consecutive clock cycles. Since each SM 310 can support up to G thread groups simultaneously, up to G*M thread groups can be executed in the GPC 208 at any given time.

[0045] In addition, multiple related thread groups may be simultaneously active (in different stages of execution) in SM 310. Such a collection of thread groups is referred to herein as a "cooperative thread array" ("CTA") or "thread array." The size of a particular CTA is equal to m*k, where k is the number of threads executing simultaneously in the thread group, typically an integer multiple of the number of execution units in SM 310, and m is the number of simultaneously active thread groups in SM 310.

[0046] Although Figure 3Not shown, each SM 310 contains a level 1 (L1) cache, or uses space in a corresponding L1 cache external to the SM 310 to support (among other things) load and store operations performed by the execution units. Each SM 310 may also access a level 2 (L2) cache (not shown) that is shared among all GPCs 208 in the PPU 202. The L2 cache may be used to transfer data between threads. Finally, the SM 310 may also access off-chip "global" memory, which may include PP memory 604 and / or system memory 104. It should be understood that any memory external to the PPU 202 may be used as global memory. In addition, as shown in FIG. Figure 3 As shown, a level 1.5 (L1.5) cache (335) may be included in GPC 208 and configured to receive and store data requested by SM 310 from memory via memory interface 214. This data includes, but is not limited to, instructions, uniform data, and constant data. In embodiments having multiple SMs 310 within GPC 6208, SMs 310 may beneficially share common instructions and data cached in L1.5 cache 335.

[0047] Each GPC 208 may have an associated memory management unit (MMU) 320 that is configured to map virtual addresses to physical addresses. In various embodiments, the MMU 320 may reside within the GPC 208 or within the memory interface 214. The MMU 320 includes a set of page table entries (PTEs) that are used to map virtual addresses to physical addresses of tiles or memory pages, and optionally cache line indexes. The MMU 320 may include an address translation lookaside buffer (TLB) or may reside within the SM 310, within one or more L1 caches, or within the GPC 208.

[0048] In graphics and compute applications, GPC 208 may be configured such that each SM 310 is coupled to a texture unit 315 that, among other things, performs texture map loads and texture operations such as determining texture sample locations, reading texture data, and filtering texture data.

[0049] In operation, each SM 310 sends processed tasks to the work distribution crossbar 330 to provide the processed tasks to another GPC 208 for further processing or store the processed tasks in an L2 cache (not shown), parallel processing memory 204, or system memory 104 via the crossbar unit 210. In addition, a pre-raster operation (preROP) unit 325 is configured to receive data from the SM 310, direct the data to one or more raster operation (ROP) units within the partition unit 215 to perform color blending optimization, organize pixel color data, and perform address translation.

[0050] It will be appreciated that the core architecture described herein is illustrative and that variations and modifications are possible. Among other things, any number of processing units may be included within GPC 608, such as SM 310, texture unit 315, or pre-raster operation unit 325. In addition, as described above in conjunction with Figure 2 As described above, the PPU 202 may include any number of GPCs 208 configured to be functionally similar to one another so that execution behavior does not depend on which GPC 208 receives a particular processing task. In addition, each GPC 208 operates independently of the other GPCs 208 in the PPU 202 to execute tasks for one or more applications. In view of the above, one of ordinary skill in the art will appreciate that Figure 1-3 The architecture described in no way limits the scope of the present disclosure.

[0051] In some embodiments, one or more of the SMs 310 may include a modulo operation generator (mod op gen) 312. As further described herein, when an SM 310 executes a modulo instruction involving a divisor supported by the modulo operation generator 312, the SM 310 may route the modulo operation through the modulo operation generator 312 to generate a residual value with improved performance relative to the prior art. Additionally, in some embodiments, the MMU 320 includes or is associated with a modulo operation generator 322. The modulo operation generator 322 performs a modulo operation on a memory address of an input value, where the divisor of the modulo is a slice number. The residual value of the modulo operation identifies a cache memory slice to store the input value.

[0052] Note that, as used herein, references to shared memory may include any one or more technically feasible memories, including but not limited to local memory shared by one or more SMs 310 or memory accessible via memory interface 214, such as cache, parallel processing memory 204, or system memory 104. Note also that, as used herein, references to cache memory may include any one or more technically feasible memories, including but not limited to a level 1 cache, a level 1.5 cache, and a level 2 cache.

[0053] The image generated by applying one or more of the techniques disclosed herein can be displayed on a monitor or other display device. In some embodiments, the display device can be directly coupled to the system or processor that generates or renders the image. In other embodiments, the display device can be indirectly coupled to the system or processor, for example, via a network. Examples of such networks include the Internet, mobile telecommunications networks, WIFI networks, and any other wired and / or wireless networking systems, etc. When the display device is indirectly coupled, the image generated by the system or processor can be streamed to the display device via a network. This streaming allows, for example, a video game or other application that renders an image to be executed on a server or in a data center, and the rendered image can be transmitted and displayed on one or more user devices (e.g., computers, video game consoles, smartphones, other mobile devices, etc.), which are physically separated from the server or data center. Therefore, the technology disclosed herein can be applied to enhance streaming images and enhance streaming image services, such as NVIDIA GeForce Now (GFN), Google Stadia, etc.

[0054] In addition, images generated using one or more of the techniques disclosed herein can be used to train, test, or verify deep neural networks (DNNs) used to recognize objects and environments in the real world. Such images can include scenes of roads, factories, buildings, urban environments, rural environments, humans, animals, and any other physical objects or real-world scenes. Such images can be used to train, test, or verify DNNs used in machines or robots to manipulate, process, or modify physical objects in the real world. In addition, such images can be used to train, test, or verify DNNs used in autonomous vehicles to navigate and move vehicles in the real world. In addition, images generated using one or more of the techniques disclosed herein can be used to convey information to users of these machines, robots, and vehicles.

[0055] Fast residual calculation for modular arithmetic

[0056] As described herein, a conventional method for calculating the result of a modular operation involves executing multiple loops, which may be executed sequentially or concurrently. One loop sums the number of digits of the dividend, also referred to herein as the "coefficient." A second loop repeatedly subtracts the divisor from the sum until the result is less than the divisor. When the divisor is a power of 2, this process of repeatedly performing subtractions may take longer than performing the modular operation.

[0057] Various embodiments include a modular operation generator in a computer-based system that performs modular operations in less time relative to these traditional methods. The modular operation generator includes an accumulation circuit that performs a first set of summations on input values ​​to generate a first sum. The first set of summations may include an addition function and / or a subtraction function. The modular operation generator also includes a lookup and correction circuit that includes a lookup table and an adder. A first portion of the first sum is applied to a lookup table that generates a correction value. The adder performs a second set of summations on the correction value and a second portion of the first sum to generate a second sum. The modular operation generator also includes a test and correction circuit that adjusts the second sum if the second sum is greater than or equal to a divisor of the modular operation generator. The test and correction circuit transmits the final residual value determined by the modular operation generator.

[0058] One use case of a modulo operation generator is to determine which cache slice receives a particular input value. Typically, an MMU (e.g., MMU 320) includes or is associated with cache control logic having a modulo operation generator such as modulo operation generator 322. Such cache control logic performs a modulo operation on the memory address of the input value, the divisor of the modulo operation being the number of slices. The residual value of the modulo operation identifies the cache memory slice in which the input value is to be stored. For cache memories where the number of cache memory slices is a power of 2, the residual value of the modulo operation is simply the least significant n bits of the memory address. If the number of cache memory slices is not a power of 2, the residual value is performed by performing sequential or concurrent loop operations. This approach can be time consuming, thereby reducing the performance of the cache memory. Using the method disclosed herein, the modulo operation generator does not perform loop operations. Instead, the modulo operation generator only generates logic delays at various stages of the modulo operation generator. If the logic delay through the modulo operation generator is less than the clock cycle of the MMU, the residual value can be determined within one clock cycle. In one example, the modular operation generator can calculate the residual value at a 2.14 GHz clock rate in one clock cycle with sufficient margin.

[0059] Another use case of the modular operation generator is in an arithmetic logic unit (ALU) of a processor (e.g., a GPU or a CPU). In some embodiments, one or more SMs 310 may include a modular operation generator 322. When performing a modular operation, the ALU may be configured to automatically detect a modular operation generator using the disclosed technology, which may be used for the divisor of the modular operation. If such a modular operation generator exists, the processor will route the modular operation through the modular operation generator to generate the residual value with improved performance relative to the prior art. Additionally or alternatively, the instruction set of the processor may include one or more special instructions for accelerating modular operations. When the processor executes such an instruction, the processor routes the modular operation through the modular operation generator to generate the residual value with improved performance relative to the prior art.

[0060] In some embodiments, the modular operation generator performs a modular operation with a divisor being a Mersenne number. The Mersenne number is of the form M=2 n -1, where n is an integer. A subset of Mersenne numbers (referred to herein as "Mersenne primes") is of the form M = 2 n -1, and its additional property is that n is prime. When n = 2, 3, 4 or 5, the corresponding Mersenne numbers are 3, 7, 15 and 31. Among these Mersenne numbers, 3, 7 and 31 are Mersenne primes, while 15 is not a Mersenne prime.

[0061] In one example, the modular operation generator performs a modulo 15 operation on an input value represented in base 16, also referred to herein as a "hexadecimal" format. In base 16 format, each digit represents a 4-bit number in the range of 0 to 15. For a given number "N" with a width of "w" bits, a coefficient "W" can be calculated for a given Mersenne divisor. Based on the selected Mersenne divisor, there is a strong relationship between W and w. For a given Mersenne divisor "M", the number of bits of each coefficient "b" is determined by b and b=int(log2(M))+1. For example, if M=15, then b=4, indicating that a Mersenne divisor of 15 results in a 4-bit coefficient. To determine the numerical value of the coefficient W, w is divided by b as follows: W=(int(w / b)!=w / b)? int(w / b)+1:int(w / b). For example, if the width w of the number N is 32 bits and the Mersenne divisor M is 15, then b is 4 bits and W=int(32 / 4)=8. Similarly, if the width w of the number N is 31 bits and the Mersenne divisor M is 15, then b is 4 bits and W=int(31 / 4)+1=8. Furthermore, if the width w of the number N is 33 bits and the Mersenne divisor M is 15, then b is a 4-bit number and W=int(33 / 4)=9.

[0062] In general, any integer N with base 16 bits in W can be represented in base 16 format as shown in Formula 1 below:

[0063]

[0064] Where W is the number of digits in base 16, (q 16 ,n) are the base 16 coefficients of the number n, and N is the number represented. A 32-bit number N represented in base 16 format has W = 32 bits ÷ 4 bits / number = 8 bits. To determine the residual value from the modulo 15 operation, and noting that 15 = 16-1, the multiplier of Formula 1 can be rewritten to yield Formula 2 as follows:

[0065]

[0066] The multiplier of Formula 1 can be converted through binomial expansion, resulting in Formula 3 as follows:

[0067]

[0068] where (Ck, n) is the binomial (15+1) n The expanded result of , and N is the number represented by the representation. Given Equation 3, for each value of n from 0 to W-1, the expression in the square brackets is the sum of products. Each of these sums has n+1 terms (for k=0 to k=n). The only term in each sum is (q 16,n )*C k,n *15 k Each of these terms is a power of 15 and therefore does not contribute to the residual value except for k=0. For k=0, the term is (q 16,n )*C 0,n *15 0 . Assume that each C 0,n Multiply by 15 0 If it is equal to 1, then Formula 3 can be rewritten to obtain Formula 4 as follows:

[0069]

[0070] The sum of the addends on the right is multiplied by 15 k , where k is an integer greater than or equal to 1. Therefore, all terms of the summation operation and the result of the summation operation are multiples of 15. Because the result of the modulo generator whose dividend is a multiple of the divisor is 0, the right-hand addend of Formula 4 does not affect the residual value. Therefore, only the left-hand addend of Formula 4 affects the residual value. This left-hand addend is referred to herein as the coefficient sum S c , as shown in the following formula 5:

[0071]

[0072] The sum shown in Formula 5 represents the sum of coefficients in base 16. Although the coefficient sum is the only contributor to the final residual value of the modular operation, the coefficient sum may be greater than 15. Therefore, the coefficient sum is processed to generate a final residual value less than 15. The disclosed modular operation generator is now described, and the disclosed modular operation generator determines the coefficients and processes the coefficient sum to generate the final residual value.

[0073] Figure 4 According to various embodiments Figure 2 A conceptual diagram of a modulo 15 operation generator that can be configured to implement a parallel processing unit. In some embodiments, the modulo 15 operation generator can be implemented as Figure 3 A portion of the modular operation generator 312 and / or is implemented as Figure 3 As shown, the modular generator includes an accumulation circuit 410, a lookup and correction circuit 420, and a test and correction circuit 430. The modular 15 generator utilizes the fact that 15 is a Mersenne number, where 15=16-1. Therefore, the input value is represented in base 16 format. As a result, each coefficient of the input value is a 4-bit number when represented in hexadecimal format.

[0074] In operation, the accumulation circuit 410 performs a summation operation on the base 16 coefficients of the input values ​​to generate the coefficient sum Because the input value is a 32-bit number, the accumulation circuit 410 performs a summation operation on the eight 4-bit coefficients. The accumulation circuit 410 adds the coefficients through a series of stages. The first stage includes adders 412(0), 412(1), 412(2), and 412(3). The second stage includes adders 414(0) and 414(1). The third stage includes adder 416.

[0075] In the first stage, adder 412(0) generates the sum of coefficients of W=0 (bits [03:00]) and W=1 (bits [04:07]). Similarly, adder 412(1) generates the sum of coefficients of W=2 (bits [11:08]) and W=3 (bits [15:12]). Adder 412(2) generates the sum of coefficients of W=4 (bits [19:16]) and W=5 (bits [23:20]). Adder 412(3) generates the sum of coefficients of W=6 (bits [27:24]) and W=7 (bits [31:28]). In the second stage, adder 414(0) generates the sum of the output of adder 412(0) and the output of adder 412(1). Similarly, adder 414(1) generates the sum of the output of adder 412(2) and the output of adder 412(3). In the third stage, adder 416 generates the sum of the output of adder 414(0) and the output of adder 414(1).

[0076] Adding two 4-bit numbers may result in a sum greater than 15, the maximum value that can be represented by a 4-bit number. Therefore, each adder 412(0), 412(1), 412(2) and 412(3) generates a sum including the fifth bit, referred to herein as the "guard bit". Similarly, adding two 5-bit numbers may result in a sum greater than 31, the maximum value that can be represented by a 5-bit number. Therefore, each adder 414(0) and 414(1) generates a sum including the sixth bit, representing the second guard bit. Adding two 6-bit numbers may result in a sum greater than 63, the maximum value that can be represented by a 6-bit number. Therefore, adder 416 generates a sum of the seventh bit, representing the third guard bit. The accumulator circuit 410 generates Sum[6:0] (sum [6:0]), which includes the 4-bit low-order portion Sum[3:0] and the 3-bit guard bit Sum[6:4]. The accumulation circuit 410 sends Sum[6:0] to the lookup and correction circuit 420 .

[0077] More generally, the number of adders, stages, and guard bits included in the accumulator circuit 410 depends on the number and width of the input value coefficients. For an input value having W coefficients and represented in a particular radix format, the number of guard bits added in the accumulator circuit 410 is log2(W / log2(radix)).

[0078] In operation, the search and correction circuit 420 receives Sum[6:0] from the accumulation circuit 410. The search and correction circuit 420 separates Sum[6:0] into two components. The first component Sum[3:0] includes the least significant bits of Sum[6:0] and has the same width as the coefficients of the input value. Because the input value is represented in base 16, each coefficient of the input value is a 4-bit number. Therefore, the first component Sum[3:0] includes the 4 least significant bits of Sum[6:0]. The second component Sum[6:4] includes the most significant bits of Sum[6:0]. The second component Sum[6:4] represents the value of the guard bit generated by the adder of the accumulation circuit 410.

[0079] The lookup and correction circuit 420 routes the first component Sum[3:0] to an adder 424. The lookup and correction circuit 420 routes the second component Sum[6:4] to a lookup table 422. The value of Sum[6:4] represents the multiple of 16 contained in Sum[6:0]. For example, Sum[6:4]=001 represents the value 16, Sum[6:4]=010 represents the value 32, Sum[6:4]=011 represents the value 48, and so on. In order to generate a residual value modulo 15, the number 15 must be subtracted from Sum[6:0] until the residual value is in the range of 0 to 14. Because the modulo divisor of 15 is a Mersenne number, the modulo divisor can be written as 16-1. Therefore, subtracting 15 from Sum[6:0] is equal to subtracting 16 and adding 1. Subtracting 30 from Sum[6:0] is equal to subtracting 32 and adding 2. Subtracting 45 from Sum[6:0] is equal to subtracting 48 and adding 3, and so on. The lookup table 422 performs this function by receiving the second component Sum[6:4], which is a multiple of 16, and generating a Correction[3:0], which represents the number to be added to the first component Sum[3:0]. The correction values ​​for various input values ​​are shown in Table 1 below.

[0080] Sum[6:4] Subtracted value Increased value Correction[3:0] 000 0 0 0000 001 16 1 0001 010 32 2 0010 011 48 3 0011 100 64 4 0100 101 80 5 0101 110 96 6 0110 111 112 7 0111

[0081] Table 1: Correction values ​​for the modulo 15 generator

[0082] For a modulo 15 generator and a 32-bit input value, the width of the input Sum[6:4] is 3 bits. The number of entries in the lookup table 422 (referred to herein as the "depth") is 8, and the width of the output Correction[3:0] is 4 bits. The range of the output Correction[3:0] is 0 to 7. More generally, the depth of the lookup table 422 is: Depth = w ÷ (log2(radix)), where "w" is the width of the input value expressed in bits. The width of the correction output of the lookup table 422 is: Width = log2(radix).

[0083] The lookup table 422 transmits Correction[3:0] to the adder 424. The adder 424 adds the first component Sum[3:0] to Correction[3:0] to generate a preliminary residual value. The adder 424 sends the preliminary residual value to the test and correction circuit 430.

[0084] In operation, if the preliminary residual value is greater than 15, the test and correction circuit 430 will perform a final correction. The first component Sum[3:0] ranges from 0 to 15, while the Correction[3:0] ranges from 0 to 7. Therefore, the preliminary residual value generated by the adder 424 is a 5-bit value ranging from 0 to 23. The final adjustment 432 tests the preliminary residual value to determine whether the preliminary residual value is less than 15. If the preliminary residual value is less than 15, the final adjustment 432 uses the least significant 4 bits of the preliminary residual value as the final Residue[3:0]. However, if the preliminary residual value is greater than or equal to 15, the final adjustment 432 subtracts 15 from the preliminary residual value to generate the final Residue[3:0].

[0085] Within the scope of the present disclosure, the disclosed techniques may be further applied to certain modular operations where the divisor is not a Mersenne number. For example, the disclosed techniques may be further applied to certain modular operations where the divisor is a Fermat number. As referred to herein, a Fermat number is of the form F=2 n +1, where n is an integer. For n = 2, 3, 4 or 5, the corresponding Fermat numbers are 5, 9, 17 and 33 respectively.

[0086] Figure 5 According to various embodiments Figure 2 A conceptual diagram of a modular 17 operation generator that can be configured to implement a parallel processing unit. In some embodiments, the modular 17 operation generator can be implemented as Figure 3 A portion of the modular operation generator 312, and / or may be implemented as Figure 3As shown in the figure, the modular operation generator includes an accumulation circuit 510, a search and correction circuit 520, and a test and correction circuit 530. The functions of the accumulation circuit 510, the search and correction circuit 520, and the test and correction circuit 530 are substantially the same as those of the accumulation circuit 410, the search and correction circuit 420, and the test and correction circuit 530, except as further described below, they are respectively Figure 4 The correction circuit 430 of is the same as the correction circuit 430. The modulo 17 operation generator utilizes the fact that 17 is a Fermat number, where 17=16+1. Therefore, the input value is represented in base 16 format. As a result, each coefficient of the input value is a 4-bit number when represented in base 16 format.

[0087] In operation, the accumulation circuit 510 adds together the base 16 coefficients of the input values ​​to generate the coefficient sum Said-1 n The term comes from the fact that the divisor of the modulus is a Fermat number rather than a Mersenne number. Therefore, the coefficients of the even values ​​of W are added, while the coefficients of the odd values ​​of W are subtracted. Because the input value is a 32-bit number, the accumulator circuit 510 performs a summation operation on the eight 4-bit coefficients. The accumulator circuit 510 performs a summation operation on the coefficients via a series of stages. The first stage includes subtractors 512(0), 512(1), 512(2), and 512(3). The second stage includes adders 514(0) and 514(1). The third stage includes adder 516.

[0088] In the first stage, subtractor 512(0) generates the difference between the coefficient W=0 ([03:00] bits) and the coefficient W=1 ([04:07] bits). Similarly, subtractor 512(1) generates the difference between the coefficient W=2 ([11:08] bits) and the coefficient W=3 ([15:12] bits). Subtractor 512(2) generates the difference between the coefficient W=4 ([19:16] bits) and the coefficient W=5 ([23:20] bits). Subtractor 512(3) generates the difference between the coefficient W=6 ([27:24] bits) and the coefficient W=7 ([31:28] bits). In the second stage, adder 514(0) generates the sum of the output of subtractor 512(0) and the output of subtractor 512(1). Similarly, adder 514(1) generates the sum of the output of subtractor 512(2) and the output of subtractor 512(3). In the third stage, adder 516 generates the sum of the output of adder 514(0) and the output of adder 514(1). The accumulation circuit 510 generates Sum[6:0], which includes the low-order portion of the 4-bit Sum[3:0] and the 3 guard bits of Sum[6:4]. The accumulation circuit 510 sends Sum[6:0] to the lookup and correction circuit 520. More generally, the number of subtractors, adders, stages, and guard bits included in the accumulation circuit 510 depends on the number and width of the input value coefficients.

[0089] In operation, the lookup and correction circuit 520 receives Sum[6:0] from the accumulation circuit 510. The lookup and correction circuit 520 separates Sum[6:0] into two components. The first component Sum[3:0] includes the least significant bits of Sum[6:0] and is the same as the coefficients of the width and input value. Because the input value is represented in base 16, each coefficient of the input value is a 4-bit number. Therefore, the first component Sum[3:0] includes the 4 least significant bits of Sum[6:0]. The second component Sum[6:4] includes the most significant bits of Sum[6:0]. The second component Sum[6:4] represents the value of the guard bit generated by the adder of the accumulation circuit 510.

[0090] The lookup and correction circuit 520 routes the first component Sum[3:0] to a subtractor 524. The lookup and correction circuit 520 routes the second component Sum[6:4] to a lookup table 522. The value of Sum[6:4] represents a multiple of 16 contained in Sum[6:0]. For example, Sum[6:4]=001 represents the value 16, Sum[6:4]=010 represents the value 32, Sum[6:4]=011 represents the value 48, and so on. In order to generate a modulo 17 residual value, the number 17 must be subtracted from Sum[6:0] until the residual value is in the range of 0 to 16. Because the modulo divisor of 17 is a Fermat number, the modulo divisor can be written as 16+1. Therefore, subtracting 17 from Sum[6:0] is equal to subtracting 16 and then subtracting 1. Subtracting 34 from Sum[6:0] is equal to subtracting 32 and then subtracting 2. Subtract 51 from Sum[6:0], which equals 48 minus 3, and so on. The lookup table 522 performs this function by receiving the second component Sum[6:4], which is a multiple of 16, and generating Correction[3:0], which represents the corresponding number subtracted from the first component Sum[3:0]. The correction values ​​for various input values ​​are shown in Table 2 below.

[0091]

[0092]

[0093] Table 2: Correction values ​​for modulo 7 generator

[0094] The lookup table 522 sends the Correction[3:0] to the subtractor 524. The subtractor 524 subtracts the Correction[3:0] from the first component Sum[3:0] to generate a preliminary residual value. The subtractor 524 sends the preliminary residual value to the test and correction circuit 530.

[0095] Alternatively and equivalently, the lookup table 522 may generate a signed integer representing a negative number added to the first component Sum[3:0]. In this case, the first subtraction value 16 of 16 may generate an addition value of -1, then the first subtraction value 32 of 32 may generate an addition value of -2, the first subtraction value 48 may generate an addition value of -3, and so on. The subtractor 524 will be replaced by an adder that adds the first component Sum[3:0] to the negative value represented by Correction[3:0] to generate a preliminary residual value. The adder sends the preliminary residual value to the test and correction circuit 530.

[0096] In operation, if the preliminary residual value is greater than 17, the test and correction circuit 530 performs a final correction. The final adjustment 532 tests the preliminary residual value to determine whether the preliminary residual value is less than 17. If the residual value is less than 17, the final adjustment 532 uses the 4 least significant bits of the preliminary residual value as the final Residue[3:0]. However, if the preliminary residual value is greater than or equal to 17, the final adjustment 532 subtracts 17 from the preliminary residual value to generate the final Residue[3:0].

[0097] In some embodiments, the modular operation generator can be multi-modal, wherein the modular operation generator is configured to generate a modular residual value for a divisor, and the divisor is selected from two or more possible divisors. In one example, the modular operation generator can be configured to generate a modular 3 residual value or a modular 15 residual value. Such a modular operation generator is now described.

[0098] Figure 6A-6B A conceptual diagram of a modulo 3 / 15 operation generator according to various embodiments is described, wherein the modulo 3 / 15 operation generator, Figure 2 In some embodiments, the modulo 3 / 15 operation generator can be implemented as Figure 3 part of the modular operation generator 312, and / or is implemented as Figure 3 As shown, the modular generator includes an accumulation circuit 610, a lookup and correction circuit 620, and a test and correction circuit 630. Except as further described below, the functions of the accumulation circuit 610, the lookup and correction circuit 620, and the test and correction circuit 630 are the same as those of the embodiment of the present invention. Figure 4 The accumulator circuit 410, the search and correction circuit 420, and the test and correction circuit 430 are substantially the same as those of the embodiment of the present invention. Similarly, except as otherwise described below, the functions of the accumulator circuit 610, the search and correction circuit 620, and the test and correction circuit 630 are respectively the same as those of the embodiment of the present invention. Figure 5 The accumulator circuit 510, the search and correction circuit 520, and the test and correction circuit 530 are substantially the same. The modulo 3 / 15 operation generator selects a divisor from a plurality of divisors, wherein the plurality of divisors include 3 and 15. If the selected divisor is 3, the modulo operation generator configures at least one of the accumulator circuit 610, the search and correction circuit 620, or the test and correction circuit 630 to perform a modulo 3 operation. If the selected divisor is 15, the modulo operation generator configures at least one of the accumulator circuit 610, the search and correction circuit 620, or the test and correction circuit 630 to perform a modulo 15 operation.

[0099] The modulo 3 / 15 operation generator takes advantage of the fact that both 3 and 15 are Mersenne numbers, where 3=4-1 and 15=16-1. Therefore, in modulo 3 mode, the input value is represented in base 4 format. As a result, each coefficient of the input value is a 2-bit number when represented in base 4 format. In modulo 15 mode, the input value is represented in base 16 format. As a result, each coefficient of the input value is a 4-bit number when represented in base 16 format.

[0100] In operation, the accumulator circuit 610 performs a sum operation on the coefficients of the input values ​​together to generate the coefficient sum The accumulator circuit 610 adds coefficients through a series of stages. The first stage includes add / concatenate units (also referred to herein as "AddConcat" units) 618(0), 618(1), 618(2), 618(3), 618(4), 618(5), 618(6), and 618(7). The second stage includes adders 612(0), 612(1), 612(2), and 612(3). The third stage includes adders 614(0) and 614(1). The fourth stage includes adder 616.

[0101] In the modulo 3 mode, because the input value is a 32-bit number, the accumulator circuit 610 performs a summation operation on 16 2-bit coefficients. In the modulo 3 mode, the add / concatenate unit 618 is configured to be in the add mode. Each add / concatenate unit 618 adds two adjacent 2-bit coefficients. In this regard, the add / concatenate unit 618 (0) generates the sum of coefficients of W=0 ([01:00] bits) and W=1 ([03:02] bits). Similarly, the add / concatenate unit 618 (1) generates the sum of coefficients of W=2 ([05:04] bits) and W=3 ([07:06] bits). Add / concatenate units 618(2), 618(3), 618(4), 618(5), and 618(6) similarly sum each coefficient pair, and add / concatenate unit 618(7) generates the sum of coefficients of W=14 (bits [29:28]) and W=15 (bits [31:30]). Each add / concatenate unit 618 generates a 3-bit sum that includes a guard bit.

[0102] In the second stage, adder 612(0) generates the sum of the output of add / cascade unit 618(0) and the output of add / cascade unit 618(1). Similarly, adders 612(1)-612(3) generate the sum of the outputs of each pair of add / cascade units 618. Each adder 612 generates a 4-bit sum, including two guard bits. In the third stage, adder 614(0) generates the sum of the output of adder 612(0) and the output of adder 612(1). Similarly, adder 614(1) generates the sum of the output of adder 612(2) and the output of adder 612(3). Each adder 614 generates a 5-bit sum, including 3 guard bits. In the fourth stage, adder 616 generates the sum of the output of adder 614(0) and the output of adder 614(1). The adder 614 generates a 6-bit sum including 3 guard bits. The accumulation circuit 610 generates Sum[6:0] including the 2 low-order bits of Sum[1:0] and the 4 guard bits of Sum[5:2]. In modulo 3 mode, Sum

[06] is 0. The accumulation circuit 610 sends Sum[6:0] to the search and correction circuit 620.

[0103] In operation, the lookup and correction circuit 620 receives Sum[6:0] from the accumulation circuit 610. The lookup and correction circuit 620 separates Sum[6:0] into two components. The first component Sum[1:0] includes the least significant bits of Sum[6:0] and has the same width as the coefficients of the input value. Because the input value is represented in base 4, each coefficient of the input value is a 2-bit number. Therefore, the first component Sum[1:0] includes the two least significant bits of Sum[6:0]. The second component Sum[6:2] includes the most significant bits of Sum[6:0]. The second component Sum[6:2] represents the value of the guard bit generated by the adder of the accumulation circuit 610, where Sum[6] is set to 0.

[0104] The lookup and correction circuit 620 routes the first component Sum[1:0] to an adder 624. The lookup and correction circuit 620 routes the second component Sum[6:2] to a lookup table 622. The value of Sum[6:2] represents the multiple of 4 contained in Sum[6:0]. For example, Sum[6:2]=0 0001 represents the value 4, Sum[6:2]=0 0010 represents the value 8, Sum[6:2]=0 0011 represents the value 12, and so on. In order to generate a modulo 3 residual value, the number 3 must be subtracted from Sum[6:0] until the residual value is in the range of 0 to 2. Because the modulo divisor of 3 is a Mersenne number, the modulo divisor can be written as 4-1. Therefore, subtracting 3 from Sum[6:0] is equal to subtracting 4 and adding 1. Subtracting 6 from Sum[6:0] is equal to subtracting 8 and adding 2. Subtracting 9 from Sum[6:0] is equal to subtracting 12 and adding 3, and so on. The lookup table 622 performs this function by receiving the second component Sum[6:2], which is a multiple of 4, and generating a Correction[1:0], which represents the corresponding value to be added to the first component Sum[1:0]. The correction values ​​for various input values ​​are shown in Table 3 below.

[0105]

[0106]

[0107] Table 3: Correction values ​​for modulo 3 generator

[0108] For a modulo 3 generator and a 32-bit input value, the width of the input Sum[6:2] is 4 bits Sum[5:2], corresponding to 4 guard bits, plus the unused bit Sum[6]. The number of active entries of the lookup table 422 corresponding to Sum[5:2] is 16, and the width of the output Correction[1:0] is 2 bits. The output Correction[1:0] is in the range of 0 to 3. The lookup table 422 sends the Correction[1:0] to the adder 624. The adder 624 adds the first component Sum[1:0] to the Correction[1:0] to generate a preliminary residual value. The adder 624 sends the preliminary residual value to the test and correction circuit 630.

[0109] In operation, if the preliminary residual value is greater than 2, the test and correction circuit 630 will perform a final correction. The first component Sum[1:0] is in the range of 0 to 3, and the Correction[1:0] is in the range of 0 to 2. Therefore, the preliminary residual value generated by the adder 624 is a 5-bit value and is in the range of 0 to 5. The final adjustment 632 tests the preliminary residual value to determine whether the preliminary residual value is less than 3. If the preliminary residual value is less than 3, the final adjustment 632 uses the least significant 2 bits of the preliminary residual value as the final Residue[1:0]. If the preliminary residual value is greater than or equal to 3, the final adjustment 632 subtracts 3 from the preliminary residual value to generate the final Residue[1:0].

[0110] In the modulo 15 mode, because the input value is a 32-bit number, the accumulation circuit 610 performs a summation operation on eight 4-bit coefficients. In the modulo 15 mode, the add / concatenate unit 618 is configured to be in a concatenation mode. Each add / concatenate unit 618 passes four input bits to the output of the add / concatenate unit 618 to generate a 4-bit coefficient. The add / concatenate unit 618 does not perform a summation operation or add any guard bits. As a result, each adder 612(0)-612(3) adds two 4-bit coefficients, as shown in FIG. Figure 4 Similarly, each adder 614(0)-614(1) adds two 5-bit coefficients, as shown in FIG. Figure 4 Adder 616 adds two 6-bit coefficients, such as Figure 4 The search and correction circuit 620 and the test and correction circuit 630 are cascaded. Figure 4 The described cascaded manner processes the output of the accumulation circuit 610. As a result, the modulo 3 / 15 operation generator can be configured to generate a modulo 3 residual value or a modulo 15 residual value in a single circuit.

[0111] It should be understood that the systems described herein are illustrative and that variations and modifications are possible. In one example, the disclosed modular operation generator may be configured to generate residual values ​​for any Mersenne number divisor. The disclosed modular operation generator may be configured to perform modular 3 operations, modular 7 operations, modular 15 operations, modular 31 operations, and so on, until the width of the input value is reached. In another example, the disclosed modular operation generator may be configured to generate residual values ​​for any Fermat number divisor. The disclosed modular operation generator may be configured to perform modular 5 operations, modular 9 operations, modular 17 operations, modular 33 operations, and so on, until the width of the input value is reached. In yet another example, the disclosed modular operation generator may be configured to generate different combinations of modular operations with Mersenne number divisors in a single circuit. If Fig. 6A and 6B If the addition / concatenation unit 618 receives two 3-bit values ​​instead of two 2-bit values, the modular operation generator can be configured to generate a residual value of modulo 7 or modulo 31. In another example, the disclosed modular operation generator can be configured to generate different combinations of modular operations with Fermat number divisors in a single circuit. The modular operation generator can be configured to generate residual values ​​of modulo 5 or modulo 17. Additionally or alternatively, the modular operation generator can be configured to generate residual values ​​of modulo 9 or modulo 33. Various such operation generators can be combined into a single circuit, which can be configured to calculate residual values ​​of modulo 3, 5, 7, 9, 15, 17, 31, 33 operations. In another example, the disclosed modular operation generator can be configured to generate residual values ​​of divisors that are neither Mersenne numbers nor Fermat numbers. If the modular operation generator is configured to perform a modular operation on more than one divisor, the modular operation generator will select a divisor from the multiple divisors. The modular operation generator configures at least one of the accumulation circuit, the lookup and correction circuit, or the test and correction circuit to perform a modular operation based on a selected divisor.

[0112] For example, the modular operation generator can be configured to generate a residual value of a modular 14 or modular 24 operation, relative to Figure 5-6B There is some additional complexity for the modular generator described.

[0113] Figure 7 According to various embodiments, Figure 2 Flowchart of steps of a method for executing a modular operation generator by a parallel processing unit. Figure 1 -6 system describes the method steps, but one of ordinary skill in the art will understand that any system configured to perform the method steps in any order is within the scope of the present disclosure.

[0114] As shown, method 700 begins at step 702, where an accumulation circuit of a modular operation generator performs a set of summations on an input value to generate a first sum. The accumulation circuit divides the input value into a plurality of coefficients, where the number of bits in each coefficient depends on the divisor of the modular operation. If the divisor is a Mersenne number, the divisor can be expressed as M=2 n -1, where n is the number of bits in each coefficient. The accumulation circuit performs the summing function on the Mersenne number divisor by adding the coefficients. The accumulation circuit may add the coefficients through a series of adder stages. The accumulation circuit generates a sum, which may include one or more guard bits to prevent overflow when summing the coefficients.

[0115] If the divisor is a Fermat number, then the divisor can be expressed by F=2 n +1, where n is the number of bits in each coefficient. The accumulator circuit performs a summing function on a Fermat number divisor by adding coefficients corresponding to even powers of 2 and subtracting coefficients corresponding to odd powers of 2. The accumulator circuit may add the coefficients through a series of adder and / or subtractor stages. The accumulator circuit generates a sum, which may include one or more guard bits to prevent overflow when summing the coefficients.

[0116] At step 704, a lookup and correction circuit of the modular operation generator accesses a correction value, the correction value being associated with a first portion of the first sum. The first portion of the first sum includes the most significant bits of the first sum and corresponds to the guard bits added by the accumulation circuit. The second portion of the first sum includes the least significant bits of the first sum and includes the same number of bits as each coefficient of the input value. If the divisor is a Mersenne number, the lookup function determines the correction value to be added to the second portion of the first sum. If the divisor is a Fermat number, the lookup function determines the correction value to be subtracted from the second portion of the first sum.

[0117] At step 706, the lookup and correction circuit performs a set of summations on the correction value and the second portion of the first sum to generate a second sum. If the divisor is a Mersenne number, the lookup and correction circuit adds the correction value to the second portion of the first sum to generate the second sum. If the divisor is a Fermat number, and if the correction value represents a positive value, the lookup and correction circuit subtracts the correction value from the second portion of the first sum to generate the second sum. However, if the divisor is a Fermat number, and if the correction value represents a negative value, the lookup and correction circuit adds the correction value to the second portion of the first sum to generate the second sum.

[0118] At step 708, the test and correction circuit generates a result of the modular operation based on the second sum. The test and correction circuit compares the second sum with the divisor of the modular operation. If the second sum is less than the divisor of the modular operation, the test and correction circuit uses the least significant bit of the second sum value as the final residual value. However, if the second sum is greater than or equal to the divisor of the modular operation, the test and correction circuit subtracts the value of the divisor from the second sum value to generate the final residual value. Then, method 700 terminates.

[0119] In summary, various embodiments include a modular operation generator in a computer-based system. The modular operation generator includes an accumulation circuit that performs a first set of summations on input values ​​to generate a first sum. The first set of summations may include an addition function and / or a subtraction function. The modular operation generator also includes a lookup and correction circuit that includes a lookup table and an adder. A first portion of the first sum is applied to the lookup table that generates a correction value. The adder performs a second set of summations on the correction value and a second portion of the first sum to generate a second sum. The modular operation generator also includes a test and correction circuit that adjusts the second sum if the sum of the second sums is greater than or equal to a divisor of the modular operation generator. The test and correction circuit sends a final residual value determined by the modular operation generator.

[0120] At least one technical advantage of the disclosed technology over the prior art is that, using the disclosed technology, modular operations involving divisors that are not powers of 2 take less time to execute relative to modular operations involving divisors that are powers of 2. In addition, modular operations involving divisors that are not powers of 2 are executed in the same time regardless of the value of the dividend. As a result, operations involving modular operations, such as allocating data items between slices in a cache memory, are performed more efficiently relative to the prior art. More specifically, the performance of a cache memory that includes 15 or 17 slices can have the same or nearly the same performance as a cache memory that includes 16 slices. These advantages represent one or more technical improvements over prior art approaches.

[0121] Any and all combinations of any claim elements recited in any claim and / or any elements described in this application, in any manner, are within the intended scope of the present disclosure and protection.

[0122] Descriptions of various embodiments have been given for purposes of illustration, but are not intended to be exhaustive or limited to the disclosed embodiments. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments.

[0123] Aspects of the present embodiment may be embodied as a system, method or computer program product. Therefore, aspects of the present disclosure may take the form of a complete hardware embodiment, a complete software embodiment (including firmware, resident software, microcode, etc.) or an embodiment that combines software and hardware aspects that can generally be mentioned in their entirety. In addition, aspects of the present disclosure may take the form of a computer program product embodied in one or more computer-readable media having computer-readable program code embodied thereon.

[0124] Any combination of one or more computer-readable media can be utilized. The computer-readable medium can be a computer-readable signal medium or a computer-readable storage medium. The computer-readable storage medium can be, for example, but not limited to, an electronic, magnetic, optical, electromagnetic, infrared or semiconductor system, device or equipment, or any suitable combination of the foregoing. More specific examples (non-exhaustive list) of computer-readable storage media will include the following: an electrical connection with one or more wires, a portable computer disk, a hard disk, a random access memory (RAM), only internal memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any other suitable combination of the foregoing. In the context of this article, a computer-readable storage medium can be any tangible medium that can contain or store a program for use by or in conjunction with an instruction execution system, a device or equipment.

[0125] Aspects of the present disclosure are described above with reference to the flowcharts and / or block diagrams of the methods, devices (systems) and computer program products according to the embodiments of the present disclosure. It will be understood that each frame of the flowchart illustration and / or block diagram and the combination of frames in the flowchart illustration and / or block diagram can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer or other programmable data processing device to generate a machine, and the instructions are executed by the processor of the computer or other programmable data processing device so that the functions / actions specified in the flowchart and / or block diagram blocks can be implemented. Such a processor can be, but is not limited to, a general-purpose processor, a special-purpose processor or a field programmable gate array.

[0126] The flow charts and block diagrams in the accompanying drawings show the possible implementation architecture, function and operation of the system, method and computer program product according to various embodiments of the present disclosure. In this regard, each square box in the flow chart or block diagram can represent a module, segment or part of a code, which includes one or more executable instructions for realizing the specified logical function. It should also be noted that in some alternative embodiments, the function indicated in the square box may not occur in the order indicated in the figure. For example, depending on the function involved, the two boxes shown in succession can actually be executed substantially at the same time, or sometimes these boxes can be executed in reverse order. It should also be noted that each square box of the block diagram and / or flow chart description and the combination of the square boxes in the block diagram and / or flow chart description can be realized by a system based on special-purpose hardware that performs a specified function or action, or a combination of special-purpose hardware and computer instructions.

[0127] While the foregoing is directed to embodiments of the present disclosure, other and further embodiments of the disclosure may be devised without departing from the basic scope thereof, and the scope of the disclosure is determined by the claims that follow.

Claims

1. A computer-implemented method for performing modular arithmetic, the method comprising: performing, via an accumulation circuit, a first set of summations on input values ​​associated with the modular operation to generate a first sum; accessing, via a lookup and correction circuit, a correction value associated with a first portion of the first sum; performing, via the lookup and correction circuit, a second set of summations on the correction value and a second portion of the first sum to generate a second sum; as well as A result of the modular operation is generated based on the second sum via a test and correction circuit.

2. The computer-implemented method of claim 1 , wherein the divisor of the modular operation is a Mersenne number, and wherein performing the first set of summations on the input values ​​comprises: dividing the input value into a set of coefficients; as well as A first coefficient included in the set of coefficients is added to a second coefficient included in the set of coefficients.

3. The computer-implemented method of claim 1 , wherein a divisor of the modular operation is a Mersenne number, and wherein accessing the correction value comprises retrieving the correction value from a lookup table, wherein the correction value represents a number to be added to the second portion of the first sum.

4. The computer-implemented method of claim 1 , wherein a divisor of the modular operation is a Mersenne number, and wherein performing a second set of summations on the correction value and the second portion of the first sum comprises adding the correction value to the second portion of the first sum.

5. The computer-implemented method of claim 1 , wherein a divisor of the modular operation is a Fermat number, and wherein performing the first set of summations on the input values ​​comprises: dividing the input values ​​into a first set of coefficients corresponding to even powers of 2 and a second set of coefficients corresponding to odd powers of 2; as well as A first coefficient included in the second set of coefficients is subtracted from a second coefficient included in the first set of coefficients.

6. The computer-implemented method of claim 1 , wherein a divisor of the modular operation is a Fermat number, and wherein accessing the correction value comprises retrieving the correction value from a lookup table, wherein the correction value represents a number to be subtracted from the second portion of the first sum.

7. The computer-implemented method of claim 1, wherein a divisor of the modular operation is a Fermat number, and wherein performing the second set of summations on the correction value and the second portion of the first sum comprises subtracting the correction value from the second portion of the first sum.

8. The computer-implemented method of claim 1 , wherein generating a result of the modular operation comprises: determining that the second sum is less than the divisor of the modulo operation; as well as Set the result as the second sum.

9. The computer-implemented method of claim 1 , wherein generating a result of the modular operation comprises: determining that the second sum is greater than or equal to the divisor of the modulo operation; calculating a difference by subtracting the divisor from the second sum; as well as The result of the modulo operation is set as the difference value.

10. A modular operation generator, comprising: an accumulation circuit that performs a first set of summations on the input values ​​to generate a first sum; a lookup and correction circuit that accesses a correction value associated with a first portion of the first sum and performs a second set of summations on the correction value and a second portion of the first sum to generate a second sum; as well as A test and correction circuit generates a result of the modulo operation based on the second sum.

11. The modular operation generator according to claim 10, further comprising: receiving a selection of a first divisor included in a plurality of divisors; as well as At least one of the accumulation circuit, the lookup and correction circuit, or the test and correction circuit is configured to perform the modulo operation based on the first divisor.

12. The modular operation generator according to claim 11, wherein the first divisor and a second divisor included in the plurality of divisors are Mersenne numbers.

13. The modular operation generator according to claim 11, wherein the first divisor and a second divisor included in the plurality of divisors are Fermat numbers.

14. The modular operation generator according to claim 11, wherein the first divisor is a Mersenne number, and a second divisor included in the plurality of divisors is a Fermat number.

15. The modular operation generator of claim 10, wherein the divisor of the modular operation is a Mersenne number, and wherein performing the first set of summations on the input values ​​comprises: dividing the input value into a set of coefficients; as well as A first coefficient included in the set of coefficients is added to a second coefficient included in the set of coefficients.

16. The modular operation generator of claim 10, wherein a divisor of the modular operation is a Mersenne number, and wherein accessing the correction value comprises retrieving the correction value from a lookup table, wherein the correction value represents a number to be added to the second portion of the first sum.

17. The modular operation generator of claim 10, wherein a divisor of the modular operation is a Mersenne number, and wherein performing the second set of summations on the correction value and the second portion of the first sum comprises adding the correction value to the second portion of the first sum.

18. The modular operation generator of claim 10, wherein a divisor of the modular operation is a Fermat number, and wherein performing the first set of summations on the input values ​​comprises: dividing the input values ​​into a first set of coefficients corresponding to even powers of 2 and a second set of coefficients corresponding to odd powers of 2; as well as A first coefficient included in the second set of coefficients is subtracted from a second coefficient included in the first set of coefficients.

19. The modular operation generator of claim 10, wherein a divisor of the modular operation is a Fermat number, and wherein accessing the correction value comprises retrieving the correction value from a lookup table, wherein the correction value represents a number to be subtracted from the second portion of the first sum.

20. A system comprising: a processor, the processor sending the memory address and the data value to a memory management unit (MMU); a cache memory, the cache memory comprising a plurality of cache memory slices; as well as The MMU, which receiving the memory address and the data value from the processor, performing a first set of summations on the memory addresses to generate a first sum, accessing a correction value associated with a first portion of said first sum, performing a second set of summations on the correction value and a second portion of the first sum to generate a second sum, Generate the result of the modulo operation based on the second sum, wherein a result of the modulo operation identifies a first cache memory slice among the plurality of cache memory slices; and The data value is stored in the first cache memory slice.

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