An instruction execution method, computing device, and storage medium based on a read-write lock

Abstract

The present invention discloses an instruction execution method, a computing device, and a storage medium based on a read-write lock. The method includes the steps of: submitting a first storage instruction for storing data in an internal memory to a processor; when the processor cannot normally execute the first storage instruction, generating a second storage instruction according to a data storage exception message; acquiring a write lock and locking the process of executing the storage instruction; storing data in the internal memory by executing the second storage instruction through the processor; when receiving a first read instruction for reading data in the internal memory, acquiring a read lock; if the write lock is occupied and the read lock cannot be acquired, then acquiring the read lock again; if the read lock is acquired, locking the process of executing the read instruction; and reading data from the internal memory by executing the first read instruction through the processor. The present invention can prevent the atomicity of data access from being lost, thereby avoiding abnormal operation problems of certain special application programs.

Description

Technical Field

[0001] The present invention relates to the field of computer instruction execution, and particularly to an instruction execution method, a computing device, and a storage medium based on a read-write lock. Background Art

[0002] With the continuous development of computer technology, more and more applications have been developed. Correspondingly, the data of applications is also increasing, and the data structure is becoming more and more complex. Therefore, the memory access performance of complex data structures in memory by the system is also becoming more and more important, directly affecting the running speed of key application programs. When storing data, special storage situations often occur. When an application accesses the stored data, the processor does not support special memory access instructions for the data, and an error will occur. The processor cannot directly process such memory access instruction operations on the data.

[0003] To this end, in the prior art, in order to access such stored data, the data memory access instruction is changed, so that the instruction for the application to access this data becomes a normal instruction, and the processor can execute the memory access of the data. One of the solutions is to convert the originally cross-boundary memory access instruction into two boundary-aligned memory access instructions. By executing the two boundary-aligned memory access instructions, the complete data can be successfully stored or read.

[0004] However, this method converts one memory access into multiple memory accesses. Therefore, in essence, the memory access model of the application program is changed. For some special application scenarios, the atomicity of one memory access is destroyed by multiple memory accesses. If the application program depends on the atomicity of memory access, in this case, due to the destruction of the atomicity, data errors or mistakes will occur, and in severe cases, the application program may run abnormally.

[0005] To this end, a new instruction execution method based on a read-write lock is needed. Summary of the Invention

[0006] Therefore, the present invention provides an instruction execution method based on a read-write lock to attempt to solve or at least alleviate the problems existing above.

[0007] According to an aspect of the present invention, there is provided an instruction execution method based on a read-write lock, which is suitable for execution in a computing device. The computing device includes a processor, an internal memory, and runs one or more applications. The storage area of the internal memory is mapped to a storage space, and the applications read and write data in the internal memory using storage addresses in the storage space. The method includes the steps of: submitting a first storage instruction for storing data of an application in the internal memory to the processor; when the processor cannot normally execute the first storage instruction due to the storage address of the data stored by the first storage instruction, generating a second storage instruction according to a data storage exception message generated by the processor, the second storage instruction being suitable for storing the data to be stored by the first storage instruction, and the processor not generating a data storage exception message when executing the second storage instruction; acquiring a write lock and locking the process of executing the storage instruction; storing data in the internal memory by the processor executing the second storage instruction; when receiving a first read instruction for reading data in the internal memory, acquiring a read lock, the write lock and the read lock being mutually exclusive, and when locking according to the write lock or the read lock, data cannot be stored and read simultaneously at the same address; if the write lock is occupied and the read lock cannot be acquired, then acquiring the read lock again; if the read lock is acquired, then locking the process of executing the read instruction; reading data from the internal memory by the processor executing the first read instruction.

[0008] Optionally, in the method according to the present invention, generating a second storage instruction according to a data storage exception message generated by the processor includes the steps of: generating a first half storage instruction and a second half storage instruction according to the storage address of the first storage instruction, the first half storage instruction and the second half storage instruction being respectively suitable for storing data according to the first half address and the second half address; using the first half storage instruction and the second half storage instruction as the second storage instruction.

[0009] Optionally, in the method according to the present invention, the method further includes the steps of: if the read lock is occupied and the write lock cannot be acquired, then acquiring the write lock again; if the write lock is acquired, then storing data by the second storage instruction.

[0010] Optionally, in the method according to the present invention, storing data in the internal memory by the memory executing the second storage instruction includes the steps of: generating a first half data and a second half data according to the data; storing the first half data according to the first half address by the processor executing the first half storage instruction; storing the second half data according to the second half address by the processor executing the second half storage instruction.

[0011] Optionally, in the method according to the present invention, the method further includes the steps of: after the data is stored in the internal memory by the processor, releasing the write lock so that other threads of the processor can acquire the read lock and read the data.

[0012] Optionally, in the method according to the present invention, the first read instruction includes a first half read instruction and a second half read instruction. Reading data by the first read instruction includes the steps of: executing the first half read instruction by a processor to read the first half data stored according to the first half address; executing the second half read instruction by the processor to read the second half data stored according to the second half address; combining the first half data read from the first half address and the second half data read from the second half address to obtain the data.

[0013] Optionally, in the method according to the present invention, it further includes the step of: after the processor finishes reading data in the internal memory, releasing the read lock so that other threads of the processor can obtain the write lock and store data.

[0014] Optionally, in the method according to the present invention, it further includes the steps of: if a second read instruction is received, submitting the second read instruction to the processor; when the processor cannot normally execute the second read instruction due to the address of the data read by the second read instruction, generating a first read instruction according to the data access exception message generated by the processor, the first read instruction being suitable for reading the data to be read by the second read instruction, and the processor will not generate a data read exception message when executing the first read instruction.

[0015] Optionally, in the method according to the present invention, generating the first read instruction according to the data access exception message generated by the processor includes the steps of: generating a first half read instruction and a second half read instruction according to the storage address of the second read instruction, the first half read instruction and the second half read instruction being respectively suitable for reading data according to the first half address and the second half address; using the first half read instruction and the second half read instruction as the first read instruction.

[0016] Optionally, in the method according to the present invention, the first storage instruction includes an unaligned storage instruction, and the first half storage instruction and the second half storage instruction include aligned storage instructions.

[0017] Optionally, in the method according to the present invention, the second read instruction includes an unaligned read instruction, and the first half read instruction and the second half read instruction include aligned read instructions.

[0018] According to another aspect of the present invention, there is provided a computing device, including: one or more processors; a memory; and one or more programs, wherein the one or more programs are stored in the memory and configured to be executed by the one or more processors, and the one or more programs include instructions for executing a method for executing instructions based on read-write locks according to the present invention.

[0019] According to another aspect of the present invention, there is provided a computer-readable storage medium storing one or more programs, the one or more programs including instructions which, when executed by a computing device, cause the computing device to execute the method in an instruction execution method based on a read-write lock according to the present invention.

[0020] The instruction execution method based on a read-write lock in the present invention is adapted to be executed in a computing device. The computing device includes a processor, an internal memory, and runs one or more applications, and includes the steps of: submitting a first storage instruction for storing data of an application in the internal memory to the processor; when the processor cannot normally execute the first storage instruction due to the storage address of the data stored by the first storage instruction, generating a second storage instruction according to a data storage exception message generated by the processor, the second storage instruction being adapted to store the data to be stored by the first storage instruction, and the processor not generating a data storage exception message when executing the second storage instruction. In order to avoid that while storing data, a thread of another core of the processor executes a data read instruction and reads incomplete data from a position where data storage has not been completed, causing an error in the operation of the application, it is first necessary to obtain a write lock and lock the process of executing the storage instruction. Then, the processor is caused to execute the second storage instruction to store data in the internal memory. When a first read instruction for reading data in the internal memory is received, a read lock is obtained. The write lock and the read lock are mutually exclusive. When locking according to the write lock or the read lock, data cannot be stored and read simultaneously at the same address. If the write lock is occupied and the read lock cannot be obtained, the read lock is obtained again. The fact that the write lock is occupied and the read lock cannot be obtained indicates that data is being stored at the current storage position. At this time, reading data will damage the integrity of the data and incorrect data will be read. Therefore, data cannot be read. If the read lock is obtained, the process of executing the read instruction is locked, and the processor is caused to execute the first read instruction to read data from the internal memory. If the write lock is obtained, data is read through the first read instruction, indicating that data storage has been completed at this time and data can be read normally. The present invention can restrict the edge effect caused by the change of the memory access model of the application program, so that the atomicity of data access is not lost, thereby avoiding certain special application program operation exception problems caused by such edge effects, and further improving the stability of the application program and the compatibility of the entire system. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] To achieve the above and related purposes, certain illustrative aspects are described herein in connection with the following description and drawings, which indicate various ways in which the principles disclosed herein can be practiced, and all aspects and their equivalent aspects are intended to fall within the scope of the claimed subject matter. The above and other objects, features and advantages of the present invention disclosed will become more apparent by reading the following detailed description in conjunction with the drawings. Throughout the disclosure, the same reference numerals generally refer to the same components or elements.

[0022] Figure 1 Shows a schematic structural diagram of deploying a processor and an internal memory in a computing device according to an exemplary embodiment of the present invention;

[0023] Figure 2 Shows a block diagram of the structure of a computing device 200 according to an exemplary embodiment of the present invention;

[0024] Figure 3 Shows a schematic flowchart of an instruction execution method 300 based on a read-write lock according to an exemplary embodiment of the present invention;

[0025] Figure 4 Shows a schematic diagram of generating a second storage instruction according to an exemplary embodiment of the present invention; and

[0026] Figure 5 Shows a schematic diagram of destroying instruction atomicity according to an exemplary embodiment of the present invention. Detailed implementation manners

[0027] Exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. Although the exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the embodiments set forth herein. On the contrary, these embodiments are provided so that the present disclosure can be more thoroughly understood and the scope of the present disclosure can be fully conveyed to those skilled in the art. The same reference numerals generally refer to the same components or elements.

[0028] Figure 1 Shows a schematic structural diagram of deploying a processor and an internal memory in a computing device according to an exemplary embodiment of the present invention. As Figure 1 shown, the computing device 200 includes a processor 204 and an internal memory 140. An operating system 220 is also installed in the computing device 200, and an application 110 runs on the operating system 220. The present invention does not limit the specific type of the operating system 220. Figure 1 The number of applications shown is only exemplary. The number and type of applications running on the operating system 220 are not limited. The internal memory 140 is suitable for storing the operating system 220 and the running data of the application 110, and the processor 204 is suitable for processing this running data.

[0029] Figure 1 The specific structure of the computing device 200 in Figure 2 is described in detail. Figure 2 Shows a block diagram of the structure of a computing device 200 according to an exemplary embodiment of the present invention. As Figure 2As shown, in the basic configuration 202, the computing device 200 typically includes a system memory 206 and one or more processors 204. A memory bus 208 can be used for communication between the processor 204 and the system memory 206.

[0030] Depending on the desired configuration, the processor 204 can be any type of processor, including but not limited to: a microprocessor (μP), a microcontroller (μC), a digital signal processor (DSP), or any combination thereof. The processor 204 can include one or more levels of cache, such as a level 1 cache 210 and a level 2 cache 212, a processor core 214, and registers 216. An example processor core 214 can include an arithmetic logic unit (ALU), a floating point unit (FPU), a digital signal processing core (DSP core), or any combination thereof. An example memory controller 218 can be used with the processor 204, or in some implementations, the memory controller 218 can be an internal part of the processor 204.

[0031] Depending on the desired configuration, the system memory 206 can be any type of memory, including but not limited to: volatile memory (such as RAM), non-volatile memory (such as ROM, flash memory, etc.), or any combination thereof. The system memory 206 can include an operating system 220, one or more programs 222, and program data 228. In some embodiments, the program 222 can be arranged to execute instructions 223 of the method 300 according to the present invention by one or more processors 204 on the operating system using the program data 228.

[0032] The computing device 200 can also include a storage interface bus 234. The storage interface bus 234 enables communication from a storage device 232 (e.g., removable storage 236 and non-removable storage 238) via a bus / interface controller 230 to the basic configuration 202. At least a portion of the operating system 220, the program 222, and the data 224 can be stored on the removable storage 236 and / or the non-removable storage 238, and when the computing device 200 is powered on or the program 222 is to be executed, it is loaded into the system memory 206 via the storage interface bus 234 and executed by one or more processors 204.

[0033] The computing device 200 may also include an interface bus 240 that facilitates communication from various interface devices (e.g., output device 242, peripheral interface 244, and communication device 246) to the basic configuration 202 via the bus / interface controller 230. Example output devices 242 include a graphics processing unit 248 and an audio processing unit 250. They may be configured to facilitate communication with various external devices such as a display or speakers via one or more A / V ports 252. Example peripheral interfaces 244 may include a serial interface controller 254 and a parallel interface controller 256, which may be configured to facilitate communication with external devices such as input devices (e.g., keyboard, mouse, pen, voice input device, touch input device) or other peripherals (e.g., printer, scanner, etc.) via one or more I / O ports 258. Example communication device 246 may include a network controller 260, which may be arranged to communicate with one or more other computing devices 262 via one or more communication ports 264 through a network communication link.

[0034] The network communication link may be an example of a communication medium. A communication medium can generally embody computer-readable instructions, data structures, program modules in a modulated data signal such as a carrier wave or other transmission mechanism, and can include any information delivery medium. A "modulated data signal" can be a signal in which one or more of its data sets or its changes can encode information in the signal. As a non-limiting example, the communication medium can include wired media such as a wired network or a dedicated line network, as well as various wireless media such as sound, radio frequency (RF), microwave, infrared (IR), or other wireless media. The term computer-readable medium as used herein can include both storage media and communication media.

[0035] In the computing device 200 according to the present invention, the program 222 includes multiple program instructions of the instruction execution method 300 based on a read-write lock, and these program instructions may instruct the processor 204 to execute some steps in the instruction execution method 300 based on a read-write lock running in the computing device 200 of the present invention, so that each part in the computing device 200 executes instructions by executing the instruction execution method 300 based on a read-write lock.

[0036] The computing device 200 may be implemented as a server, such as a file server 240, a database 250, a server, an application server, etc. These electronic devices may be, for example, a personal digital assistant (PDA), a wireless network browsing device, an application-specific device, or a hybrid device that may include any of the above functions. It may be implemented as a personal computer including a desktop computer and a laptop computer configuration. Also, in some embodiments, the computing device 200 is configured to execute the instruction execution method 300 based on a read-write lock.

[0037] Figure 3 The flowchart shows a method 300 for instruction execution based on a read-write lock according to an exemplary embodiment of the present invention. The method 300 for instruction execution based on a read-write lock in the present invention is adapted to be executed in a computing device and further adapted to be executed in an operating system 220 as shown in Figure 1 shown. As Figure 3 shown, the method 300 for instruction execution based on a read-write lock starts from step S310, where a first storage instruction for storing data of the application 110 in the internal memory 140 is submitted to the processor 204. When the application 110 needs to store data in the internal memory 140, it needs to submit the first storage instruction for storing the data to the processor 204 for execution via the operating system 220. The storage area of the internal memory 140 is mapped to a storage space, and the application 110 stores data in the internal memory 140 at a storage address in the storage space.

[0038] Subsequently, step S320 is executed. When the processor 204 cannot normally execute the first storage instruction due to the storage address of the data stored by the first storage instruction, a second storage instruction is generated according to the data storage exception message generated by the processor 204. The second storage instruction is adapted to store the data to be stored by the first storage instruction, and the processor 204 will not generate a data storage exception message when executing the second storage instruction.

[0039] According to an embodiment of the present invention, when the storage address is unaligned in the internal memory 140, the processor 204 cannot execute the special operation instruction, and a data storage exception message will be generated. The first storage instruction includes an unaligned storage instruction. When the data to be read by the application 110 is stored unaligned in the internal memory 140, the first operation instruction is an unaligned memory access instruction, and the data storage exception message is an unaligned memory storage exception. Unaligned means that the starting position where the data is stored in the memory is not aligned with the natural boundary where the data of this type is stored sequentially in the memory. For example, for a 32-bit register, when storing data normally, the register stores a complete 32-bit data, and the starting address of the data storage is the starting address of the register. But when the storage is unaligned, the calculator only stores a part of the 32-bit data, the starting address of the 32-bit data is offset from the starting address of the register, and the starting address of the data is at a certain middle address in the register. The other part of the 32-bit data is stored sequentially in the next register. Or for a 32-bit register, the processor 204 supports reading 16-bit data at a time. When the starting address of the 16-bit data is in the middle part of the 32-bit register, that is, a cross-boundary storage of the 16-bit data occurs, and the processor 204 cannot read the data normally. The processor 204 cannot completely retrieve the separately stored 16-bit data according to an instruction, so the processor 204 will throw an exception. Unaligned memory storage exception means that on a processor 204 that does not support directly storing unaligned data, directly storing unaligned data will cause the processor 204 to throw an exception.

[0040] Figure 4 FIG. shows a schematic diagram of generating a second storage instruction according to an exemplary embodiment of the present invention. As Figure 4 shown, when converting the unaligned memory access instruction, first execute the instruction decomposition calculation sequence, generate the first half storage instruction and the second half storage instruction according to the storage address of the first storage instruction. The first half storage instruction and the second half storage instruction are respectively suitable for storing data according to the first half address and the second half address. Finally, the first half storage instruction and the second half storage instruction are used as the second storage instruction. The first half storage instruction and the second half storage instruction include aligned storage instructions.

[0041] During the above instruction conversion process, since the memory access model of the application 110 is changed and one memory operation is split into multiple ones, edge effects are caused, especially, the change of memory access atomicity. When the correctness of the running logic of the application 110 depends on the assumption of atomicity, due to the lack of atomicity, the application 110 will run abnormally.

[0042] Figure 5 FIG. shows a schematic diagram of destroying the atomicity of an instruction according to an exemplary embodiment of the present invention. As Figure 5As shown, since the first half memory access instruction and the second half memory access instruction are two independent operations without atomicity, there is a horizon gap between them, and other horizons can be inserted. If there is a thread of another processing core executing a memory access write operation within its horizon, it will destroy the data integrity and may cause the application 110 to run abnormally.

[0043] Therefore, it is necessary to execute step S330 to obtain a write lock and lock the process of executing the store instruction. The global read-write lock includes a write lock and a read lock. The write lock and the read lock lock the process of executing the store instruction and the process of executing the read instruction respectively, so that data cannot be stored and read simultaneously at the same address in the internal memory. The store instruction includes a first store instruction and a second store instruction, and the read instruction includes a first read instruction and a second read instruction. After locking the process of executing the store instruction, data cannot be read at the storage address of the store instruction in the internal memory, avoiding destroying the data integrity and reading incorrect data when reading data.

[0044] According to an embodiment of the present invention, when obtaining the write lock at this time, if the read lock is occupied and the write lock cannot be obtained, then obtain the write lock again. The read lock being occupied means that the data at this storage address is being read, and writing data at this time will cause a storage error. It is necessary to obtain the write lock again. If the write lock is obtained, then store the data through the second store instruction. If the write lock is obtained, it means that the data at this storage address has been read and new data can be written. If the read lock is still occupied and the write lock cannot be obtained, then continue to obtain the write lock until the read lock is released and the write lock is obtained. During the process of continuously obtaining the write lock, other threads that have obtained the read lock are reading the data. After the data reading is completed, the read lock can be released, and other threads can obtain the write lock.

[0045] Subsequently, execute step S340 to store data in the internal memory 140 through the processor by executing the second store instruction. Specifically, first generate the first half data and the second half data according to the data, then execute the first half store instruction through the processor 204 to store the first half data according to the first half address, and finally execute the second half store instruction through the processor 204 to store the second half data according to the second half address.

[0046] After the data is stored in the internal memory 140 through the processor 204, release the write lock so that other threads of the processor can obtain the read lock and read the data.

[0047] During the process of storing data, if a thread executes an instruction to access stored data and needs to operate on the current storage section where data is being written, step S350 is executed to protect the atomicity of the data-writing process. When a first read instruction to read data from the internal memory is received, a read lock is acquired. If there is no write lock and the read lock is acquired, it indicates that the data storage in this storage section has been completed and data can be read normally.

[0048] Subsequently, step S360 is executed. If the write lock is occupied and the read lock cannot be acquired, the read lock is acquired again. If the write lock is occupied, it means that data is being stored in this storage section. At this time, if data is read, incorrect and incomplete data will be read. Acquiring the read lock again means judging again whether the data storage is completed.

[0049] If the read lock still cannot be acquired at this time, the read lock is continuously acquired and it is continuously judged whether the data storage is completed until the data storage is completed and the read lock can be acquired. During the process of continuously acquiring the read lock, data is also being written. When the data writing is completed, data can be read normally and the loop exits, thus preventing incorrect data from being read.

[0050] Subsequently, step S370 is executed. If the read lock is acquired, the process of executing the read instruction is locked. After locking the process of executing the read instruction, data storage operations cannot be performed at the read address of the read instruction in the internal memory, avoiding storage data errors when storing data, damaging the integrity of the data, and reading incorrect data. Therefore, data cannot be written.

[0051] Finally, step S380 is executed. The first read instruction is executed by the processor to read data from the internal memory. When reading data, the first half of the read instruction is executed by the processor 204 to read the first half of the stored data according to the first half address; the second half of the instruction is executed by the processor 204 to read the second half of the stored data according to the second half address; then the first half of the data read from the first half address and the second half of the data read from the second half address are combined to obtain the data. When combining and sorting the first half of the data and the second half of the data, according to the data structures of the first half of the data and the second half of the data, logical bit operations such as shifting, ANDing, and ORing are performed on the obtained first half of the data and the second half of the data, and the required data is intercepted and aligned from the data obtained from the aligned memory access instruction.

[0052] After the processor 204 finishes reading data from the internal memory 140, the read lock is released so that other threads of the processor can acquire the write lock and store data.

[0053] According to an embodiment of the present invention, when performing instruction conversion, when a certain instruction in the instruction stream is an unaligned memory access instruction, it is converted to obtain an aligned memory access instruction. Then, all instructions after the instruction stream are traversed, and subsequent unaligned memory access instructions are converted to obtain aligned memory access instructions. Unaligned memory access instructions include unaligned read instructions and unaligned store instructions, and aligned memory access instructions include aligned read instructions and aligned store instructions.

[0054] If a second read instruction in the instruction stream is received, and the second read instruction includes an unaligned read instruction that has not been converted, the second read instruction is first submitted to the processor 204. When the processor 204 cannot normally execute the second read instruction due to the address of the data read by the second read instruction, a first read instruction is generated according to the data access exception message generated by the processor 204. The first read instruction is suitable for reading the data that the second read instruction is to read, and the processor 204 will not generate a data read exception message when executing the first read instruction.

[0055] When generating the first read instruction according to the data access exception message generated by the processor 204, first execute the instruction decomposition sequence, generate a first half read instruction and a second half read instruction according to the storage address of the second read instruction. The first half read instruction and the second half read instruction are respectively suitable for reading data according to the first half address and the second half address, and the first half read instruction and the second half read instruction are used as the first read instruction.

[0056] The instruction execution method based on a read-write lock in the present invention is suitable for execution in a computing device. The computing device includes a processor, an internal memory, and runs one or more applications. The method includes the steps of: submitting a first storage instruction for storing data of an application in the internal memory to the processor. When the processor cannot normally execute the first storage instruction due to the storage address of the data to be stored by the first storage instruction, a second storage instruction is generated according to the data storage exception message generated by the processor. The second storage instruction is suitable for storing the data to be stored by the first storage instruction, and the processor will not generate a data storage exception message when executing the second storage instruction. To avoid, while storing data, a thread of another core of the processor executing a data read instruction and reading incomplete data from a position where data storage has not been completed yet, causing an error in the operation of the application, it is first necessary to obtain a write lock and lock the process of executing the storage instruction. Then, the processor executes the second storage instruction to store data in the internal memory. When a first read instruction for reading data in the internal memory is received, a read lock is obtained. The write lock and the read lock are mutually exclusive. When locking according to the write lock or the read lock, data cannot be stored and read simultaneously at the same address. If the write lock is occupied and the read lock cannot be obtained, the read lock is obtained again. The fact that the write lock is occupied and the read lock cannot be obtained indicates that data is being stored at the current storage position. At this time, reading data will damage the integrity of the data and read incorrect data. Therefore, data cannot be read. If the read lock is obtained, the process of executing the read instruction is locked, and the processor executes the first read instruction to read data from the internal memory. If the write lock is obtained, data is read through the first read instruction, indicating that data storage has been completed at this time and data can be read normally. The present invention can restrict the edge effect caused by the change of the memory access model of the application program, so that the atomicity of data access is not lost, thereby avoiding some special application program operation exception problems caused by such edge effects, and further improving the stability of the application program and the compatibility of the entire system.

[0057] In the specification provided herein, a large number of specific details are set forth. However, it is understood that embodiments of the present invention may be practiced without these specific details. In some instances, well-known methods, structures, and technologies have not been shown in detail so as not to obscure the understanding of this specification.

[0058] Similarly, it should be understood that, in order to streamline the present disclosure and assist in understanding one or more of the various inventive aspects, in the foregoing description of the exemplary embodiments of the present invention, the various features of the present invention are sometimes grouped together into a single embodiment, figure, or description thereof. However, the disclosed method should not be construed as reflecting an intention that the claimed invention requires more features than are expressly recited in each claim.

[0059] Those skilled in the art should understand that the modules or units or groups of the devices in the examples disclosed herein can be arranged in the devices as described in this embodiment, or alternatively can be located in one or more devices different from the devices in this example. The modules in the foregoing examples can be combined into one module or furthermore can be divided into multiple sub-modules.

[0060] Those skilled in the art can understand that the modules in the devices of the embodiments can be adaptively changed and arranged in one or more devices different from this embodiment. The modules or units or groups in the embodiments can be combined into one module or unit or group, and furthermore can be divided into multiple sub-modules or sub-units or sub-groups. Except that at least some of such features and / or processes or units are mutually exclusive, any combination can be adopted to combine all the features disclosed in this specification (including the accompanying claims, abstract and drawings) and all the processes or units of any method or device so disclosed. Unless otherwise explicitly stated, each feature disclosed in this specification (including the accompanying claims, abstract and drawings) can be replaced by an alternative feature that provides the same, equivalent or similar purpose.

[0061] In addition, those skilled in the art can understand that although some of the embodiments described herein include certain features included in other embodiments rather than other features, the combination of the features of different embodiments means that it is within the scope of the present invention and forms different embodiments.

[0062] In addition, some of the embodiments described herein are described as combinations of methods or method elements that can be implemented by a processor of a computer system or by other devices performing the functions. Therefore, a processor having the necessary instructions for implementing the method or method element forms a device for implementing the method or method element. In addition, the elements described herein in the device embodiments are examples of the following devices: the device is used to implement the functions performed by the elements for the purpose of implementing the present invention.

[0063] The various technologies described herein can be implemented in combination with hardware or software, or a combination thereof. Thus, the methods and devices of the present invention, or certain aspects or parts of the methods and devices of the present invention, can take the form of program code (i.e., instructions) embedded in a tangible medium, such as a floppy disk, CD-ROM, hard disk drive, or any other machine-readable storage medium, where when the program is loaded into a machine such as a computer and executed by the machine, the machine becomes a device for practicing the present invention.

[0064] In the case where program code is executed on a programmable computer, a computing device generally includes a processor, a processor-readable storage medium (including volatile and non-volatile memory and / or storage elements), at least one input device, and at least one output device. Among them, the memory is configured to store the program code; the processor is configured to execute the instruction execution method based on read-write locks of the present invention according to the instructions in the program code stored in the memory.

[0065] By way of example, and not limitation, computer-readable media includes computer storage media and communication media. Computer-readable media includes computer storage media and communication media. Computer storage media stores information such as computer-readable instructions, data structures, program modules, or other data. Communication media generally embodies computer-readable instructions, data structures, program modules, or other data in a modulated data signal such as a carrier wave or other transmission mechanism, and includes any information delivery media. A combination of any of the above is also included within the scope of computer-readable media.

[0066] As used herein, unless otherwise specified, the use of ordinal numbers "first", "second", "third", etc. to describe ordinary objects merely indicates different instances of similar objects and is not intended to imply that the objects so described must have a given order in terms of time, space, ranking, or in any other way.

[0067] Although the present invention has been described in terms of a limited number of embodiments, those skilled in the art of this technology will appreciate, from the above description, that other embodiments can be contemplated within the scope of the present invention thus described. In addition, it should be noted that the language used in this specification has been primarily selected for readability and teaching purposes rather than for the purpose of explaining or limiting the subject matter of the present invention. Thus, many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the appended claims. For the scope of the present invention, the disclosure of the present invention is illustrative, not restrictive, and the scope of the present invention is defined by the appended claims.

Claims

1. An instruction execution method based on a read-write lock, suitable for execution in a computing device, the computing device including a processor, an internal memory, and running one or more applications, the storage area of the internal memory being mapped to a storage space, and the applications reading and writing data in the internal memory with storage addresses in the storage space, the method comprising the steps: Submit a first storage instruction of the stored data of the application in the internal memory to the processor; When the processor cannot normally execute the first storage instruction due to the storage address of the data stored by the first storage instruction, generate a second storage instruction according to the data storage exception message generated by the processor, the first storage instruction including an unaligned storage instruction, the second storage instruction being suitable for storing the data to be stored by the first storage instruction, and the processor not generating a data storage exception message when executing the second storage instruction; Obtain a write lock and lock the process of executing the storage instruction; Execute the second storage instruction through the processor to store data in the internal memory; When a first read instruction for reading data in the internal memory is received, obtain a read lock, the write lock and the read lock being mutually exclusive, and when locking according to the write lock or the read lock, data cannot be stored and read simultaneously at the same address; If the write lock is occupied and the read lock cannot be obtained, then obtain the read lock again; If the read lock is obtained, lock the process of executing the read instruction; Execute the first read instruction through the processor to read data from the internal memory; Wherein, generating the second storage instruction according to the data storage exception message generated by the processor includes the steps: Generate a first half storage instruction and a second half storage instruction according to the storage address of the first storage instruction, the first half storage instruction and the second half storage instruction being respectively suitable for storing data according to the first half address and the second half address, and the first half storage instruction and the second half storage instruction being two independent operations; Use the first half storage instruction and the second half storage instruction as the second storage instruction; The method further includes: If a second read instruction is received, submit the second read instruction to the processor, the second read instruction including an unaligned read instruction; When the processor cannot normally execute the second read instruction due to the address of the data read by the second read instruction, generate a first read instruction according to the data access exception message generated by the processor, the first read instruction being suitable for reading the data to be read by the second read instruction, and the processor not generating a data read exception message when executing the first read instruction; Generating the first read instruction according to the data access exception message generated by the processor includes the steps: Generate a first half read instruction and a second half read instruction according to the storage address of the second read instruction, the first half read instruction and the second half read instruction being respectively suitable for reading data according to the first half address and the second half address, and the first half read instruction and the second half read instruction being two independent operations; Use the first half read instruction and the second half read instruction as the first read instruction.

2. The method according to claim 1, wherein, The method further includes the steps of: If the read lock is occupied and the write lock cannot be acquired, then acquire the write lock again; If the write lock is acquired, store data by a second storage instruction.

3. The method according to claim 2, wherein The storing data in the internal memory by executing the second storage instruction by the processor includes the steps of: Generate first half data and second half data according to the data; Execute the first half storage instruction by the processor and store the first half data according to the first half address; Execute the second half storage instruction by the processor and store the second half data according to the second half address.

4. The method according to claim 3, wherein The method further includes the steps of: After storing data in the internal memory by the processor, release the write lock so that other threads of the processor can acquire the read lock and read data.

5. The method according to claim 4, wherein The first read instruction includes a first half read instruction and a second half read instruction. Reading data by the first read instruction includes the steps of: Execute the first half read instruction by the processor and read the stored first half data according to the first half address; Execute the second half read instruction by the processor and read the stored second half data according to the second half address; Combine the first half data read from the first half address and the second half data read from the second half address to obtain data.

6. The method according to claim 5, wherein, The method further includes the steps of: After reading data in the internal memory by the processor, release the read lock so that other threads of the processor can acquire the write lock and store data.

7. The method according to any one of claims 1-6, wherein, The first half storage instruction and the second half storage instruction include alignment storage instructions.

8. The method according to any one of claims 1-6, wherein, The first half read instruction and the second half read instruction include alignment read instructions.

9. A computing device, comprising: One or more processors; A memory; And One or more devices, the one or more devices including instructions for performing the method according to any one of claims 1-8.

10. A computer-readable storage medium storing one or more programs, the one or more programs including instructions which, when executed by a computing device, cause the computing device to perform the method according to any one of claims 1-8.

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