Method and device for analyzing critical failure path of integrated circuit, computer equipment

Abstract

The application relates to an integrated circuit analysis method and device, computer equipment and a storage medium. The method comprises the following steps: acquiring a gate-level netlist corresponding to a digital integrated circuit included in a device to be measured, the gate-level netlist being used for describing a plurality of paths included in the digital integrated circuit and at least one logic gate included in a gate circuit on each path; acquiring path information of each path according to the gate-level netlist; calculating a delay increment of each path according to the path information and a preset device degradation model; calculating a failure time of each path according to the delay increment and a failure boundary condition, and taking a path corresponding to a minimum failure time as a critical failure path of the digital integrated circuit. Through the method, a critical failure path causing reliability degradation in an integrated circuit can be analyzed based on circuit load and timing requirements, so that the path is reinforced at an early design stage, and the reliability of the integrated circuit is improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of integrated circuit detection, in particular to an integrated circuit key failure path analysis method and device, computer equipment and storage medium. BACKGROUND

[0002] Reliability is an important index that integrated circuits need to meet. Due to the influence of reliability degradation effects such as negative bias temperature instability (NBTI) and hot carrier injection (HCI), the threshold voltage of the integrated circuit composed of metal-oxide-semiconductor (MOS) field effect transistors will drift, causing the performance of the device to degrade, and even causing failure. It is crucial to consider the influence of the above reliability effects in the early design of integrated circuits, find the key path of the degradation and failure of the integrated circuit caused by the above effects, and reinforce it to improve the reliability of the integrated circuit.

[0003] Generally, the life of the integrated circuit can be simulated by using a reliability simulation tool. The principle is to obtain test data by performing an accelerated aging test of the device under the effects of HCI, NBTI, etc., extract a reliability degradation model, and analyze the life of the device using simulation software such as a simulation program with integrated circuit emphasis (SPICE). However, the above technology can only obtain the life of the device, and cannot confirm the key failure path. Moreover, the above method is based on SPICE simulation, mainly for analog circuits, and is not suitable for large-scale digital integrated circuits. SUMMARY

[0004] Therefore, it is necessary to provide an integrated circuit key failure path analysis method, device, computer equipment and storage medium to solve the above technical problems.

[0005] An integrated circuit key failure path analysis method, the method comprising:

[0006] Obtaining a gate-level netlist corresponding to a to-be-tested digital integrated circuit, the gate-level netlist being used to describe a plurality of paths included in the digital integrated circuit and at least one logic gate included in a gate circuit on each path, the logic gate including a plurality of devices;

[0007] Obtaining path information of each path according to the gate-level netlist;

[0008] calculating a delay increment of each of the paths according to the path information and a preset device degradation model, wherein the device degradation model is used to represent a threshold voltage degradation amount of a device caused by a negative bias temperature instability or a hot carrier injection effect;

[0009] calculating a failure time of each of the paths according to the delay increment and a failure boundary condition, and taking a path corresponding to a minimum failure time as a critical failure path of the digital integrated circuit.

[0010] In one of the embodiments, the path information at least includes a timing margin of a path, a number of nodes, and a node probability; wherein the calculating a delay increment of each of the paths according to the path information and a preset device degradation model comprises:

[0011] obtaining working state information of a device to be tested; wherein the working state information of the device to be tested at least includes a working voltage and a threshold voltage of the device to be tested;

[0012] calculating a stress time of each of the logic gates on each of the paths according to the node probability;

[0013] calculating a threshold voltage degradation amount of the device according to the stress time and the device degradation model;

[0014] calculating a delay increment of each of the logic gates according to the threshold voltage degradation amount of the device and the working state information of the device;

[0015] adding the delay increment of each of the logic gates on each of the paths to obtain the delay increment of each of the paths.

[0016] In one of the embodiments, the node probability includes a probability of the logic gate input being 0 based on a negative bias temperature instability effect, and a probability of the logic gate input being flipped based on a hot carrier injection effect.

[0017] In one of the embodiments, the calculating a stress time of each of the logic gates on each of the paths according to the node probability comprises:

[0018] the stress time is a product of the probability of the logic gate input being 0 and a total working time of the device to be tested based on the negative bias temperature instability effect;

[0019] the stress time is a product of the probability of the logic gate input being flipped and the total working time of the device to be tested based on the hot carrier injection effect.

[0020] In one of the embodiments, the failure boundary condition is that the delay increment of the path caused by the negative bias temperature instability or the hot carrier injection effect is equal to the timing margin of the path.

[0021] In one of the embodiments, the calculating the failure time of each of the paths according to the delay increment and the failure boundary condition comprises:

[0022] According to the delay increment, the timing margin and the failure boundary condition, the total working time of the device under test at the time of failure is calculated, and the total working time of the device under test at the time of failure is confirmed as the failure time of the device.

[0023] In one of the embodiments, the path corresponding to the minimum failure time is taken as the critical failure path of the digital integrated circuit.

[0024] The failure times of each of the paths under the influence of the negative bias temperature instability effect are compared to obtain a first minimum failure time;

[0025] The failure times of each of the paths under the influence of the hot carrier injection effect are compared to obtain a second minimum failure time;

[0026] The first minimum failure time and the second minimum failure time are compared to obtain a third minimum failure time, and the path corresponding to the third minimum failure time is taken as the critical failure path of the device under test.

[0027] An analysis device of an integrated circuit, the device comprising:

[0028] A first obtaining module is configured to obtain a gate-level netlist corresponding to a digital integrated circuit under test, the gate-level netlist being used to describe a plurality of paths included in the digital integrated circuit and at least one logic gate included in a gate circuit on each path, the logic gate comprising a plurality of devices;

[0029] A second obtaining module is configured to obtain path information of each path according to the gate-level netlist, the path information at least comprising a timing margin of the path, a number of nodes and a node probability;

[0030] A first calculating module is configured to calculate a delay increment of each of the paths according to the path information and a preset device degradation model, wherein the device degradation model is used to represent a threshold voltage degradation amount caused by a negative bias temperature instability or a hot carrier injection effect;

[0031] A second calculating module is configured to calculate a failure time of each of the paths according to the delay increment and a failure boundary condition, and to take a path corresponding to a minimum failure time as a critical failure path of the device under test.

[0032] A computer device comprising a memory and a processor, the memory storing a computer program, characterized in that the processor implements the steps of the integrated circuit analysis method when executing the computer program.

[0033] A computer readable storage medium, having stored thereon a computer program, wherein the computer program is executed by a processor to implement the steps of the integrated circuit analysis method.

[0034] The integrated circuit analysis method, device, computer equipment and storage medium consider the device reliability degradation caused by HCI, NBTI and other effects, obtain the gate-level netlist corresponding to the device under test, and obtain the path information based on the gate-level netlist, calculate the delay increment of each path according to the path information and the preset device degradation model, calculate the failure time of each path according to the delay increment and the failure boundary condition, compare the failure time of each path, and analyze the key failure path in the integrated circuit which causes reliability degradation. BRIEF DESCRIPTION OF DRAWINGS

[0035] Figure 1 A schematic diagram of the paths of an integrated circuit in an embodiment;

[0036] Figure 2 A schematic diagram of the flow of the integrated circuit analysis method in an embodiment;

[0037] Figure 3 A schematic diagram of the flow of the integrated circuit analysis method in an embodiment;

[0038] Figure 4 A schematic diagram of the flow of the integrated circuit analysis method in another embodiment;

[0039] Figure 5 A structural block diagram of the integrated circuit analysis device in an embodiment;

[0040] Figure 6 A structural block diagram of the integrated circuit analysis device in an embodiment;

[0041] Figure 7 A structural block diagram of the integrated circuit analysis device in an embodiment. DETAILED DESCRIPTION

[0042] In order to make the purposes, technical solutions and advantages of the present application clearer, the present application is further described in detail below with reference to the drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and not to limit the present application.

[0043] The integrated circuit analysis method provided by the present application can be applied to an integrated circuit as shown in Figure 1 The integrated circuit includes a plurality of paths 102, each path 102 including a plurality of logic gates 104, and the plurality of paths are denoted as Path1, Path2,..., Path i ,..., Pathn. wherein i is an integer greater than or equal to 1 and less than or equal to n; the ith path Path i The number of logic gates 104 included is m, denoted as {G j}, wherein j is an integer greater than or equal to 1 and less than or equal to m.

[0044] In one embodiment, as Figure 2 shown, a method for analyzing an integrated circuit is provided, which is applied to an integrated circuit in Figure 1 for example, and includes steps 202 to 208.

[0045] Step 202, obtaining a gate-level netlist corresponding to a digital integrated circuit to be tested, the gate-level netlist being used to describe a plurality of paths 102 included in the digital integrated circuit and at least one logic gate 104 included in a gate circuit on each path 102, the logic gate including a plurality of devices.

[0046] Wherein, the integrated circuit to be tested can be a digital integrated circuit mainly composed of metal-oxide-semiconductor (MOS) field effect transistors. By performing logic synthesis on the digital integrated circuit, for example, converting a digital integrated circuit described by an RTL-level netlist, the gate-level netlist corresponding to the digital integrated circuit can be obtained.

[0047] Step 204, obtaining path information of each path according to the gate-level netlist.

[0048] Wherein, the path information at least includes timing slack i , number of nodes, and node probability P0 i,j or Pt i,j The path information can be directly calculated by electronic design automation (EDA) simulation software or the like.

[0049] Step 206, calculating a delay increment At d,i of each path according to the path information and a preset device degradation model; wherein the device degradation model is used to represent a threshold voltage degradation amount AVt caused by negative bias temperature instability (NBTI) or hot carrier injection effect (HCI).

[0050] Wherein, the degradation model is obtained in advance by testing for NBTI or HCI effect. Under the influence of NBTI or HCI effect, the device will cause threshold voltage degradation due to stress, thereby further causing the device delay to increase. Therefore, the path information obtained by EDA simulation software or the like and the preset device degradation model can be combined to calculate the delay increment At d,i.

[0051] Step 208, calculating the failure time T of each path according to the delay increment Δt d,i and the failure boundary condition f,i , and taking the path corresponding to the minimum failure time as the critical failure path of the digital integrated circuit.

[0052] Wherein, the failure boundary condition is directly related to the delay increment Δt d,i , and the delay increment Δt d,i is related to the total working time T W,i of the device, and the total working time T W,i of the device when failure occurs can be determined according to the failure boundary condition, that is, the failure time T f,i of the device; comparing the failure time of each path obtained to obtain the minimum value, and the path corresponding to the minimum value fails first, which can be determined as the critical failure path of the device under test.

[0053] In the above integrated circuit analysis method, considering the reliability degradation of the device caused by HCI, NBTI and other effects, the path information is obtained based on the gate-level netlist corresponding to the device under test, the delay increment of each path is calculated according to the path information and the preset device degradation model, the failure time of each path is calculated according to the delay increment and the failure boundary condition, and the critical failure path caused by reliability degradation in the circuit can be analyzed by comparing the failure time of each path.

[0054] In one embodiment, as shown in Figure 3 , the path information at least includes the timing slack slack i , the number of nodes and the node probability of the path.

[0055] Wherein, the timing slack slack i of the path i can be calculated by simulation software, and its meaning is:

[0056] slack i = T required -T arrived (1)

[0057] Wherein, T required represents the required arrival time of data; T arrived represents the preset arrival time of data.

[0058] The logic gate is connected through nodes, and the number of nodes is related to the number of logic gates.

[0059] The node probability includes the probability P0 i,j of the logic gate input being 0 based on NBTI effect.and the probability Pt of the input of the logic gate being flipped based on the HCI effect i,j .

[0060] The calculating of the delay increment of each path according to the path information and a preset device degradation model comprises steps 302 to 310.

[0061] In step 302, the working state information of the device to be measured is acquired; the working state information of the device to be measured comprises at least a working voltage Vdd and a threshold voltage Vt of the device to be measured.

[0062] The working voltage Vdd can be read by simulation software, and the threshold voltage Vt is the input voltage corresponding to the midpoint of the sharp change transition zone of the output current with the input voltage in the device transfer characteristic curve, and is known for a certain device. Further, the working state information of the device can further comprise a constant β related to the device process and a speed saturation factor α. g .

[0063] In step 304, the stress time of each logic gate on each path is calculated according to the node probability.

[0064] The stress of the jth logic gate is related to the node probability and the total working time of the device, so the stress time of each logic gate on each path can be calculated according to the node probability. Specifically, when the total working time of the device is T W,i , the stress time t is the product of the total working time T W,i and the node probability.

[0065] In step 306, the threshold voltage degradation of the device is calculated according to the stress time and the device degradation model.

[0066] The device degradation model is used to represent the threshold voltage degradation of the MOS device caused by the HCI and NBTI effects, and specifically, the device degradation model can be represented by the following function relationship:

[0067] ΔVt=At p (2)

[0068] Wherein, ΔVt represents the threshold voltage degradation of the device; A is a parameter related to the material and process of the device, and is represented as A N , A H for NBTI and HCI effects respectively; t is the stress time; p is an exponential constant determined by the device degradation model, and is represented as p N , p H for NBTI and HCI effects respectively.

[0069] Step 308, calculating the delay increment of each logic gate according to the device threshold voltage degradation and the device working state information.

[0070] MOS devices will cause their threshold voltage to degrade due to the influence of HCI, NBTI effect, which further leads to the increase of device delay, wherein the delay increment of each logic gate is Δt d,i,j The following function relationship can be used to express:

[0071]

[0072] Wherein, Δt d,i,j represents the delay increment of the jth logic gate on the ith path; Vdd represents the working voltage of the device; Vt is the threshold voltage of the device; β g is a physical constant related to the device process, and α is a speed saturation factor; ΔVt j is the threshold voltage degradation of the device.

[0073] Step 310, adding the delay increment of each logic gate on each path to obtain the delay increment of each path.

[0074] Since each path contains m logic gates, each logic gate may cause its delay to increase due to stress, so the delay increment of each path is the sum of the delay increments caused by each logic gate. Specifically, the delay increment of each path Δt d,i can be expressed as:

[0075]

[0076] Wherein, Δt d,i represents the delay increment of the jth logic gate on the ith path; Vdd represents the working voltage of the device; Vt is the threshold voltage of the device; β g is a physical constant related to the device process, and α is a speed saturation factor; ΔVt j is the threshold voltage degradation of the device. In this embodiment, the time of each logic gate applying stress is calculated according to the node probability, and the threshold voltage degradation of the device is further calculated, and the delay increment of each path can be obtained by combining the device working state information obtained by the simulation software, which provides a calculation basis for the subsequent failure time calculation.

[0077] In one embodiment, the node probability includes the probability P0 i,j of the logic gate input being 0 based on NBTI effect, and the probability Pt i,j of the logic gate input flipping based on HCI effect.

[0078] Wherein, when the logic gate input is 0, the device is affected by NBTI effect, thus leading to failure, therefore, when calculating based on NBTI effect, the node probability specifically refers to the probability P0 that the logic gate input is 0 i,j Since in the circuit, the input of the logic gate is connected through nodes, therefore, it can also represent the probability that the jth node in the path i is 0; when the logic gate occurs level conversion, including the input state is flipped from 1 to 0 and from 0 to 1, the device is affected by HCI effect, thus leading to failure, therefore, when calculating based on HCI effect, the node probability specifically refers to the probability Pt that the logic gate input is flipped i,j .

[0079] In the embodiment, the node probability is considered based on NBTI and HCI effects respectively, which provides a basis for further calculating the stress time of the logic gate based on the two effects respectively.

[0080] In one embodiment, the stress time of each logic gate on each path is calculated according to the node probability, which includes:

[0081] Based on NBTI effect, the stress time is the product of the probability that the logic gate input is 0 and the total working time of the device under test, that is,

[0082] t j,N = T W,i P0 i,j (5)

[0083] Wherein, t j,N represents the stress time of the jth logic gate based on NBTI effect, T W,i represents the total working time of the device, P0 i,j represents the probability that the jth logic gate input of the ith path is 0. Based on HCI effect, the stress time is the product of the probability that the logic gate input is flipped and the total working time of the device under test, that is,

[0084] t j,H = T W,i Pt i,j (6)

[0085] Wherein, t j,H represents the stress time of the jth logic gate based on HCI effect, T W,i represents the total working time of the device, Pt i,j represents the probability that the jth logic gate input of the ith path is flipped.

[0086] In the embodiment, the stress time of the logic gate is calculated based on NBTI and HCI effects respectively, which provides a basis for further calculating the threshold voltage degradation of the device based on the two effects respectively.

[0087] In one embodiment, the failure boundary condition is the delay increment Δt of the path caused by the NBTI or HCI effect. d,i With the timing margin slack of the path i equal.

[0088] The timing margin slack of path i i Its meaning is:

[0089] Slack i =T required -T arrived (1)

[0090] Among them, T required Indicates the required arrival time of the data; T arrived This indicates the preset arrival time of the data; for path i, the data travels through the entire path at the input end and must arrive at the required time T after a certain period of time. required The internal circuitry must reach the output terminal; otherwise, the function will not be normal. In other words, to ensure the normal functioning of a digital integrated circuit, slack is required. i It must be greater than 0, otherwise it will cause timing errors and device malfunctions. (This is related to slack.) i When the value is 0, the path does not meet the timing requirements, the path fails, and thus the device fails.

[0091] The delay increment Δt d,i The actual arrival time of the data relative to the preset arrival time of the data, when the delay increment Δt of the path. d,i With the timing margin slack of the path i When they are equal, that is

[0092] Slack i =Δt d,i (7)

[0093] If the actual arrival time of the data is equal to the required arrival time, then this is the boundary condition for the path to fail.

[0094] In this embodiment, the delay increment Δt of the path is used. d,i With the timing margin slack of the path i Analysis was conducted to determine the failure boundary conditions of path i contained in the digital integrated circuit, so as to further calculate the failure time based on the failure boundary conditions.

[0095] In one embodiment, the calculating the failure time of each path according to the delay increment and the failure boundary condition comprises calculating the total working time of the device under test when the device fails according to the delay increment, the timing slack, and the failure boundary condition, and confirming the total working time of the device under test when the device fails as the failure time of the device.

[0096] The delay increment Δt d,i of the path (Formula 4) and the timing slack slack i of the path are substituted into the failure boundary condition (Formula 7). Since the failure boundary condition defines the condition met when the device fails, T W,i calculated according to the failure boundary condition is the failure time T f,i of the device under test.

[0097] Specifically, based on the NBTI effect, the failure time is:

[0098]

[0099] Based on the HCI effect, the failure time is:

[0100]

[0101] wherein T f,i,N represents the failure time of the path i based on the NBTI effect, T f,i,H represents the failure time of the path i based on the HCI effect, Vdd represents the working voltage of the device, Vt represents the threshold voltage of the device, β g , α, A N , A H are physical constants related to the device process; P0 i,j represents the probability that the input of the jth logic gate of the ith path is 0; Pt i,j represents the probability that the input of the jth logic gate of the ith path is flipped; p N , p H are exponential constants determined by the device degradation model for the NBTI and HCI effects, respectively.

[0102] In this embodiment, the delay increment Δt d,i of the path, the timing slack slack i of the path, and the failure boundary condition are processed, achieving the purpose of calculating the failure time of the device under the influence of the NBTI effect and the HCI effect, respectively.

[0103] In one embodiment, the step of taking the path corresponding to the minimum failure time as the critical failure path of the digital integrated circuit comprises the steps of: comparing the failure times of each path under the influence of NBTI effect to obtain a first minimum failure time; comparing the failure times of each path under the influence of HCI effect to obtain a second minimum failure time; comparing the first minimum failure time and the second minimum failure time to obtain a third minimum failure time, and taking the path corresponding to the third minimum failure time as the critical failure path of the device under test.

[0104] The present solution considers both NBTI and HCI effects, and obtains a first minimum failure time and a second minimum failure time by solving for NBTI and HCI effects respectively. For the same device, the influences of the two effects should be considered simultaneously, and the smaller one is taken as the third minimum failure time. In the entire integrated circuit, the path corresponding to the third minimum failure time fails first, and thus it is identified as the critical failure path. Alternatively, the path corresponding to the third minimum failure time can be multiple, and the critical failure path is the multiple paths corresponding to the third minimum failure time.

[0105] In the present embodiment, the minimum failure time is obtained by calculating the minimum failure time under the influence of NBTI and HCI effects respectively and considering both effects for the same device, and the effect of determining the critical failure path of the device based on the minimum failure time is achieved, thereby providing guidance for reinforcing the critical failure path at the early stage of design and improving the reliability of the integrated circuit.

[0106] In one embodiment, as shown in FIG. 4, a method for analyzing the critical failure path of an integrated circuit is provided, and the method comprises steps 402 to 418. Figure 4

[0107] Step 402: performing logic synthesis on the RTL netlist description of the digital integrated circuit to obtain a gate-level netlist.

[0108] Step 404: obtaining path information of each path according to the gate-level netlist; the path information at least comprises timing slack of the path, number of nodes, and node probabilities P0 and Pt. i i,j i,j

[0109] Step 406: obtaining working state information of the device under test; the working state information of the device at least comprises working voltage Vdd, threshold voltage Vt, β, and α of the device under test. g

[0110] ​​​​​Step 408, calculating stress time t of each logic gate on each path according to the node probability.

[0111] Based on NBTI effect, the stress time is

[0112] t j,N = T W,i P0 i,j (10)

[0113] Based on HCI effect, the stress time is

[0114] t j,H = T W,i Pt i,j (11)

[0115] Wherein, T W,i is total working time of device path i, P0 i,j represents probability of input of jth logic gate in ith path being 0, Pt i,j represents probability of input of jth logic gate in ith path being flip.

[0116] Step 410, calculating device threshold voltage degradation amount according to the stress time and the device degradation model.

[0117] Based on NBTI effect, the device threshold voltage degradation amount ΔVt j,N is

[0118]

[0119] Based on HCI effect, the device threshold voltage degradation amount ΔVt j,H is

[0120]

[0121] Step 412, calculating delay increment of each logic gate according to the device threshold voltage degradation amount and the device working state information.

[0122] Based on NBTI effect, the delay increment Δt d,j,N of jth logic gate is represented as

[0123]

[0124] Based on HCI effect, the delay increment Δt d,j,H of jth logic gate is represented as

[0125]

[0126] Step 414, adding the delay increment of each logic gate on each path to obtain the delay increment of each path.

[0127] Based on NBTI effect, the delay increment of path i Δt d,i,N is expressed as

[0128]

[0129]

[0130] Based on HCI effect, the delay increment of path i Δt d,i,H is expressed as

[0131]

[0132] Step 416, substituting the delay increment Δt d,i (formula 16 or 17) into the timing slack slack i , and substituting the slack into the failure boundary condition slack i = Δt d,i to solve the failure time.

[0133] Based on NBTI effect, from we can obtain:

[0134]

[0135] Then the failure time T f,i,N of path i based on NBTI effect is

[0136]

[0137] Based on HCI effect, from we can obtain:

[0138]

[0139] Then the failure time T f,i,H of path i based on HCI effect is

[0140]

[0141] Step 418, comparing the failure time of each path under the influence of NBTI effect to obtain the first minimum failure time T fail,1 ; comparing the failure time of each path under the influence of HCI effect to obtain the second minimum failure time T fail,2 ; comparing the first minimum failure time T fail,1 and the second minimum failure time T fail,2 to obtain the third minimum failure time Tfail,3 And the third minimum failure time T fail,3 The corresponding path serves as the critical failure path for the device under test.

[0142]

[0143]

[0144] T fail,3 =min{T fail,1 T fail,2} (twenty four)

[0145] Then T fail,3 The corresponding path is the critical failure path of the device under test.

[0146] In this embodiment, device reliability degradation caused by HCI, NBTI, and other effects is considered respectively. By obtaining the gate-level netlist corresponding to the device under test and obtaining path information based on the gate-level netlist, the delay increment of each path is calculated according to the path information and the preset device degradation model. The failure time of each path is calculated according to the delay increment and the failure boundary condition. By comparing the failure time of each path, the critical failure paths in the circuit caused by reliability degradation can be analyzed.

[0147] It should be understood that, although Figures 1-4 The steps in the flowchart are shown sequentially as indicated by the arrows, but these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified herein, there is no strict order in which these steps are executed, and they can be performed in other orders. Figures 1-4 At least some of the steps in the process may include multiple steps or multiple stages. These steps or stages are not necessarily completed at the same time, but may be executed at different times. The execution order of these steps or stages is not necessarily sequential, but may be executed in turn or alternately with other steps or at least some of the steps or stages in other steps.

[0148] In one embodiment, such as Figure 5 As shown, an integrated circuit analysis device is provided. The device includes a first acquisition module 502, a second acquisition module 504, a first calculation module 506, and a second calculation module 508, wherein:

[0149] The first acquisition module 502 is used to acquire the gate-level netlist corresponding to the digital integrated circuit under test. The gate-level netlist is used to describe the multiple paths included in the digital integrated circuit and the gate circuits on each path include at least one logic gate. The logic gate includes multiple devices.

[0150] The second acquisition module 504 is used to acquire path information for each path according to the gate-level netlist. The path information includes at least the path's time margin, number of nodes, and node probability.

[0151] The first calculation module 506 is used to calculate the delay increment of each path according to the path information and the preset device degradation model; wherein, the device degradation model is used to characterize the device threshold voltage degradation caused by negative bias temperature instability or hot carrier injection effect;

[0152] The second calculation module 508 is used to calculate the failure time of each path based on the delay increment and failure boundary conditions, and to take the path corresponding to the minimum failure time as the critical failure path of the device under test.

[0153] In this embodiment, device reliability degradation caused by HCI, NBTI, and other effects are considered respectively. The first acquisition module 502 acquires the gate-level netlist corresponding to the device under test, the second acquisition module 504 acquires the path information based on the gate-level netlist, the first calculation module 506 calculates the delay increment of each path according to the path information and the preset device degradation model, and the second calculation module 508 calculates the failure time of each path according to the delay increment and the failure boundary condition. By comparing the failure times of each path, the critical failure paths in the circuit caused by reliability degradation can be analyzed.

[0154] In one embodiment, such as Figure 6 As shown, the first calculation module 506 includes a first acquisition unit 602, a first calculation unit 604, a second calculation unit 606, a third calculation unit 608, and a fourth calculation unit 610.

[0155] The first acquisition unit 602 is used to acquire the operating status information of the device under test; the operating status information of the device under test includes at least the operating voltage and threshold voltage of the device under test.

[0156] The first calculation unit 604 is used to calculate the stress time of each logic gate on each path according to the node probability;

[0157] The second calculation unit 606 is used to calculate the device threshold voltage degradation amount based on the stress time and the device degradation model;

[0158] The third calculation unit 608 is used to calculate the delay increment of each logic gate based on the device threshold voltage degradation amount and the device operating state information;

[0159] The fourth calculation unit 610 is used to add the delay increments of each logic gate on each path to obtain the delay increment of each path.

[0160] In one embodiment, as shown in FIG. 7, the second calculating module 508 comprises a fifth calculating unit 702, a first comparing unit 704, a second comparing unit 706 and a third comparing unit 708. Figure 7

[0161] The fifth calculating unit 702 is configured to calculate the total working time of the device under test at the time of failure according to the delay increment, the timing margin and the failure boundary condition, and confirm the total working time of the device under test at the time of failure as the failure time of the device.

[0162] The first comparing unit 704 is configured to compare the failure times of each of the paths under the influence of the negative bias temperature instability effect to obtain a first minimum failure time.

[0163] The second comparing unit 706 is configured to compare the failure times of each of the paths under the influence of the hot carrier injection effect to obtain a second minimum failure time.

[0164] The third comparing unit 708 is configured to compare the first minimum failure time and the second minimum failure time to obtain a third minimum failure time, and take the path corresponding to the third minimum failure time as the critical failure path of the device under test.

[0165] The specific definitions of the integrated circuit analysis apparatus can refer to the definitions of the integrated circuit analysis method, which will not be repeated here. Each module in the above integrated circuit analysis apparatus can be realized by software, hardware and a combination thereof in whole or in part. Each module can be embedded in or independent of the processor in the computer device in hardware form, or can be stored in the memory in the computer device in software form, so as to be called and executed by the processor to perform the operations corresponding to each module.

[0166] In one embodiment, a computer device is provided, comprising a memory and a processor, the memory stores a computer program, and the processor executes the computer program to realize the steps in each method embodiment.

[0167] In one embodiment, a computer readable storage medium is also provided, which stores a computer program, and the computer program is executed by a processor to realize the steps in each method embodiment.

[0168] ​Those skilled in the art can understand that all or part of the processes in the above-mentioned embodiment methods can be completed by instructing the relevant hardware through a computer program. The computer program can be stored in a non-volatile computer readable storage medium, and when executed, can include the processes of the above-mentioned embodiment methods. Any reference to memory, storage, database or other medium used in the embodiments provided in the present application can include at least one of non-volatile and volatile memory. Non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory or optical memory. Volatile memory can include random access memory (RAM) or external cache memory. As an illustration but not limitation, RAM can be in various forms, such as static random access memory (SRAM) or dynamic random access memory (DRAM).

[0169] Any combination of the technical features of the above embodiments can be made. In order to make the description simple, all possible combinations of the technical features in the above embodiments are not described, but as long as the combination of the technical features does not exist, it should be considered as the scope of the present application.

[0170] The above embodiments only express several implementation manners of the present application, and the description is more specific and detailed, but it should not be understood as a limitation on the scope of the patent. It should be pointed out that for those skilled in the art, without departing from the concept of the present application, some modifications and improvements can be made, which are all within the protection scope of the present application. Therefore, the protection scope of the patent of the present application should be subject to the appended claims.

Claims

1. An analysis method of an integrated circuit, characterized by, The method comprises: acquiring a gate-level netlist corresponding to a digital integrated circuit to be tested, the gate-level netlist being used to describe a plurality of paths included in the digital integrated circuit and at least one logic gate included in a gate circuit on each path, the logic gate comprising a plurality of devices; acquiring path information of each path according to the gate-level netlist; calculating a delay increment of each path according to the path information and a preset device degradation model, wherein the device degradation model is used to represent a device threshold voltage degradation amount caused by a negative bias temperature instability or a hot carrier injection effect; calculating a failure time of each path according to the delay increment and a failure boundary condition, and taking a path corresponding to a minimum failure time as a critical failure path of the digital integrated circuit; wherein the path information at least comprises a timing margin of a path, a number of nodes and a node probability; the calculation of the delay increment of each path according to the path information and the preset device degradation model comprises: acquiring working state information of a device to be tested, the working state information of the device at least comprising a working voltage and a threshold voltage of the device to be tested; calculating a stress time of each logic gate on each path according to the node probability; calculating the device threshold voltage degradation amount according to the stress time and the device degradation model; calculating a delay increment of each logic gate according to the device threshold voltage degradation amount and the working state information of the device; adding the delay increments of each logic gate on each path to obtain the delay increment of each path.

2. The method of claim 1, wherein, The node probability comprises a probability of the logic gate input being 0 based on the negative bias temperature instability effect and a probability of the logic gate input being flipped based on the hot carrier injection effect.

3. The method of claim 2, wherein, The calculation of the stress time of each logic gate on each path according to the node probability comprises: the stress time being a product of the probability of the logic gate input being 0 and a total working time of the device to be tested based on the negative bias temperature instability effect; the stress time being a product of the probability of the logic gate input being flipped and the total working time of the device to be tested based on the hot carrier injection effect.

4. The method of claim 1, wherein, The failure boundary condition is that the delay increment of the path caused by the negative bias temperature instability or the hot carrier injection effect is equal to the timing margin of the path.

5. The method of claim 1, wherein, The calculation of the failure time of each path according to the delay increment and the failure boundary condition comprises: calculating the total working time of the device to be tested when the device fails according to the delay increment, the timing margin and the failure boundary condition, and confirming the total working time of the device to be tested when the device fails as the failure time of the device.

6. The method of claim 1, wherein, The taking of the path corresponding to the minimum failure time as the critical failure path of the digital integrated circuit comprises: comparing the failure times of each path under the influence of the negative bias temperature instability effect to obtain a first minimum failure time; comparing the failure times of each path under the influence of the hot carrier injection effect to obtain a second minimum failure time; The first minimum failure time and the second minimum failure time are compared to obtain a third minimum failure time, and a path corresponding to the third minimum failure time is taken as a critical failure path of the device under test.

7. An analysis device of an integrated circuit, characterized by comprising: The device comprises: The first obtaining module is configured to obtain a gate-level netlist corresponding to a digital integrated circuit under test, the gate-level netlist being used to describe a plurality of paths included in the digital integrated circuit and at least one logic gate included in a gate circuit on each path, the logic gate including a plurality of devices; The second obtaining module is configured to obtain path information of each path according to the gate-level netlist, the path information at least including a timing margin, a number of nodes, and a node probability of the path; The first calculating module is configured to calculate a delay increment of each path according to the path information and a preset device degradation model, the device degradation model being used to represent a threshold voltage degradation amount of a device caused by a negative bias temperature instability or a hot carrier injection effect; The second calculating module is configured to calculate a failure time of each path according to the delay increment and a failure boundary condition, and take a path corresponding to a minimum failure time as a critical failure path of the digital integrated circuit; The first calculating module comprises a first obtaining unit, a first calculating unit, a second calculating unit, a third calculating unit, and a fourth calculating unit. The first obtaining unit is configured to obtain working state information of a device under test, the working state information of the device at least including a working voltage and a threshold voltage of the device under test; The first calculating unit is configured to calculate a stress time of each logic gate on each path according to the node probability; The second calculating unit is configured to calculate the threshold voltage degradation amount of the device according to the stress time and the device degradation model; The third calculating unit is configured to calculate a delay increment of each logic gate according to the threshold voltage degradation amount of the device and the working state information of the device; The fourth calculating unit is configured to add the delay increment of each logic gate on each path to obtain the delay increment of each path.

8. The integrated circuit analysis apparatus according to claim 7, characterized by The second calculating module comprises a fifth calculating unit, a first comparing unit, a second comparing unit, and a third comparing unit. The fifth calculating unit is configured to calculate a total working time of the device under test when the device under test fails according to the delay increment, the timing margin, and the failure boundary condition, and confirm the total working time of the device under test when the device under test fails as a failure time of the device. The first comparing unit is configured to compare the failure times of each path under the influence of a negative bias temperature instability effect to obtain a first minimum failure time. The second comparing unit is configured to compare the failure times of each path under the influence of a hot carrier injection effect to obtain a second minimum failure time. The third comparing unit is configured to compare the first minimum failure time and the second minimum failure time to obtain a third minimum failure time, and take a path corresponding to the third minimum failure time as a critical failure path of the device under test. 9.A computer device, comprising a memory and a processor, wherein the memory stores a computer program, and the computer device is configured to perform the method according to any one of claims 1-8 when the computer program is executed by the processor. The processor implements the steps of the method of any one of claims 1 to 6 when executing the computer program.

10. A computer-readable storage medium having stored thereon a computer program, characterized in that, The computer program, which is executed by a processor, implements the steps of the method according to any one of claims 1 to 6.

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