Resistive random access memory and manufacturing method thereof

Abstract

The present invention provides a resistance random access memory and a manufacturing method thereof. The resistance random access memory comprises a first electrode layer and a second electrode layer, which are arranged opposite to each other; a variable resistance layer, which is located between the first electrode layer and the second electrode layer; an oxygen exchange layer, which is located between the variable resistance layer and the second electrode layer; a conductor layer, which laterally surrounds the side wall of the oxygen exchange layer; a first barrier layer, which is located between the conductor layer and the oxygen exchange layer and between the oxygen exchange layer and the variable resistance layer; and a second barrier layer, which is located between the conductor layer and the second electrode layer and between the second electrode layer and the oxygen exchange layer.

Description

Technical Field

[0001] The present invention relates to a memory and a manufacturing method thereof, and in particular to a resistive random access memory (RRAM) and a manufacturing method thereof. Background Art

[0002] RRAM has the advantages of fast operation speed and low power consumption, and has become a widely studied non-volatile memory in recent years. However, the etchant used in the manufacturing process of RRAM, or in the deposition process of the dielectric layer or in the detection process, can easily cause the sidewall of the oxygen exchange layer to oxidize, resulting in different effective areas of the oxygen exchange layers of multiple RRAMs, causing uneven oxygen distribution, resulting in uneven RRAM forming current distribution, and affecting the reliability of RRAM. Summary of the invention

[0003] The present invention is directed to a resistance random access memory and a manufacturing method thereof, which can prevent the side wall of an oxygen exchange layer from being oxidized.

[0004] According to an embodiment of the present invention, a resistance random access memory and a manufacturing method thereof are provided, which can control the oxygen exchange layer to have substantially the same effective area to uniformly distribute oxygen, so that the RRAM can have a uniform formation current distribution.

[0005] According to an embodiment of the present invention, a resistive random access memory is also provided, comprising a first electrode layer and a second electrode layer, which are arranged opposite to each other; a variable resistance layer, located between the first electrode layer and the second electrode layer; an oxygen exchange layer, located between the variable resistance layer and the second electrode layer; a conductor layer, laterally surrounding the side wall of the oxygen exchange layer; a first barrier layer, located between the conductor layer and the oxygen exchange layer and between the oxygen exchange layer and the variable resistance layer; and a second barrier layer, located between the conductor layer and the second electrode layer and between the second electrode layer and the oxygen exchange layer.

[0006] According to an embodiment of the present invention, a method for manufacturing a resistive random access memory is also provided, comprising: forming a variable resistance layer on a first electrode layer; forming a conductor layer on the variable resistance layer; forming an opening in the conductor layer; forming a first blocking layer and an oxygen exchange layer in the opening; forming a second blocking layer on the conductor layer and the oxygen exchange layer; and forming a second electrode layer on the blocking layer.

[0007] Based on the above, the present invention provides a resistive random access memory and a manufacturing method thereof, which can prevent the sidewall of the oxygen exchange layer from being oxidized, and can control the oxygen exchange layer to have substantially the same effective area to uniformly distribute oxygen, so that the RRAM can have a uniform formation current distribution. In addition, when performing a SET operation, in addition to the formation current generated by the formation of the filaments, FN tunneling can also be induced between the variable resistance layer and the conductor layer around the oxygen exchange layer, and the leakage current caused can increase the total current. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figures 1A to 1F It is a cross-sectional schematic diagram of a manufacturing process of a resistance random access memory according to an embodiment of the present invention. DETAILED DESCRIPTION

[0009] Reference will now be made in detail to exemplary embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Whenever possible, the same reference numerals are used in the drawings and the description to refer to the same or like parts.

[0010] Please refer to Figure 1F The resistive random access memory (RRAM) cell 10 includes a first electrode 102a, a variable resistance layer 104a, a conductor layer 106a, an oxygen exchange layer 112, a first barrier layer 110, a second barrier layer 114a, and a second electrode 116a.

[0011] The first electrode 102a may be connected to the via 100. The via 100 is, for example, any via of a metal interconnect structure formed on a substrate, for example, a via at the same height as a first via in contact with a first metal layer closest to the substrate. The substrate may be a semiconductor substrate or a semiconductor-on-insulator (SOI) substrate. Other components, such as transistors, may be included between the substrate and the first metal layer. The second electrode 116a may be connected to the via 120. The via 120 is, for example, any via of a metal interconnect structure, for example, a via at the same height as a second via in contact with a second metal layer. The vias 100 and 120 are, for example, tungsten, aluminum, copper, or a combination thereof formed by physical vapor deposition.

[0012] The materials of the first electrode layer 102a and the second electrode 116a may include metal, metal nitride, other materials or a combination thereof. The materials of the first electrode layer 102a and the second electrode 116a are, for example, titanium nitride (TiN), tantalum nitride (TaN), titanium aluminum nitride (TiAlN), titanium tungsten (TiW) alloy, platinum (Pt), iridium (Ir), ruthenium (Ru), titanium (Ti), tungsten (W), tantalum (Ta), aluminum (Al), zirconium (Zr), hafnium (Hf), nickel (Ni), copper (Cu), cobalt (Co), iron (Fe), gadolinium (Gd), manganese (Mo), graphite or a combination of the above materials, and the formation method may be, for example, physical vapor deposition or chemical vapor deposition. The first electrode layer 102a and the second electrode 116a may be a single layer or a multilayer. The thickness of the first electrode layer 102a and the second electrode 116a is not particularly limited, but is generally between 5 nanometers (nm) and 500 nanometers.

[0013] The variable resistance layer 104a is located between the first electrode layer 102a and the second electrode 116a. The variable resistance layer 104a may have the following characteristics: when a positive bias is applied to the resistance random access memory, oxygen ions are attracted by the positive bias to leave the variable resistance layer 104a and generate oxygen vacancy, forming a filament and presenting a conductive state. At this time, the variable resistance layer 104a is converted from a high resistance state (HRS) to a low resistance state (LRS); and when a negative bias is applied to the resistance random access memory, oxygen ions enter the variable resistance layer 104a, causing the filament to break and present a non-conductive state. At this time, the variable resistance layer 104a is converted from LRS to HRS. Generally speaking, the conversion of the variable resistance layer 104a from HRS to LRS is called a set (hereinafter referred to as SET) operation, and the conversion of the variable resistance layer 104a from LRS to HRS is called a reset (hereinafter referred to as RESET) operation. The material of the variable resistance layer 104a is not particularly limited, and any material that can change its own resistance by applying a voltage can be used. In the present embodiment, the material of the variable resistance layer 104a includes a metal oxide, such as hafnium oxide (HfO2), tantalum oxide (Ta2O5), titanium oxide (TiO2), magnesium oxide (MgO), nickel oxide (NiO), niobium oxide (Nb2O5), aluminum oxide (Al2O3), vanadium oxide (V2O5), tungsten oxide (WO3), zinc oxide (ZnO) or cobalt oxide (CoO), and the formation method is, for example, chemical vapor deposition or atomic layer deposition. In the present embodiment, the oxygen content of the variable resistance layer 104a can be about 75 atomic percent (at%) to about 100 atomic percent. The thickness of the variable resistance layer 104a is, for example, 2 nanometers to 10 nanometers.

[0014] The conductive layer 106a, the first barrier layer 110, the oxygen exchange layer 112, and the second barrier layer 114a are located between the variable resistance layer 104a and the second electrode layer 116a. The first barrier layer 110 and the second barrier layer 114a surround and cover the oxygen exchange layer 112. The first barrier layer 110 is located between the conductive layer 106a and the oxygen exchange layer 112, and between the oxygen exchange layer 112 and the variable resistance layer 104a. The second barrier layer 114a is located between the second electrode 116a and the conductive layer 106a, and between the second electrode 116a and the oxygen exchange layer 112. The first barrier layer 110 and the second barrier layer 114a may include a dielectric material layer with a high dielectric constant, such as aluminum oxide (Al2O3), hafnium oxide (HfO2), or zirconium oxide (ZrO2). In this embodiment, when the RRAM cell 10 performs a RESET operation, the first barrier layer 110 and the second barrier layer 114 a can block oxygen ions in the oxygen exchange layer 112 from diffusing to the second electrode 116 .

[0015] The oxygen exchange layer 112 is surrounded and coated by the first barrier layer 110 and the second barrier layer 114a. The sidewalls and bottom surface of the oxygen exchange layer 112 are covered by the first barrier layer 110, and the top surface of the oxygen exchange layer 112 is covered by the second barrier layer 114a. The oxygen exchange layer 112 can be a material that is easier to bond with oxygen than the conductive layer 106a and the variable resistance layer 104a. When the RRAM cell 10 performs a SET operation, the oxygen ions in the variable resistance layer 104a will enter the oxygen exchange layer 112 after being attracted by the positive bias to leave the variable resistance layer 104a; and when the RRAM cell 10 performs a RESET operation, the oxygen ions in the oxygen exchange layer 112 will return to the variable resistance layer 104a. The material of the oxygen exchange layer 112 may include an incompletely oxidized metal oxide. In other words, the oxygen exchange layer 112 itself is a metal layer containing oxygen ions. When the RRAM cell 10 performs a RESET operation, there are enough oxygen ions in the oxygen exchange layer 112 to enter the variable resistance layer 104, because the oxygen exchange layer 112 contains oxygen ions from the variable resistance layer 104a and oxygen ions in the oxygen exchange layer 112. Specifically, in the present embodiment, the material of the oxygen exchange layer 112 may include, for example, TiO 2-x , HfO 2-x or TaO 2-x , wherein x is 0.2 to 0.7. In this embodiment, the top area of ​​the oxygen exchange layer 112 is smaller than the bottom area of ​​the second electrode 116a, and the bottom area of ​​the oxygen exchange layer 112 is smaller than the top area of ​​the variable resistance layer 104a.

[0016] The conductor layer 106a is located between the second barrier layer 114a and the variable resistance layer 104a, and laterally surrounds the sidewalls of the oxygen exchange layer 112 and the first barrier layer 110 to prevent oxygen from diffusing into the oxygen exchange layer 112. In one embodiment, the top surface of the conductor layer 106a is coplanar with the top surface of the first barrier layer 110 and the top surface of the oxygen exchange layer 112. The bottom surface of the conductor layer 106a is coplanar with the top surface of the first barrier layer 110. The conductor layer 106a includes a material that is less likely to bond with oxygen than the oxygen exchange layer 112. The conductor layer 106a can also be called an inert conductor layer 106a. The conductor layer 106a can be a single layer or multiple layers. The material of the conductor layer 106a can be a metal or a metal nitride, such as platinum, iridium, ruthenium, rhodium, tungsten, titanium, hafnium, tantalum, hafnium nitride, tantalum nitride, titanium nitride, tungsten nitride, or a combination thereof, and the formation method is, for example, physical vapor deposition. The thickness of the conductor layer 106a is, for example, 10 nanometers to 100 nanometers. From the top view, each conductor layer 106a can be a ring surrounding the oxygen exchange layer 112. The width W1 of the conductor layer 106a ring is less than the width W2 of the oxygen exchange layer 112. The ratio of the width W1 of the conductor layer 106a ring to the width W2 of the oxygen exchange layer 112 is, for example, 0.2 to 0.8. The width W1 of the conductor layer 106a ring is, for example, 50 nanometers to 200 nanometers.

[0017] When the resistance random access memory performs a SET operation, the oxygen ions in the variable resistance layer 104a are attracted by the positive bias voltage to leave the variable resistance layer 104a and enter the oxygen exchange layer 112, and oxygen vacancies are generated in the variable resistance layer 104a, thereby forming a filament current. In addition, when the SET operation is performed, the electrons in the variable resistance layer 104a are attracted by the positive bias voltage, and Fowler-Nordheim (FN) tunneling is induced between the conductor layer 106a and the variable resistance layer 104a, thereby causing leakage current. The formation of leakage current can increase the total current of the SET operation. When the RRAM cell 10 performs a RESET operation, the oxygen ions in the oxygen exchange layer 112 return to the variable resistance layer 104a, and FN tunneling will not be induced between the variable resistance layer 104a and the conductor layer 106a.

[0018] The sidewalls and top surface of the RRAM cell 10 are surrounded and covered by the dielectric layer 118. The sidewalls of the first electrode 102a, the variable resistance layer 104a, the conductor layer 106a, the first barrier layer 110, and the sidewalls and top surface of the second electrode 116a of the RRAM cell 10 are covered and in contact with the dielectric layer 118. The oxygen exchange layer 112 and the dielectric layer 118 are separated by the first barrier layer 110 and the conductor layer 106a, and are not in contact with each other.

[0019] The manufacturing method of the RRAM cell 10 can refer to Figures 1A to 1FThe description is as follows. In this document, the same or similar components use the same or similar reference numerals and can be formed by the same material or method. For example, the components of the first electrode layers 102 and 102a can be formed by the same material or method.

[0020] Reference Figure 1A , a first electrode layer 102, a variable resistance layer 104 and a conductor layer 106 are sequentially formed on a substrate (not shown) having a via 100 formed thereon. The material of the via 100 is, for example, tungsten.

[0021] Reference Figure 1B , a photolithography and etching process (eg, anisotropic etching process) is performed to pattern the conductive layer 106 and form an opening 108 in the conductive layer 106 . The opening 108 exposes the variable resistance layer 104 .

[0022] Reference Figure 1C , forming a first barrier layer 110 and an oxygen exchange layer 112 in the opening 108. The method for forming the first barrier layer 110 and the oxygen exchange layer 112, for example, includes the following steps: forming the first barrier layer 110 and the oxygen exchange layer 112 on the conductive layer 106 and in the opening 108, and then performing a chemical mechanical polishing process to remove the first barrier layer 110 and the oxygen exchange layer 112 on the conductive layer 106.

[0023] Reference Figure 1D , a second barrier layer 114 and a second electrode layer 116 are formed on the conductive layer 106 , the first barrier layer 110 and the oxygen exchange layer 112 .

[0024] Reference Figure 1E , photolithography and etching processes are performed to pattern the second electrode layer 116, the second barrier layer 114, the conductor layer 106, the variable resistance layer 104 and the first electrode layer 102 to form a plurality of RRAM cells 10. Each RRAM cell 10 includes a first electrode 102a, a variable resistance layer 104a, a conductor layer 106a, an oxygen exchange layer 112, a first barrier layer 110, a second barrier layer 114a and a second electrode 116a.

[0025] Reference Figure 1F , a dielectric layer 118 is formed on the substrate. The dielectric layer 118 is, for example, silicon oxide or a low dielectric constant material formed by chemical vapor deposition. Afterwards, photolithography and etching processes are performed to form a via window opening in the dielectric layer 118. Then, a via window 120 is formed in the via window opening. The material of the via window 120 is, for example, tungsten.

[0026] In summary, since the oxygen exchange layer of the embodiment of the present invention is covered by the variable resistance layer, the conductor layer, the second barrier layer and the second electrode layer, the etchant used in etching the conductor layer will not contact the oxygen exchange layer, and the dielectric layer will not contact the oxygen exchange layer. Therefore, the sidewall of the oxygen exchange layer will not be oxidized during etching, deposition of the dielectric layer, thermal process or testing, thereby affecting its effective area and volume.

[0027] In the method of the embodiment of the present invention, by controlling the patterning process, the oxygen exchange layer of each RRAM unit can have substantially the same effective area to uniformly distribute oxygen. Therefore, the RRAM can have a uniform formation current distribution.

[0028] Furthermore, since the method of the embodiment of the present invention can prevent the sidewall of the oxygen exchange layer from being oxidized to form an oxide layer, during the operation of the RRAM, it can prevent these additional oxide layers from providing additional oxygen atoms or oxygen ions to cause reliability problems.

[0029] On the other hand, when the RRAM cell performs a SET operation, in addition to the formation current generated by the formation of the filaments, FN tunneling can also be induced between the variable resistance layer and the conductor layer around the oxygen exchange layer to generate leakage current, thereby increasing the cycling window, reducing the bias voltage during the RESET operation, and avoiding the complementary switching (CS) effect.

[0030] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A resistance random access memory, characterized in that: include: The first electrode layer and the second electrode layer are arranged opposite to each other; a variable resistance layer, located between the first electrode layer and the second electrode layer; an oxygen exchange layer, located between the variable resistance layer and the second electrode layer; A conductor layer laterally surrounding the side wall of the oxygen exchange layer; a first barrier layer, located between the conductor layer and the oxygen exchange layer and between the oxygen exchange layer and the variable resistance layer; a second barrier layer, located between the conductor layer and the second electrode layer and between the second electrode layer and the oxygen exchange layer; as well as a dielectric layer covering the top surface and side walls of the second electrode layer, the second barrier layer, the conductor layer, the variable resistance layer, and a plurality of side walls of the first electrode layer, and the dielectric layer and the oxygen exchange layer are separated by the conductor layer, The bottom surface of the conductor layer contacts the top surface of the variable resistance layer. 2 . The resistance random access memory according to claim 1 , wherein the conductor layer comprises a material that is less likely to bond with oxygen than the oxygen exchange layer.

3. The resistance random access memory according to claim 1, wherein a material of the conductive layer comprises platinum, iridium, ruthenium, rhodium, tungsten, titanium, hafnium, tantalum, hafnium nitride, tantalum nitride, titanium nitride, tungsten nitride, or a combination thereof. 4 . The resistance random access memory according to claim 1 , wherein a top surface of the conductive layer is coplanar with a top surface of the first barrier layer and a top surface of the oxygen exchange layer. 5 . The resistance random access memory according to claim 1 , wherein a bottom surface of the conductive layer is coplanar with a bottom surface of the first barrier layer.

6. A method for manufacturing a resistance random access memory, characterized in that: include: forming a variable resistance layer on the first electrode layer; forming a conductor layer on the variable resistance layer; forming an opening in the conductor layer; forming a first barrier layer and an oxygen exchange layer in the opening; forming a second barrier layer on the conductor layer and the oxygen exchange layer; as well as A second electrode layer is formed on the second barrier layer.

7. The method for manufacturing a resistance random access memory according to claim 6, further comprising: The second electrode layer, the second barrier layer, the conductor layer, the variable resistance layer and the first electrode layer are patterned to form a plurality of resistance random access memory cells. 8 . The method for manufacturing a resistance random access memory according to claim 7 , further comprising forming a dielectric layer to cover top surfaces and side walls of the resistance random access memory cells.

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