A structure and preparation method for optimizing the surface electric field of a lateral gallium oxide power device

Abstract

The present invention discloses a structure for optimizing the surface electric field of a lateral gallium oxide power device and a preparation method thereof, the structure comprising: a substrate, an n-type gallium oxide channel layer, a source, a drain, a p-type oxide semiconductor layer and a gate stack, the substrate being connected to the n-type gallium oxide channel layer, the source, the drain, the p-type oxide semiconductor layer and the gate stack being arranged on the gallium oxide channel layer and away from the side of the substrate, and the p-type oxide semiconductor layer being arranged between the source and the drain and close to the drain side. The method comprises steps for preparing the above-mentioned structure for optimizing the surface electric field of a lateral gallium oxide power device. By using the present invention, the forward specific on-resistance of the device can be improved while the withstand voltage characteristics of the device are not affected. The present invention can be widely used in the field of semiconductor devices.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor devices, and in particular to a structure and a preparation method for optimizing the surface electric field of a lateral gallium oxide power device. Background Art

[0002] Power semiconductor devices are used in switch control for efficient conversion of electric energy in circuits, high-power circuit driving, and circuit loads under high voltage and high current density, and are the core of power electronics technology. The characteristics of semiconductor materials affect the performance of power devices made from them. At present, traditional silicon-based semiconductor power devices have gradually approached the physical limits of silicon materials and are gradually unable to meet the development needs of the industry. In recent years, in order to break through the limits of devices, the wide bandgap semiconductor industry represented by silicon carbide and gallium nitride has developed rapidly. Gallium oxide (Ga2O3) is an emerging wide bandgap semiconductor with a bandgap width of up to 4.8eV and a breakdown field strength of 8MV / cm. In addition, large-scale gallium oxide single crystals can be produced by low-cost melt growth technology. These advantages make gallium oxide materials have excellent development prospects in the field of power semiconductor devices.

[0003] For semiconductor power devices, people hope that they have the characteristics of high withstand voltage and low energy consumption, that is, they are required to have higher breakdown voltage and lower on-resistance. However, in practical applications, the two are always in a contradictory relationship. A higher breakdown voltage requires a thicker drift layer with a lower doping concentration, but a lower on-resistance requires a higher doping concentration and a thinner thickness of the drift layer.

[0004] Research on gallium oxide power semiconductor devices mainly focuses on unipolar devices, such as field effect transistors. When the gallium oxide field effect transistor is in the off state, the reverse peak electric field is mainly distributed on the side of the gate near the drain on the surface of the channel layer of the device, which will cause pre-breakdown at this point under high voltage, reduce the breakdown voltage of the device, and cause device performance degradation. Summary of the invention

[0005] In order to solve the above technical problems, the purpose of the present invention is to provide a structure and a preparation method for optimizing the surface electric field of a lateral gallium oxide power device, which can improve the device's withstand voltage characteristics without affecting the device's forward specific on-resistance.

[0006] The first technical solution adopted by the present invention is: a structure for optimizing the surface electric field of a lateral gallium oxide power device, comprising a substrate (101), an n-type gallium oxide channel layer (102), a source (103), a drain (104), a p-type oxide semiconductor layer (105) and a gate stack, wherein the substrate (101) is connected to the n-type gallium oxide channel layer (102), the source (103), the drain (104), the p-type oxide semiconductor layer (105) and the gate stack are arranged on the gallium oxide channel layer (102) and away from the substrate (101), and the p-type oxide semiconductor layer (105) is arranged between the source (103) and the drain (104) and close to the drain (104).

[0007] Preferably, the p-type oxide semiconductor layer (105) is not in contact with the drain (104).

[0008] Preferably, the gate stack comprises a gate dielectric layer (106) and a gate electrode (107), the p-type oxide semiconductor layer (105) and the gate electrode (107) are respectively connected to the gate dielectric layer (106), and the source electrode (103), the drain electrode (104) and the gate electrode (107) are not in contact with each other.

[0009] Preferably, the gate stack comprises a heavily doped p-type oxide semiconductor layer (108) and a gate (107), the p-type oxide semiconductor layer (105) and the gate (107) are respectively connected to the heavily doped p-type oxide semiconductor layer (108), and the source (103), the drain (104) and the gate (107) are not in contact with each other.

[0010] Preferably, the p-type oxide semiconductor layer (105) is an amorphous or polycrystalline structure.

[0011] Preferably, the p-type oxide semiconductor layer (105) is a single-layer or multi-layer structure.

[0012] Preferably, the hole concentration of the p-type oxide semiconductor layer (105) is 1×10 16 / cm 3 ~1×10 18 / cm 3 The doping concentration of the n-type gallium oxide channel layer (102) is higher than the hole concentration of the p-type oxide semiconductor layer (105).

[0013] Furthermore, the p-type oxide semiconductor layer (105) has a thickness of 10 nm to 500 nm.

[0014] Furthermore, the n-type gallium oxide channel layer (102) is a single crystal structure with a doping concentration of 5×10 14 cm -3 Up to 1×10 18 cm-3 , with a thickness of 10nm to 10μm.

[0015] The second technical solution adopted by the present invention is: a method for preparing a structure for optimizing the surface electric field of a lateral gallium oxide power device, comprising:

[0016] epitaxially growing an n-type gallium oxide channel layer (102) on a substrate (101);

[0017] Defining electrode patterns and depositing metal on the n-type gallium oxide channel layer (102) to form a source electrode (103) and a drain electrode (104);

[0018] Depositing a p-type oxide semiconductor material on the n-type gallium oxide channel layer (102) to obtain a p-type oxide semiconductor layer (105) and form a heterogeneous pn junction;

[0019] Depositing an insulating dielectric material on the n-type gallium oxide channel layer (102) and the p-type oxide semiconductor layer (105) to obtain a gate dielectric layer (106);

[0020] An electrode pattern is defined and metal is deposited on the gate dielectric layer (106) to form a gate (107).

[0021] The beneficial effects of the method and system of the present invention are as follows: the present invention forms a heterogeneous pn junction structure by introducing a p-type oxide semiconductor layer and an n-type gallium oxide channel layer between the n-type gallium oxide channel layer and the gate dielectric layer, and utilizes the depletion region formed in the channel layer by the heterogeneous pn junction under reverse bias to improve the electric field distribution on the surface of the device channel layer, thereby improving the withstand voltage characteristics of the device without affecting the forward specific on-resistance of the device. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Figure 1 It is a schematic diagram of a structure for optimizing the surface electric field of a lateral gallium oxide power device according to a specific embodiment 1 of the present invention;

[0023] Figure 2 is a schematic diagram of a structure for optimizing the surface electric field of a lateral gallium oxide power device according to a specific embodiment 2 of the present invention;

[0024] Figure 3 is a schematic diagram of a structure for optimizing the surface electric field of a lateral gallium oxide power device according to specific embodiment 3 of the present invention;

[0025] Figure 4 It is a flowchart of the steps of a method for preparing a structure for optimizing the surface electric field of a lateral gallium oxide power device according to a specific embodiment of the present invention;

[0026] Figure 5 This is a data simulation diagram of the structure for optimizing the surface electric field of the lateral gallium oxide power device according to the specific embodiment 1 of the present invention.

[0027] Reference numerals: 101, substrate; 102, n-type gallium oxide channel layer; 103, source; 104, drain; 105, p-type oxide semiconductor layer; 106, gate dielectric layer; 107, gate; 108, heavily doped p-type oxide semiconductor layer. DETAILED DESCRIPTION

[0028] The present invention is further described in detail below in conjunction with the accompanying drawings and specific embodiments. The step numbers in the following embodiments are only provided for the convenience of explanation and description, and the order between the steps is not limited in any way. The execution order of each step in the embodiment can be adaptively adjusted according to the understanding of those skilled in the art.

[0029] Reference Figure 1 , the description of embodiment 1 of the present invention is as follows:

[0030] A structure for optimizing the surface electric field of a lateral gallium oxide power device comprises a substrate (101), an n-type gallium oxide channel layer (102), a source electrode (103), a drain electrode (104), a p-type oxide semiconductor layer (105), a gate dielectric layer (106) and a gate electrode (107), wherein the substrate (101) is connected to the n-type gallium oxide channel layer (102), and the source electrode (103), the drain electrode (104), the p-type oxide semiconductor layer (105) and the gate dielectric layer (106) are arranged on the gallium oxide channel layer (102). The p-type oxide semiconductor layer (105) is disposed between the source electrode (103) and the drain electrode (104) and close to the drain electrode (104). The gate dielectric layer (106) is disposed between the source electrode (103) and the drain electrode (104). The source electrode (103), the drain electrode (104), the p-type oxide semiconductor layer (105) and the gate electrode (107) are respectively connected to the gate dielectric layer (106). The gate dielectric layer (106) covers the p-type oxide semiconductor layer (105).

[0031] The p-type oxide semiconductor layer (105) is not in contact with the drain electrode (104), and the source electrode (103), the drain electrode (104) and the gate electrode (107) are not in contact with each other.

[0032] The p-type oxide semiconductor layer (105) is an amorphous or polycrystalline structure, a single layer or a multilayer structure, and has a hole concentration of 1×10 16 / cm 3 ~1×10 18 / cm 3, and the hole concentration of the p-type oxide semiconductor layer (105) is not lower than the doping concentration of the n-type gallium oxide channel layer (102), the p-type oxide semiconductor layer (105) has a thickness of 10 nm to 500 nm, and the n-type gallium oxide drift layer (102) is a single crystal structure with a doping concentration of 5×10 14 cm -3 Up to 1×10 18 cm -3 , with a thickness of 10nm to 10μm.

[0033] The structure of optimizing the surface electric field of the lateral gallium oxide power device is formed by introducing a p-type oxide semiconductor layer and an n-type gallium oxide channel layer between the n-type gallium oxide channel layer and the gate dielectric layer to form a heterogeneous pn junction structure. When the device is turned off, the heterogeneous pn junction is in a reverse bias state, forming a depletion region in the channel layer, which assists the gate control to turn off the device on the one hand, and smoothes the channel electric field distribution between the gate and the drain on the other hand, reducing the electric field peak in the channel layer on the side of the device gate close to the drain. This structure optimizes the electric field distribution on the surface of the channel layer, so that the electric field peak is reduced under the same doping concentration, and the added p-type oxide semiconductor layer does not affect the channel conduction of the device when it is forward-conducted, and can improve the reverse withstand voltage without increasing the forward specific on-resistance, improve the switching characteristics of the device, and the preparation process is simple.

[0034] Figure 5 The present invention is a data simulation diagram of the structure for optimizing the surface electric field of a lateral gallium oxide power device as described in Example 1. The introduction of the p-type oxide semiconductor layer (105) of the structure significantly reduces the peak electric field on the surface of the channel layer of the device in the off state, improves the electric field distribution of the device on the surface of the channel layer, and allows the device to increase the doping concentration of the gallium oxide channel layer while maintaining high withstand voltage performance, thereby achieving a lower forward specific on-resistance.

[0035] Reference Figure 2 , the description of embodiment 2 of the present invention is as follows:

[0036] A structure for optimizing the surface electric field of a lateral gallium oxide power device comprises a substrate (101), an n-type gallium oxide channel layer (102), a source electrode (103), a drain electrode (104), a p-type oxide semiconductor layer (105), a gate dielectric layer (106) and a gate electrode (107); the substrate (101) is connected to the n-type gallium oxide channel layer (102); the source electrode (103), the drain electrode (104), the p-type oxide semiconductor layer (105) and the gate dielectric layer (106) are arranged on the gallium oxide channel layer (102) and away from the substrate (101); the p-type oxide semiconductor layer (105) is arranged between the source electrode (103) and the drain electrode (104); 04) and close to the drain (104); the gate dielectric layer (106) is arranged between the source (103) and the drain (104); the source (103), the drain (104), the p-type oxide semiconductor layer (105) and the gate (107) are respectively connected to the gate dielectric layer (106); a groove is etched on the gallium oxide channel layer (102) on the side close to the drain (104); the p-type oxide semiconductor layer (105) is deposited on the groove to form a structure in which the p-type oxide semiconductor layer (105) is embedded in the gallium oxide channel layer (102); and the gate dielectric layer (106) covers the p-type oxide semiconductor layer (105).

[0037] Specifically, the channel layer grooves may be formed by using methods such as inductively coupled plasma etching or reactive ion etching.

[0038] The p-type oxide semiconductor layer (105) is not in contact with the drain (104), and the source (103), the drain (104) and the gate (107) are not in contact with each other.

[0039] The p-type oxide semiconductor layer (105) is an amorphous or polycrystalline structure, a single layer or a multilayer structure, and has a hole concentration of 1×10 16 / cm 3 ~1×10 18 / cm 3 , and the hole concentration of the p-type oxide semiconductor layer (105) is not lower than the doping concentration of the n-type gallium oxide channel layer (102), the p-type oxide semiconductor layer (105) has a thickness of 10 nm to 500 nm, and the n-type gallium oxide drift layer (102) is a single crystal structure with a doping concentration of 5×10 14 cm -3 Up to 1×10 18 cm -3 , with a thickness of 10nm to 10μm.

[0040] When the device is in the off state, the heterojunction formed by the p-type oxide semiconductor layer and the n-type gallium oxide channel layer is reverse biased, forming a depletion region in the channel layer. The embedded structure allows the depletion region to expand in the horizontal and vertical directions, introduces the surface electric field peak into the body, and smoothes the channel electric field distribution from the gate to the drain side, reducing the electric field peak in the channel and optimizing the breakdown characteristics of the device.

[0041] Reference Figure 3 , the description of embodiment 3 of the present invention is as follows:

[0042] A structure for optimizing the surface electric field of a lateral gallium oxide power device comprises a substrate (101), an n-type gallium oxide channel layer (102), a source electrode (103), a drain electrode (104), a p-type oxide semiconductor layer (105), a heavily doped p-type oxide semiconductor layer (108) and a gate electrode (107), wherein the substrate (101) is connected to the n-type gallium oxide channel layer (102), and the source electrode (103), the drain electrode (104), the p-type oxide semiconductor layer (105) and the heavily doped p-type oxide semiconductor layer (108) are arranged on the gallium oxide channel layer (107). 2) and on a side away from the substrate (101), the p-type oxide semiconductor layer (105) is arranged between the source (103) and the drain (104) and close to the drain (104), the heavily doped p-type oxide semiconductor layer (108) is arranged between the source (103) and the drain (104), the p-type oxide semiconductor layer (105) and the gate (107) are respectively connected to the heavily doped p-type oxide semiconductor layer (108), and the heavily doped p-type oxide semiconductor layer (108) covers a portion of the p-type oxide semiconductor layer (105).

[0043] The p-type oxide semiconductor layer (105) does not contact the drain (104), the source (103), the drain (104) and the gate (107) do not contact each other, and the source (103) and the drain (104) do not contact the heavily doped p-type oxide semiconductor layer (108).

[0044] The p-type oxide semiconductor layer (105) is an amorphous or polycrystalline structure, a single layer or a multilayer structure, and has a hole concentration of 1×10 16 / cm 3 ~1×10 18 / cm 3 , and the hole concentration of the p-type oxide semiconductor layer (105) is not lower than the doping concentration of the n-type gallium oxide channel layer (102), the p-type oxide semiconductor layer (105) has a thickness of 10 nm to 500 nm, and the n-type gallium oxide drift layer (102) is a single crystal structure with a doping concentration of 5×10 14 cm -3 Up to 1×10 18 cm-3 , with a thickness of 10 nm to 10 μm, the heavily doped p-type oxide semiconductor layer (108) is an amorphous or polycrystalline structure, a single layer or a multilayer structure, and has a hole concentration of 1×10 18 ~1×10 20 cm -3 , with a thickness of 10 nm to 500 nm, and the material that can be used for the heavily doped p-type oxide semiconductor layer (108) is the same as that for the p-type oxide semiconductor layer (105).

[0045] When the device is in the off state, the heterogeneous pn junction formed by the p-type oxide semiconductor layer and the n-type gallium oxide channel layer is reverse biased, forming a depletion region in the channel layer, so that the depletion region formed by the heavily doped p-type layer and the n-type gallium oxide channel layer expands in the horizontal direction, which not only assists the gate to turn off the device, but also smoothes the channel electric field distribution from the gate to the drain, reduces the electric field peak on the side of the contact interface between the heavily doped p-type layer and the channel layer close to the drain, and improves the breakdown voltage of the device.

[0046] The structure of optimizing the surface electric field of a lateral gallium oxide power device described in the present invention forms a heterogeneous pn junction structure by introducing a p-type oxide semiconductor layer and an n-type gallium oxide channel layer between an n-type gallium oxide channel layer and a gate dielectric layer, so that the reverse biased pn junction of the device forms a depletion region in the channel layer when the device is in the off state, smoothing the electric field distribution on the surface of the channel layer between the gate and the drain, reducing the peak electric field on the surface of the channel layer, avoiding pre-breakdown of the device at this location under high voltage, and improving the breakdown voltage of the device. When forward-conducting, the added p-type oxide semiconductor layer does not affect the channel conduction of the device. This structure does not affect the forward specific on-resistance of the device while improving the withstand voltage of the device. It can break through the limitations of the breakdown voltage and on-resistance of the device to a certain extent, and maintain lower energy consumption while achieving higher withstand voltage.

[0047] like Figure 4 As shown, a method for preparing a structure for optimizing the surface electric field of a lateral gallium oxide power device comprises the following steps:

[0048] S1, epitaxially growing a gallium oxide channel layer (102) on a substrate (101) to obtain an n-type doped gallium oxide-based wafer;

[0049] S2, defining an electrode pattern on the n-type gallium oxide drift layer (102) by photolithography, and depositing metal to form a source electrode (103) and a drain electrode (104);

[0050] Specifically, the electrode forms an ohmic contact with the n-type gallium oxide channel layer (102), and the source (103) and the drain (104) can be deposited with a Ti / Au alloy or a Ti / Al / Ti / Au alloy by magnetron sputtering or electron beam evaporation;

[0051] S3, depositing a p-type oxide semiconductor layer (105) on the n-type gallium oxide channel layer (102);

[0052] Specifically, the p-type oxide semiconductor layer (105) forms a heterogeneous PN junction with the n-type gallium oxide channel layer (102); the p-type oxide semiconductor layer (105) can be prepared by magnetron sputtering, solution method, metal oxidation method, physical or chemical vapor deposition, etc., and the material can be NiO, Cu2O or other single-layer or multi-layer p-type oxide semiconductor materials.

[0053] S4, depositing a gate dielectric layer (106) on the n-type gallium oxide channel layer (102) and the p-type oxide semiconductor layer (105),

[0054] Specifically, the gate dielectric layer (106) can be prepared by atomic layer deposition, plasma enhanced chemical vapor deposition, magnetron sputtering, other physical or chemical vapor deposition methods, and the material can be Al2O3, SiO2, SiN x Or other single-layer or multi-layer insulating dielectric materials;

[0055] In addition, if it corresponds to Example 3, the heavily doped p-type oxide semiconductor layer (108) replaces the gate dielectric layer (106), and the deposited material is the same as that of the p-type oxide semiconductor layer (105).

[0056] S5. Define an electrode pattern on the gate dielectric layer (106) by photolithography, and deposit metal to form a gate (107).

[0057] Specifically, the metal gate (107) can be formed by depositing Ti / Au alloy or Pt / Au alloy by magnetron sputtering or electron beam evaporation.

[0058] The contents of the above structural embodiments are all applicable to the present method embodiments. The functions specifically implemented by the present method embodiments are the same as those of the above structural embodiments, and the beneficial effects achieved are also the same as those achieved by the above structural embodiments.

[0059] The above is a specific description of the preferred implementation of the present invention, but the invention is not limited to the embodiments. Those skilled in the art may make various equivalent modifications or substitutions without violating the spirit of the present invention. These equivalent modifications or substitutions are all included in the scope defined by the claims of this application.

Claims

1. A structure for optimizing the surface electric field of a lateral gallium oxide power device, characterized in that: The invention comprises a substrate (101), an n-type gallium oxide channel layer (102), a source electrode (103), a drain electrode (104), a p-type oxide semiconductor layer (105) and a gate stack, wherein the substrate (101) is connected to the n-type gallium oxide channel layer (102), the source electrode (103), the drain electrode (104), the p-type oxide semiconductor layer (105) and the gate stack are arranged on the gallium oxide channel layer (102) and on a side away from the substrate (101), and the p-type oxide semiconductor layer (105) is arranged between the source electrode (103) and the drain electrode (104) and on a side close to the drain electrode (104); the p-type oxide semiconductor layer (105) is arranged between the source electrode (103) and the drain electrode (104) and on a side close to the drain electrode (104); The source electrode (103), the drain electrode (104) and the gate electrode (107) are not in contact with each other, and the gate electrode (107) is disposed on the heavily doped p-type oxide semiconductor layer (108), and the heavily doped p-type oxide semiconductor layer (108) covers part of the p-type oxide semiconductor layer (105).

2. The structure for optimizing the surface electric field of a lateral gallium oxide power device according to claim 1, characterized in that: The p-type oxide semiconductor layer (105) is an amorphous or polycrystalline structure.

3. The structure for optimizing the surface electric field of a lateral gallium oxide power device according to claim 1, characterized in that: The p-type oxide semiconductor layer (105) is a single-layer or multi-layer structure.

4. The structure for optimizing the surface electric field of a lateral gallium oxide power device according to claim 1, characterized in that: The hole concentration of the p-type oxide semiconductor layer (105) is 1×10 16 / cm 3 ~1×10 18 / cm 3 The doping concentration of the n-type gallium oxide channel layer (102) is higher than the hole concentration of the p-type oxide semiconductor layer (105).

5. According to the structure for optimizing the surface electric field of a lateral gallium oxide power device as claimed in claim 1, the thickness of the p-type oxide semiconductor layer (105) is 10 nm to 500 nm.

6. According to the structure for optimizing the surface electric field of a lateral gallium oxide power device as claimed in claim 1, the n-type gallium oxide channel layer (102) is a single crystal structure with a doping concentration of 5×10 14 cm -3 Up to 1×10 18 cm -3 , with a thickness of 10nm to 10μm.

7. A method for preparing a structure for optimizing the surface electric field of a lateral gallium oxide power device as claimed in any one of claims 1 to 6, characterized in that: The following steps are involved: epitaxially growing an n-type gallium oxide channel layer (102) on a substrate (101); Defining electrode patterns and depositing metal on the n-type gallium oxide channel layer (102) to form a source electrode (103) and a drain electrode (104); Depositing a p-type oxide semiconductor material on the n-type gallium oxide channel layer (102) to obtain a p-type oxide semiconductor layer (105) and form a heterogeneous pn junction; Depositing a heavily doped p-type oxide semiconductor on the n-type gallium oxide channel layer (102) and the p-type oxide semiconductor layer (105) to obtain a heavily doped p-type oxide semiconductor layer (108); Defining an electrode pattern and depositing metal on the heavily doped p-type oxide semiconductor layer (108) to form a gate (107); The p-type oxide semiconductor layer (105) is not in contact with the drain electrode (104).

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