Silicon heterojunction battery with electrode through-hole and preparation method thereof

Abstract

The present invention discloses a silicon heterojunction battery with an electrode through hole and a preparation method thereof. The silicon heterojunction battery comprises a silicon heterojunction body, a grid line and a conductive pattern; the silicon heterojunction body is provided with an electrode through hole along its thickness direction, and the electrode through hole is filled with a conductive material; the grid lines are arranged on the upper surface and the lower surface of the silicon heterojunction body, and the upper end of the electrode through hole is connected to the grid line on the upper surface of the silicon heterojunction body; the conductive pattern is arranged on the lower surface of the silicon heterojunction body, and the lower end of the electrode through hole is connected to the conductive pattern, and the conductive pattern is suitable for connecting to the grid line of an adjacent silicon heterojunction battery. The current collected by the grid line on the upper surface of the battery is collected and guided to the conductive pattern on the lower surface of the battery through the electrode through hole, and the conductive pattern on the lower surface of the battery is connected to the grid line on the lower surface of the adjacent battery using a welding strip between adjacent batteries, thereby improving the yield and reliability of the assembly, and can maximize the weldability and conductivity, which is conducive to ensuring the long-term reliability of the assembly.

Description

Technical Field

[0001] The present invention relates to the technical field of solar cells, and in particular to a silicon heterojunction cell with electrode through holes and a preparation method thereof. Background Art

[0002] According to the difference of grid electrode, there are two technical routes for silicon heterojunction solar cells: silver grid silicon heterojunction cells and copper grid silicon heterojunction cells. Compared with silver grid, copper grid has the advantages of no precious metal slurry consumption, high conductivity, excellent grid morphology, low temperature process preparation, further reduction of grid width, and increase of light receiving area, and is considered to be a strong competitor of silver grid electrode.

[0003] In the related art, welding strips are required between adjacent batteries to connect the grid lines on the front of the battery with the grid lines on the back of the adjacent battery. However, the welding lamp of the stringing machine will heat and release heat instantly, with a fast heating and cooling speed, a large temperature change range and low control accuracy. When a large area of ​​the battery surface is stringed, if the instantaneous temperature rises to a high level, it will damage the heterojunction film or have a very adverse effect on the copper electrode. If the temperature drops to a low level, serious cold solder joints will occur. Too high or too low temperature will affect the quality of the battery. Summary of the invention

[0004] The present invention aims to solve one of the technical problems in the related art at least to a certain extent.

[0005] To this end, an embodiment of the present invention provides a silicon heterojunction cell with electrode through-holes, and a photovoltaic module made of the silicon heterojunction cell has higher performance.

[0006] The present invention also provides a method for preparing the silicon heterojunction battery.

[0007] The silicon heterojunction battery with electrode through-holes of the embodiment of the first aspect of the present invention comprises: a silicon heterojunction body, a gate line, and a conductive pattern; the silicon heterojunction body is provided with an electrode through-hole along its thickness direction, and the electrode through-hole is filled with a conductive material; the gate lines are arranged on the upper surface and the lower surface of the silicon heterojunction body, and the upper end of the electrode through-hole is connected to the gate line on the upper surface of the silicon heterojunction body; the conductive pattern is arranged on the lower surface of the silicon heterojunction body, and the lower end of the electrode through-hole is connected to the conductive pattern, and the conductive pattern is suitable for being connected to the gate line of an adjacent silicon heterojunction battery.

[0008] In the silicon heterojunction cell of the embodiment of the present invention, the cell collects the current collected by the grid line on the upper surface and guides it to the conductive pattern on the lower surface of the cell by setting the electrode through-hole. The conductive pattern on the lower surface of the first cell is connected to the grid line on the lower surface of the adjacent second cell by using a welding strip between adjacent cells. This not only greatly reduces the scope involved in welding, eliminates the adverse effects of large-area series welding on the upper surface of the cell on the heterojunction film and the copper electrode, improves the yield and reliability of the module, but also reduces the requirements for the width and optical properties of the welding strip, and can maximize the weldability and conductivity; the welding strip does not need to be bent when welding between adjacent cells, avoiding the internal stress that may be generated when the conventional front main grid and the back main grid are interconnected due to the bending of the welding strip to deform the edge of the cell, which is conducive to ensuring the long-term reliability of the module. In addition, under this battery structure and interconnection method, the cells in the module can be arranged more closely, which is conducive to improving the power of the module per unit area.

[0009] In some embodiments, the gate lines include a plurality of main gate lines and a plurality of fine gate lines, the plurality of main gate lines are parallel to each other, the plurality of fine gate lines are parallel to each other, and the main gate lines and the fine gate lines are perpendicular to each other.

[0010] In some embodiments, the electrode through holes are all connected to the main grid lines on the upper surface of the silicon heterojunction body, there are multiple electrode through holes, and the relative positions of the multiple electrode through holes and their corresponding main grid lines are the same.

[0011] In some embodiments, in the length direction of the main grid line, the distance from the electrode through hole to the edge of the silicon heterojunction body is 0.1-10 mm.

[0012] In some embodiments, the diameter of the electrode through-hole is 10-2000 μm.

[0013] In some embodiments, the diameter of the electrode through-hole is 50-500 μm.

[0014] In some embodiments, the silicon heterojunction body includes a silicon wafer, a first intrinsic amorphous silicon film respectively arranged on the upper surface of the silicon wafer and a second intrinsic amorphous silicon film respectively arranged on the lower surface, a first doped amorphous silicon film respectively arranged on the upper surface of the first intrinsic amorphous silicon film and a second doped amorphous silicon film respectively arranged on the lower surface of the second intrinsic amorphous silicon film, a first TCO film respectively arranged on the upper surface of the first doped amorphous silicon film and a second TCO film respectively arranged on the lower surface of the second doped amorphous silicon film, and the gate lines are respectively arranged on the upper surface of the first TCO film and the lower surface of the second TCO film.

[0015] In some embodiments, an isolation region is further provided on the lower surface of the second TCO film, and the conductive pattern is located in the isolation region.

[0016] In some embodiments, the conductive pattern has the same cross-sectional shape as the electrode through-hole, or the conductive pattern extends along the length direction of the main grid line to the edge of the silicon heterojunction body; or, the conductive pattern extends along the length direction of the main grid line to a position adjacent to the edge of the silicon heterojunction body.

[0017] In some embodiments, the gate lines are copper gate lines.

[0018] The preparation method of a silicon heterojunction battery with electrode through-holes in an embodiment of the second aspect of the present invention includes: providing a silicon wafer, drilling a hole on the silicon wafer using a laser, and forming an electrode through-hole penetrating the front and back sides at a preset position on the silicon wafer; cleaning and texturing the silicon wafer to remove original damage, impurities on the surface of the silicon wafer and laser damage near the electrode through-hole; coating the silicon wafer with a plasma enhanced chemical vapor deposition method, forming a first intrinsic amorphous silicon film and a first doped amorphous silicon film in sequence on the upper surface of the silicon wafer, forming a second intrinsic amorphous silicon film on the lower surface of the silicon wafer, using a mask to cover the isolation area, and forming a second doped amorphous silicon film on the second intrinsic amorphous silicon film in the area of ​​the lower surface of the silicon wafer other than the isolation area; placing the silicon wafer on a carrier, coating the silicon wafer with a physical vapor deposition method, A first TCO film and a copper seed layer are sequentially formed on the upper surface of the first doped amorphous silicon film, a second TCO film and a copper seed layer are sequentially formed on the lower surface of the second doped amorphous silicon film outside the isolation region, the second TCO film and the copper seed layer are sequentially formed in the region of the conductive pattern and the inner wall of the electrode through hole, and the silicon wafer forms a silicon heterojunction body; a mask is formed on the upper and lower surfaces of the silicon heterojunction body by using a photolithography patterning process, and the mask should avoid the region corresponding to the gate line and the conductive pattern; a metal copper layer is formed in the region corresponding to the gate line, the electrode through hole and the conductive pattern by using an electroplating process; the mask and the copper seed layer under the mask are removed; a metal tin coating layer is coated on the surface of the metal copper layer formed in the region corresponding to the gate line; and the silicon heterojunction body is subjected to a low-temperature heat treatment. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 It is a front view of a silicon heterojunction battery with electrode through-holes according to an embodiment of the present invention.

[0020] Figure 2 yes Figure 1 A magnified schematic diagram of area A in the middle.

[0021] Figure 3 It is a schematic diagram of the conductive pattern on the back side of a silicon heterojunction battery with electrode through holes according to the first embodiment of the present invention.

[0022] Figure 4Schematic diagram of the conductive pattern on the back side of a silicon heterojunction cell with electrode through holes according to the second embodiment of the present invention.

[0023] Figure 5 It is a schematic diagram of adjacent silicon heterojunction cells with electrode through holes welded in series according to an embodiment of the present invention.

[0024] Figure 6 It is a schematic structural diagram of a silicon heterojunction battery with electrode through-holes according to an embodiment of the present invention.

[0025] Figure 7 It is a schematic diagram of a silicon heterojunction battery with electrode through holes according to an embodiment of the present invention installed on a physical vapor deposition carrier.

[0026] Figure 8 Schematic diagram of a carrier for physical vapor deposition of a silicon heterojunction battery with electrode through holes according to an embodiment of the present invention.

[0027] Figure numerals: silicon heterojunction body 1, silicon wafer 11, first intrinsic amorphous silicon film 12, first doped amorphous silicon film 121, first TCO film 122, second intrinsic amorphous silicon film 13, second doped amorphous silicon film 131, second TCO film 132, isolation region 141, electrode through-hole 2, gate line 4, main gate line 41, fine gate line 42, conductive pattern 5, carrier 6. DETAILED DESCRIPTION

[0028] Embodiments of the present invention are described in detail below, and examples of the embodiments are shown in the accompanying drawings. The embodiments described below with reference to the accompanying drawings are exemplary and intended to be used to explain the present invention, but should not be understood as limiting the present invention.

[0029] The silicon heterojunction battery with electrode through holes according to an embodiment of the present invention will be described below with reference to the accompanying drawings.

[0030] like Figure 1 and Figure 3 As shown, the silicon heterojunction battery of the embodiment of the first aspect of the present invention includes: a silicon heterojunction body 1, a gate line 4, and a conductive pattern 5; an electrode through hole 2 is provided on the silicon heterojunction body 1 along its thickness direction, and the electrode through hole 2 is filled with a conductive material; the gate line 4 is arranged on the upper surface and the lower surface of the silicon heterojunction body 1, and the upper end of the electrode through hole 2 is connected to the gate line 4 on the upper surface of the silicon heterojunction body 1; the conductive pattern 5 is arranged on the lower surface of the silicon heterojunction body 1, and the lower end of the electrode through hole 2 is connected to the conductive pattern 5, and the conductive pattern 5 is suitable for connecting to the gate line 4 on the lower surface of the adjacent silicon heterojunction battery, and the connecting medium can be a welding strip, a conductive tape or other materials with conductive properties.

[0031] Specifically, Figure 1As shown, the electrode through hole 2 is located at the rear end of the silicon heterojunction body 1, and the electrode through hole 2 penetrates the silicon heterojunction body 1 in the up-down direction. The current collected by the grid line 4 on the upper surface of the battery is collected at the upper end of the electrode through hole 2, and the collected current reaches the conductive pattern 5 on the lower surface of the battery through the conductive material. The conductive pattern 5 is connected to the grid line 4 on the lower surface of the adjacent silicon heterojunction battery via a welding strip, so that the series connection between adjacent batteries only occurs on the lower surface of the battery; when the stringer performs string welding between adjacent batteries, the heating and cooling speed of the welding lamp of the stringer is fast, the temperature change range is large and the control accuracy is not high. A high instantaneous temperature will have an adverse effect on the heterojunction film or copper electrode, and a low instantaneous temperature will cause serious cold welding. For the photovoltaic module composed of silicon heterojunction batteries, the module interconnection only occurs between the conductive pattern 5 on the lower surface of the battery and the grid line 4 on the lower surface of the adjacent battery. Therefore, the large-area string welding on the upper surface of the battery is eliminated, thereby preventing the instantaneous temperature from being too high or too low to affect the battery quality, and also reducing the requirements for the width of the welding strip and the optical properties.

[0032] In the related art, welding strips are used between adjacent solar cells to connect the grid lines 4 on the front of the cells with the grid lines 4 on the back of the adjacent cells. The welding strips in the above connection method may be bent, which may cause deformation of the edges of the cells and generate internal stress. The photovoltaic modules composed of cells connected in this way have poor reliability during long-term use. Compared with the solar cells in the related art, the silicon heterojunction cells with electrode through holes in the embodiments of the present invention do not need to be bent, thereby avoiding deformation of the edges of the silicon heterojunction body 1 and the possible internal stress, which is beneficial to ensuring the long-term reliability of the modules.

[0033] In the silicon heterojunction battery of the embodiment of the present invention, the battery collects the current collected by the grid lines 4 on the upper surface and guides it to the grid lines 4 on the lower surface of the battery by setting electrode through holes 2, and uses welding strips between adjacent batteries to connect the conductive patterns 5 on the lower surface of the battery with the grid lines 4 on the lower surface of the adjacent battery, which not only greatly reduces the scope involved in welding, eliminates the adverse effects of large-area series welding on the upper surface of the battery on the heterojunction film and copper electrodes, improves the yield and reliability of the component, but also reduces the requirements for the width and optical properties of the welding strip, and can maximize the weldability and conductivity; the welding strip does not need to be bent when welding between adjacent batteries, which is beneficial to ensuring the long-term reliability of the component.

[0034] like Figure 2 As shown, in some embodiments, the grid lines 4 include multiple main grid lines 41 and multiple fine grid lines 42, the multiple main grid lines 41 are parallel to each other, the multiple fine grid lines 42 are parallel to each other, the main grid lines 41 and the fine grid lines 42 are perpendicular to each other, and the multiple main grid lines 41 enhance the current collection capability of the silicon heterojunction battery.

[0035] like Figure 1 and Figure 2As shown, in some embodiments, the electrode through holes 2 are all connected to the main grid lines 41 on the upper surface of the silicon heterojunction body 1 , there are multiple electrode through holes 2 , and the multiple electrode through holes 2 correspond to the multiple main grid lines 41 one by one.

[0036] Specifically, Figure 1 and Figure 5 As shown, the electrode through hole 2 is arranged at the rear end of the main grid line 41 on the upper surface of the silicon heterojunction body 1, and there are multiple conductive patterns 5, and the multiple conductive patterns 5 correspond to the multiple electrode through holes 2 one by one. Figure 5 The conductive pattern 5 of the battery located below is Figure 5 The main grid lines 41 of the cells located above are connected via welding strips. Figure 5 The connection length of the main busbar 41 of the upper battery can be from 1 mm to the entire length of the main busbar 41.

[0037] In some embodiments, in the length direction of the main grid line 41 , the straight-line distance from the center of the electrode through hole 2 to the edge of the silicon heterojunction body 1 is 0.1-10 mm, for example, 0.1 mm, 5 mm or 10 mm.

[0038] In some embodiments, the diameter of the electrode through hole 2 is 10-2000 μm, for example, 10 μm, 1000 μm or 2000 μm. Optionally, the diameter of the electrode through hole 2 is preferably 50-500 μm, for example, 50 μm, 300 μm or 500 μm.

[0039] With this battery structure and interconnection method, the batteries in the module can be arranged more closely, which is conducive to improving the module power per unit area.

[0040] like Figure 6 As shown, in some embodiments, the silicon heterojunction body 1 includes a silicon wafer 11, an electrode through hole 2 penetrating the entire thickness of the silicon wafer 11, a first intrinsic amorphous silicon film 12 arranged on the upper surface of the silicon wafer 11, a first doped amorphous silicon film 121 arranged on the upper surface of the first intrinsic amorphous silicon film 12, and a first TCO film 122 arranged on the upper surface of the first doped amorphous silicon film 121; a second intrinsic amorphous silicon film 13 arranged on the lower surface of the silicon wafer 11, a second doped amorphous silicon film 131 arranged on the lower surface of the second intrinsic amorphous silicon film 13, and a second TCO film 132 arranged on the lower surface of the second doped amorphous silicon film 131, wherein the gate line 4 located above the silicon wafer 11 is arranged on the upper surface of the first TCO film 122, and the gate line 4 located below the silicon wafer 11 is arranged on the lower surface of the second TCO film 132.

[0041] like Figure 5As shown, in some embodiments, an isolation area 141 is further provided on the lower surface of the second TCO film 132. The isolation area 141 is a serrated area around the through hole and surrounded by the edge of the silicon wafer. The width of the serrations in the isolation area 141 is 0.1-5 mm. The conductive pattern 5 is located in the isolation area 141. A plurality of conductive patterns 5 correspond one-to-one to a plurality of serrations in the isolation area 141. There is no gate line 4 in the isolation area 141. The isolation area 141 separates the welding range of the welding strip and the conductive pattern 5 from the gate line 4 to prevent the string welding machine from causing adverse effects on other areas during the string welding process.

[0042] Specifically, the interior of the electrode through-hole 2 and the upper and lower surfaces around the hole are passivated with an intrinsic amorphous silicon film, and there is no emitter amorphous silicon film deposited inside the electrode through-hole 2 and on the surface of the isolation area 141, ensuring that the electrons collected on the upper surface of the battery are low-recombination transmitted when passing through the electrode through-hole 2 and avoiding the risk of leakage.

[0043] like Figure 3 As shown, in some embodiments, the cross-sectional shape of the conductive pattern 5 is the same as that of the electrode through-hole 2 .

[0044] like Figure 4 As shown, in some other embodiments, the conductive pattern 5 extends along the length direction of the main grid line 41 to the edge of the silicon heterojunction body 1.

[0045] Specifically, in the above two examples of the shape of the conductive pattern 5 , the second example has a larger range of welding points than the first example.

[0046] In addition, the conductive pattern 5 may also extend along the length direction of the main grid line 41 to a position adjacent to the edge of the silicon heterojunction body 1 , and the shape of the conductive pattern 5 may be selected according to actual conditions.

[0047] In some embodiments, the gate line 4 is a copper gate line 4. Compared with the silver gate line 4, the copper gate line 4 has the advantages of no consumption of precious metal slurry, high electrical conductivity, excellent gate line 4 morphology, and is prepared using a low-temperature process and can further reduce the line width of the gate line 4 and increase the light-receiving area. It is considered to be a strong competitor to the silver gate line 4 electrode.

[0048] The method for preparing a silicon heterojunction battery having electrode through-holes according to the second aspect of the present invention comprises:

[0049] A silicon wafer 11 is provided, and a hole is drilled on the silicon wafer 11 using a laser to form an electrode through hole 2 penetrating the front and back sides at a preset position on the silicon wafer 11; the silicon wafer 11 is cleaned and textured to remove original damage, impurities and laser damage near the electrode through hole 2 on the surface of the silicon wafer 11, so as to prevent the original damage, impurities and laser damage from affecting the quality of the formed component;

[0050] Plasma enhanced chemical vapor deposition is used to coat the silicon wafer 11, and a first intrinsic amorphous silicon film 12 and a first doped amorphous silicon film 121 are sequentially formed on the upper surface of the silicon wafer 11. A mask is used to cover the isolation region 141 (including the conductive pattern 5), and a second intrinsic amorphous silicon film 13 and a second doped amorphous silicon film 131 are sequentially formed on the lower surface of the silicon wafer 11, so that there is no emitter in this region;

[0051] like Figure 7 As shown, a silicon wafer 11 is placed on a carrier 6, and a physical vapor deposition method is used to coat the silicon wafer 11. A first TCO film 122 and a copper seed layer are sequentially formed on the upper surface of the first doped non-crystalline silicon film, a second TCO film 132 and a copper seed layer are sequentially formed on the lower surface of the second doped non-crystalline silicon film in an area other than the isolation area 141, and a second TCO film 132 and a copper seed layer are sequentially formed on the surface area of ​​the conductive pattern 5 and the inner wall of the electrode through hole 2, and the silicon wafer 11 forms a silicon heterojunction body 1;

[0052] A mask is formed on the upper and lower surfaces of the silicon heterojunction body 1 using a photolithography patterning process, and the mask should avoid the area corresponding to the gate line 4 and the conductive pattern 5; a metal copper layer is formed in the area corresponding to the gate line 4, the electrode through hole 2 and the conductive pattern 5 using an electroplating process; the mask and the copper seed layer under the mask are removed; a metal tin coating layer is coated on the surface of the metal copper layer formed in the area corresponding to the gate line 4; the silicon heterojunction body 1 is subjected to a low-temperature heat treatment, which has the functions of removing stress, alloying, and improving contact, and the low-temperature process preparation can further reduce the line width of the gate line 4.

[0053] In the description of the present invention, it is to be understood that the terms “center”, “longitudinal”, “lateral”, “length”, “width”, “thickness”, “up”, “down”, “front”, “back”, “left”, “right”, “vertical”, “horizontal”, “top”, “bottom”, “inside”, “outside”, “clockwise”, “counterclockwise”, “axial”, “radial”, “circumferential”, etc., indicating orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the referred device or element must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as limiting the present invention.

[0054] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include at least one of the features. In the description of the present invention, the meaning of "plurality" is at least two, such as two, three, etc., unless otherwise clearly and specifically defined.

[0055] In the present invention, unless otherwise clearly specified and limited, the terms "installed", "connected", "connected", "fixed" and the like should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral one; it can be a mechanical connection, an electrical connection, or communication with each other; it can be a direct connection, or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements, unless otherwise clearly defined. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0056] In the present invention, unless otherwise clearly specified and limited, a first feature being "above" or "below" a second feature may mean that the first and second features are in direct contact, or the first and second features are in indirect contact through an intermediate medium. Moreover, a first feature being "above", "above" or "above" a second feature may mean that the first feature is directly above or obliquely above the second feature, or simply means that the first feature is higher in level than the second feature. A first feature being "below", "below" or "below" a second feature may mean that the first feature is directly below or obliquely below the second feature, or simply means that the first feature is lower in level than the second feature.

[0057] In the present invention, the terms "one embodiment", "some embodiments", "examples", "specific examples", or "some examples" etc. mean that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the described specific features, structures, materials or characteristics may be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art may combine and combine the different embodiments or examples described in this specification and the features of the different embodiments or examples, without contradiction.

[0058] Although the embodiments of the present invention have been shown and described above, it is to be understood that the above embodiments are exemplary and are not to be construed as limitations of the present invention. A person skilled in the art may change, modify, replace and vary the above embodiments within the scope of the present invention.

Claims

1. A silicon heterojunction battery with electrode through-holes, characterized in that: include: A silicon heterojunction body, wherein the silicon heterojunction body is provided with an electrode through hole along the thickness direction thereof, and the electrode through hole is filled with a conductive material; Gate lines are arranged on the upper surface and the lower surface of the silicon heterojunction body, and the upper end of the electrode through hole is connected to the gate line on the upper surface of the silicon heterojunction body; A conductive pattern is arranged on the lower surface of the silicon heterojunction body, the lower end of the electrode through hole is connected to the conductive pattern, and the conductive pattern is suitable for connecting to the grid line on the lower surface of the adjacent silicon heterojunction battery; The grid lines include a plurality of main grid lines and a plurality of fine grid lines, the plurality of main grid lines are parallel to each other, the plurality of fine grid lines are parallel to each other, and the main grid lines and the fine grid lines are perpendicular to each other; The electrode through holes are all connected to the main grid lines on the upper surface of the silicon heterojunction body, there are multiple electrode through holes, the multiple electrode through holes correspond to the multiple main grid lines one by one, and the relative positions of the multiple electrode through holes and the corresponding main grid lines are the same; The silicon heterojunction body comprises: Silicon wafer; A first intrinsic amorphous silicon thin film disposed on the upper surface and a second intrinsic amorphous silicon thin film disposed on the lower surface of the silicon wafer respectively; A first doped amorphous silicon film disposed on an upper surface of the first intrinsic amorphous silicon film and a second doped amorphous silicon film disposed on a lower surface of the second intrinsic amorphous silicon film; A first TCO film disposed on the upper surface of the first doped amorphous silicon film and a second TCO film disposed on the lower surface of the second doped amorphous silicon film, respectively, and the gate lines are disposed on the upper surface of the first TCO film and the lower surface of the second TCO film, respectively; The surface of the second TCO film is also provided with an isolation area, and the conductive pattern is located in the isolation area; The interior of the electrode through hole and the upper and lower surfaces around the hole are passivated with an intrinsic amorphous silicon film, and there is no emitter amorphous silicon film deposited inside the electrode through hole and on the surface of the isolation area.

2. The silicon heterojunction battery with electrode through-holes according to claim 1, characterized in that: In the length direction of the main grid line, the distance from the electrode through hole to the edge of the silicon heterojunction body is 0.1-10 mm.

3. The silicon heterojunction battery with electrode through-holes according to claim 1, characterized in that: The diameter of the electrode through hole is 10-2000 μm.

4. The silicon heterojunction battery with electrode through-holes according to claim 3, characterized in that: The diameter of the electrode through hole is 50-500 μm.

5. The silicon heterojunction battery with electrode through-holes according to claim 1, characterized in that: The conductive pattern and the electrode through hole have the same cross-sectional shape; Alternatively, the conductive pattern extends along the length direction of the main grid line to the edge of the silicon heterojunction body; Alternatively, the conductive pattern extends along the length direction of the main grid line to a position adjacent to an edge of the silicon heterojunction body.

6. The silicon heterojunction battery with electrode through-holes according to any one of claims 1 to 5, characterized in that: The gate wire is a copper gate wire.

7. A method for preparing a silicon heterojunction battery with an electrode through hole, for preparing a silicon heterojunction battery with an electrode through hole as claimed in any one of claims 1 to 6, characterized in that: include: Providing a silicon wafer, and drilling holes on the silicon wafer using a laser to form electrode through-holes penetrating the front and back surfaces at preset positions on the silicon wafer; Cleaning and texturing the silicon wafer to remove original damage and impurities on the surface of the silicon wafer and laser damage near the electrode through-hole; Plating the silicon wafer with a plasma enhanced chemical vapor deposition method, sequentially forming a first intrinsic amorphous silicon film and a first doped amorphous silicon film on the upper surface of the silicon wafer, forming a second intrinsic amorphous silicon film on the lower surface of the silicon wafer, shielding the isolation area with a mask, and forming a second doped amorphous silicon film on the second intrinsic amorphous silicon film in the area of ​​the lower surface of the silicon wafer other than the isolation area; Placing the silicon wafer on a carrier, coating the silicon wafer with a physical vapor deposition method, sequentially forming a first TCO film and a copper seed layer on the upper surface of the first doped amorphous silicon film, sequentially forming a second TCO film and a copper seed layer on the lower surface of the second doped amorphous silicon film outside the isolation region, sequentially forming the second TCO film and the copper seed layer in the region of the conductive pattern and the inner wall of the electrode through hole, and the silicon wafer forms a silicon heterojunction body; Using a photolithography patterning process to form a mask on the upper surface and the lower surface of the silicon heterojunction body, wherein the mask should avoid the area corresponding to the gate line and the conductive pattern; Using an electroplating process to form a metal copper layer on the gate line, the electrode through hole and the corresponding area of ​​the conductive pattern; removing the mask and the copper seed layer under the mask; A metal tin coating layer is coated on the surface of the metal copper layer formed in the area corresponding to the gate line; The silicon heterojunction body is subjected to low temperature heat treatment.

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