Solar cell and method for manufacturing the same

Abstract

A solar cell unit and a method for manufacturing the solar cell unit are provided. The solar cell unit includes: a silicon substrate; a passivation dielectric layer disposed on the silicon substrate; a first silicon layer, a second silicon layer, and a third silicon layer disposed sequentially on a surface of the passivation dielectric layer facing away from the silicon substrate and in direct contact with each other; and a metal contact electrode disposed on a side of the first silicon layer facing away from the passivation dielectric layer.

Description

Technical Field

[0001] The present disclosure relates to a solar cell unit and a method for manufacturing a solar cell unit. Background Art

[0002] Human survival and development are inseparable from energy. Solar energy is one of the most advantageous renewable, abundant, and clean energy sources. Crystalline silicon solar cells are semiconductor devices that convert light energy directly into electrical energy. High photoelectric conversion rates and low operating costs are what humans crave for crystalline silicon solar cells. High-efficiency solar cells must possess good surface passivation and a low surface recombination rate, thereby achieving high open-circuit voltage, short-circuit current, and conversion efficiency. Currently, surface passivation is primarily achieved through single-layer or multi-layer dielectric film structures. However, metallization is required after surface passivation. For example, metallization is achieved by printing metal contact electrodes on the dielectric film structure. In this case, the metal contact electrodes are inevitably damaged when the dielectric film structure is formed beneath the printed metal contact electrodes, resulting in a relatively high surface recombination rate in the metal contact area, which in turn reduces the open-circuit voltage of the cell.

[0003] A passivated contact solar cell has been proposed, comprising an ultrathin oxide layer and a doped silicon film layer on top. This cell effectively achieves passivation while reducing surface contact recombination caused by metal contacts, effectively improving the cell's open-circuit voltage and conversion efficiency. However, further improvements in these two areas are still needed. Summary of the Invention

[0004] At least some embodiments of the present disclosure provide a solar cell unit comprising: a silicon substrate; a passivation dielectric layer disposed on the silicon substrate; a first silicon layer, a second silicon layer, and a third silicon layer, which are sequentially disposed on a surface of the passivation dielectric layer facing away from the silicon substrate and are in direct contact with each other; and a metal contact electrode disposed on a side of the first silicon layer facing away from the passivation dielectric layer.

[0005] For example, in some embodiments, the solar cell unit further includes: a transparent conductive layer disposed on a surface of the third silicon layer facing away from the second silicon layer; and the metal contact electrode disposed on a surface of the transparent conductive layer facing away from the silicon substrate and in direct contact with the surface of the transparent conductive layer.

[0006] For example, in some embodiments, the first silicon layer is a doped polycrystalline silicon layer, the second silicon layer is a single layer or a stack of one or more of an undoped microcrystalline silicon layer, an amorphous silicon layer, and a polymorphic silicon layer, the third silicon layer is a single layer or a stack of one or more of a doped microcrystalline silicon layer, an amorphous silicon layer, and a polymorphic silicon layer, and the first silicon layer and the third silicon layer have the same doping type, which is n-type or p-type.

[0007] For example, in some embodiments, the doping concentration of the first silicon layer is 1*10 20 to 1*10 21 Number of atoms / cm 3 The doping concentration of the third silicon layer is within the range of 5*10 18 Up to 5*10 20 Number of atoms / cm 3 within the range.

[0008] For example, in some embodiments, the first silicon layer is a crystallized polysilicon layer.

[0009] For example, in some embodiments, the passivation dielectric layer includes a single layer or a stack of one or more of silicon oxide, titanium oxide, aluminum oxide, aluminum nitride, and silicon nitride.

[0010] For example, in some embodiments, the thickness of the first silicon layer is in the range of 10-300 nm, the thickness of the second silicon layer is in the range of 1-100 nm, and the thickness of the third silicon layer is in the range of 1-100 nm.

[0011] For example, in some embodiments, the transparent conductive layer includes a metal oxide with a doping element or a metal nitride with a doping element.

[0012] For example, in some embodiments, the metal oxide includes at least one of indium oxide, tin oxide, zinc oxide, and cadmium oxide, the metal nitride includes at least one of titanium nitride, and the doping element includes at least one of indium, tin, calcium, aluminum, and fluorine.

[0013] At least some embodiments of the present disclosure provide a method for manufacturing a solar cell unit, comprising: providing a silicon substrate; forming a passivation dielectric layer on a surface of the silicon substrate; sequentially forming a first silicon layer, a second silicon layer, and a third silicon layer on a surface of the passivation dielectric layer facing away from the silicon substrate, wherein the first silicon layer, the second silicon layer, and the third silicon layer are in direct contact with each other; and forming a metal contact electrode on a side of the first silicon layer facing away from the passivation dielectric layer.

[0014] For example, in some embodiments, the manufacturing method further includes: forming a transparent conductive layer on a surface of the third silicon layer facing away from the second silicon layer. The metal contact electrode is formed on a surface of the transparent conductive layer facing away from the silicon substrate and directly contacts the surface of the transparent conductive layer.

[0015] For example, in some embodiments, the first silicon layer is a doped polysilicon layer. Forming the first silicon layer includes: forming a first pre-layer, the first pre-layer including a single layer or a stack of one or more of a microcrystalline silicon layer, an amorphous silicon layer, and polysilicon with dopant atoms; and performing a high-temperature annealing heat treatment to activate the dopant atoms and crystallize the first pre-layer to transform it into the first silicon layer.

[0016] For example, in some embodiments, the first pre-layer further includes a single layer or a stacked layer of one or more of an undoped microcrystalline silicon layer, an amorphous silicon layer, and a polycrystalline silicon layer.

[0017] For example, in some embodiments, the second silicon layer is a single layer or a stack of one or more of an undoped microcrystalline silicon layer, an amorphous silicon layer, and a polymorphic silicon layer, the third silicon layer is a single layer or a stack of one or more of a doped microcrystalline silicon layer, an amorphous silicon layer, and a polymorphic silicon layer, and the first silicon layer and the third silicon layer have the same doping type, which is n-type or p-type.

[0018] For example, in some embodiments, the passivation dielectric layer includes a single layer or a stack of one or more of silicon oxide, titanium oxide, aluminum oxide, aluminum nitride, and silicon nitride.

[0019] For example, in some embodiments, the transparent conductive layer includes a metal oxide with a doping element or a metal nitride with a doping element, and the metal oxide includes at least one of indium oxide, tin oxide, zinc oxide and cadmium oxide, the metal nitride includes at least one of titanium nitride, and the doping element includes at least one of indium, tin, calcium, aluminum and fluorine. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1 A schematic diagram of a partial structure of a solar cell unit according to an embodiment of the present disclosure is shown;

[0021] Figure 2 Shown Figure 1 A schematic plan view of a solar cell unit is shown;

[0022] Figure 3 A flow chart showing a method for manufacturing a solar cell unit according to an embodiment of the present disclosure is shown;

[0023] Figures 4A-4F Shown respectively with Figure 3 Schematic diagram of the structure corresponding to each step of the manufacturing method of the solar cell unit shown;

[0024] Figure 5 A schematic plan view of a solar cell unit according to another embodiment of the present disclosure is shown; and

[0025] Figure 6 A partial structural schematic diagram of a solar cell unit according to another embodiment of the present disclosure is shown.

[0026] Wherein, the accompanying drawings are marked as follows:

[0027] 1 Silicon substrate

[0028] 2 Passivation dielectric layer

[0029] 3 First silicon layer

[0030] 4 Second silicon layer

[0031] 5 Third silicon layer

[0032] 6 Transparent conductive layer

[0033] 7 Metal contact electrodes DETAILED DESCRIPTION

[0034] Hereinafter, a solar cell unit and a method for manufacturing the same according to embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0035] According to at least one embodiment of the present disclosure, a solar cell unit is provided, which may include: a silicon substrate; a passivation dielectric layer, which is arranged on the silicon substrate; a first silicon layer, a second silicon layer, and a third silicon layer, which are arranged in sequence on the surface of the passivation dielectric layer facing away from the silicon substrate and are in direct contact with each other; and a metal contact electrode, which is arranged on the side of the first silicon layer facing away from the passivation dielectric layer.

[0036] The structural layer of the solar cell unit not only forms a silicon thin film structure with a relatively high bandgap width, but also further improves the surface passivation performance of the solar cell and increases the open circuit voltage of the cell.

[0037] For example, the silicon substrate may be an n-type or p-type silicon substrate. For example, the silicon substrate may be a single crystal silicon substrate or a polycrystalline silicon substrate. For example, the resistivity of the silicon substrate is in the range of 0.1-20 Ω·cm, and the thickness thereof is in the range of 40-300 μm.

[0038] For example, the first silicon layer is a doped polycrystalline silicon layer that has undergone a high-temperature annealing heat treatment and is therefore a crystallized polycrystalline silicon layer. For example, the second silicon layer is a single layer or a stack of one or more of an undoped microcrystalline silicon layer, an amorphous silicon layer, and a polysilicon layer. For example, the third silicon layer is a single layer or a stack of one or more of a doped microcrystalline silicon layer, an amorphous silicon layer, and a polysilicon layer. The first silicon layer and the third silicon layer have the same doping type, which is n-type or p-type.

[0039] The second silicon layer and the third silicon layer have a wider bandgap than the first silicon layer. As an example, the bandgap of the second silicon layer and the third silicon layer is about 1.74 eV, and the bandgap of the first silicon layer is about 1.38 eV.

[0040] For example, the doping concentration of the first silicon layer is greater than the doping concentration of the third silicon layer. 20 to 1*10 21 Number of atoms / cm 3 The doping concentration of the third silicon layer is within the range of 5*10 18 Up to 5*1020 Number of atoms / cm 3 within the range.

[0041] For example, the thickness of the first silicon layer is in the range of 10-300 nm, the thickness of the second silicon layer is in the range of 1-100 nm, and the thickness of the third silicon layer is in the range of 1-100 nm.

[0042] Herein, the term "polymorphic silicon" refers to silicon that exists in a mixed manner in multiple crystalline states, including, for example, amorphous silicon, nanocrystalline silicon, and microcrystalline silicon mixed together, or amorphous silicon and microcrystalline silicon mixed together, or amorphous silicon and nanocrystalline silicon mixed together.

[0043] For example, the passivation dielectric layer includes a single layer or a stack of one or more of silicon oxide, titanium oxide, aluminum oxide, aluminum nitride, and silicon nitride. For example, the thickness of the passivation dielectric layer is in the range of 0.1-10 nm. For example, the passivation dielectric layer can be disposed on the backlight side of the silicon substrate in the solar cell.

[0044] For example, in some embodiments, the solar cell unit may be a heterojunction cell, such as an n-type heterojunction cell having an n-type silicon substrate. For n-type heterojunction cells, reference may be made to Chapter 10, Section 10.1 of "Principles of Crystalline Silicon Solar Cell Manufacturing Process" edited by Chen Zhegen and Zheng Zhidong (China Industry and Information Technology Publishing Group, Electronics Industry Press, first edition, March 2017), which is incorporated herein by reference. For example, a passivation dielectric layer may be disposed on the backlight side of the silicon substrate in the n-type heterojunction cell.

[0045] In addition, in some embodiments, the solar cell unit may further include a transparent conductive layer disposed on the surface of the third silicon layer facing away from the second silicon layer, and the metal contact electrode is disposed on the surface of the transparent conductive layer facing away from the silicon substrate and in direct contact with the surface of the transparent conductive layer.

[0046] The provision of a transparent conductive layer and metal contact electrodes is beneficial to the lateral transmission of current, which improves the fill factor and thus improves the conversion efficiency of the battery.

[0047] For example, the transparent conductive layer includes a metal oxide or metal nitride with a doping element, wherein the metal oxide includes indium oxide, tin oxide, zinc oxide, and cadmium oxide, and the metal nitride includes titanium nitride, and the doping element includes indium, tin, calcium, aluminum, and fluorine. For example, the thickness of the transparent conductive layer can be in the range of 1-300 nm, or 1-100 nm.

[0048] Furthermore, in some other embodiments, the metal contact electrode of the solar cell unit may pass through the third silicon layer and the second silicon layer to directly contact the first silicon layer, and the metal contact electrode may also directly contact the surface of the third silicon layer facing away from the second silicon layer.

[0049] According to at least one embodiment of the present disclosure, a method for manufacturing a solar cell unit is provided, which may include: providing a silicon substrate; forming a passivation dielectric layer on a surface of the silicon substrate; sequentially forming a first silicon layer, a second silicon layer, and a third silicon layer on a surface of the passivation dielectric layer facing away from the silicon substrate, wherein the first silicon layer, the second silicon layer, and the third silicon layer are in direct contact with each other; and forming a metal contact electrode on a side of the first silicon layer facing away from the passivation dielectric layer.

[0050] This method can be used to manufacture the solar cell unit described above.

[0051] Specifically, forming the first silicon layer may include: forming a first prelayer, which includes a single layer or a stack of one or more of a microcrystalline silicon layer, an amorphous silicon layer and polycrystalline silicon with doped atoms; and performing a high-temperature annealing heat treatment to activate the doping atoms and crystallize the first prelayer to transform it into the first silicon layer.

[0052] In addition, for example, the first pre-layer may further include a single layer or a stacked layer of one or more of an undoped microcrystalline silicon layer, an amorphous silicon layer, and a polycrystalline silicon layer.

[0053] In some embodiments, compared to a first pre-layer having only a doped portion, a first pre-layer having both a doped portion and an undoped portion can form a film layer of the same thickness in a shorter time, for example, through a plasma-enhanced chemical vapor deposition (PECVD) process. This improves production efficiency. Here, both the doped portion and the undoped portion of the first pre-layer are doped and crystallized after the high-temperature annealing treatment, so that the entire first pre-layer is converted into a doped polysilicon layer.

[0054] For example, the method may also include surface treatment of the surface of the silicon substrate on which the passivation dielectric layer is to be formed before forming the passivation dielectric layer, including first texturing the surface of the silicon substrate, then smoothing the pyramids of the texturized surface, or further wet etching or polishing the surface.

[0055] For example, the passivation dielectric layer can be formed by using a low-temperature furnace tube oxidation process, a nitric acid oxidation process, an ozone oxidation process, an atomic layer deposition (ALD) process (for example, including plasma enhanced atomic layer deposition (PEALD), plasma enhanced atomic layer deposition (PEALD), etc.), a chemical vapor deposition (CVD) process (for example, including plasma enhanced chemical vapor deposition (PECVD), low pressure chemical vapor deposition (LPCVD), atmospheric pressure chemical vapor deposition (APCVD), etc.), a physical vapor deposition (PVD) process (such as sputtering or evaporation), a reactive plasma deposition (RPD) process, etc.

[0056] For example, the first prelayer, the second silicon layer or the third silicon layer may be formed by plasma enhanced chemical vapor deposition (PECVD), physical vapor deposition (PVD), low pressure chemical vapor deposition (LPCVD) or atmospheric pressure chemical vapor deposition (APCVD) processes.

[0057] In addition, the method may further include forming a transparent conductive layer on a surface of the third silicon layer facing away from the second silicon layer. For example, the transparent conductive layer may be formed by physical vapor deposition (PVD) or reactive plasma deposition (RPD).

[0058] For example, the metal contact electrodes may be formed by screen printing, electroplating, or a combination of the two.

[0059] It should be noted that the embodiments of the present disclosure only describe the structure on one surface of the silicon substrate. Such a structure can be provided on the front side of the solar cell unit that receives light or on the back side opposite to the front side, and the present disclosure is not limited thereto. The present disclosure does not limit the structure on the other surface of the silicon substrate. As an example, a doping layer having a doping type opposite to that of the first silicon layer, a passivation layer on the surface of the doping layer facing away from the silicon substrate, and a metal contact electrode that passes through the passivation layer and contacts the doping layer can be formed on the other surface of the silicon substrate. As an example, a heterojunction structure can be formed on the other surface of the silicon substrate.

[0060] Figure 1FIG2 shows a partial structural diagram of a solar cell unit according to an embodiment of the present disclosure. Figure 2 Shown Figure 1 Schematic plan view of a solar cell unit shown.

[0061] like Figure 1 As shown, the solar cell unit includes: a silicon substrate 1; a passivation dielectric layer 2 arranged on a surface of the silicon substrate 1; a first silicon layer 3, a second silicon layer 4 and a third silicon layer 5 arranged in sequence on the surface of the passivation dielectric layer 2 facing away from the silicon substrate 1 and in contact with each other; a transparent conductive layer 6 arranged on the surface of the third silicon layer 5 facing away from the second silicon layer 4; and a metal contact electrode 7 arranged on the surface of the transparent conductive layer 6 facing away from the third silicon layer 5 and in direct contact with the surface of the transparent conductive layer 6.

[0062] The solar cell unit has three silicon layers 3, 4, 5, which form a silicon thin film structure with a relatively high band gap, which not only further improves the surface passivation performance of the solar cell, but also increases the open circuit voltage of the cell.

[0063] In addition, a transparent conductive layer 6 and a metal contact electrode 7 in direct contact with the transparent conductive layer 6 are sequentially formed on the surface of the third silicon layer 5 facing away from the second silicon layer 4. The provision of the transparent conductive layer 6 and the metal contact electrode 7 facilitates lateral current transmission, improves the fill factor, and thus improves the conversion efficiency of the battery.

[0064] Specifically, the silicon substrate 1 uses an n-type single-crystal silicon wafer with a resistivity of 0.1-20Ω·cm, the passivation dielectric layer 2 is a silicon dioxide layer with a thickness of 1.5nm, the first silicon layer 3 is a phosphorus (P)-doped polycrystalline silicon layer with a thickness of 70nm, the second silicon layer 4 is an intrinsic amorphous silicon layer with a thickness of 7nm, the third silicon layer 5 is a phosphorus-doped amorphous silicon layer with a thickness of 10nm, the transparent conductive layer 6 is an ITO (In2O3:Sn) layer with a thickness of 90nm, the ITO (In2O3:Sn) layer is an indium oxide layer with tin doping elements, and the metal contact electrode 7 is, for example, a silver electrode, an aluminum electrode or a silver-aluminum electrode.

[0065] like Figure 2 As shown, the metal contact electrode 7 may include a plurality of first strip electrodes 71 extending in a first direction and a plurality of second strip electrodes 72 extending in a second direction perpendicular to the first direction, wherein the width of the second strip electrodes is greater than the width of the first strip electrodes. For example, the plurality of first strip electrodes 71 may serve as fine grids of a solar cell, and the plurality of second strip electrodes 72 may serve as busbars of the solar cell.

[0066] Figure 3 A flow chart showing a method for manufacturing a solar cell unit according to an embodiment of the present disclosure is shown. Figures 4A-4F Shown respectively with Figure 3 The schematic diagram of the structure corresponding to each step of the manufacturing method of the solar cell unit shown in FIG. For example, the manufacturing method can be used to manufacture Figure 1 and Figure 2 The solar cell shown.

[0067] like Figure 3 As shown, the manufacturing method for manufacturing a solar cell unit includes:

[0068] Step S11, surface treatment of the silicon substrate 1: placing the silicon substrate 1 in a texturing tank containing KOH or NaOH solution to perform surface texturing to form a velvet structure, and then using a mixed solution of HNO3 and HF to smooth the pyramids of the velvet surface. Figure 4A shown.

[0069] Step S12, forming a passivation dielectric layer 2: using plasma enhanced chemical vapor deposition (PECVD) process to form a passivation dielectric layer 2 of silicon dioxide (SiO2) with a thickness of 1.5 nm on one surface of the silicon substrate 1, as shown in FIG. Figure 4B shown.

[0070] Step S13, forming a first silicon layer 3: In the same equipment used in step S12, a first pre-layer (not shown) of in-situ phosphorus-doped polysilicon with a thickness of 70 nm is formed on the surface of the passivation dielectric layer 2 facing away from the silicon substrate 1 by a PECVD process.

[0071] Step S14, annealing treatment: placing the silicon substrate 1 with the first pre-layer formed thereon in a furnace tube, and performing high temperature annealing heat treatment to activate the phosphorus atoms in situ doped in the first pre-layer and crystallize the first pre-layer to transform into the first silicon layer 3, thereby achieving high concentration doping and further improving the passivation performance, such as Figure 4C shown.

[0072] Step S15, forming a second silicon layer 4: using a PECVD process to form a second silicon layer 4 of undoped intrinsic amorphous silicon with a thickness of 7 nm on the surface of the first silicon layer 3 facing away from the passivation dielectric layer 2. Figure 4D shown.

[0073] Step S16, forming a third silicon layer 5: forming a third silicon layer 5 of in-situ phosphorus-doped amorphous silicon with a thickness of 10 nm on the surface of the second silicon layer 4 facing away from the first silicon layer 3 by a PECVD process, as shown in FIG. Figure 4E shown.

[0074] Step S17, forming a transparent conductive layer 6: forming a transparent conductive layer 6 of indium tin oxide ITO (In2O3: Sn) with a thickness of 90nm on the surface of the third silicon layer 5 facing away from the third silicon layer 5 by using a magnetron sputtering physical vapor deposition (PVD) process, as shown in FIG. Figure 4F shown.

[0075] Step S18, forming a metal contact electrode 7: using a screen printing process to directly form a patterned metal contact layer on the surface of the transparent conductive layer 6 facing away from the third silicon layer 5 to realize the metal contact electrode 7, such as Figure 1 shown.

[0076] According to another embodiment of the present disclosure, a solar cell unit includes: a silicon substrate 1; a passivation dielectric layer 2 arranged on a surface of the silicon substrate 1; a first silicon layer 3, a second silicon layer 4 and a third silicon layer 5 arranged in sequence on the surface of the passivation dielectric layer 2 facing away from the silicon substrate 1 and in contact with each other; a transparent conductive layer 6 arranged on the surface of the third silicon layer 5 facing away from the second silicon layer 4; and a metal contact electrode 7 arranged on the surface of the transparent conductive layer 6 facing away from the third silicon layer 5 and in direct contact with the surface of the transparent conductive layer 6.

[0077] Specifically, the silicon substrate 1 adopts a p-type single-crystal silicon wafer with a resistivity of 0.1-20Ω·cm, the passivation dielectric layer 2 is a 1.3nm thick aluminum oxide (Al2O3) and titanium oxide (TiO2) stack, the first silicon layer 3 is a 100nm thick phosphorus (P) doped polycrystalline silicon layer, the second silicon layer 4 is a 5nm thick intrinsic amorphous silicon layer, the third silicon layer 5 is a 15nm phosphorus doped amorphous silicon layer, the transparent conductive layer 6 is a 100nm thick aluminum zinc oxide AZO (ZnO:Al) layer, the AZO (ZnO:Al) layer is a zinc oxide layer with aluminum doping elements, and the metal contact electrode 7 is, for example, a silver electrode, an aluminum electrode or a silver-aluminum electrode.

[0078] According to another embodiment of the present disclosure, a method for manufacturing a solar cell unit includes:

[0079] Step S21, surface treatment of the silicon substrate 1: placing a p-type single crystal silicon wafer with a resistivity of 0.1 to 20 Ω·cm in a texturing tank containing KOH or NaOH solution for surface texturing to form a velvet structure, then using a mixed solution of HNO3 and HF to smooth the pyramids of the velvet surface, and finally polishing one surface of the silicon substrate 1 with a NaOH solution.

[0080] Step S22, forming a passivation dielectric layer 2: forming a passivation dielectric layer 2 of aluminum oxide (Al2O3) and titanium oxide (TiO2) stacked layers with a thickness of 1.3 nm on the polished surface of the silicon substrate 1 by using an atomic layer deposition (ALD) process.

[0081] Step S23 , forming a first silicon layer 3 : forming a first pre-layer of in-situ phosphorus-doped amorphous silicon with a thickness of 100 nm on the surface of the passivation dielectric layer 2 facing away from the silicon substrate 1 by a physical vapor deposition (PVD) process.

[0082] Step S24, annealing treatment: the silicon substrate 1 with the first pre-layer formed thereon is placed in a furnace tube and subjected to high-temperature annealing heat treatment to activate the phosphorus atoms in situ doped in the first pre-layer and crystallize the first pre-layer to transform from the first pre-layer of amorphous silicon into the first silicon layer 3 of polycrystalline silicon, thereby achieving high-concentration doping and further improving the passivation performance.

[0083] Step S25 , forming a second silicon layer 4 : forming a second silicon layer 4 of undoped intrinsic amorphous silicon with a thickness of 5 nm on the surface of the first silicon layer 3 facing away from the passivation dielectric layer 2 by using a PECVD process.

[0084] Step S26 , forming a third silicon layer 5 : forming a third silicon layer 5 of phosphorus-doped amorphous silicon with a thickness of 15 nm on the surface of the second silicon layer 4 facing away from the first silicon layer 3 by using a PECVD process.

[0085] Step S27 , forming a transparent conductive layer 6 : forming a transparent conductive layer 6 of aluminum zinc oxide AZO (ZnO:Al) with a thickness of 100 nm on the surface of the third silicon layer 5 facing away from the second silicon layer 4 by using a reactive plasma deposition (RPD) process.

[0086] Step S28 , forming a metal contact electrode 7 : directly forming a patterned metal contact layer on the surface of the transparent conductive layer 6 facing away from the third silicon layer 5 by using a screen printing process to realize the metal contact electrode 7 .

[0087] According to another embodiment of the present disclosure, a solar cell unit includes: a silicon substrate 1; a passivation dielectric layer 2 disposed on a surface of the silicon substrate 1; a first silicon layer 3, a second silicon layer 4, and a third silicon layer 5 sequentially disposed on a surface of the passivation dielectric layer 2 facing away from the silicon substrate 1 and in contact with each other; a transparent conductive layer 6 disposed on a surface of the third silicon layer 5 facing away from the second silicon layer 4; and a metal contact electrode 7 disposed on a surface of the transparent conductive layer 6 facing away from the third silicon layer 5 and in direct contact with the surface of the transparent conductive layer 6.

[0088] Specifically, the silicon substrate 1 is an n-type single-crystal silicon wafer with a resistivity of 0.1-20Ω·cm, the passivation dielectric layer 2 is a silicon dioxide layer with a thickness of 1.0nm, the first silicon layer 3 is an 80nm phosphorus-doped polycrystalline silicon layer, the second silicon layer 4 is an intrinsic amorphous silicon layer with a thickness of 10nm, the third silicon layer 5 is a phosphorus-doped microcrystalline silicon layer with a thickness of 10nm, the transparent conductive layer 6 is an indium tin oxide ITO (In2O3:Sn) layer with a thickness of 80nm, and the metal contact electrode 7 is, for example, a silver electrode, an aluminum electrode or a silver-aluminum electrode.

[0089] According to yet another embodiment of the present disclosure, a method for manufacturing a solar cell unit includes:

[0090] Step S31, surface treatment of the silicon substrate 1: placing an n-type single crystal silicon wafer with a resistivity of 0.1-20Ω·cm in a texturing tank containing KOH or NaOH solution for surface texturing to form a textured surface structure, and then wet etching the textured surface with a mixed solution of HNO3 and HF.

[0091] Step S32 , forming a passivation dielectric layer 2 : forming a passivation dielectric layer 2 of silicon dioxide (SiO 2 ) with a thickness of 1.0 nm on one surface of the silicon substrate 1 by a nitric acid oxidation process, as shown in FIG. 4 .

[0092] Step S33, forming a first silicon layer 3: A first pre-layer having a thickness of 80 nm is formed on the surface of the passivation dielectric layer 2 facing away from the silicon substrate 1 using a physical vapor deposition (PVD) process. The first pre-layer includes a 40 nm thick intrinsic non-doped portion and a 40 nm thick in-situ phosphorus-doped doped portion. Here, the non-doped portion is positioned closer to the passivation dielectric layer 2 than the doped portion. In other examples, the doped portion may be positioned closer to the passivation dielectric layer 2 than the non-doped portion.

[0093] Step S34, annealing treatment: the silicon substrate 1 with the first pre-layer formed thereon is placed in a furnace tube, and a high-temperature annealing heat treatment is performed to activate the phosphorus atoms in the doped part of the first pre-layer and diffuse them to the non-doped part, and at the same time, the first pre-layer is crystallized to convert it into the first silicon layer 3 of polycrystalline silicon, thereby finally achieving full high-concentration doping and further improving the passivation performance.

[0094] Step S35 , forming a second silicon layer 4 : forming a second silicon layer 4 of undoped intrinsic amorphous silicon with a thickness of 10 nm on the surface of the first silicon layer 3 facing away from the passivation dielectric layer 2 by using a PECVD process.

[0095] Step S36 , forming a third silicon layer 5 : forming a third silicon layer 5 of phosphorus-doped microcrystalline silicon with a thickness of 10 nm on the surface of the second silicon layer 4 facing away from the first silicon layer 3 by using a PECVD process.

[0096] Step S37 , forming a transparent conductive layer 6 : forming a transparent conductive layer 6 of indium tin oxide ITO (In 2 O 3 : Sn) with a thickness of 80 nm on the surface of the third silicon layer 5 facing away from the second silicon layer 4 by using a PVD process.

[0097] Step S38 , forming a metal contact electrode 7 : directly forming a patterned metal contact layer on the surface of the transparent conductive layer 6 facing away from the third silicon layer 5 by using a screen printing process to realize the metal contact electrode 7 .

[0098] According to another embodiment of the present disclosure, a solar cell unit includes: a silicon substrate 1; a passivation dielectric layer 2 disposed on a surface of the silicon substrate 1; a first silicon layer 3, a second silicon layer 4, and a third silicon layer 5 sequentially disposed on a surface of the passivation dielectric layer 2 facing away from the silicon substrate 1 and in contact with each other; a transparent conductive layer 6 disposed on a surface of the third silicon layer 5 facing away from the second silicon layer 4; and a metal contact electrode 7 disposed on a surface of the transparent conductive layer 6 facing away from the third silicon layer 5 and in direct contact with the surface of the transparent conductive layer 6.

[0099] Figure 5 FIG. 1 shows a schematic plan view of a solar cell unit according to another embodiment of the present disclosure. Figure 5 As shown, the metal contact electrode 7 only includes a plurality of first strip electrodes 71 extending in a first direction. For example, the plurality of first strip electrodes 71 can be used as fine grids of a solar cell unit.

[0100] Specifically, the silicon substrate 1 is a p-type single-crystal silicon wafer with a resistivity of 0.1-20Ω·cm, the passivation dielectric layer 2 is a silicon dioxide layer with a thickness of 2.0nm, the first silicon layer 3 is a 120nm boron (B)-doped polycrystalline silicon layer, the second silicon layer 4 is an intrinsic microcrystalline silicon layer with a thickness of 15nm, the third silicon layer 5 is a 9nm boron-doped polysilicon layer, the transparent conductive layer 6 is a 110nm thick fluorine (F)-doped tin oxide FTO (SnO2:F) layer, and the metal contact electrode 7 is, for example, a silver electrode, an aluminum electrode or a silver-aluminum electrode.

[0101] According to yet another embodiment of the present disclosure, a method for manufacturing a solar cell unit includes:

[0102] Step S41, surface treatment of the silicon substrate 1: texturing the surface of a p-type single crystal silicon wafer with a resistivity of 0.1-20Ω·cm in a texturing tank containing KOH or NaOH solution to form a textured surface structure, and then wet etching the textured surface with a mixed solution of HNO3 and HF.

[0103] In step S42 , a passivation dielectric layer 2 of silicon dioxide (SiO 2 ) with a thickness of 2.0 nm is formed on one surface of the silicon substrate 1 by a low pressure chemical vapor deposition (LPCVD) process.

[0104] Step S43, forming a first silicon layer 3: In the same equipment used in step S42, a first pre-layer of in-situ boron (B) doped amorphous silicon with a thickness of 120 nm is formed on the surface of the passivation dielectric layer 2 facing away from the silicon substrate 1 by an LPCVD process.

[0105] Step S44, annealing treatment: the silicon substrate 1 with the first pre-layer formed thereon is placed in a furnace tube and subjected to high-temperature annealing heat treatment to activate the boron atoms in situ doped in the first pre-layer and crystallize the first pre-layer to transform from the first pre-layer of amorphous silicon into the first silicon layer 3 of polycrystalline silicon, thereby achieving high-concentration doping and further improving the passivation performance.

[0106] Step S45 , forming a second silicon layer 4 : forming a second silicon layer 4 of undoped intrinsic microcrystalline silicon with a thickness of 15 nm on the surface of the first silicon layer 3 facing away from the passivation dielectric layer 2 by a PECVD process.

[0107] Step S46 , forming a third silicon layer 5 : forming a third silicon layer 5 of boron-doped polysilicon with a thickness of 9 nm on the surface of the second silicon layer 4 facing away from the first silicon layer 3 by using a PECVD process.

[0108] Step S47 , forming a transparent conductive layer 6 : forming a transparent conductive layer 6 of fluorine (F)-doped tin oxide FTO (SnO 2 :F) with a thickness of 110 nm on the surface of the third silicon layer 5 facing away from the second silicon layer 4 by using an RPD process.

[0109] Step S48 , forming a metal contact electrode 7 : using a mask and an electroplating process to form a patterned metal contact layer on the surface of the transparent conductive layer 6 facing away from the third silicon layer 5 , thereby realizing the metal contact electrode 7 .

[0110] Figure 6 A partial structural schematic diagram of a solar cell unit according to yet another embodiment of the present disclosure is shown.

[0111] like Figure 6 As shown, the solar cell unit includes: a silicon substrate 1; a passivation dielectric layer 2 arranged on one surface of the silicon substrate 1; a first silicon layer 3, a second silicon layer 4 and a third silicon layer 5 arranged in sequence on the surface of the passivation dielectric layer 2 facing away from the silicon substrate 1 and in contact with each other; and a metal contact electrode 7, which passes through the third silicon layer 5 and the second silicon layer 4 and is in direct contact with the first silicon layer 3.

[0112] In this embodiment, the metal contact electrode 7 passes through the third silicon layer 5 and the second silicon layer 4 and directly contacts the heavily doped first silicon layer 3. Therefore, the fill factor is improved, thereby improving the conversion efficiency of the battery.

[0113] Specifically, the silicon substrate 1 uses an n-type single-crystal silicon wafer with a resistivity of 0.1-20Ω·cm, the passivation dielectric layer 2 is a silicon dioxide layer with a thickness of 1.5nm, the first silicon layer 3 is a phosphorus (P)-doped polycrystalline silicon layer with a thickness of 70nm, the second silicon layer 4 is an intrinsic amorphous silicon layer with a thickness of 7nm, the third silicon layer 5 is a phosphorus-doped polycrystalline silicon layer with a thickness of 9nm, and the metal contact electrode 7 is, for example, a silver electrode, an aluminum electrode or a silver-aluminum electrode.

[0114] The manufacturing method is not limited to the order of the steps described herein. Alternatively, in alternative embodiments, steps may be omitted, or other steps may be added. Alternatively, in alternative embodiments, the order of the steps may be rearranged. Alternatively, one or more of the steps may be performed simultaneously.

[0115] This disclosure describes at least the following technical solutions:

[0116] Solution 1: A solar cell unit comprising:

[0117] Silicon substrate (1);

[0118] a passivation dielectric layer (2) disposed on the silicon substrate (1);

[0119] A first silicon layer (3), a second silicon layer (4) and a third silicon layer (5), which are sequentially arranged on the surface of the passivation dielectric layer (2) facing away from the silicon substrate (1) and are in direct contact with each other; and a metal contact electrode (7), which is arranged on the side of the first silicon layer (3) facing away from the passivation dielectric layer (2).

[0120] Solution 2: The solar cell unit according to Solution 1, further comprising:

[0121] a transparent conductive layer (6) disposed on a surface of the third silicon layer (5) facing away from the second silicon layer (4),

[0122] The metal contact electrode (7) is arranged on the surface of the transparent conductive layer (6) facing away from the silicon substrate (1) and is in direct contact with the surface of the transparent conductive layer (6).

[0123] Solution 3: The solar cell unit according to solution 1 or 2, wherein:

[0124] The first silicon layer (3) is a doped polysilicon layer,

[0125] The second silicon layer (4) is a single layer or a stack of one or more of an undoped microcrystalline silicon layer, an amorphous silicon layer, and a polymorphic silicon layer.

[0126] The third silicon layer (5) is a single layer or a stack of one or more of a doped microcrystalline silicon layer, an amorphous silicon layer, and a polymorphic silicon layer, and

[0127] The first silicon layer (3) and the third silicon layer (5) have the same doping type, which is n-type or p-type.

[0128] Solution 4: The solar cell unit according to Solution 3, wherein:

[0129] The doping concentration of the first silicon layer (3) is in the range of 1*1020 to 1*1021 atoms / cm3, and

[0130] The doping concentration of the third silicon layer (5) is in the range of 5*1018 to 5*1020 atoms / cm3.

[0131] Solution 5: The solar cell unit according to solution 1 or 2, wherein:

[0132] The first silicon layer (3) is a crystallized polysilicon layer.

[0133] Solution 6: The solar cell unit according to solution 1 or 2, wherein:

[0134] The passivation dielectric layer (2) comprises a single layer or a stacked layer of one or more of silicon oxide, titanium oxide, aluminum oxide, aluminum nitride and silicon nitride.

[0135] Solution 7: The solar cell unit according to solution 1 or 2, wherein:

[0136] The thickness of the first silicon layer (3) is in the range of 10-300 nm,

[0137] The thickness of the second silicon layer (4) is in the range of 1-100 nm, and

[0138] The thickness of the third silicon layer (5) is in the range of 1-100 nm.

[0139] Solution 8: The solar cell unit according to solution 1 or 2, wherein:

[0140] The transparent conductive layer (6) comprises a metal oxide with a doping element or a metal nitride with a doping element.

[0141] Solution 9. The solar cell unit according to Solution 8, wherein:

[0142] The metal oxide includes at least one of indium oxide, tin oxide, zinc oxide and cadmium oxide, the metal nitride includes at least one of titanium nitride, and the doping element includes at least one of indium, tin, calcium, aluminum and fluorine.

[0143] Solution 10: A method for manufacturing a solar cell unit, comprising:

[0144] Providing a silicon substrate (1);

[0145] forming a passivation dielectric layer (2) on a surface of the silicon substrate (1);

[0146] forming a first silicon layer (3), a second silicon layer (4) and a third silicon layer (5) in sequence on a surface of the passivation dielectric layer (2) facing away from the silicon substrate (1), wherein the first silicon layer (3), the second silicon layer (4) and the third silicon layer (5) are in direct contact with each other; and

[0147] A metal contact electrode (7) is formed on the side of the first silicon layer (3) facing away from the passivation dielectric layer (2).

[0148] Solution 11: The manufacturing method according to Solution 10, further comprising:

[0149] forming a transparent conductive layer (6) on the surface of the third silicon layer (5) facing away from the second silicon layer (4);

[0150] The metal contact electrode (7) is formed on the surface of the transparent conductive layer (6) facing away from the silicon substrate (1) and is in direct contact with the surface of the transparent conductive layer (6).

[0151] Option 12: The manufacturing method according to Option 10 or 11, wherein:

[0152] The first silicon layer (3) is a doped polysilicon layer,

[0153] Forming the first silicon layer (3) includes:

[0154] forming a first pre-layer including a single layer or a stack of one or more of a microcrystalline silicon layer, an amorphous silicon layer, and polycrystalline silicon with doped atoms; and

[0155] A high temperature annealing heat treatment is performed to activate the doping atoms and crystallize the first pre-layer to transform it into the first silicon layer (3).

[0156] Option 13. The manufacturing method according to Option 12, wherein:

[0157] The first front layer further includes a single layer or a stacked layer of one or more of an undoped microcrystalline silicon layer, an amorphous silicon layer and a polycrystalline silicon layer.

[0158] Option 14. The manufacturing method according to Option 10 or 11, wherein:

[0159] The second silicon layer (4) is a single layer or a stack of one or more of an undoped microcrystalline silicon layer, an amorphous silicon layer, and a polymorphic silicon layer.

[0160] The third silicon layer (5) is a single layer or a stack of one or more of a doped microcrystalline silicon layer, an amorphous silicon layer, and a polymorphic silicon layer, and

[0161] The first silicon layer (3) and the third silicon layer (5) have the same doping type, which is n-type or p-type.

[0162] Option 15. The manufacturing method according to Option 10 or 11, wherein:

[0163] The passivation dielectric layer (2) comprises a single layer or a stacked layer of one or more of silicon oxide, titanium oxide, aluminum oxide, aluminum nitride and silicon nitride.

[0164] Option 16. The manufacturing method according to Option 10 or 11, wherein:

[0165] The transparent conductive layer (6) comprises a metal oxide with a doping element or a metal nitride with a doping element, and

[0166] The metal oxide includes at least one of indium oxide, tin oxide, zinc oxide and cadmium oxide, the metal nitride includes at least one of titanium nitride, and the doping element includes at least one of indium, tin, calcium, aluminum and fluorine.

[0167] The scope of the present disclosure is not limited by the above-described embodiments but by the appended claims and their equivalents.

Claims

1. A solar cell unit comprising: Silicon substrate (1); a passivation dielectric layer (2) disposed on the silicon substrate (1); A first silicon layer (3), a second silicon layer (4) and a third silicon layer (5), which are sequentially arranged on a surface of the passivation dielectric layer (2) facing away from the silicon substrate (1) and are in direct contact with each other; and a metal contact electrode (7) disposed on a side of the first silicon layer (3) facing away from the passivation dielectric layer (2), The first silicon layer (3) is a doped polysilicon layer, The second silicon layer (4) is a single layer or a stack of one or more of an undoped microcrystalline silicon layer, an amorphous silicon layer, and a polymorphic silicon layer. The third silicon layer (5) is a single layer or a stack of one or more of a doped microcrystalline silicon layer, an amorphous silicon layer, and a polymorphic silicon layer, and The first silicon layer (3) and the third silicon layer (5) have the same doping type, which is n-type or p-type.

2. The solar cell unit according to claim 1, further comprising: a transparent conductive layer (6) disposed on a surface of the third silicon layer (5) facing away from the second silicon layer (4), The metal contact electrode (7) is arranged on the surface of the transparent conductive layer (6) facing away from the silicon substrate (1) and is in direct contact with the surface of the transparent conductive layer (6).

3. The solar cell unit according to claim 1 or 2, wherein: The doping concentration of the first silicon layer (3) is 1*10 20 to 1*10 21 Number of atoms / cm 3 within the range, and The doping concentration of the third silicon layer (5) is 5*10 18 Up to 5*10 20 Number of atoms / cm 3 within the range.

4. The solar cell unit according to claim 1 or 2, wherein: The first silicon layer (3) is a crystallized polysilicon layer.

5. The solar cell unit according to claim 1 or 2, wherein: The passivation dielectric layer (2) comprises a single layer or a stacked layer of one or more of silicon oxide, titanium oxide, aluminum oxide, aluminum nitride and silicon nitride.

6. The solar cell unit according to claim 1 or 2, wherein: The thickness of the first silicon layer (3) is in the range of 10-300 nm, The thickness of the second silicon layer (4) is in the range of 1-100 nm, and The thickness of the third silicon layer (5) is in the range of 1-100 nm.

7. The solar cell unit according to claim 1 or 2, wherein: The transparent conductive layer (6) comprises a metal oxide with a doping element or a metal nitride with a doping element.

8. The solar cell unit according to claim 7, wherein: The metal oxide includes at least one of indium oxide, tin oxide, zinc oxide and cadmium oxide, the metal nitride includes at least one of titanium nitride, and the doping element includes at least one of indium, tin, calcium, aluminum and fluorine.

9. A method for manufacturing a solar cell unit, comprising: Providing a silicon substrate (1); forming a passivation dielectric layer (2) on a surface of the silicon substrate (1); forming a first silicon layer (3), a second silicon layer (4) and a third silicon layer (5) in sequence on a surface of the passivation dielectric layer (2) facing away from the silicon substrate (1), wherein the first silicon layer (3), the second silicon layer (4) and the third silicon layer (5) are in direct contact with each other; as well as forming a metal contact electrode (7) on a side of the first silicon layer (3) facing away from the passivation dielectric layer (2), The first silicon layer (3) is a doped polysilicon layer, The second silicon layer (4) is a single layer or a stack of one or more of an undoped microcrystalline silicon layer, an amorphous silicon layer, and a polymorphic silicon layer. The third silicon layer (5) is a single layer or a stack of one or more of a doped microcrystalline silicon layer, an amorphous silicon layer, and a polymorphic silicon layer, and The first silicon layer (3) and the third silicon layer (5) have the same doping type, which is n-type or p-type.

10. The manufacturing method according to claim 9, further comprising: forming a transparent conductive layer (6) on the surface of the third silicon layer (5) facing away from the second silicon layer (4); The metal contact electrode (7) is formed on the surface of the transparent conductive layer (6) facing away from the silicon substrate (1) and is in direct contact with the surface of the transparent conductive layer (6).

11. The manufacturing method according to claim 9 or 10, wherein: Forming the first silicon layer (3) includes: forming a first pre-layer including a single layer or a stack of one or more of a microcrystalline silicon layer, an amorphous silicon layer, and polycrystalline silicon with doped atoms; and A high temperature annealing heat treatment is performed to activate the doping atoms and crystallize the first pre-layer to transform it into the first silicon layer (3).

12. The manufacturing method according to claim 11, wherein: The first front layer further includes a single layer or a stacked layer of one or more of an undoped microcrystalline silicon layer, an amorphous silicon layer and a polycrystalline silicon layer.

13. The manufacturing method according to claim 9 or 10, wherein: The passivation dielectric layer (2) comprises a single layer or a stacked layer of one or more of silicon oxide, titanium oxide, aluminum oxide, aluminum nitride and silicon nitride.

14. The manufacturing method according to claim 9 or 10, wherein: The transparent conductive layer (6) comprises a metal oxide with a doping element or a metal nitride with a doping element, and The metal oxide includes at least one of indium oxide, tin oxide, zinc oxide and cadmium oxide, the metal nitride includes at least one of titanium nitride, and the doping element includes at least one of indium, tin, calcium, aluminum and fluorine.

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