A dual-ion gate neuromorphic device and a preparation method thereof

Abstract

The application discloses a dual-ion grid type neuromorphic device and a preparation method thereof. The device comprises a substrate, a back gate electrode formed on the substrate, a back gate dielectric which is an ion oxide film and is formed on the back gate electrode, a two-dimensional film formed on the back gate dielectric and located above the back gate electrode as a channel, a source electrode and a drain electrode respectively formed at two ends of the channel, a top gate electrode formed on the back gate dielectric and arranged in parallel at a certain interval with the channel, the extension direction of the top gate electrode is orthogonal to the extension direction of the back gate electrode but does not overlap, and a top gate dielectric which is an ion gel and covers the channel and the top gate electrode. When pulse timing is applied to the top gate and the back gate at the same time, the channel conductance is regulated, the quantitative increase or decrease of the device conductance range is realized through the migration and injection of ions, the regulation process of two front ends of a heterogenous synapse to one post-synaptic end is simulated, and the simulation of the cooperative work of the heterogenous neuromorphic calculation is realized.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor technology, and particularly relates to a double-ion gate type neuromorphic device and a preparation method thereof. BACKGROUND

[0002] The neuromorphic device is a new type of electronic device with storage and computing functions, has the ability to simulate the working mode of the human brain, and is an important component unit of the next generation of high-efficiency computing chips. Therefore, it is of great significance to design the structure and develop the function of the neuromorphic device and make it have higher energy efficiency. The ion gate transistor utilizes the double-electron layer sensing function of ions and the movement of ions to realize the regulation of channel current, which is very similar to the process of ion regulating potential in biological bodies. Therefore, the ion gate transistor is gradually applied to simulate neuromorphic devices.

[0003] The structure of the commonly used three-terminal transistor device currently only has a single gate electrode, and the channel is regulated through the gate dielectric. Such a single-gate transistor has limited gate control ability on the channel, and has limited functions, and can only complete a single switch, which is difficult to meet the needs of the next generation of semiconductor high-gate control and multi-mode control.

[0004] Unlike the traditional front-end-back-end type synapse, the heterogeneity synapse can modulate one synapse through two presynaptic ends, thereby realizing efficient weight iteration and calculation, and is crucial for the normal life activities of biological bodies. Although the single-gate transistor can realize the simulation of the traditional synapse function, it cannot realize the function of the "two front ends and one back end" heterogeneity synapse. Therefore, in order to simulate the "two front ends and one back end" complex biological nervous system, it is of great value to explore a neuromorphic transistor device with double gates to simulate the behavior of the heterogeneity synapse. SUMMARY

[0005] The present application discloses a double-ion gate type neuromorphic device, which utilizes ion gel as a gate dielectric, utilizes the double-electron layer effect and the migration characteristics of movable ions, realizes the double-end synapse regulation function, and is used for constructing a new type of neuromorphic computing system with high gate control.

[0006] The dual-ion gate neuromorphic device includes: a substrate; a back gate electrode formed on the substrate; a back gate dielectric, which is an ion oxide thin film, formed on the back gate electrode; a two-dimensional thin film, formed on the back gate dielectric and located above the back gate electrode, serving as a channel; a source electrode and a drain electrode, respectively formed at both ends of the channel; a top gate electrode, formed on the back gate dielectric, arranged parallel to the channel at a certain interval, the extension direction of the gate electrode being orthogonal to the extension direction of the back gate electrode, but the top gate electrode and the back gate electrode do not overlap; a top gate dielectric, which is an ion gel, covering the channel and the top gate electrode, and applying pulse timing to the top gate and the back gate at the same time to regulate the channel conductance, and achieving a quantitative increase or decrease in the device conductance range through ion migration and injection, simulating the regulation process of two front ends of a heterogeneous neural synapse on a back end of a synapse, and realizing the simulation of heterogeneous neuromorphic computing collaborative work.

[0007] In the dual ion gate neuromorphic device of the present invention, preferably, the back gate dielectric is Li x SiO2、Li x AlO2 or Li x Ti2O4.

[0008] In the dual-ion gate neuromorphic device of the present invention, preferably, the top gate dielectric is Li ion gel.

[0009] In the dual ion gate neuromorphic device of the present invention, preferably, the two-dimensional thin film is WSe2, MoSe2, WS2 or MoS2.

[0010] In the dual ion gate neuromorphic device of the present invention, preferably, the distance between the top gate electrode and the channel is 50 μm to 150 μm.

[0011] The present invention also discloses a method for preparing a dual-ion gate neuromorphic device, comprising the following steps: forming a back gate electrode on a substrate; forming a back gate dielectric on the back gate electrode, which is an ion oxide film; forming a two-dimensional thin film as a channel on the back gate dielectric, which is located above the back gate electrode; forming a source electrode and a drain electrode at both ends of the channel respectively; forming a top gate electrode on the back gate dielectric, which is arranged parallel to the channel at a certain interval, and the extension direction of the gate electrode is orthogonal to the extension direction of the back gate electrode, but the top gate electrode does not overlap with the back gate electrode; dripping an ion gel solution on the channel and the top gate electrode, heating it to solidify it to form an ion gel as a top gate dielectric, and simultaneously applying a pulse sequence to the top gate and back gate to regulate the channel conductance, and achieving a quantitative increase or decrease in the device conductance range through ion migration and injection, simulating the regulation process of two front ends of heterologous neural synapses on a back end of a synapse, and realizing the simulation of heterologous neuromorphic computing collaborative work.

[0012] In the preparation method of the dual-ion gate type neuromorphic device, preferably, the back gate medium is Li x SiO2, Li x AlO2 or Li x Ti2O4.

[0013] In the preparation method of the dual-ion gate type neuromorphic device, preferably, the solute of the ion gel solution is LiClO4 crystals and polyvinyl alcohol with a mass ratio controlled at 1:8, the solvent is deionized water, and the concentration is 0.05 g / ml-2 g / ml.

[0014] In the preparation method of the dual-ion gate type neuromorphic device, preferably, the two-dimensional film is WSe2, MoSe2, WS2 or MoS2.

[0015] In the preparation method of the dual-ion gate type neuromorphic device, preferably, the heating temperature is 60-130℃, and the heating time is 5-20 min.

[0016] Beneficial effects:

[0017] (1) Break the traditional single gate working mode, introduce the double gate parallel operation of top gate and back gate, can improve the gate control ability of the device, and has great potential in improving the computing efficiency.

[0018] (2) Use ion gel as the gate medium layer to prepare neuromorphic transistors, use the ion movement in the gel to realize the conductance modulation of electronic synapses, which is more close to the weight adjustment and calculation process in the actual human brain.

[0019] (3) The emergence of the heterologous dual-ion gate type neuromorphic device makes the neuromorphic computing more flexible and controllable, realizes the integration of storage and calculation, and is suitable for more complex cooperative calculation and weight alternation, which provides guidance for the construction of the next generation of heterologous neuromorphic system. BRIEF DESCRIPTION OF DRAWINGS

[0020] Figure 1 It is a preparation method flow chart of the dual-ion gate type neuromorphic device.

[0021] Figure 2 It is a device structure schematic diagram after forming a back gate electrode.

[0022] Figure 3 It is a device structure schematic diagram after forming a back gate medium.

[0023] Figure 4 It is a device structure schematic diagram after forming a two-dimensional material layer.

[0024] Figure 5 It is a device structure schematic diagram after forming a source-drain electrode and a top gate electrode.

[0025] Figure 6 is a schematic diagram of a device structure after forming a top gate dielectric.

[0026] Figure 7 is a schematic diagram of the working principle of a double-ion gate type neuromorphic device. DETAILED DESCRIPTION

[0027] In order to make the objects, technical solutions and advantages of the present application clearer, the technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the drawings in the embodiments of the present application. It should be understood that the specific embodiments described herein are only used to explain the present application and not to limit the present application. The described embodiments are only some of the embodiments of the present application, not all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative labor fall within the scope of protection of the present application.

[0028] In the description of the present application, it should be noted that the terms "upper", "lower", "vertical", "horizontal" and the like indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the devices or elements referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as limiting the present application. In addition, the terms "first", "second" are only for the purpose of description, and cannot be understood as indicating or implying relative importance.

[0029] In addition, many specific details of the present application are described below, such as the structure, materials, dimensions, processing and technology of the device, in order to make the present application clearer. But as those skilled in the art can understand, the present application can be implemented without these specific details. Unless specifically indicated below, each part in the device can be composed of materials known to those skilled in the art, or materials with similar functions developed in the future can be used.

[0030] Figure 1 is a flow chart of a preparation method of a double-ion gate type neuromorphic device. As shown in Figure 1 the preparation method of the double-ion gate type neuromorphic device comprises the following steps:

[0031] Step S1, a 1.5cmx1.5cm silicon oxide marker sheet is prepared as a substrate 100 for preparing a double-ion gate neuromorphic device. The preferred substrate can be selected from a silicon oxide sheet, a silicon sheet, glass, sapphire, etc. Then, an electron beam lithography and a magnetron sputtering technology are used to prepare a back gate electrode Pd 101 with a thickness of 50nm on the substrate 100, and the obtained structure is as shown in Figure 2The back gate electrode material can also be Pt, Au, etc.; the thickness is preferably in the range of 30-100 nm.

[0032] Step S2: 50 nm thick Li x SiO2as the back gate medium 102, and the resulting structure is as shown in FIG. 2B. Figure 3 The material of the back gate medium can also be Li x AlO2, Li x Ti2O4, etc.; the thickness is preferably in the range of 30-80 nm.

[0033] Step S3: using a two-dimensional film transfer platform to transfer a 5 nm thick WSe2two-dimensional film 103 to the back gate as the channel material of the neuromorphic device, and the resulting structure is as shown in FIG. 3B. Figure 4 The channel material is preferably MoSe2, WS2, MoS2, etc.; the channel thickness is preferably in the range of 1-10 nm.

[0034] Step S4: using electron beam lithography and magnetron sputtering technology to grow Ti / Pd as the source electrode 104 and the drain electrode 105 at both ends of the channel, and to grow Ti / Pd as the top gate electrode 107 at a distance of 100 pm from the channel, and the resulting structure is as shown in FIG. 4B. Figure 5 The extension direction of the formed top gate electrode 107 is parallel to the extension direction of the channel, the extension direction of the top gate electrode 107 is orthogonal to the extension direction of the back gate electrode 101, but the top gate electrode 107 and the back gate electrode 101 do not overlap, i.e., the projections of the top gate electrode 107 and the back gate electrode 101 on the same horizontal plane do not cross and overlap each other. The source-drain electrode material can also be Ti / Au, Cr / Pd, Cr / Au, Ni / Pd, Ni / Au, etc.; the thickness is preferably in the range of 5-15 nm / 30-100 nm; the distance between the top electrode and the channel is preferably in the range of 50-150 pm; the area of the source-drain electrode and the top gate electrode is preferably in the range of 60 pm x 60 pm-150 pm x 150 pm, and is further preferably 100 pm x 100 pm.

[0035] Step S5: using a pipette to drop Li-ion gel solution on the two-dimensional film 103 and the top gate electrode 107, and then heating on a hot plate at 100°C for 10 min, so that the state of the ion gel is solidified as the top gate medium 108, and the preparation of the double-ion gate type neuromorphic device is completed, and the resulting structure is as shown in FIG. 6B. Figure 6 The solute in the ion gel solution is LiClO4crystal + polyvinyl alcohol (the mass ratio of LiClO4and polyvinyl alcohol is controlled at 1:8), and the solvent in the solution is deionized water. The concentration of the solution is preferably in the range of 0.05-2 g / ml, and is further preferably 0.1 g / ml. The baking temperature is preferably in the range of 60-130°C; and the heating time is preferably in the range of 5-20 min.

[0036] like Figure 7 As shown, by applying pulse timing simultaneously to the top gate and the back gate to regulate the channel conductance, the device conductance range can be quantitatively increased or decreased through the migration and injection of ions, which is similar to the regulation process of the two front ends of a heterogeneous neural synapse on a back end of a synapse, thereby realizing collaborative work simulations such as heterogeneous neuromorphic computing.

[0037] The above description is only a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any changes or substitutions that can be easily conceived by any technician familiar with this technical field within the technical scope disclosed in the present invention should be covered by the scope of protection of the present invention.

Claims

1. A dual ion gate neuromorphic device, characterized in that: include: substrate; a back gate electrode formed on the substrate; Back gate dielectric, which is Li x SiO2、Li x AlO2 or Li x A Ti2O4 ion oxide film formed on the back gate electrode; a two-dimensional thin film formed on the back gate dielectric and located above the back gate electrode, serving as a channel; A source electrode and a drain electrode are formed at both ends of the channel respectively; a top gate electrode formed on the back gate dielectric and arranged parallel to the channel at a certain interval, wherein the extension direction of the top gate electrode is orthogonal to the extension direction of the back gate electrode, but the top gate electrode and the back gate electrode do not overlap; A top gate dielectric, which is a Li ion gel, covers the channel and the top gate electrode, By applying pulse timing to the top gate and back gate simultaneously, the channel conductance is regulated, and the device conductance range is quantitatively increased or decreased through ion migration and injection, simulating the regulation process of two front ends of heterogeneous neural synapses on one synaptic back end, realizing the simulation of heterogeneous neuromorphic computing collaborative work.

2. The dual ion gate neuromorphic device according to claim 1, characterized in that The two-dimensional film is WSe2, MoSe2, WS2 or MoS2.

3. The dual ion gate neuromorphic device according to claim 1, wherein: The distance between the top gate electrode and the channel is 50 μm to 150 μm.

4. A method for preparing a dual-ion gate neuromorphic device, characterized in that: The following steps are involved: forming a back gate electrode on the substrate; A back gate dielectric is formed on the back gate electrode, which is Li x SiO2、Li x AlO2 or Li x Ti2O4 ionic oxide film; forming a two-dimensional thin film as a channel on the back gate dielectric, which is located above the back gate electrode; forming a source electrode and a drain electrode at both ends of the channel respectively; forming a top gate electrode on the back gate dielectric, the top gate electrode being arranged parallel to the channel at a certain interval, the extension direction of the top gate electrode being orthogonal to the extension direction of the back gate electrode, but the top gate electrode and the back gate electrode do not overlap; Li ion gel solution is dripped onto the channel and the top gate electrode, and heated to solidify to form Li ion gel as the top gate dielectric. By applying pulse timing simultaneously to the top gate and back gate, the channel conductance is regulated, and the device conductance range is quantitatively increased or decreased through ion migration and injection, simulating the regulation process of two front ends of heterogeneous neural synapses on one synaptic back end, realizing the simulation of heterogeneous neuromorphic computing collaborative work.

5. The method for preparing a dual ion gate neuromorphic device according to claim 4, wherein: The solute of the Li ion gel solution is LiClO4 crystals and polyvinyl alcohol with a mass ratio controlled at 1:8, and the solvent is deionized water with a concentration of 0.05 g / ml to 2 g / ml.

6. The method for preparing a dual ion gate neuromorphic device according to claim 4, wherein: The two-dimensional film is WSe2, MoSe2, WS2 or MoS2.

7. The method for preparing a dual ion gate neuromorphic device according to claim 4, wherein: The heating temperature is 60° C. to 130° C., and the heating time is 5 to 20 minutes.

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