Interpolation control for current balancing in interleaved power converters

Abstract

An interleaved power converter includes a control circuit and a plurality of phase-shifted subconverters, each of the subconverters having at least one power switch. The control circuit is coupled to the subconverters for controlling the power switches to balance currents in the subconverters over a plurality of cycles. The control circuit includes a current compensator configured to: determine a first duty cycle multiple times over a plurality of cycles, generate a PWM control signal having a present value of the first duty cycle for controlling a power switch of one of the subconverters during a cycle, determine a second duty cycle based on the present value of the first duty cycle and a previous value of the first duty cycle, and generate another PWM control signal having the second duty cycle for controlling a power switch of another of the subconverters during the cycle. Other example power converters and control circuits are also disclosed.

Description

Technical Field

[0001] The present disclosure relates to interpolation control for balancing currents in interleaved power converters. Background Art

[0002] This section provides background information related to the present disclosure which is not necessarily prior art.

[0003] The multiphase power converter typically includes an interleaved PFC boost subconverter and a control circuit for controlling a power switch in the subconverter. In some embodiments, the control circuit can control the duty cycle of the power switch to balance the rail current in the subconverter. In such an embodiment, the rail current can be balanced by using a split boost inductor, multiple current sensors, and / or multiple current compensators for balancing the rail current. In other embodiments, the input voltage and current of the power converter can be sampled multiple times per cycle, and the current compensator of the control circuit can be executed multiple times per cycle to adjust the duty cycle to balance the rail current. Summary of the invention

[0004] This section provides a general summary of the disclosure, and is not a comprehensive disclosure of its full scope or all of its features.

[0005] According to one aspect of the present disclosure, an interleaved multi-phase switching power converter includes a plurality of subconverters and a control circuit. The subconverter includes a first subconverter having a power switch and a second subconverter having a power switch. The second subconverter is phase-shifted relative to the first subconverter. The control circuit is coupled to the first subconverter and the second subconverter, and is used to control the power switch of the first subconverter and the power switch of the second subconverter to balance the current in the first subconverter and the second subconverter over a plurality of cycles. The control circuit includes a current compensator, which is configured to: determine a first duty cycle multiple times over the plurality of cycles based on a reference signal and a sensed current in the switching power converter, generate a first PWM control signal having a present value of the first duty cycle for controlling the power switch of the first subconverter during one of the plurality of cycles, determine a second duty cycle based on the present value of the first duty cycle and a previous value of the first duty cycle, and generate a second PWM control signal having the second duty cycle for controlling the power switch of the second subconverter during the one cycle.

[0006] According to another aspect of the present disclosure, a method for controlling an interleaved multi-phase switching power converter is disclosed. The switching power converter includes at least a first subconverter having a power switch and a second subconverter having a power switch. The second subconverter is phase-shifted relative to the first subconverter. The control circuit is configured to be coupled to the first subconverter and the second subconverter, and is used to control the power switch of the first subconverter and the power switch of the second subconverter to balance the current in the first subconverter and the second subconverter over a plurality of cycles. The control circuit includes a current compensator, which is configured to: determine a first duty cycle multiple times over the plurality of cycles based on a reference signal and a sensed current in the switching power converter, generate a first PWM control signal having a present value of the first duty cycle for controlling the power switch of the first subconverter during one of the plurality of cycles, determine a second duty cycle based on the present value of the first duty cycle and a previous value of the first duty cycle, and generate a second PWM control signal having the second duty cycle for controlling the power switch of the second subconverter during the one cycle.

[0007] Other aspects and areas of applicability will become apparent from the description provided herein. It should be understood that the various aspects of the present disclosure can be implemented individually or in combination with one or more other aspects. It should also be understood that the description and specific embodiments herein are intended only for illustrative purposes and are not intended to limit the scope of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] The drawings described herein are for illustrative purposes only of selected embodiments and not all possible implementations, and are not intended to limit the scope of the present disclosure.

[0009] Figure 1 is a block diagram of an interleaved multiphase switching power converter according to an example embodiment of the present disclosure, the interleaved multiphase switching power converter including two subconverters having power switches and a control circuit that employs interpolation-based control for determining a duty cycle of the power switches to balance rail currents in the subconverters.

[0010] Figure 2 is a graph showing duty cycle values ​​for two sub-converters and input voltage when conventional control techniques are used.

[0011] Figure 3 is a graph showing duty cycle values ​​for two sub-converters when conventional control techniques are used.

[0012] Figure 4is a graph showing unbalanced rail currents in two sub-converters when conventional control techniques are used.

[0013] Figure 5A-5C is a graph showing the peaks during the beginning of the positive cycle, at the positive peak, and at the negative peak. Figure 4 A magnified portion of the graph of the unbalanced rail current.

[0014] Figure 6 is a block diagram of a current compensator of a control circuit implementing interpolation-based control for determining duty cycles to balance rail currents in two sub-converters according to another example embodiment.

[0015] Figure 7 FIG. 1 is a diagram showing a method for implementing interpolation-based control according to yet another example embodiment. Figure 6 A graph showing the duty cycle value of the sub-converter controlled by the current compensator and the input voltage.

[0016] Figure 8 is a graph illustrating duty cycle values ​​for two sub-converters when interpolation-based control is used according to another example embodiment.

[0017] Fig. 9 is a graph illustrating balanced rail currents in two sub-converters when interpolation-based control is implemented according to another example embodiment.

[0018] Figure 10A-10C is a graph showing the peaks during the beginning of the positive cycle, at the positive peak, and at the negative peak. Fig. 9 A magnified portion of the graph of the balanced rail current.

[0019] Fig.11 is a block diagram of a current compensator of a control circuit implementing interpolation-based control for balancing rail currents in three sub-converters according to yet another example embodiment.

[0020] Fig.12 is a block diagram of a control circuit including a voltage compensator and a current compensator implementing interpolation-based control for balancing rail currents in two sub-converters according to another example embodiment.

[0021] Fig.13A and Fig.14A is a graph showing unbalanced rail currents in two sub-converters including inductors having values ​​that differ by ten percent when conventional control techniques are used.

[0022] Fig. 13B and Fig. 14B The positive peak values ​​are shown in Fig.13Aand Fig.14A A magnified portion of the graph of the unbalanced rail current.

[0023] Fig.15A and Fig.16A is a graph illustrating balanced rail currents in two sub-converters including inductors having values ​​that differ by ten percent when interpolation-based control is implemented according to another example embodiment.

[0024] Fig. 15B and Fig. 16B The positive peak values ​​are shown in Fig.15A and Fig.16A A magnified portion of the graph of the unbalanced rail current.

[0025] Fig.17A and Fig.18A is a graph showing unbalanced rail currents in two sub-converters having resistance values ​​that differ by ten milliohms when conventional control techniques are used.

[0026] Fig. 17B and Fig.18B The positive peak values ​​are shown in Fig.17A and Fig.18A A magnified portion of the graph of the unbalanced rail current.

[0027] Fig.19A and Fig. 20A is a graph illustrating balanced rail currents in two sub-converters having resistance values ​​differing by ten milliohms when interpolation-based control is implemented according to yet another example embodiment.

[0028] Fig.19B and Fig. 20B The positive peak values ​​are shown in Fig.19A and Fig. 20A A magnified portion of the graph of the unbalanced rail current.

[0029] Fig.21 is a schematic diagram of an interleaved multiphase switching power converter according to another example embodiment, the interleaved multiphase switching power converter including three subconverters having power switches and a control circuit that employs interpolation-based control for balancing rail currents in the subconverters.

[0030] Corresponding reference numerals indicate corresponding (but not necessarily identical) parts and / or features throughout the several views of the drawings. DETAILED DESCRIPTION

[0031] Example embodiments are provided so that the present disclosure will be thorough and will fully convey the scope to those skilled in the art. Many specific details, such as embodiments of specific parts, devices and methods, are set forth to provide a thorough understanding of the embodiments of the present disclosure. It will be apparent to those skilled in the art that specific details need not be employed, that example embodiments may be embodied in many different forms and should not be construed as limiting the scope of the present disclosure. In some example embodiments, well-known processes, well-known device structures and well-known techniques are not described in detail.

[0032] The terms used herein are only for the purpose of describing specific example embodiments and are not intended to be limiting. As used herein, the singular forms "a", "an", and "the" may also be intended to include plural forms unless the context clearly indicates otherwise. The terms "comprises", "comprising", "including", and "having" are inclusive and therefore specify the presence of stated features, integers, steps, operations, elements, and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts, and / or groups thereof. The method steps, processes, and operations described herein are not to be interpreted as necessarily requiring them to be performed in the specific order discussed or illustrated, unless explicitly identified as an execution order. It should also be understood that additional steps or alternative steps may be adopted.

[0033] Although the term first, second, third etc. can be used herein to describe various elements, components, regions, layers and / or parts, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms can only be used to distinguish an element, component, region, layer or part from another region, layer or part. Terms such as "first", "second" and other numerical terms do not imply an order or sequence when used in this article, unless the context clearly indicates. Therefore, without departing from the teaching of the example embodiment, the first element, component, region, layer or part discussed below can be referred to as the second element, component, region, layer or part.

[0034] For ease of description, spatially relative terms such as "inside", "outside", "below", "below", "lower", "above", "upper", etc. may be used herein to describe the relationship of an element or feature to another element or feature as illustrated in the drawings. In addition to the orientation depicted in the drawings, spatially relative terms may be intended to include different orientations of the device in use or operation. For example, if the device in the drawings is flipped, the elements described as being "below" or "below" other elements or features will be oriented to be "above" the other elements or features. Therefore, the example term "below" may include both an orientation of "above" and an orientation of "below". The device may be oriented in other ways (rotated 90 degrees or in other orientations) and the spatially relative descriptions used herein may be interpreted accordingly.

[0035] Example embodiments will now be described more fully with reference to the accompanying drawings.

[0036] An interleaved multiphase switching power converter according to an example embodiment of the present disclosure is illustrated in Figure 1 and is generally indicated by reference numeral 100. Figure 1 As shown in FIG. 1 , an interleaved multiphase switching power converter 100 includes: phase-shifted subconverters 102 and 104 having power switches 106 and 108; and a control circuit 110 coupled to the subconverters 102 and 104 for controlling the power switches 106 and 108 to balance the currents in the subconverters 102 and 104 over a plurality of cycles. The control circuit 110 includes a current compensator 112 configured to: determine a duty cycle D1 multiple times over the plurality of cycles based on a reference signal Iref and a sense current Isense in the switching power converter 100, generate a PWM control signal 114 having a present value of the duty cycle D1 for controlling the power switch 106 of the subconverter 102 during one of the plurality of cycles, determine another duty cycle D2 based on the present value of the duty cycle D1 and a previous value of the duty cycle D1, and generate a PWM control signal 116 having the duty cycle D2 for controlling the power switch 108 of the subconverter 104 during the cycle.

[0037] When operating the subconverters in average current mode control, the control circuit 110 uses interpolation-based control to balance the rail currents in the subconverters 102 and 104. For example, the control circuit 110 determines the duty cycle D2 for controlling the subconverter 104 based on the known value of the duty cycle D1. In such an embodiment, the interpolation-based control mitigates the current imbalance between the subconverter 102 (e.g., the master subconverter) and the subconverter 104 (e.g., the slave subconverter), which is caused by, for example, control signal delays, control peripheral delays, different inductance values ​​in the subconverters 102 and 104, and unmatched PCB traces in the subconverters 102 and 104. In this way, the rail currents in the subconverters 102 and 104 can be phase-synchronized and have similar waveform shapes and amplitudes. By balancing the rail currents in the subconverters 102 and 104, heat can be evenly spread and dissipated in the power switches 106 and 108, while effectively reducing the ripple current by a factor inversely proportional to the number of subconverters.

[0038] Conventionally, the duty cycle of the control signal for controlling different subconverters is updated based on the same current value and voltage value. For example, in average current mode, the duty cycle of the control signal is calculated based on the error between the current reference (e.g., Iref(t)) and the sensed current (e.g., input current Iint(t)), both of which change over time. The current reference Iref(t) is greatly affected by the input voltage V(t). For example, Figure 2 A graph 200 is illustrated showing duty cycles 202, 204 and input voltage V for two subconverters using conventional control techniques over multiple cycle cycles. In this embodiment, the PWM module for generating the PWM control signal operates with a 180 degree phase shift φ. Figure 2 As shown in FIG. 1 , increasing the input voltage V(t) (e.g., during an upward AC ramp of the input voltage) causes the duty cycle value (u) to decrease. The duty cycle value continues to decrease until the input voltage V(t) reaches a peak voltage value. During a downward AC ramp of the input voltage (not shown in FIG. 1 ), the duty cycle value (u) decreases. Figure 2 The duty cycle value increases until the input voltage V(t) reaches the minimum voltage value.

[0039] The compensator updates the duty cycle value (u) for the subconverters once per cycle T based on the same input voltage V(t). Thus, when the compensator updates the duty cycle value (u), the duty cycle value 204 for one subconverter is offset and overcompensated relative to the duty cycle value 202 for another subconverter. For example, and as Figure 2As shown in FIG, the duty cycle values ​​202, 204 take different paths as the input voltage V changes while the updated duty cycle value (u) remains the same within each cycle T. As a result, one subconverter may store more energy than the other subconverter, resulting in an imbalance between the rail currents (e.g., inductor currents) in the subconverters.

[0040] For example, Figure 3 , Figure 4 and Figure 5A-5C Graphs 300, 400, 500A, 500B, 500C illustrate duty cycle values ​​302, 304 and rail currents 402, 404 in two subconverters of a power converter employing conventional control techniques. Specifically, graph 300 illustrates duty cycle values ​​302, 304 varying with time when the input voltage of the power converter is on an upward slope of one of its AC cycles, and graph 400 illustrates rail currents 402, 404 over two AC cycles. Graphs 500A, 500B, 500C show that during the beginning of a positive cycle (see Figure 5A ), at the positive peak (see Figure 5B ) and at the negative peak (see Figure 5C )of Figure 4 The amplified portion of the rail current 402, 404. In this embodiment, the power converter may be a two-phase interleaved totem pole (push-pull) PFC operating at 40 kHz.

[0041] like Figure 3 As shown in FIG. 3 , the duty cycle value 304 for one of the subconverters is offset and overcompensated relative to the duty cycle value 302 of the other subconverter. This results in an imbalance between the rail currents 402, 404 (eg, inductor currents) in the subconverters, such as Figure 4 and Figure 5A-5C As shown in .

[0042] However, and as further explained below, if an interpolation-based control approach is employed as disclosed herein, one of the duty cycles can be corrected to ensure that the duty cycles track along the same path. As a result, balanced rail currents in the subconverters can be achieved.

[0043] Figure 1 The control circuit 110 may include various components for generating a duty cycle to achieve balanced rail currents in the subconverters 102, 104. For example, Figure 6 A current compensator 612 is illustrated, which may be used in the control circuit 110 to determine the values ​​of the duty cycles D1, D2 to balance the rail currents in the subconverters 102, 104 over a plurality of periods (eg, cycles). Figure 6As shown in FIG. 6 , the current compensator 612 includes comparators 620 , 628 , a controller 622 , limiters 624 , 634 , a delay device 626 , a multiplier 630 , an adder 632 , and PWM modules DPWM1 , DPWM2 .

[0044] exist Figure 6 In the embodiment of the present invention, the current compensator 612 receives the current reference signal Iref and the sensed current Isense (eg, Figure 1 The current reference signal Iref may vary from one cycle to the next because, for example, the input voltage of the switching power converter changes over time. The comparator 620 compares the current reference signal Iref and the sensed current Isense during one cycle, and generates a current error signal err_i based on the comparison (e.g., difference) between the current reference signal Iref and the sensed current Isense.

[0045] Then, the controller 622 generates a signal u(t) representing the duty cycle D1 for the cycle based on the current error signal err_i. The signal u(t) is passed through a limiter 624 to limit the value of the signal u(t). In such an embodiment, when the signal u(t) is less than a defined value, the signal u(t) may be forced to the defined value. However, if the signal u(t) is greater than another defined value, the signal u(t) may be forced to another defined value. Then, the PWM module DPWM1 generates a control signal PWM1 having the current value u(t) of the duty cycle D1 for controlling the subconverter (e.g., Figure 1 One or more power switches in the subconverter 102).

[0046] Figure 6 The controller 622 is shown as including a proportional integral (PI) controller. In such an embodiment, the controller 622 may include one or more amplifiers for multiplying the current error signal err_i with a proportional gain coefficient and an integrator coefficient. In other embodiments, the controller 622 may include another suitable type of controller, such as a proportional integral derivative (PID) controller.

[0047] like Figure 6 As shown in FIG. 1 , the comparator 628 compares the current value u(t) of the duty cycle D1 with the previous value u(t-1), and generates an error signal err based on the comparison (eg, the difference) between these values. Figure 6 As shown in , the current value u(t) of the duty cycle D1 is passed through the delay device 626 to obtain the previous value u(t-1) of the duty cycle D1 from the previous cycle.

[0048] The multiplier 630 receives the error signal err and the reference signal C1, and generates a signal based on the product of the error signal err and the reference signal C1. For example, the reference signal C1 can be a constant value defined based on the phase delay and period cycle between the subconverters (e.g., subconverters 102, 104). For example, if the switching power converter includes two interleaved subconverters, the phase delay between one subconverter and the other subconverter is 180 degrees, and the period cycle is 360 degrees. In such an embodiment, the reference signal C1 can be obtained by dividing the phase delay (e.g., 180 degrees) by the cycle (e.g., 360 degrees).

[0049] Then, the adder 632 adds the signal provided by the multiplier 630 and the current value u(t) of the duty cycle D1 to determine the duty cycle D2. For example, the signal u(t)' representing the current value of the duty cycle D2 is provided by the adder 632 and passed through the limiter 634, which functions in a similar manner to the limiter 624. The signal u(t)' representing the current value of the duty cycle D2 is then passed to the PWM module DPWM2. The PWM module DPWM2 generates a control signal PWM2 having the current value u(t)' of the duty cycle D2 for controlling another subconverter (e.g., Figure 1 The calculation for determining the value of the signal u(t)' is shown in equation (1) below.

[0050] Equation (1)u(t)'=[(u(t)-u(t-1))*C1]+u(t)

[0051] The values ​​of the signals u(t), u(t)' are referenced to time. Thus, the values ​​of the signals u(t), u(t)' may be valid for one PWM period (e.g., one cycle). For the previous and / or subsequent PWM periods, the signal values ​​may be determined again in a similar manner as explained above.

[0052] When the value of the signal u(t)' for duty cycle D2 is determined as explained above, the duty cycles D1, D2 can track along the same path, thereby forcing the rail currents in the subconverters to be balanced. Figure 7 Graph 700 is illustrated, which shows that when using Figure 6 The current compensator 612 is used for the duty cycle values ​​D1 and D2 of the two sub-converters. Figure 7 As shown in , as the input voltage V changes, the duty cycle values ​​D1, D2 follow similar paths.

[0053] exist Figure 6 and Figure 7In a specific embodiment, the duty cycle D2 is corrected by half of the error between the current value u(t) and the previous value u(t-1) of the duty cycle D1. As a result, the duty cycle D2 is calculated to match the midpoint between the current value u(t) and the future value u(t+1) of the duty cycle D1. For example, if the input voltage was 95 volts in the previous cycle (e.g., V(t-1)), 100 volts in the current cycle (e.g., V(t)), and 105 volts in the future cycle (e.g., V(t+1)), then when the duty cycle D2 is calculated to match the midpoint (e.g., u(t+0.5)) between the current value u(t) and the future value u(t+1) of the duty cycle D1, the input voltage is 102.5 volts (e.g., V(t+0.5)).

[0054] Since the duty cycles D1, D2 follow similar paths, the power switches can be controlled to achieve balanced currents in the subconverters. Figure 8 , Fig. 9 and Figure 10A-10C Graphs 800, 900, 1000A, 1000B, 1000C of duty cycle values ​​802, 804 and rail currents ia, ib in two subconverters of a power converter employing the interpolation-based control method disclosed herein are illustrated. Specifically, graph 800 illustrates the duty cycle values ​​802, 804 varying with time when the input voltage of the power converter is on an upward slope of one of its AC cycles, and graph 900 illustrates the rail currents ia, ib within two AC cycles. Graphs 1000A, 1000B, 1000C show that during the beginning of the positive cycle (see Fig. 10A ), at the positive peak (see Fig. 10B ) and at the negative peak (see Fig. 10C )of Fig. 9 In this embodiment, the power converter may be a two-phase interleaved totem pole PFC operating at 40 kHz.

[0055] like Figure 8 As shown in FIG, the duty cycle values ​​802, 804 follow similar paths. As a result, the current flowing through one of the subconverters (e.g., Figure 1 The rail current ia of the subconverter 102) and the rail current ia flowing through another subconverter (eg, Figure 1 The rail current ib of the subconverter 104 is balanced, such as Fig. 9 and Figure 10A-10C Specifically, the rail currents ia, ib are phase synchronized and have similar waveform shapes and amplitudes.

[0056] although Figure 1 and Figure 6The present invention relates to an interpolation-based control method for controlling two interleaved subconverters in a power converter, but it should be clear that the method can be used to control more than two interleaved subconverters. For example, Fig.11 A current compensator 1112 is illustrated which may be used to determine the duty cycles D1 , D2 , D3 for balancing the rail currents in the three sub-converters. Fig.11 The current compensator 1112 is substantially similar to Figure 6 The current compensator 612 of FIG. 1 is different from the current compensator 612 of FIG. 1 , but includes another control loop for generating a duty cycle D3 for the third subconverter. For example, Fig.11 The current compensator 1112 includes comparators 620, 628, a controller 622, limiters 624, 634, a delay device 626, a multiplier 630, an adder 632 and Figure 6 PWM modules DPWM1, DPWM2, as well as multiplier 1130, adder 1132, limiter 1134 and PWM module DPWM3.

[0057] The duty cycle D1 and D2 are based on the above Figure 6 For example, during one cycle, the duty cycle D1 (e.g., the signal u(t) representing the current value of the duty cycle D1) is determined based on the reference signal Iref and the current value of the sensed current Isense, and the duty cycle D2 (e.g., the signal u(t)′ representing the current value of the duty cycle D2) is determined based on the current value u(t) of the duty cycle D1 and the previous value u(t-1), as explained above.

[0058] exist Fig.11 In the embodiment of , the multiplier 630 receives the error signal err from the comparator 628 and the reference signal C1 and generates a signal based on the product of the error signal err and the reference signal C1, as explained above. Fig.11 In a specific embodiment, Figure 6 Compared with the reference signal C1, the reference signal C1 is changed. Specifically, Fig.11 The reference signal C1 of is determined by dividing the phase delay between the first subconverter (e.g., the master subconverter) and the second subconverter (e.g., the slave subconverter) by a cycle (e.g., 360 degrees). In such an embodiment, the phase delay between the first subconverter and the second subconverter is 120 degrees. Therefore, Fig.11 In a specific embodiment, the reference signal C1 is 0.333 (eg, 120 / 360).

[0059] Similar to the duty cycle D2, the duty cycle D3 for the third subconverter is determined based on the current value u(t) and the previous value u(t-1) of the duty cycle D1. Fig.11 As shown in , the multiplier 1130 receives the error signal err from the comparator 628 and the reference signal C2, and generates a signal based on the product of the error signal err and the reference signal C2.

[0060] The reference signal C2 may be a defined constant value determined in a similar manner to the reference signal C1. For example, the reference signal C2 may be determined based on a phase delay and a cycle between a first subconverter (e.g., a master subconverter) and a third subconverter (e.g., a slave subconverter). In such an embodiment, the phase delay between the first subconverter and the third subconverter is 240 degrees. Thus, the reference signal C2 may be obtained by dividing the phase delay (e.g., 240 degrees) by the cycle (e.g., 360 degrees). Thus, in Fig.11 In a specific embodiment, the reference signal C2 is 0.667 (eg, 240 degrees / 360 degrees).

[0061] The adder 1132 then adds the signal provided by the multiplier 1130 and the current value u(t) of the duty cycle D1 to determine the current value of the duty cycle D3 (e.g., signal u(t)”). The signal u(t)” representing the current value of the duty cycle D3 is passed through a limiter 1134, which functions in a manner similar to the limiter 634 explained above. The signal u(t)” is then passed to the PWM module DPWM3. The PWM module DPWM3 generates a control signal PWM3 having the current value u(t)” of the duty cycle D3 for controlling one or more power switches in the third sub-converter during the period cycle. The calculation for determining the value of the signal u(t)” is shown in equation (2) below.

[0062] Equation (2)u(t)"=[(u(t)-u(t-1))*C2]+u(t)

[0063] exist Fig.11 In a specific embodiment, due to the reference signal C1, the duty cycle D2 is corrected by one third of the error between the current value u(t) and the previous value u(t-1) of the duty cycle D1. As a result, the duty cycle D2 is calculated to match a point one third between the current value u(t) and the future value u(t+1) of the duty cycle D1. In addition, due to the reference signal C2, the duty cycle D3 is corrected by two thirds of the error between the current value u(t) and the previous value u(t-1) of the duty cycle D1. In this way, the duty cycle D3 is calculated to match a point two thirds between the current value u(t) and the future value u(t+1) of the duty cycle D1.

[0064] The reference signal Iref disclosed herein may be generated based on the output of the voltage compensator. For example, Fig.12An example method for controlling a switching power converter (eg, Figure 1 The control circuit 1210 of the switching power converter 100) is used to control the power switches in the two sub-converters to balance the current in multiple cycles. As shown, the control circuit 1210 includes Figure 6 A current compensator 612 and a circuit 1212 for generating a current reference signal Iref for the current compensator 612.

[0065] exist Fig.12 In the embodiment of the present invention, the current reference signal Iref is generated based on the input voltage Vin of the switching power converter, the output voltage Vo of the switching power converter and the reference voltage Vref. Fig.12 As shown in FIG. 1 , circuit 1212 includes a comparator 1214, a multiplier 1216, and a power limiting function 1218. Comparator 1214 compares a reference voltage Vref and an output voltage Vo, and provides an output to multiplier 1216. The output voltage Vo may be passed through an optional zero-order hold (ZOH) device, such as a sample and hold (S&H) circuit, which samples the output voltage Vo (e.g., an analog signal) and holds its value at a constant level for a period of time (e.g., a sampling interval) to generate a digital signal.

[0066] In some embodiments, comparator 1214 may represent a voltage compensator. Thus, the output of comparator 1214 may be the output of the voltage compensator. In such embodiments, a controller (e.g., similar to Figure 6 The PI controller 622) can be coupled to the comparator 1214.

[0067] The power limiting function 1218 receives the input voltage Vin of the power converter (e.g., the rectified input voltage) and provides an output to the multiplier 1216. For example, the power limiting function 1218 can output a signal representing the inverse of the square of the average input voltage (e.g., 1 / (average(Vin))A 2, 1 / Vacrms A 2, etc.). Alternatively, the power limiting function 1218 can output another signal if desired. Similar to the output voltage Vo, the input voltage Vin can be passed through an optional ZOH device if desired.

[0068] The multiplier 1216 generates a current reference signal Iref based on the product of the output of the comparator 1214 (eg, the output of the voltage compensator), the output of the power limiting function 1218, and the input voltage Vin of the power converter. The current reference signal Iref is then passed to the comparator 620 of the current compensator 612, as explained above.

[0069] exist Fig.12In the embodiment of the present invention, the duty cycle of the PWM control signals PWM1, PWM2 can be determined using a minimum number of sensors. For example, a single current sensor, a single input voltage sensor, and a single output voltage sensor can be used to determine the duty cycle.

[0070] In some embodiments, the subconverters disclosed herein may include one or more inductors and / or PCB traces. In such embodiments, different inductor values ​​and / or PCB traces (e.g., mismatched resistors) may be attributable to at least some current imbalance between the subconverters. However, if the interpolation-based control method disclosed herein is employed, the rail currents in the subconverters may be substantially balanced in magnitude and phase even if the inductor values ​​differ by ±10% and / or the resistor values ​​differ by ±10 milliohms.

[0071] For example, Figures 13A-16B Graphs 1300A, 1300B, 1400A, 1400B, 1500A, 1500B, 1600A, 1600B are illustrated showing rail currents 1302, 1304, 1402, 1404, 1502, 1504, 1602, 1604 in inductors L1, L2. Inductor L1 may be coupled to a subconverter (e.g., a main subconverter such as Figure 1 The inductor L2 may be coupled to a rail of a subconverter 102 of the embodiment of the present invention, and the inductor L2 may be coupled to another subconverter (eg, a slave subconverter such as Figure 1 in the rail of the subconverter 104). Fig. 13B , Fig. 14B , Fig. 15B , Fig. 16B The graphs 1300B, 1400B, 1500B, 1600B show Fig.13A , Fig.14A , Fig.15A , Fig.16A The rail currents 1302, 1304, 1402, 1404, 1502, 1504, 1602, 1604 are amplified at their positive peaks. Figures 13A-16B In the embodiment of FIG. 1 , the inductors L1 and L2 have values ​​that differ by 10%. Figure 13A-13B and Figure 15A-15B In the example, the value of inductor L2 is 90% of the value of inductor L1 (e.g., L2=0.90*L1), and Figure 14A-14B and Figure 16A-16B , the value of inductor L2 is 110% of the value of inductor L1 (eg, L2 = 1.1*L1).

[0072] like Figure 13A-13B and Figure 14A-14BAs shown in , when the interpolation control method is not used, the 10% difference in inductance causes an imbalance between the currents 1302, 1402 in the inductor L1 and the currents 1304, 1404 in the inductor L2. However, and as Figure 15A-15B and Figure 16A-16B As shown in , a 10% difference in inductance results in a minimum imbalance between the current 1502 , 1602 in the inductor L1 and the current 1504 , 1604 in the inductor L2 if the interpolation control method is employed.

[0073] also, Figures 17A-20B Graphs 1700A, 1700B, 1800A, 1800B, 1900A, 1900B, 2000A, 2000B are illustrated, which show rail currents 1702, 1704, 1802, 1804, 1902, 1904, 2002, 2004 flowing through subconverters including resistors R1, R2. In some embodiments, the rail currents 1702, 1704, 1802, 1804, 1902, 1904, 2002, 2004 may represent inductor currents in the subconverters. Resistor R1 may represent a subconverter (e.g., a master subconverter, such as Figure 1 102), and resistor R2 may represent another subconverter (e.g., from a subconverter such as Figure 1 PCB traces in the subconverter 104). Fig. 17B , Fig.18B , Fig.19B , Fig. 20B The graphs 1700B, 1800B, 1900B, and 2000B show Fig.17A , Fig.18A , Fig.19A , Fig. 20A Amplified portion of the rail currents 1702, 1704, 1802, 1804, 1902, 1904, 2002, 2004 at their positive peaks. Figures 17A-20B In the embodiment of FIG. 1 , resistors R1 and R2 have values ​​that differ by 10 milliohms. Figure 17A-17B and Figure 19A-19B In the example, the value of resistor R2 is 10 milliohms greater than the value of resistor R1 (eg, R2 = R1 + 10 milliohms), and Figure 18A-18B and Figure 20A-20B In the example, the value of resistor R1 is 10 milliohms greater than the value of resistor R2 (eg, R1 = R2 + 10 milliohms).

[0074] like Figure 17A-17B and Figure 18A-18BAs shown in FIG. 1 , when the interpolation control method is not adopted, the 10 milliohm difference between the resistors R1 and R2 causes an imbalance between the current 1702 and 1802 flowing through the master sub-converter and the current 1704 and 1804 flowing through the slave sub-converter. Specifically, the current 1704 and 1804 in the slave sub-converter is greater than and leads the current 1702 and 1802 in the master sub-converter. However, and as Figure 19A-19B and Figure 20A-20B As shown in , a resistance difference of 10 milliohms results in a minimum imbalance between the current 1902 , 2002 flowing through the master sub-converter and the current 1904 , 2004 flowing through the slave sub-converter if an interpolation-based control method is employed.

[0075] The interleaved multiphase switching power converter disclosed herein may include any suitable topology for providing AC / DC, DC / AC and / or DC / DC power conversion, such as buck, boost, buck-boost, totem pole, etc. In some preferred embodiments, the subconverter may be a front-end stage in a switching power converter and include, for example, an AC / DC boost PFC power circuit, a totem pole PFC power circuit, etc., operating with a defined phase shift and with average current mode control. In such an embodiment, the power converter may have a rated power of 3000W, greater than or less than 3000W, etc.

[0076] For example, Fig.21 An interleaved multiphase switching power converter 2100 including three interleaved subconverters 2102, 2104, 2106 and a control circuit 2108 is illustrated. The subconverters 2102, 2104, 2106 are coupled in parallel and include inductors L1, L2, L3, diodes D1, D2, D3, and power switches S1, S2, S3, respectively. The inductors, diodes, and power switches of the subconverters 2102, 2104, 2106 are arranged in a PFC boost topology. In some embodiments, the subconverter 2102 may be a master subconverter, and the subconverters 2104, 2106 may be slave subconverters.

[0077] The control circuit 2108 is coupled to the subconverters 2102, 2104, 2106 for controlling the power switches S1, S2, S3 to operate the subconverters 2102, 2104, 2106 with a 120 degree phase shift between them. The control circuit 2108 may include, for example Fig.11 Current compensator 1112, Fig.12circuit 1212, or another suitable current compensator and / or voltage compensator for balancing the rail currents in subconverters 2102, 2104, 2106. In a scenario where interleaved multiphase switching power converter 2100 includes only two subconverters (e.g., subconverters 2102, 2104), control circuit 2108 may include, for example Figure 6 A current compensator 612 or another suitable current compensator for balancing the rail currents.

[0078] like Fig.21 As shown in , the switching power converter 2100 also includes a rectifier (e.g., a diode bridge rectifier, etc.) for rectifying the AC input voltage V_ac, a capacitor C3 coupled between the subconverters 2102, 2104, 2106 and the rectifier, and a capacitor C4 coupled between the subconverters 2102, 2104, 2106 and the output of the converter. In addition, the switching power converter 2100 includes an optional diode D4 (e.g., a bypass diode) coupled across the subconverters 2102, 2104, 2106 for rerouting the current flow from the input to the output when the input voltage is greater than the output voltage. During this condition, the energy in the inductor cannot be transferred to the output. When the input voltage is less than the output voltage, the diode D4 is in its inactive state.

[0079] The control circuit 2108 may employ any of the interpolation-based control methods disclosed herein to ensure that the rail currents passing through the inductors L1, L2, and L3 are balanced. For example, the control circuit 2108 may determine the duty cycle D1 for the power switch S1 (e.g., of the main sub-converter 2102) based on the sensed current Isense and the reference signal. The reference signal may be determined based on the sensed input voltage Vin and the sensed output voltage Vo, as explained above. The control circuit 2108 may also determine the duty cycle D1 based on the present and previous values ​​of the duty cycle D1 and a constant reference signal (e.g., Fig.11 The reference signals C1, C2 of the control circuit 2108 (e.g., from the subconverters 2104, 2106) determine the duty cycles D2, D3 for the power switches S2, S3, as explained above. The control circuit 2108 can then generate PWM control signals PWM1, PWM2, PWM3 having the duty cycles D1, D2, D3 for controlling the power switches S1, S2, S3, respectively.

[0080] exist Fig.21In the embodiment of , signal Isense represents the combined current flowing through subconverters 2102, 2104, 2106 and is generated by a single current sensor R1. Alternatively, if desired, a current sensor can be associated with each subconverter 2102, 2104, 2106. However, using multiple current sensors increases components and, as a result, increases the cost and complexity of power converter 2100.

[0081] The control circuit disclosed herein may include an analog control circuit, a digital control circuit, or a hybrid control circuit (e.g., a digital control unit and an analog circuit). For example, if the control circuit is a digital control circuit, the control circuit may be implemented using one or more hardware components and / or software. For example, instructions for executing any one or more of the features of the interpolation-based control method disclosed herein may be stored in a non-transitory computer-readable medium, etc. and / or transferred from a non-transitory computer-readable medium, etc. to one or more existing digital control circuits, new digital control circuits, etc. In such an embodiment, one or more of the instructions may be stored in a volatile memory, a non-volatile memory, a ROM, a RAM, one or more hard disks, a disk drive, an optical drive, a removable memory, a non-removable memory, a cassette, a flash memory card, a CD-ROM, a DVD, a cloud storage device, etc.

[0082] The digital control circuits may be implemented using one or more types of digital control circuit systems. For example, each of the digital control circuits may include a digital signal controller (DSC), a digital signal processor (DSP), a microcontroller unit (MCU), a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), etc.

[0083] The power switch disclosed herein may include a transistor and / or another suitable switching device. For example, the power switch may include a metal oxide semiconductor field effect transistor (MOSFET), such as Fig.21 As shown in .

[0084] The interpolation-based control method disclosed herein can be used to balance rail currents in two or more subconverters of an interleaved multiphase switching power converter. In some embodiments, it may be preferred to employ an interpolation-based control method in a switching power converter having two interleaved subconverters or three interleaved subconverters to minimize the noise level in the generated control signal. The control method can be implemented under any suitable load and / or input range conditions while always maintaining balanced currents (e.g., phase synchronization, similar waveform shapes, similar amplitudes, etc.).

[0085] In addition, the interpolation-based control method can be implemented in combination with the average current mode control technique without the need for additional sensors, calibration (or recalibration) of the control circuit, etc. In addition, the implemented control method requires minimal calculations to control the subconverters so that their rail currents are balanced. In some embodiments, the control circuit may already include components for implementing the required calculations. In this way, the control method has little impact on the control loop in the control circuit. For example, for a converter with two interleaved subconverters (e.g., a two-phase interleaved system), subtraction operations, multiplication operations, accumulation operations, and minimum / maximum limit operations may be the only additional required calculations. For converters with three or more interleaved subconverters, the required calculations may include the operations mentioned above for the two interleaved subconverters, as well as multiplication operations, accumulation operations, and minimum / maximum limit operations for each additional rail.

[0086] The foregoing description of the embodiments has been provided for the purpose of illustration and description. It is not intended to be exhaustive or to limit the present disclosure. The individual elements or features of a specific embodiment are generally not limited to that specific embodiment, but are interchangeable where applicable and can be used in a selected embodiment, even if not specifically shown or described. It can also be varied in a variety of ways. Such variations should not be considered as departing from the present disclosure, and all such modifications are intended to be included within the scope of the present disclosure.

Claims

1. An interleaved multiphase switching power converter, comprising: a plurality of subconverters, the plurality of subconverters comprising a first subconverter having a power switch and a second subconverter having a power switch, the second subconverter being phase-shifted relative to the first subconverter; as well as a control circuit coupled to the first subconverter and the second subconverter for controlling the power switch of the first subconverter and the power switch of the second subconverter to balance currents in the first subconverter and the second subconverter over a plurality of cycles, the control circuit comprising a current compensator, the current compensator being configured to: determine a first duty cycle a plurality of times over the plurality of cycles based on a reference signal and a sensed current in the switching power converter, generate a first PWM control signal having a present value of the first duty cycle for controlling the power switch of the first subconverter during one cycle of the plurality of cycles, determine a second duty cycle based on the present value of the first duty cycle and a previous value of the first duty cycle, and generate a second PWM control signal having the second duty cycle for controlling the power switch of the second subconverter during the one cycle; wherein the control circuit is configured to generate an error signal for determining the second duty cycle based on a comparison between the present value of the first duty cycle and the previous value of the first duty cycle; wherein the reference signal is a first reference signal; wherein the control circuit is configured to generate a signal for determining the second duty cycle based on a product of the error signal and a second reference signal; and The second reference signal is a constant reference signal. 2 . The interleaved multi-phase switching power converter of claim 1 , wherein the second reference signal is determined by dividing a phase delay between the first sub-converter and the second sub-converter by 360 degrees. 3 . The interleaved multiphase switching power converter of claim 1 , wherein the control circuit is configured to add the signal to the present value of the first duty cycle to determine the second duty cycle.

4. The interleaved multi-phase switching power converter of claim 1 , wherein the control circuit comprises a voltage compensator configured to generate the reference signal based on an input voltage of the switching power converter, an output voltage of the switching power converter, and a reference voltage.

5. The interleaved multiphase switching power converter of claim 1 , wherein the plurality of subconverters include a third subconverter having a power switch, wherein the third subconverter is phase-shifted relative to the second subconverter and the first subconverter, and wherein the current compensator is configured to: determine a third duty cycle based on the present value of the first duty cycle, the previous value of the first duty cycle, and a third reference signal, and generate a third PWM control signal having the third duty cycle for controlling the power switch of the third subconverter during the one period. 6 . The interleaved multi-phase switching power converter of claim 5 , wherein the third reference signal is determined by dividing a phase delay between the first sub-converter and the third sub-converter by 360 degrees. 7 . The interleaved multi-phase switching power converter of claim 1 , wherein the control circuit is configured to control the power switches of the first subconverter and the power switches of the second subconverter in average current mode control.

8. The interleaved multiphase switching power converter of claim 1, wherein the control circuit comprises a digital controller. 9 . The interleaved multiphase switching power converter of claim 1 , wherein the first subconverter and the second subconverter comprise a PFC boost topology.

10. A method for controlling an interleaved multiphase switching power converter to balance currents in a plurality of subconverters in the interleaved multiphase switching power converter over a plurality of cycles, the plurality of subconverters comprising a first subconverter having a power switch and comprising a second subconverter having a power switch, the second subconverter being phase-shifted relative to the first subconverter, the method comprising: determining, via a current compensator coupled to a control circuit of the first subconverter and the second subconverter, a first duty cycle a plurality of times within the plurality of cycles based on a first reference signal and a sensed current in the switching power converter; generating a first PWM control signal having a present value of the first duty cycle for controlling the power switch of the first subconverter during one of a plurality of cycles; determining a second duty cycle based on the present value of the first duty cycle and a previous value of the first duty cycle; generating a second PWM control signal having the second duty cycle for controlling the power switch of the second subconverter during the one period; generating an error signal for determining the second duty cycle based on a comparison between the present value of the first duty cycle and the previous value of the first duty cycle; as well as generating a signal for determining the second duty cycle based on a product of the error signal and a second reference signal; The second reference signal is a constant reference signal. 11 . The method of claim 10 , further comprising controlling the power switch of the first subconverter and the power switch of the second subconverter in average current mode control.

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