High-side gate drive circuit

Abstract

This application discloses a high-voltage-side gate drive circuit, belonging to the field of high-voltage power integrated circuit technology. The circuit comprises a sequentially connected dynamic pulse generation circuit, a high-voltage level shift circuit, a common-mode filter circuit, an RS flip-flop, and an output-stage buffer circuit. When the input signal is a narrow pulse, the dynamic pulse generation circuit is configured to adjust the pulse width of the rising and / or falling edges of the narrow pulse so that the adjusted pulse ends later than the end time of the high-voltage side floating ground mutation. This application can prevent the output signal from being incorrectly latched, thereby improving chip reliability.

Description

Technical Field

[0001] The embodiments of the present application relate to the technical field of high-voltage power integrated circuits, and in particular to a high-voltage side gate drive circuit. Background Art

[0002] In high-voltage floating gate driver chips, a high-voltage level shift circuit is required to transfer low-voltage domain signals to high-voltage domains, such as Figure 1 As shown, M H It is the high-side switch device in the half-bridge topology. L It is the low-side switch device in the half-bridge topology. Usually a floating gate driver chip is used to effectively drive the high-side switch device M H The floating gate driver chip includes a low-voltage input logic, a high-voltage area gate driver circuit, and a low-voltage area gate driver circuit. LIN is the input signal of the low-side channel, and HIN is the input signal of the high-side channel. Both LIN and HIN are connected to the low-voltage input logic. The low-voltage input logic outputs two signals, IN_L and IN_H. IN_L is output to the low-voltage area gate driver circuit, and IN_H is output to the high-voltage area gate driver circuit. LO is the output signal of the low-side channel and is connected to the M L The gate of the high-side channel, HO is the output signal, connected to M H The VCC to GND voltage domain is used to power the low-voltage circuit, the VB to VS floating voltage domain is used to power the high-voltage circuit, and the VS terminal is connected to the M H The source and M L The drain of the MOSFET is connected by a bootstrap diode D B and the bootstrap capacitor C B Supply power to VB, when M L When turned on, VCC passes through D B is the bootstrap capacitor C B Charge and power the high voltage area gate drive circuit; when M H When turned on, the bootstrap capacitor C BIt is responsible for supplying power to the gate drive circuit in the high-voltage area, and so on. One end of the inductor L is connected to the VS end and the other end is connected to the output voltage Vout. The capacitor C and the resistor R0 are connected in parallel, one end of which is connected to Vout and the other end is connected to GND. In the high-voltage floating gate driver chip, it is necessary to transfer the low-voltage domain signal from VCC to GND to the high-voltage domain between VB and VS, so a high-voltage level shift circuit is needed to achieve the above purpose. The traditional single-channel LDMOS (Laterally Diffused Metal Oxide Semiconductor) level shift circuit will cause the LDMOS to be turned on for a long time when turned on, and has extremely high reliability requirements for the integrated high-voltage lateral field-effect transistor. While limiting the maximum operating voltage of the chip, it will also cause huge power consumption and reliability problems.

[0003] To solve the above problems, the commonly used signal transmission methods are as follows: Figure 2 As shown, the rising and falling edges of the input wide pulse signal are each converted into a narrow pulse signal. After the signal is transmitted to the high-voltage area, the two narrow pulse signals are restored to the same signal width as the original signal through an RS flip-flop. This solution greatly reduces the conduction time of the LDMOS and reduces the power consumption of the entire chip, allowing the LDMOS to operate reliably and stably. With the rise of third-generation semiconductors, power devices made of third-generation semiconductors, especially power devices made of gallium nitride materials, have extremely high switching frequencies, placing higher requirements on the minimum pulse width that the chip can respond to.

[0004] Figure 3 The figure shows the output response of the chip when a wider input pulse and a narrower input pulse are input. When the input signal IN is a wider pulse ( Figure 3(The left half of the diagram shows the pulse generator circuitry). The pulse generator circuitry generates narrow pulse signals at the PG_S and PG_R ports at times t1 and t4, respectively, based on the rising and falling edges of the input signal. The PG_S signal is then transmitted to the HD_S port in the high-voltage region via the high-voltage level shifter circuitry, forming a narrow low-level pulse. Simultaneously, the driven MOS device in the high-voltage region turns on at time t2 after a delay, causing the potential at the VS port to rise. This rise causes the drain potential of the LDMOS to reach a logic low (with VS as the reference zero point). Therefore, from t2 to t3, both the HD_S and HD_R ports are at a logic low. The common-mode low potential of HD_R and HD_S is filtered out by the common-mode filter circuitry. Therefore, during this period, the voltages at both the S and R ports are at a logic low. At t4, the PG_R signal is transmitted to the high-voltage area HD_R port through the high-voltage level shift circuit. After passing through the common-mode filter circuit, a high-level narrow pulse signal is formed at the R terminal. After a period of delay, HO turns into a low-level signal, and then the voltage at the VS terminal gradually drops to zero level. When the input signal IN is a narrow pulse ( Figure 3 At t6, the rising edge of the input signal IN forms a narrow pulse signal at the PG_S port. This signal is transmitted to the high-voltage area through the high-voltage level shift circuit and causes the HD_S signal to change to a low-level signal. After a delay, at t7, HO becomes a high level and turns on the power device of the high-voltage bridge wall. Then the VS voltage begins to rise. As can be seen from the above description, when the VS voltage rises, the LDMOS drain potential shows a logic low-level signal. Therefore, from t7 to t 10 During this time period, the voltages at both HD_R and HD_S terminals are at a logic low level, and all signals are filtered out by the common-mode filter circuitry. Between t8 and t9, the falling edge pulses caused by the input signal occur during the rising phase of VS. This reset pulse is lost, causing the high-voltage output signal HO to remain latched after going high, unable to shut down until the next falling edge pulse effectively reaches the high-voltage region. If the low-side signal outputs a high level during this period, turning on the low-side power devices, this will cause a direct current flow through the upper and lower bridge arms, damaging the devices. Similarly, when the input signal IN exhibits a high duty cycle—that is, a narrow negative pulse—the HD_S signal is overwhelmed during the falling phase of VS, resulting in HO output dropout. Summary of the Invention

[0005] The present application provides a high-side gate drive circuit that can solve the problem of the output signal being mistakenly locked in a constant high state during the VS rising phase due to the falling edge of a high-level narrow pulse, thereby damaging the low-side power device. It can also solve the problem of the output signal being mistakenly locked in a constant low state during the VS rising phase due to the rising edge of a low-level narrow pulse, thereby causing output wave loss. The technical solution is as follows:

[0006] On the one hand, a high-voltage side gate drive circuit is provided, wherein the high-voltage side gate drive circuit includes a dynamic pulse generation circuit, a high-voltage level shift circuit, a common-mode filter circuit, an RS trigger, and an output stage buffer circuit;

[0007] The input end of the dynamic pulse generating circuit serves as the input end of the high-voltage side gate driving circuit, the first output end of the dynamic pulse generating circuit is connected to the first input end of the high-voltage level shift circuit, and the second output end of the dynamic pulse generating circuit is connected to the second input end of the high-voltage level shift circuit;

[0008] The two output terminals of the high-voltage level shift circuit are respectively connected to the two input terminals of the common-mode filter circuit, and the two output terminals of the common-mode filter circuit are respectively connected to the set terminal and the reset terminal of the RS trigger;

[0009] The output end of the RS trigger is connected to the input end of the output stage buffer circuit, and the output end of the output stage buffer circuit serves as the output end of the high-voltage side gate drive circuit;

[0010] The high-voltage level shift circuit, the common-mode filter circuit, the RS trigger and the output stage buffer circuit are respectively connected to the high-voltage side power supply and the high-voltage side floating ground;

[0011] When the input signal is a narrow pulse, the dynamic pulse generating circuit is used to adjust the pulse width of the rising edge and / or falling edge of the narrow pulse so that the adjusted pulse end time is later than the end time of the high-voltage side floating ground mutation.

[0012] In a possible implementation, the high-voltage level shift circuit includes: a first LDMOS, a second LDMOS, a first resistor, a second resistor, a first diode, and a second diode;

[0013] The gate of the first LDMOS serves as a first input terminal of the high-voltage level shift circuit, the gate of the second LDMOS serves as a second input terminal of the high-voltage level shift circuit, and the sources of the first LDMOS and the second LDMOS are grounded;

[0014] The drain of the first LDMOS, the first port of the first resistor, and the cathode of the first diode are connected to a first connection point, and the first connection point serves as a first output end of the high-voltage level shift circuit;

[0015] The drain of the second LDMOS, the first port of the second resistor, and the cathode of the second diode are connected to a second connection point, and the second connection point serves as a second output end of the high-voltage level shift circuit;

[0016] The second port of the first resistor and the second port of the second resistor are respectively connected to the high-voltage side power supply, and the anodes of the first diode and the second diode are respectively connected to the high-voltage side floating ground.

[0017] In one possible implementation,

[0018] When the input signal includes a high-level narrow pulse, the dynamic pulse generating circuit is used to control the falling edge pulse width of the high-level narrow pulse; or,

[0019] When the input signal includes a low-level narrow pulse, the dynamic pulse generating circuit is used to control the rising edge pulse width of the low-level narrow pulse; or,

[0020] When the input signal includes a high-level narrow pulse and a low-level narrow pulse, the dynamic pulse generating circuit is used to control the falling edge pulse width of the high-level narrow pulse and the rising edge pulse width of the low-level narrow pulse.

[0021] In a possible implementation, when the dynamic pulse generating circuit is used to control the falling edge pulse width, the dynamic pulse generating circuit includes a rising edge pulse generating circuit, a delay circuit, a controlled current source, and a falling edge pulse generating circuit;

[0022] The input end of the rising edge pulse generating circuit is connected to the first input end of the falling edge pulse generating circuit and serves as the input end of the dynamic pulse generating circuit; the output end of the rising edge pulse generating circuit serves as the first output end of the dynamic pulse generating circuit, and the output end of the rising edge pulse generating circuit is connected to the input end of the delay circuit;

[0023] The output end of the delay circuit is connected to the input end of the controlled current source, and the output end of the controlled current source is connected to the second input end of the falling edge pulse generating circuit;

[0024] The output end of the falling edge pulse generating circuit serves as the second output end of the dynamic pulse generating circuit.

[0025] In a possible implementation, when the dynamic pulse generating circuit is used to control the falling edge pulse width, the dynamic pulse generating circuit includes a rising edge pulse generating circuit, a delay circuit, a falling edge pulse generating circuit, a first inverter, a second inverter, a first NOR gate, a second NOR gate, a third NOR gate, and a fourth NOR gate;

[0026] The input end of the rising edge pulse generating circuit and the input end of the falling edge pulse generating circuit are connected to serve as the input end of the dynamic pulse generating circuit; the output end of the rising edge pulse generating circuit serves as the first output end of the dynamic pulse generating circuit, and the output end of the rising edge pulse generating circuit is connected to the input end of the delay circuit;

[0027] The output end of the delay circuit is connected to the first input end of the first NOR gate and the first input end of the second NOR gate at a third connection point respectively;

[0028] The output end of the falling edge pulse generating circuit is respectively connected to the input end of the first inverter and the second input end of the fourth NOR gate at a fourth connection point; the output end of the first inverter is connected to the second input end of the first NOR gate; the output end of the first NOR gate is connected to the second input end of the second NOR gate; the output end of the second NOR gate is connected to the first input end of the third NOR gate; the output end of the third NOR gate is connected to the first input end of the fourth NOR gate; the output end of the fourth NOR gate is respectively connected to the input end of the second inverter and the second input end of the third NOR gate; the output end of the second inverter serves as the second output end of the dynamic pulse generating circuit.

[0029] In one possible implementation,

[0030] When the third connection point is at a high level and the fourth connection point is at a high level, the output of the second output terminal of the dynamic pulse generating circuit is at a high level;

[0031] When the third connection point is at a high level and the fourth connection point is at a low level, the output of the second output terminal of the dynamic pulse generating circuit is the same as the previous state;

[0032] When the third connection point is at a low level and the fourth connection point is at a high level, the output of the second output terminal of the dynamic pulse generating circuit is an effective high potential;

[0033] When the third connection point is at a low level and the fourth connection point is at a low level, the output of the second output terminal of the dynamic pulse generating circuit is an invalid low potential.

[0034] In a possible implementation, when the dynamic pulse generating circuit is used to control the rising edge pulse width, the dynamic pulse generating circuit includes a rising edge pulse generating circuit, a falling edge pulse generating circuit, a delay circuit, and a controlled current source;

[0035] The first input end of the rising edge pulse generating circuit and the input end of the falling edge pulse generating circuit are connected to each other and serve as the input end of the dynamic pulse generating circuit; the output end of the falling edge pulse generating circuit serves as the second output end of the dynamic pulse generating circuit, and the output end of the falling edge pulse generating circuit is connected to the input end of the delay circuit;

[0036] The output end of the delay circuit is connected to the input end of the controlled current source, and the output end of the controlled current source is connected to the second input end of the rising edge pulse generating circuit;

[0037] The output end of the rising edge pulse generating circuit serves as the first output end of the dynamic pulse generating circuit.

[0038] In a possible implementation, when the dynamic pulse generating circuit is used to control the falling edge pulse width and the rising edge pulse width, the dynamic pulse generating circuit includes a rising edge pulse generating circuit, a falling edge pulse generating circuit, a first delay circuit, a second delay circuit, a first controlled current source, and a second controlled current source;

[0039] The first input end of the rising edge pulse generating circuit and the first input end of the falling edge pulse generating circuit are connected to each other and serve as the input end of the dynamic pulse generating circuit; the output end of the rising edge pulse generating circuit serves as the first output end of the dynamic pulse generating circuit, and the output end of the rising edge pulse generating circuit is connected to the input end of the first delay circuit; the output end of the falling edge pulse generating circuit serves as the second output end of the dynamic pulse generating circuit, and the output end of the falling edge pulse generating circuit is connected to the input end of the second delay circuit;

[0040] The output end of the first delay circuit is connected to the input end of the first controlled current source, and the output end of the first controlled current source is connected to the second input end of the falling edge pulse generating circuit; the output end of the second delay circuit is connected to the input end of the second controlled current source, and the output end of the second controlled current source is connected to the second input end of the rising edge pulse generating circuit.

[0041] In one possible implementation,

[0042] The rising edge pulse generating circuit includes a third inverter, a fourth inverter, a fifth inverter, a sixth inverter, a first capacitor and a fifth NOR gate. When the rising edge pulse generating circuit includes one input end, the input end of the third inverter serves as the input end of the rising edge pulse generating circuit; when the rising edge pulse generating circuit includes two input ends, the two input ends of the third inverter serve as the first input end and the second input end of the rising edge pulse generating circuit respectively; the output end of the third inverter is respectively connected to the input end of the fourth inverter and the second input end of the fifth NOR gate, the output end of the fourth inverter is respectively connected to the positive electrode of the first capacitor and the input end of the fifth inverter, the negative electrode of the first capacitor is grounded, the output end of the fifth inverter is connected to the input end of the sixth inverter, the output end of the sixth inverter is connected to the first input end of the fifth NOR gate, and the output end of the fifth NOR gate serves as the output end of the rising edge pulse generating circuit;

[0043] The falling edge pulse generating circuit includes a seventh inverter, an eighth inverter, a ninth inverter, a second capacitor and a sixth NOR gate. When the falling edge pulse generating circuit includes one input terminal, the input terminal of the seventh inverter serves as the input terminal of the falling edge pulse generating circuit, and the input terminal of the falling edge pulse generating circuit is connected to the second input terminal of the sixth NOR gate. When the falling edge pulse generating circuit includes two input terminals, the two input terminals of the seventh inverter serve as the first input terminal and the second input terminal of the falling edge pulse generating circuit respectively, and the first input terminal of the falling edge pulse generating circuit is connected to the second input terminal of the sixth NOR gate. The output terminal of the seventh inverter is respectively connected to the positive electrode of the second capacitor and the input terminal of the eighth inverter, and the negative electrode of the second capacitor is grounded. The output terminal of the eighth inverter is connected to the input terminal of the ninth inverter, the output terminal of the ninth inverter is connected to the first input terminal of the sixth NOR gate, and the output terminal of the sixth NOR gate serves as the output terminal of the falling edge pulse generating circuit.

[0044] The delay circuit includes a tenth inverter, an eleventh inverter, and a third capacitor, wherein the input end of the tenth inverter serves as the input end of the delay circuit, the output end of the tenth inverter is connected to the positive electrode of the third capacitor and the input end of the eleventh inverter respectively, the negative electrode of the third capacitor is grounded, and the output end of the eleventh inverter serves as the output end of the delay circuit;

[0045] When the dynamic pulse generating circuit also includes the controlled current source, the controlled current source includes a current source and a PMOS tube, the current source is connected between a power supply and a source level of the PMOS tube, the gate of the PMOS tube serves as the input end of the controlled current source, and the drain of the PMOS tube serves as the output end of the controlled current source.

[0046] In a possible implementation, the delay value of the delay circuit is calculated according to the formula t P +(ΔV S × R L ×C DS ) / (VB-Vth), wherein the VB is the high-voltage side power supply, the R L is the load resistance of the high voltage level shift circuit, the C DS is the drain-source parasitic capacitance of LDMOS, Vth is the threshold of the common-mode filter circuit, and ΔV S is the voltage change of the high-voltage side floating ground, and the t P is the delay time from the LDMOS to the high-side output terminal.

[0047] The beneficial effects of the technical solution provided by this application include at least:

[0048] 1. The high-voltage side gate drive circuit in this application can dynamically adjust the pulse width of the rising edge and / or falling edge of the narrow pulse to prevent the output signal from being mistakenly locked in a constant high or constant low state, thereby ensuring the reliability of the chip.

[0049] 2. The maximum delay value of the pulse width comes from the minimum speed of charge discharge at the LDMOS drain end, which ensures that the pulse signal will not be submerged in the VS voltage change stage.

[0050] 3. Simple structure, avoiding extra costs. BRIEF DESCRIPTION OF THE DRAWINGS

[0051] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0052] Figure 1 It is a half-bridge topology using a high-voltage floating gate driver chip;

[0053] Figure 2 A high-voltage level shift circuit using dual-path LDMOS in the prior art;

[0054] Figure 3for Figure 2 The double pulse circuit normal working and fault working waveforms shown in FIG;

[0055] Figure 4 A circuit diagram of a high-voltage side gate drive circuit of the present application;

[0056] Figure 5 A circuit diagram of a dynamic pulse generating circuit;

[0057] Figure 6 for Figure 5 The working schematic waveform diagram of the circuit in FIG.

[0058] Figure 7 for Figure 5 A circuit diagram of the circuit in;

[0059] Figure 8 The following is a circuit diagram of another dynamic pulse generating circuit;

[0060] Figure 9 for Figure 8 The working schematic waveform diagram of the circuit in FIG.

[0061] Figure 10 The following is a circuit diagram of another dynamic pulse generating circuit;

[0062] Figure 11 This is a circuit diagram of another dynamic pulse generating circuit. DETAILED DESCRIPTION

[0063] In order to make the objectives, technical solutions and advantages of the embodiments of the present application clearer, the implementation methods of the present application will be further described in detail below with reference to the accompanying drawings.

[0064] Please refer to Figure 4 , which shows a high-voltage side gate drive circuit provided by an embodiment of the present application, including a dynamic pulse generation circuit, a high-voltage level shift circuit, a common-mode filter circuit, an RS trigger and an output stage buffer circuit (Buffer).

[0065] The input of the dynamic pulse generation circuit serves as the input of the high-voltage-side gate driver circuit. The first output of the dynamic pulse generation circuit is connected to the first input of the high-voltage level shift circuit, and the second output of the dynamic pulse generation circuit is connected to the second input of the high-voltage level shift circuit. The input signal IN_H of the dynamic pulse generation circuit comes from the input signal of the high-voltage-side channel. The output signal of the first output of the dynamic pulse generation circuit is PG_S, and the output signal of the second output of the dynamic pulse generation circuit is PG_R.

[0066] The two output terminals of the high-voltage level shift circuit are respectively connected to the two input terminals of the common-mode filter circuit, and the two output terminals of the common-mode filter circuit are respectively connected to the set terminal S and the reset terminal R of the RS trigger.

[0067] The output of the RS trigger is connected to the input of the output-stage buffer circuit, and the output of the output-stage buffer circuit serves as the output of the high-side gate drive circuit. The output of the output-stage buffer circuit is the output port of the high-side channel.

[0068] The high-voltage level shifter circuit, common-mode filter circuit, RS flip-flop, and output-stage buffer circuit are connected to the high-voltage side power supply VB and the high-voltage side floating ground VS, respectively. That is, the high-voltage level shifter circuit, common-mode filter circuit, RS flip-flop, and output-stage buffer circuit are connected between VB and VS.

[0069] When the input signal is a narrow pulse, the dynamic pulse generation circuit is used to adjust the pulse width of the rising and / or falling edges of the narrow pulse so that the adjusted pulse ends later than the end time of the sudden change in the high-side floating ground VS. In other words, when the input pulse width is narrow, the pulse width of the rising and / or falling edges of the input signal can be adaptively adjusted to obtain the pulse block width of PG_S and PG_R.

[0070] Among them, a narrow pulse refers to a pulse whose pulse width is less than a predetermined threshold. The predetermined threshold here is based on the formula t P +(ΔV S ×R L ×C DS ) / (VB-Vth), where VB is the high-voltage side power supply, R L is the load resistance of the high voltage level shift circuit, C DS is the drain-source parasitic capacitance of LDMOS, Vth is the threshold of the common-mode filter circuit, ΔV S is the voltage change of the floating ground on the high-voltage side, t P is the delay time from LDMOS to high-side output.

[0071] like Figure 4 As shown, the high voltage level shift circuit includes: a first LDMOS LD3, a second LDMOS LD4, a first resistor R1, a second resistor R2, a first diode D3 and a second diode D4;

[0072] The gate of the first LDMOS LD3 serves as the first input terminal of the high-voltage level shift circuit, the gate of the second LDMOS LD4 serves as the second input terminal of the high-voltage level shift circuit, and the sources of the first LDMOS LD3 and the second LDMOS LD4 are grounded; the drain of the first LDMOS LD3, the first port of the first resistor R1, and the cathode of the first diode D3 are connected to a first connection point HD_S, and the first connection point HD_S serves as the first output terminal of the high-voltage level shift circuit; the drain of the second LDMOS LD4, the first port of the second resistor R2, and the cathode of the second diode D4 are connected to a second connection point HD_R, and the second connection point HD_R serves as the second output terminal of the high-voltage level shift circuit; the second port of the first resistor R1 and the second port of the second resistor R2 are respectively connected to the high-voltage side power supply VB, and the anodes of the first diode D3 and the second diode D4 are respectively connected to the high-voltage side floating ground VS.

[0073] The first input of the high-voltage level shift circuit is PG_S, which acts on the gate of LD3. The second input of the high-voltage level shift circuit is PG_R, which acts on the gate of LD4. The first diode D3 and the second diode D4 clamp the voltages at points HD_S and HD_R, protecting the gates of the common-mode filter circuit.

[0074] There are three types of dynamic pulse generating circuits:

[0075] 1) When the input signal includes a high-level narrow pulse, the dynamic pulse generating circuit is used to control the falling edge pulse width of the high-level narrow pulse.

[0076] 2) When the input signal includes a low-level narrow pulse, the dynamic pulse generating circuit is used to control the rising edge pulse width of the low-level narrow pulse.

[0077] 3) When the input signal includes a high-level narrow pulse and a low-level narrow pulse, the dynamic pulse generating circuit is used to control the falling edge pulse width of the high-level narrow pulse and the rising edge pulse width of the low-level narrow pulse.

[0078] The high-level narrow pulse has a relatively low duty cycle, for example, a duty cycle close to 0%, while the low-level narrow pulse has a relatively high duty cycle, for example, a duty cycle close to 100%.

[0079] The circuit structures of these three types of dynamic pulse generating circuits are introduced below.

[0080] like Figure 5 As shown, in the first implementation of the first form, when the dynamic pulse generating circuit is used to control the falling edge pulse width, the dynamic pulse generating circuit includes a rising edge pulse generating circuit, a delay circuit, a controlled current source and a falling edge pulse generating circuit.

[0081] The input terminal of the rising-edge pulse generating circuit and the first input terminal of the falling-edge pulse generating circuit are connected to each other and serve as the input terminal of the dynamic pulse generating circuit; the output terminal of the rising-edge pulse generating circuit serves as the first output terminal of the dynamic pulse generating circuit. The input terminal of the rising-edge pulse generating circuit and the first input terminal of the falling-edge pulse generating circuit input IN_H, and the output terminal of the rising-edge pulse generating circuit outputs PG_S.

[0082] The output of the rising-edge pulse generator circuit is connected to the input of the delay circuit; the output of the delay circuit is connected to the input of a controlled current source, and the output of the controlled current source is connected to the second input of the falling-edge pulse generator circuit to control the width of the falling-edge pulse. The output of the falling-edge pulse generator circuit serves as the second output of the dynamic pulse generator circuit. The output of the falling-edge pulse generator circuit outputs PG_R.

[0083] Figure 6 Shown Figure 5 The working waveform of the dynamic pulse generating circuit is shown in Figure 2. Figure 2 Similarly, the operating waveform can be divided into the left and right halves. The left half shows an input signal with a wider pulse width. The rising edge pulse signal and its delayed signal do not overlap with the falling edge pulse signal, and the circuit can operate normally. The right half shows an input signal with a narrower pulse width. In this case, to prevent the falling edge pulse from being overwhelmed by dV / dt noise, the falling edge pulse signal is delayed for a period of time. The delay time is determined by Formula 2. Assuming that the threshold for the common-mode filter circuit to generate a response is Vth, the expression for the dV / dt that can cause the common-mode filter circuit to generate a response can be obtained as:

[0084]

[0085] Among them, VB is the high-voltage side power supply, R L is the load resistance of the high level shift circuit, C DS is the drain-source parasitic capacitance of the LDMOS. From Formula 1, we can see that when the dV / dt value is less than this value, the common-mode filter circuit will not respond. Therefore, the delay value of the delay circuit can be obtained:

[0086]

[0087] Among them, t P It is the delay time from LDMOS to the high-side output terminal HO.

[0088] like Figure 7 As shown, the structures of the rising edge pulse generating circuit, the falling edge pulse generating circuit, the delay circuit and the controlled current source are described below respectively.

[0089] The rising edge pulse generating circuit includes a third inverter INV8, a fourth inverter INV9, a fifth inverter INV 10 , the sixth inverter INV 11 , the first capacitor C1 and the fifth NOR gate NOR3, the input end of the third inverter INV8 serves as the input end of the rising edge pulse generating circuit; the output end of the third inverter INV8 is respectively connected to the input end of the fourth inverter INV9 and the second input end of the fifth NOR gate NOR3, the output end of the fourth inverter INV9 is respectively connected to the positive electrode of the first capacitor C1 and the fifth inverter INV 10 The negative electrode of the first capacitor C1 is grounded, and the fifth inverter INV 10 The output terminal of the sixth inverter INV 11 The input terminal of the sixth inverter INV 11 The output end of is connected to the first input end of the fifth NOR gate NOR3, and the output end of the fifth NOR gate NOR3 serves as the output end of the rising edge pulse generating circuit.

[0090] The falling edge pulse generating circuit includes a seventh inverter INV 14 , the eighth inverter INV 15 , the ninth inverter INV 16 , the second capacitor C2 and the sixth NOR gate NOR4, the seventh inverter INV 14 The two input ends of the falling edge pulse generating circuit are respectively used as the first input end and the second input end, and the first input end of the falling edge pulse generating circuit is connected to the second input end of the sixth NOR gate NOR4; the seventh inverter INV 14 The output end is connected to the positive electrode of the second capacitor C2 and the eighth inverter INV 15 The negative electrode of the second capacitor C2 is grounded, and the eighth inverter INV 15 The output terminal of the ninth inverter INV 16 The input terminal of the ninth inverter INV 16 The output end of is connected to the first input end of the sixth NOR gate NOR4, and the output end of the sixth NOR gate NOR4 serves as the output end of the falling edge pulse generating circuit.

[0091] The delay circuit includes a tenth inverter INV 12 、The eleventh inverter INV 13 and the third capacitor C3, the tenth inverter INV 12 The input end of the delay circuit is used as the input end of the tenth inverter INV 12 The output end is connected to the positive electrode of the third capacitor C3 and the eleventh inverter INV 13 The negative electrode of the third capacitor C3 is grounded, and the eleventh inverter INV13 The output end of is used as the output end of the delay circuit.

[0092] The controlled current source includes a current source I1 and a PMOS transistor M1. The current source I1 is connected between the power supply and the source of the PMOS transistor M1. The gate of the PMOS transistor M1 serves as the input end of the controlled current source, and the drain of the PMOS transistor M1 serves as the output end of the controlled current source.

[0093] like Figure 8 As shown, in the second implementation of the first form, when the dynamic pulse generating circuit is used to control the falling edge pulse width, the dynamic pulse generating circuit includes a rising edge pulse generating circuit, a delay circuit, a falling edge pulse generating circuit, a first inverter INV 17 , the second inverter INV 18 , a first NOR gate NOR5, a second NOR gate NOR6, a third NOR gate NOR7 and a fourth NOR gate NOR8.

[0094] The input end of the rising edge pulse generating circuit and the input end of the falling edge pulse generating circuit are connected to serve as the input end of the dynamic pulse generating circuit; the output end of the rising edge pulse generating circuit serves as the first output end of the dynamic pulse generating circuit, and the output end of the rising edge pulse generating circuit is connected to the input end of the delay circuit. Among them, the input end of the rising edge pulse generating circuit and the input end of the falling edge pulse generating circuit input IN_H, and the output end of the rising edge pulse generating circuit outputs PG_S. The output end of the delay circuit is respectively connected to the first input end of the first NOR gate NOR5 and the first input end of the second NOR gate NOR6 at the third connection point IN1. The output end of the falling edge pulse generating circuit is respectively connected to the first inverter INV 17 The input terminal of the first inverter INV and the second input terminal of the fourth NOR gate NOR8 are connected to the fourth connection point IN2; 17 The output end of the first NOR gate NOR5 is connected to the second input end of the second NOR gate NOR6; the output end of the second NOR gate NOR6 is connected to the first input end of the third NOR gate NOR7; the output end of the third NOR gate NOR7 is connected to the first input end of the fourth NOR gate NOR8; the output end of the fourth NOR gate NOR8 is connected to the second inverter INV 18 The input end of the second inverter INV is connected to the second input end of the third NOR gate NOR7; 18 The output end of the second inverter INV is used as the second output end of the dynamic pulse generating circuit. 18 The output of the output is PG_R.

[0095] Among them, the rising edge pulse generating circuit and delay circuit can refer to Figure 6 In addition, Figure 6 The falling edge pulse generating circuit has two input terminals, and Figure 8 The falling edge pulse generating circuit in the circuit has an input terminal, so it can be Figure 6 After the modification, the input end of the seventh inverter INV14 serves as the input end of the falling edge pulse generating circuit, and the input end of the falling edge pulse generating circuit is connected to the second input end of the sixth NOR gate NOR4, and the rest of the structure remains unchanged.

[0096] In this embodiment, when the third connection point IN1 is at a high level and the fourth connection point IN2 is at a high level, the output of the second output terminal of the dynamic pulse generating circuit is at a high level; when the third connection point IN1 is at a high level and the fourth connection point IN2 is at a low level, the output of the second output terminal of the dynamic pulse generating circuit is the same as the previous state; when the third connection point IN1 is at a low level and the fourth connection point IN2 is at a high level, the output of the second output terminal of the dynamic pulse generating circuit is a valid high potential; when the third connection point IN1 is at a low level and the fourth connection point IN2 is at a low level, the output of the second output terminal of the dynamic pulse generating circuit is an invalid low potential.

[0097] Simply put, when IN1=1 and IN2=1, the reset pulse PG_R outputs a high level; when IN1=1 and IN2=0, the PG_R signal remains unchanged; when IN1=0 and IN2=1, PG_R outputs a valid high level; when IN1=0 and IN2=0, PG_R outputs an invalid low level. This way, when the rising edge pulse delay signal ends later than the falling edge pulse, PG_R maintains a valid signal until the rising edge pulse delay signal ends.

[0098] Figure 9 for Figure 8 The schematic waveform of the circuit in the figure shows that the left half shows the input signal with a wider pulse width. It can be seen that the delay circuit has no effect on the operation of the circuit and the circuit works normally. The right half shows the input signal with a narrower pulse width. IN1 is the delayed signal of the rising edge pulse signal PG_S. According to the timing rules of the logic circuit, the falling edge starts when IN2 is high and remains until the IN1 signal changes from high to low, effectively preventing the chip from triggering incorrectly. Among them, the delay value of the delay circuit is based on the formula t P +(ΔV S ×R L ×C DS ) / (VB-Vth), where VB is the high-voltage side power supply, R L is the load resistance of the high voltage level shift circuit, C DSis the drain-source parasitic capacitance of LDMOS, Vth is the threshold of the common-mode filter circuit, ΔV S is the voltage change of the floating ground on the high-voltage side, t P is the delay time from LDMOS to high-side output.

[0099] like Figure 10 As shown, in the second form, when the dynamic pulse generating circuit is used to control the rising edge pulse width, the dynamic pulse generating circuit includes a rising edge pulse generating circuit, a falling edge pulse generating circuit, a delay circuit and a controlled current source.

[0100] The first input terminal of the rising-edge pulse generating circuit and the input terminal of the falling-edge pulse generating circuit are connected to each other and serve as the input terminal of the dynamic pulse generating circuit; the output terminal of the falling-edge pulse generating circuit serves as the second output terminal of the dynamic pulse generating circuit. The first input terminal of the rising-edge pulse generating circuit and the input terminal of the falling-edge pulse generating circuit input IN_H, and the output terminal of the falling-edge pulse generating circuit outputs PG_R.

[0101] The output of the falling-edge pulse generating circuit is connected to the input of the delay circuit; the output of the delay circuit is connected to the input of the controlled current source; the output of the controlled current source is connected to the second input of the rising-edge pulse generating circuit; the output of the rising-edge pulse generating circuit serves as the first output of the dynamic pulse generating circuit. The output of the rising-edge pulse generating circuit outputs PG_S.

[0102] Among them, the delay circuit and the controlled current source can refer to Figure 6 The implementation method in the falling edge pulse generation circuit can refer to Figure 8 In addition, Figure 6 The rising edge pulse generating circuit has an input terminal, and Figure 10 The rising edge pulse generating circuit in has two input terminals, so it can be Figure 6 After the modification, the two input terminals of the third inverter INV8 serve as the first input terminal and the second input terminal of the rising edge pulse generating circuit respectively.

[0103] Among them, the delay value of the delay circuit is based on the formula t P +(ΔV S ×R L ×C DS ) / (VB-Vth), where VB is the high-voltage side power supply, R L is the load resistance of the high voltage level shift circuit, C DS is the drain-source parasitic capacitance of LDMOS, Vth is the threshold of the common-mode filter circuit, ΔV Sis the voltage change of the floating ground on the high-voltage side, t P is the delay time from LDMOS to high-side output.

[0104] like Figure 11 As shown, in the third form, when the dynamic pulse generating circuit is used to control the falling edge pulse width and the rising edge pulse width, the dynamic pulse generating circuit includes a rising edge pulse generating circuit, a falling edge pulse generating circuit, a first delay circuit, a second delay circuit, a first controlled current source and a second controlled current source.

[0105] The first input of the rising-edge pulse generating circuit and the first input of the falling-edge pulse generating circuit are connected to each other and serve as the input of the dynamic pulse generating circuit; the output of the rising-edge pulse generating circuit serves as the first output of the dynamic pulse generating circuit; the output of the rising-edge pulse generating circuit is connected to the input of the first delay circuit; the output of the falling-edge pulse generating circuit serves as the second output of the dynamic pulse generating circuit, and the output of the falling-edge pulse generating circuit is connected to the input of the second delay circuit. The first input of the rising-edge pulse generating circuit and the first input of the falling-edge pulse generating circuit input IN_H, the output of the rising-edge pulse generating circuit outputs PG_S, and the output of the falling-edge pulse generating circuit outputs PG_R.

[0106] The output end of the first delay circuit is connected to the input end of the first controlled current source, and the output end of the first controlled current source is connected to the second input end of the falling edge pulse generating circuit; the output end of the second delay circuit is connected to the input end of the second controlled current source, and the output end of the second controlled current source is connected to the second input end of the rising edge pulse generating circuit.

[0107] The rising edge pulse generating circuit can refer to Figure 10 The implementation of the rising edge pulse generating circuit in the Figure 6 The implementation of the falling edge pulse generating circuit, the first delay circuit and the second delay circuit can refer to Figure 6 The implementation of the delay circuit, the first controlled current source and the second controlled current source can refer to Figure 6 Implementation of controlled current source.

[0108] Among them, the delay value of the delay circuit is based on the formula t P +(ΔV S ×R L ×C DS ) / (VB-Vth), where VB is the high-voltage side power supply, R L is the load resistance of the high voltage level shift circuit, C DS is the drain-source parasitic capacitance of LDMOS, Vth is the threshold of the common-mode filter circuit, ΔVS is the voltage change of the floating ground on the high-voltage side, t P is the delay time from LDMOS to high-side output.

[0109] Those skilled in the art will understand that all or part of the steps to implement the above embodiments may be accomplished by hardware, or by a program to instruct the relevant hardware, and the program may be stored in a computer-readable storage medium, which may be a read-only memory, a disk, or an optical disk, etc.

[0110] The above description is not intended to limit the embodiments of the present application. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the embodiments of the present application should be included in the scope of protection of the embodiments of the present application.

Claims

1. A high-voltage side gate drive circuit, characterized in that: The high-voltage side gate drive circuit includes a dynamic pulse generating circuit, a high-voltage level shifting circuit, a common-mode filtering circuit, an RS trigger and an output stage buffer circuit; The input end of the dynamic pulse generating circuit serves as the input end of the high-voltage side gate driving circuit, the first output end of the dynamic pulse generating circuit is connected to the first input end of the high-voltage level shift circuit, and the second output end of the dynamic pulse generating circuit is connected to the second input end of the high-voltage level shift circuit; The two output terminals of the high-voltage level shift circuit are respectively connected to the two input terminals of the common-mode filter circuit, and the two output terminals of the common-mode filter circuit are respectively connected to the set terminal and the reset terminal of the RS trigger; The output end of the RS trigger is connected to the input end of the output stage buffer circuit, and the output end of the output stage buffer circuit serves as the output end of the high-voltage side gate drive circuit; The high-voltage level shift circuit, the common-mode filter circuit, the RS trigger and the output stage buffer circuit are respectively connected to the high-voltage side power supply and the high-voltage side floating ground; When the input signal is a narrow pulse, the dynamic pulse generating circuit is used to adjust the pulse width of the rising edge and / or falling edge of the narrow pulse so that the adjusted pulse end time is later than the end time of the high-voltage side floating ground mutation; When the input signal includes a high-level narrow pulse, the dynamic pulse generating circuit is used to control the falling edge pulse width of the high-level narrow pulse; or, When the input signal includes a low-level narrow pulse, the dynamic pulse generating circuit is used to control the rising edge pulse width of the low-level narrow pulse; or, When the input signal includes a high-level narrow pulse and a low-level narrow pulse, the dynamic pulse generating circuit is used to control the falling edge pulse width of the high-level narrow pulse and the rising edge pulse width of the low-level narrow pulse.

2. The circuit according to claim 1, wherein: The high-voltage level shift circuit includes: a first LDMOS, a second LDMOS, a first resistor, a second resistor, a first diode and a second diode; The gate of the first LDMOS serves as a first input terminal of the high-voltage level shift circuit, the gate of the second LDMOS serves as a second input terminal of the high-voltage level shift circuit, and the sources of the first LDMOS and the second LDMOS are grounded; The drain of the first LDMOS, the first port of the first resistor, and the cathode of the first diode are connected to a first connection point, and the first connection point serves as a first output end of the high-voltage level shift circuit; The drain of the second LDMOS, the first port of the second resistor, and the cathode of the second diode are connected to a second connection point, and the second connection point serves as a second output end of the high-voltage level shift circuit; The second port of the first resistor and the second port of the second resistor are respectively connected to the high-voltage side power supply, and the anodes of the first diode and the second diode are respectively connected to the high-voltage side floating ground.

3. The circuit according to claim 1, wherein: When the dynamic pulse generating circuit is used to control the falling edge pulse width, the dynamic pulse generating circuit includes a rising edge pulse generating circuit, a delay circuit, a controlled current source and a falling edge pulse generating circuit; The input end of the rising edge pulse generating circuit and the first input end of the falling edge pulse generating circuit are connected to serve as the input end of the dynamic pulse generating circuit; The output end of the rising edge pulse generating circuit serves as the first output end of the dynamic pulse generating circuit, and the output end of the rising edge pulse generating circuit is connected to the input end of the delay circuit; The output end of the delay circuit is connected to the input end of the controlled current source, and the output end of the controlled current source is connected to the second input end of the falling edge pulse generating circuit; The output end of the falling edge pulse generating circuit serves as the second output end of the dynamic pulse generating circuit.

4. The circuit according to claim 1, wherein: When the dynamic pulse generating circuit is used to control the falling edge pulse width, the dynamic pulse generating circuit includes a rising edge pulse generating circuit, a delay circuit, a falling edge pulse generating circuit, a first inverter, a second inverter, a first NOR gate, a second NOR gate, a third NOR gate and a fourth NOR gate; The input end of the rising edge pulse generating circuit and the input end of the falling edge pulse generating circuit are connected to serve as the input end of the dynamic pulse generating circuit; the output end of the rising edge pulse generating circuit serves as the first output end of the dynamic pulse generating circuit, and the output end of the rising edge pulse generating circuit is connected to the input end of the delay circuit; The output end of the delay circuit is connected to the first input end of the first NOR gate and the first input end of the second NOR gate at a third connection point respectively; The output end of the falling edge pulse generating circuit is respectively connected to the input end of the first inverter and the second input end of the fourth NOR gate at a fourth connection point; the output end of the first inverter is connected to the second input end of the first NOR gate; the output end of the first NOR gate is connected to the second input end of the second NOR gate; the output end of the second NOR gate is connected to the first input end of the third NOR gate; the output end of the third NOR gate is connected to the first input end of the fourth NOR gate; the output end of the fourth NOR gate is respectively connected to the input end of the second inverter and the second input end of the third NOR gate; the output end of the second inverter serves as the second output end of the dynamic pulse generating circuit.

5. The circuit according to claim 4, characterized in that When the third connection point is at a high level and the fourth connection point is at a high level, the output of the second output terminal of the dynamic pulse generating circuit is at a high level; When the third connection point is at a high level and the fourth connection point is at a low level, the output of the second output terminal of the dynamic pulse generating circuit is the same as the previous state; When the third connection point is at a low level and the fourth connection point is at a high level, the output of the second output terminal of the dynamic pulse generating circuit is an effective high potential; When the third connection point is at a low level and the fourth connection point is at a low level, the output of the second output terminal of the dynamic pulse generating circuit is an invalid low potential.

6. The circuit according to claim 1, wherein: When the dynamic pulse generating circuit is used to control the rising edge pulse width, the dynamic pulse generating circuit includes a rising edge pulse generating circuit, a falling edge pulse generating circuit, a delay circuit and a controlled current source; The first input end of the rising edge pulse generating circuit and the input end of the falling edge pulse generating circuit are connected to each other and serve as the input end of the dynamic pulse generating circuit; the output end of the falling edge pulse generating circuit serves as the second output end of the dynamic pulse generating circuit, and the output end of the falling edge pulse generating circuit is connected to the input end of the delay circuit; The output end of the delay circuit is connected to the input end of the controlled current source, and the output end of the controlled current source is connected to the second input end of the rising edge pulse generating circuit; The output end of the rising edge pulse generating circuit serves as the first output end of the dynamic pulse generating circuit.

7. The circuit according to claim 1, characterized in that When the dynamic pulse generating circuit is used to control the falling edge pulse width and the rising edge pulse width, the dynamic pulse generating circuit includes a rising edge pulse generating circuit, a falling edge pulse generating circuit, a first delay circuit, a second delay circuit, a first controlled current source, and a second controlled current source; The first input end of the rising edge pulse generating circuit and the first input end of the falling edge pulse generating circuit are connected to serve as the input end of the dynamic pulse generating circuit; The output end of the rising edge pulse generating circuit serves as the first output end of the dynamic pulse generating circuit, and the output end of the rising edge pulse generating circuit is connected to the input end of the first delay circuit; the output end of the falling edge pulse generating circuit serves as the second output end of the dynamic pulse generating circuit, and the output end of the falling edge pulse generating circuit is connected to the input end of the second delay circuit; The output end of the first delay circuit is connected to the input end of the first controlled current source, and the output end of the first controlled current source is connected to the second input end of the falling edge pulse generating circuit; the output end of the second delay circuit is connected to the input end of the second controlled current source, and the output end of the second controlled current source is connected to the second input end of the rising edge pulse generating circuit.

8. The circuit according to any one of claims 3 to 6, characterized in that The rising edge pulse generating circuit includes a third inverter, a fourth inverter, a fifth inverter, a sixth inverter, a first capacitor and a fifth NOR gate. When the rising edge pulse generating circuit includes one input end, the input end of the third inverter serves as the input end of the rising edge pulse generating circuit; when the rising edge pulse generating circuit includes two input ends, the two input ends of the third inverter serve as the first input end and the second input end of the rising edge pulse generating circuit respectively; the output end of the third inverter is respectively connected to the input end of the fourth inverter and the second input end of the fifth NOR gate, the output end of the fourth inverter is respectively connected to the positive electrode of the first capacitor and the input end of the fifth inverter, the negative electrode of the first capacitor is grounded, the output end of the fifth inverter is connected to the input end of the sixth inverter, the output end of the sixth inverter is connected to the first input end of the fifth NOR gate, and the output end of the fifth NOR gate serves as the output end of the rising edge pulse generating circuit; The falling edge pulse generating circuit includes a seventh inverter, an eighth inverter, a ninth inverter, a second capacitor and a sixth NOR gate. When the falling edge pulse generating circuit includes one input terminal, the input terminal of the seventh inverter serves as the input terminal of the falling edge pulse generating circuit, and the input terminal of the falling edge pulse generating circuit is connected to the second input terminal of the sixth NOR gate. When the falling edge pulse generating circuit includes two input terminals, the two input terminals of the seventh inverter serve as the first input terminal and the second input terminal of the falling edge pulse generating circuit respectively, and the first input terminal of the falling edge pulse generating circuit is connected to the second input terminal of the sixth NOR gate. The output terminal of the seventh inverter is respectively connected to the positive electrode of the second capacitor and the input terminal of the eighth inverter, and the negative electrode of the second capacitor is grounded. The output terminal of the eighth inverter is connected to the input terminal of the ninth inverter, the output terminal of the ninth inverter is connected to the first input terminal of the sixth NOR gate, and the output terminal of the sixth NOR gate serves as the output terminal of the falling edge pulse generating circuit. The delay circuit includes a tenth inverter, an eleventh inverter, and a third capacitor, wherein the input end of the tenth inverter serves as the input end of the delay circuit, the output end of the tenth inverter is connected to the positive electrode of the third capacitor and the input end of the eleventh inverter respectively, the negative electrode of the third capacitor is grounded, and the output end of the eleventh inverter serves as the output end of the delay circuit; When the dynamic pulse generating circuit also includes the controlled current source, the controlled current source includes a current source and a PMOS tube, the current source is connected between a power supply and a source level of the PMOS tube, the gate of the PMOS tube serves as the input end of the controlled current source, and the drain of the PMOS tube serves as the output end of the controlled current source.

9. The circuit according to any one of claims 3 to 6, characterized in that The delay value of the delay circuit is calculated according to the formula t P +(ΔV S ×R L ×C DS ) / (VB-Vth), wherein VB is the high-voltage side power supply, and R L is the load resistance of the high voltage level shift circuit, the C DS is the drain-source parasitic capacitance of LDMOS, Vth is the threshold of the common-mode filter circuit, and ΔV S is the voltage change of the high-voltage side floating ground, and the t P is the delay time from the LDMOS to the high-side output terminal.

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