Depth pixel with multi-tap structure and time-of-flight sensor including depth pixel

Abstract

A depth pixel of a time-of-flight (ToF) sensor includes a common photogate disposed in a central region of the depth pixel, a plurality of floating diffusion regions disposed in a peripheral region surrounding the central region, a plurality of demodulation transfer gates disposed in the peripheral region, and a plurality of overflow gates disposed in the peripheral region. The demodulation transfer gates transfer photocharge collected by the common photogate to the plurality of floating diffusion regions. The demodulation transfer gates are symmetric about each of a horizontal line and a vertical line passing through a center of the depth pixel and substantially perpendicular to each other. The overflow gates drain the photocharge collected by the common photogate and are symmetric about each of the horizontal line and the vertical line.

Description

[0001] Cross-reference to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2020-0087667, filed with the Korean Intellectual Property Office (KIPO) on July 15, 2020, the entire disclosure of which is incorporated herein by reference. Technical Field

[0003] Embodiments of the present invention generally relate to semiconductor integrated circuits, and more specifically, to depth pixels having a multi-tap structure and time-of-flight (ToF) sensors including depth pixels. Background Technology

[0004] Recently, there has been a growing interest in image sensing for acquiring three-dimensional information about objects, and various 3D cameras are under development. Time-of-flight (ToF) sensors are a type of 3D camera that features simple circuitry and high distance resolution. ToF sensors use a light source to illuminate an object with transmitted light and calculate the distance to the object by measuring the phase difference of the time of flight of the received light reflected from the object using a demodulated signal. Summary of the Invention

[0005] Embodiments of the present invention may provide depth pixels and a time-of-flight (ToF) sensor including at least one depth pixel, which is capable of effectively measuring the distance to an object.

[0006] According to an embodiment of the present invention, a depth pixel of a ToF sensor includes: a common photogate disposed in a central region of the depth pixel; a plurality of floating diffusion regions disposed in a peripheral region surrounding the central region; a plurality of demodulation transmission gates disposed in the peripheral region; and a plurality of overflow gates disposed in the peripheral region. The plurality of demodulation transmission gates transfer photocharge collected by the common photogate to the plurality of floating diffusion regions. The plurality of demodulation transmission gates are symmetrical about each of a horizontal and a vertical line passing through the center of the depth pixel and substantially perpendicular to each other. The plurality of overflow gates discharge the photocharge collected by the common photogate. The plurality of overflow gates are symmetrical about each of the horizontal and vertical lines.

[0007] According to an embodiment of the present invention, a ToF sensor includes: a light source configured to illuminate an object with transmitted light; a pixel array including one or more depth pixels configured to provide information about the distance to the object based on reflected light as transmitted light reflected by the object; and a controller configured to control the light source and the pixel array. The depth pixel includes: a common photogate disposed in a central region of the depth pixel; a plurality of floating diffusion regions disposed in a peripheral region surrounding the central region; and a plurality of demodulation transmission gates disposed in the peripheral region and configured to transfer photocharge collected by the common photogate to the plurality of floating diffusion regions. The plurality of demodulation transmission gates are symmetrical about each of a horizontal and a vertical line passing through the center of the depth pixel and substantially perpendicular to each other. The depth pixel also includes a plurality of overflow gates disposed in the peripheral region and configured to discharge the photocharge collected by the common photogate. The plurality of overflow gates are symmetrical about each of the horizontal and vertical lines.

[0008] According to an embodiment of the present invention, a depth pixel of a ToF sensor includes: a common photogate disposed in the central region of the depth pixel. The common photogate includes at least one vertical photogate extending in a vertical direction substantially perpendicular to the upper surface of the semiconductor substrate, and the at least one vertical photogate is disposed in a trench formed in the upper portion of the semiconductor substrate. The depth pixel further includes: a plurality of floating diffusion regions disposed in a peripheral region surrounding the central region; a plurality of demodulation transmission gates disposed in the peripheral region and configured to transfer photocharge collected by the common photogate to the plurality of floating diffusion regions; and a plurality of overflow gates disposed in the peripheral region and configured to discharge the photocharge collected by the common photogate.

[0009] According to embodiments of the present invention, depth pixels can reduce the size and power consumption of a ToF sensor including depth pixels by applying a common photoelectric gate. Furthermore, depth pixels according to embodiments can improve sensing accuracy and sensitivity through symmetrical and modified structures of the common photoelectric gate, thereby enhancing the performance of the ToF sensor including depth pixels. Attached Figure Description

[0010] The above and other features of this disclosure will become clearer from the detailed description of its embodiments with reference to the accompanying drawings, in which:

[0011] Figure 1 This is a diagram illustrating the layout of depth pixels according to an embodiment of the present invention.

[0012] Figure 2A , Figure 2B , Figure 3A and Figure 3BThis is a cross-sectional view showing the vertical structure of a depth pixel according to an embodiment of the present invention.

[0013] Figure 4 This is a circuit diagram illustrating a depth pixel with a dual-tap structure according to an embodiment of the present invention.

[0014] Figure 5 This illustrates an embodiment of the concept according to the present invention. Figure 4 An example illustration of a layout of depth pixels with a double-tap structure.

[0015] Figure 6 and Figure 7 This illustrates an embodiment of the concept according to the present invention. Figure 4 A timing diagram of an example operation of a depth pixel with a double-tap structure.

[0016] Figure 8 This is a circuit diagram showing a depth pixel with a dual-tap structure having individual photoelectric gates, according to a comparative example.

[0017] Figure 9 It shows Figure 8 Timing diagram of operations on depth pixels with a double-tap structure.

[0018] Figure 10 This is a block diagram illustrating a time-of-flight (ToF) sensor according to an embodiment of the present invention.

[0019] Figure 11 and Figure 12 This is a diagram illustrating an example of a method for measuring and calculating distances to an object.

[0020] Figure 13 This is a circuit diagram illustrating a depth pixel with a four-tap structure according to an embodiment of the present invention.

[0021] Figure 14 This illustrates an embodiment of the concept according to the present invention. Figure 13 An example illustration of a layout of depth pixels with a four-tap structure.

[0022] Figure 15 This illustrates an embodiment of the concept according to the present invention. Figure 13 A timing diagram of an example operation of a depth pixel with a four-tap structure.

[0023] Figure 16 and Figure 17 This is a diagram illustrating an example of the structure of a shared floating diffusion region of depth pixels according to an embodiment of the present invention.

[0024] Figure 18A , Figure 18B , Figure 18C, Figure 19A , Figure 19B and 19C This is a diagram illustrating an example of the layout of depth pixels according to an embodiment of the present invention.

[0025] Figure 20 This is a cross-sectional view showing a depth pixel according to an embodiment of the present invention.

[0026] Figure 21A and 21B This illustrates an embodiment of the concept according to the present invention. Figure 20 A perspective view of an example of a common photoelectric gate with depth pixels.

[0027] Figure 22 This is a cross-sectional view showing a depth pixel according to an embodiment of the present invention.

[0028] Figure 23A and 23B This illustrates an embodiment of the concept according to the present invention. Figure 20 A perspective view of an example of a common photoelectric gate with depth pixels.

[0029] Figure 24 , Figure 25 , Figure 26 and Figure 27 This is a diagram illustrating an example of the layout of depth pixels according to an embodiment of the present invention.

[0030] Figure 28 This is a cross-sectional view showing a depth pixel according to an embodiment of the present invention.

[0031] Figure 29 This illustrates an embodiment of the concept according to the present invention. Figure 28 A perspective view of an example of a common photoelectric gate with depth pixels.

[0032] Figure 30A , Figure 30B , Figure 30C , Figure 31A , Figure 31B , Figure 31C and Figure 32 This is a cross-sectional view showing a depth pixel according to an embodiment of the present invention.

[0033] Figure 33A and Figure 33B This illustrates an embodiment of the concept according to the present invention. Figure 32 An example illustration of the polarization structure of a depth pixel.

[0034] Figure 34 This is a block diagram illustrating a computing system including a ToF sensor according to an embodiment of the present invention.

[0035] Figure 35 This illustrates an embodiment of the concept according to the present invention. Figure 34 A block diagram illustrating examples of interfaces used in computing systems. Detailed Implementation

[0036] Various embodiments will be described more fully below with reference to the accompanying drawings. Similar reference numerals may refer to similar elements throughout the drawings. For ease of explanation, repeated descriptions may be omitted.

[0037] The terms “first,” “second,” “third,” etc., are used herein to distinguish one element from another, and these elements are not limited by these terms. Thus, a “first” element in one embodiment may be described as a “second” element in another embodiment.

[0038] Unless the context explicitly indicates otherwise, the description of features or aspects within each embodiment should generally be considered as other similar features or aspects that may be used in other embodiments.

[0039] Unless the context explicitly indicates otherwise, the singular forms “a,” “one,” and “the” are intended to include the plural forms as used herein.

[0040] For ease of description, spatial relative terms such as “below,” “under,” “lower,” “below,” “above,” and “upper” may be used herein to describe the relationship of one element or feature relative to another element(s) or feature(s) as shown in the accompanying figures. It will be understood that, in addition to the orientation depicted in the figures, the spatial relative terms are also intended to cover different orientations of the device during use or operation. For example, if the device in the figures is flipped, the element described as “below,” “under,” or “below” to other elements or features will be oriented “above” to those other elements or features. Therefore, the exemplary terms “below” and “below” can encompass both the orientations above and below.

[0041] When a component such as a membrane, region, layer, or element is referred to as being "on," "connected to," "coupled to," or "adjacent to" another component, it may be directly on, connected to, coupled to, or adjacent to the other component, or there may be intermediate components present. It will also be understood that when a component is referred to as being "between" two components, it may be the only component between the two components, or there may be one or more intermediate components present. Other terms used to describe relationships between components should be interpreted in a similar manner.

[0042] When two or more elements or values ​​are described as substantially the same or approximately equal to each other, it should be understood that the elements or values ​​are the same, the elements or values ​​are equal to each other within the measurement error, or, as those skilled in the art will understand, are sufficiently close in value to be functionally equal if they are measurably unequal. For example, considering the measurement under discussion and the error associated with the measurement of a particular quantity (e.g., limitations of the measurement system), the term “approximately” as used herein includes the stated value and refers to an acceptable deviation from a particular value as determined by those skilled in the art. For example, “approximately” can mean within one or more standard deviations, as understood by those skilled in the art. Furthermore, as those skilled in the art will understand, although a parameter may be described herein as having an “approximately” specific value, it should be understood from the example embodiments that the parameter may be exactly that specific value or approximately that specific value within the measurement error.

[0043] Those skilled in the art will understand that when two components or directions are described as extending substantially parallel or perpendicular to each other, the two components or directions extend precisely parallel or perpendicular to each other, or extend approximately parallel or perpendicular to each other within measurement error.

[0044] Figure 1 This is a diagram illustrating the layout of depth pixels according to an embodiment of the present invention. Figure 2A , Figure 2B , Figure 3A and Figure 3B This is a cross-sectional view showing the vertical structure of a depth pixel according to an embodiment of the present invention.

[0045] In the following description, the structure of the integrated circuit according to the embodiment is described using a first horizontal direction X, a second horizontal direction Y, and a vertical direction Z in three-dimensional space. The first horizontal direction X and the second horizontal direction Y may be substantially parallel to the upper surface of the semiconductor substrate and substantially perpendicular to each other. The vertical direction Z may be substantially perpendicular to the upper surface of the semiconductor substrate. The first direction X may be a row direction, and the second direction Y may be a column direction.

[0046] refer to Figure 1 , Figure 2A , Figure 2B , Figure 3A and Figure 3B The depth pixel PX may include a common photoelectric gate (CPG), multiple floating diffusion regions (FDA and FDB), multiple demodulation transmission gates (TGA and TGB), and multiple overflow gates (OG1 and OG2). For ease of explanation, Figure 1 , Figure 2A , Figure 2B , Figure 3A and Figure 3BThe diagram shows two floating diffusion regions (FDA and FDB) and two demodulation transmission gates (TGA and TGB) corresponding to the two tap structures. However, the number of floating diffusion regions and demodulation transmission gates can be varied in the embodiment depending on the number of taps for the depth pixels. Additionally, the number of overflow gates can be determined differently.

[0047] The common photoelectric gate (CPG) can be set in the central region CREG of the depth pixel PX, and multiple floating diffusion regions (FDA and FDB), multiple demodulation transmission gates (TGA and TGB), and multiple overflow gates (OG1 and OG2) can be set in the peripheral region PREG surrounding the central region CREG.

[0048] Multiple demodulation transmission gates (TGA) and TGB can transfer the photocharge collected by the common photogate (CPG) to multiple floating diffusion regions (FDA) and FDB, and multiple overflow gates (OG1 and OG2) can discharge the photocharge collected by the common photogate (CPG). The following will refer to... Figure 6 and Figure 7 To describe the operation of depth pixel PX.

[0049] Multiple demodulation transmission gates TGA and TGB can be symmetrical about each of the horizontal line HLX (e.g., an imaginary horizontal line) and the vertical line HLY (e.g., an imaginary vertical line) that pass through the center CP of the depth pixel PX and are substantially perpendicular to each other. Additionally, multiple overflow gates OG1 and OG2 can be symmetrical about each of the horizontal line HLX and the vertical line HLY.

[0050] In the embodiments, reference will be made to the following: Figure 4 and Figure 5 As described, the depth pixel PX may also include multiple charge storage structures disposed in the peripheral region PREG between multiple floating diffusion regions FDA and FDB and demodulation transmission gates TGA and TGB. These multiple charge storage structures can temporarily store photoelectric charge transferred from the common photoelectric gate CPG before transferring photoelectric charge to the multiple floating diffusion regions FDA and FDB.

[0051] In the comparative example, the depth pixel includes multiple photogates, and multiple demodulated signals of different phases are applied to the multiple photogates during the integration period to sense the intensity of incident light. Conversely, the depth pixel PX according to an embodiment of the present invention includes a single common photogate CPG disposed in the central region CREG. (See below for reference.) Figure 6 and 7As described, in the embodiment, multiple demodulated signals of different phases are applied to multiple demodulated transmission gates TGA and TGB during the integration period. The photogate voltage applied to the common photogate CPG may have a DC voltage level that allows photocharge to be collected during the integration period, and the overflow gate voltage applied to the multiple overflow gates OG1 and OG2 may have a turn-off voltage level that prevents photocharge from being discharged during the integration period.

[0052] refer to Figure 2A and Figure 2B The depth pixel PX may include floating diffusion regions FDA and FDB, drain regions DR1 and DR2 formed in the semiconductor substrate 10, and common photogates CPG, demodulation transmission gates TGA and TGB, and overflow gates OG1 and OG2 formed above the semiconductor substrate 10. The floating diffusion regions FDA and FDB, drain regions DR1 and DR2, common photogates CPG, demodulation transmission gates TGA and TGB, and overflow gates OG1 and OG2 may be symmetrical about the vertical line VLZ passing through the center CP of the depth pixel PX.

[0053] The floating diffusion regions FDA and FDB, as well as the drain regions DR1 and DR2, can be formed using processes such as ion implantation. Common photogates CPG, demodulation transmission gates TGA and TGB, and overflow gates OG1 and OG2 can be spaced from the upper surface 11 of the semiconductor substrate 10 using processes such as deposition and etching. An insulating layer DL (e.g., an oxide layer) can be formed between the upper surface 11 of the semiconductor substrate 10 and the gates CPG, TGA, TGB, OG1, and OG2.

[0054] Gates CPG, TGA, TGB, OG1, and OG2 may include, for example, polycrystalline silicon and transparent conductive oxides (TCOs), such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), titanium dioxide (TiO2), etc.

[0055] More specifically, for example, in one or more embodiments where light incident on the depth pixel PX passes through the upper surface 11 of the semiconductor substrate 10, the gates CPG, TGA, TGB, OG1, and OG2 may, for example, comprise transparent conductive oxides. In embodiments where light incident on the depth pixel PX passes through the lower surface of the semiconductor substrate 10, the gates CPG, TGA, TGB, OG1, and OG2 may, for example, comprise opaque conductive oxides.

[0056] The depth pixel PX may also include a photocharge storage region, such as a photodiode PD formed in the semiconductor substrate 10 below a common photogate CPG. The photodiode PD may be spaced apart from the floating diffusion regions FDA and FDB and the drain regions DR1 and DR2. In an embodiment, the semiconductor substrate 10 may be a P-type semiconductor substrate, and the photodiode PD may be doped with N-type impurities. However, the embodiments are not limited thereto. For example, in an embodiment, the semiconductor substrate 10 may be an N-type semiconductor substrate or may include an N-type well, and the photodiode PD may be doped with P-type impurities.

[0057] The photogate voltage VPG can be applied to the common photogate CPG, and the demodulated signals STGA and STGB can be applied to the demodulated transmission gates TGA and TGB, respectively. The demodulated signals STGA and STGB can have different phases, and the photocharges corresponding to the phases of the demodulated signals STGA and STGB can be transferred to the floating diffusion regions FDA and FDB, respectively.

[0058] An overflow voltage VOG can be applied to overflow gates OG1 and OG2, and a power supply voltage VDD can be applied to drain regions DR1 and DR2. The overflow voltage VOG can have a turn-off voltage level that prevents photocharge discharge during the integration period, and a turn-on voltage level that allows the photocharge collected by the common photogate to be discharged during other periods (such as the reset period and readout period). During periods other than the integration period, a channel can be formed in the semiconductor substrate between the photodiode PD and drain regions DR1 and DR2 using the turn-on voltage level, and the photocharge collected in the common photogate CPG can be discharged to the terminals of the power supply voltage VDD. Thus, a global shutter function can be implemented using overflow gates OG1 and OG2.

[0059] Time-of-flight (TOF) photoelectric detection equipment measures the light reflected from an object to determine the distance to the object. Typically, locking detection methods using two or four taps corresponding to different phases are widely used for distance determination.

[0060] In typical lock-on detection methods, these taps are phased with each other by approximately 180 degrees (in the case of two taps) or approximately 90 degrees (in the case of four taps), and a sinusoidal modulated wave or a pulse sequence signal with approximately 50% duty cycle is used for each tap. Lock-on detection methods generally use depth pixels with a multi-tap structure, where the photocharge storage region and / or photocharge generation region (such as a photodiode PD) can be shared by multiple floating diffusion regions.

[0061] and Figure 2A and 2B Compared to the vertical structure, such as Figure 3A and3B As shown, the semiconductor substrate 10 may include multiple regions 13, 14, and 15 doped with impurities of different conductivity types and / or different concentrations. For example, if the semiconductor substrate 10 has P-type conductivity, the semiconductor substrate 10 may sequentially include an N-region 13, a P-region 14, and a P+ region 15 starting from the upper surface 11 of the semiconductor substrate 10. The N-region 13 is doped with N-type impurities, while the P-region 14 and P+ region 15 are doped with P-type impurities. The P-region 14 is lightly doped than the P+ region 15.

[0062] When near-infrared (NIR) light with wavelengths ranging from about 700 nm to about 850 nm is used as the light source in a TOF sensor, a P-type semiconductor substrate can be used as the semiconductor substrate 10.

[0063] Photons incident on the depth pixel PX can enter P-region 14 and generate electron-hole pairs within it. That is, P-region 14 can correspond to the main photocharge generation region, where photocharge can be primarily generated. Photoelectrons generated as minority carriers can move to the depletion region of the NP junction at the boundary between N-region 13 and P-region 14, and then diffuse and be collected by the common photogate CPG. Since the heavily doped P+ region 15 is located below P-region 14 compared to P-region 14, photoelectrons generated near the boundary between P-region 14 and P+ region 15 may tend to move into the NP junction portion.

[0064] According to an embodiment, N-region 13 can be replaced by P-region. Since this P-region is located above P-region 14, it can block photoelectrons when gates CPG, TGA, TGB, OG1, and OG2 are in the off state, and can transmit photoelectrons when gates CPG, TGA, TGB, OG1, and OG2 are in the on state.

[0065] Thus, the semiconductor substrate 10 may include multiple photocharge generation regions 13, 14, and 15 doped with impurities of different conductivity types and / or different concentrations, which can improve the sensitivity of the depth pixel PX. In addition to the photocharge generation regions 13, 14, and 15, a photodiode PD may also be formed.

[0066] Figure 4 This is a circuit diagram illustrating a depth pixel with a dual-tap structure according to an embodiment of the present invention. Figure 5 This illustrates an embodiment of the concept according to the present invention. Figure 4 An example illustration of a layout for depth pixels with a double-tap structure. For ease of explanation, previous references may be omitted below. Figure 1 , Figure 2A , Figure 2B , Figure 3A and Figure 3B Further description of the components and technologies described.

[0067] refer to Figure 4 and Figure 5 The depth pixel PX1 may include transistors TMA, TS and TT corresponding to the first tap TA, transistors TMB, TS and TT corresponding to the second tap TB, transistors TRS, TSF and TSL corresponding to the readout circuit, and common photoelectric gates CPG, overflow gates OG1 and OG2 and photodiode PD corresponding to the shared circuit.

[0068] Each of transistors TMA, TMB, TS, TT, and TRS may include a gate disposed above a semiconductor substrate, and source and drain regions disposed on either side of the gate in the semiconductor substrate. The gates of transistors TMA, TMB, TS, TT, and TRS correspond to a first demodulation transmission gate TGA, a second demodulation transmission gate TGB, a memory gate SG, a floating diffusion (FD) transmission gate TG, and a reset gate RG, respectively.

[0069] The photoelectric gate voltage VPG is applied to the common photoelectric gate CPG, the overflow gate voltage VOG is applied to overflow gates OG1 and OG2, the storage control signal SSG is applied to the storage gate SG, the FD transfer control signal STG is applied to the FD transfer gate TG, the reset signal SRG is applied to the reset gate RG, and the select signal SEL is applied to the gate of the select transistor TSL. A first demodulation signal STGA and a second demodulation signal STGB with different phases are applied to the first demodulation transfer gate TGA and the second demodulation transfer gate TGB, respectively.

[0070] The following will be a reference Figure 10 As described, under the control of the controller 150, the row scanning circuit 130 can provide the photoelectric gate voltage VPG, the overflow gate voltage VOG, the storage control signal SSG, the FD transfer control signal STG, the reset signal SRG, the selection signal SEL, and the demodulation signals STGA and STGB.

[0071] The storage gate SG is one type of charge storage structure that temporarily stores the photocharge transferred from the common photogate CPG before transferring the photocharge to the floating diffusion regions FDA and FDB. In embodiments, the charge storage structure can be implemented using only the storage gate SG. In embodiments, the charge storage structure can be implemented using the storage gate SG and a storage diode formed in the semiconductor substrate below the storage gate SG. Using this charge storage structure, true correlated double sampling (CDS) can be performed, and noise in the readout signal can be reduced. According to embodiments, the FD transfer gate TG and / or the storage gate SG can be omitted.

[0072] The charge stored in the floating diffusion regions FDA and FDB can be provided as output signals VOUTA and VOUTB using the source follower transistor TSF and the select transistor TSL.

[0073] like Figure 5 As shown, a common photogate CPG can be positioned in the central region of the depth pixel PX1, and demodulation transmission gates TGA and TGB, as well as overflow gates OG1 and OG2, can form a symmetrical structure about the common photogate CPG. For example, demodulation transmission gates TGA and TGB can be symmetrical about each line in the horizontal line HLX and the vertical line HLY, that is, symmetrical about the central CP of the depth pixel PX1. Similarly, overflow gates OG1 and OG2 can be symmetrical about each line in the horizontal line HLX and the vertical line HLY, that is, symmetrical about the central CP of the depth pixel PX1. This symmetrical structure reduces the deviation in the operational characteristics of taps TA and TB, and improves the sensing accuracy of the depth pixel PX1.

[0074] Figure 6 and Figure 7 This illustrates an embodiment of the concept according to the present invention. Figure 4 Timing diagram of an example operation for a depth pixel with a double-tap structure.

[0075] refer to Figures 4 to 7 During the integration period TINT, the photogate voltage VPG applied to the common photogate CPG can have a DC voltage level VDC that collects photocharge, and the overflow gate voltage VOG applied to the overflow gates OG1 and OG2 can have a turn-off voltage level VOFF that prevents the discharge of photocharge. Additionally, during the integration period TINT, a first demodulated signal STGA and a second demodulated signal STGB with different phases can be applied to the first demodulated transmission gate TGA and the second demodulated transmission gate TGB, respectively. The phase of the first demodulated signal STGA can be synchronized with the phase of the transmitted light TL. In an embodiment, the phase difference between the first demodulated signal STGA and the second demodulated signal STGB can be approximately 180 degrees. Reference will be made below. Figures 10 to 12 This describes a method for measuring distance using demodulated signals with different phases.

[0076] During other time periods, such as the reset period TRST that initializes the depth pixel PX1 and the readout period TRD that measures the amount of photocharge collected by the common photogate CPG, the overflow gate voltage VOG can have a turn-on voltage level VON that allows the photocharge collected by the common photogate CPG to be discharged. Thus, a global shutter function can be achieved by using overflow gates OG1 and OG2 to discharge charge during periods other than the integration period TINT.

[0077] In an embodiment, such as Figure 6 As shown, the DC voltage level VDC of the photogate voltage VPG during the reset period TRST and the readout period TRD can be approximately equal to the DC voltage level VDC during the integration period TINT. The DC voltage level VDC can be the voltage level between the high voltage level VH and the low voltage level VL of the demodulated signals STGA and STGB. In the embodiment, as... Figure 7 As shown, the second DC voltage level VDC' of the photogate voltage VPG during the reset period TRST and readout period TRD can differ from the first DC voltage level VDC during the integration period TINT. The first DC voltage level VDC during the integration period TINT can be the voltage level between the high voltage level VH and the low voltage level VL of the demodulated signals STGA and STGB. During the reset period TRST and readout period TRD, overflow gates OG1 and OG2 are in the ON state, and the second DC voltage level VDC' can be determined based on the potential distribution of the channel formed in the semiconductor substrate. Even Figure 7 The second DC voltage level VDC' is shown to be higher than the first DC voltage level VDC, but embodiments of the present invention are not limited thereto. For example, in an embodiment, the second DC voltage level VDC' may be lower than the first DC voltage level VDC, depending on the potential distribution of the channel.

[0078] Figure 8 This is a circuit diagram showing a depth pixel with a dual-tap structure having individual photoelectric gates, according to a comparative example. Figure 9 It shows Figure 8 Timing diagram of operations on depth pixels with a double-tap structure. Figure 8 The depth pixel PX1' and Figure 4 The depth pixels PX1 are similar. Therefore, for ease of explanation, the previous reference can be omitted. Figures 4 to 7 Further description of the components and technologies described.

[0079] refer to Figure 8 The depth pixel PX1' may include a first photogate PGA corresponding to the first tap TA and a second photogate PGB corresponding to the second tap TB, which replace the Figure 4 and Figure 5 Public photoelectric gate CPG.

[0080] refer to Figure 8 and Figure 9During the integration period TINT, the first demodulated signal SPGA and the second demodulated signal SPGB, with different phases, are applied to the first photogate PGA and the second photogate PGB, respectively. During the integration period TINT, the first transmission control signal STGA and the second transmission control signal STGB, applied to the first transmission gate TGA and the second transmission gate TGB, have constant voltage levels.

[0081] Thus, the toggling demodulation signals SPGA and SPGB are applied to Figure 8 Individual photogates PGA and PGB corresponding to taps TA and TB in the depth pixel PX1′. Generally, photogates have relatively large sizes to increase the amount of photocharge collected. Therefore, power consumption may increase when trigger demodulation signals SPGA and SPGB are applied to large photogates PGA and PGB. Conversely, in embodiments of the present invention... Figure 4 and Figure 5 In the depth pixel PX1, a constant DC voltage level VDC is applied to the common photogate CPG, and triggers demodulation signals STGA and STGB to be applied to the relatively smaller demodulation transmission gates TGA and TGB. Therefore, with... Figure 8 Compared to the depth pixel PX1', it can reduce power consumption.

[0082] Furthermore, the number of signal lines for the depth pixel PX1' can be increased by adjusting the number of taps or photogates. Increasing the number of signal lines can constrain semiconductor manufacturing processes and limit the reduction in depth pixel size. Conversely, reference... Figure 4 and Figure 5 In the inventive embodiment of the invention, regardless of the number of taps, the depth pixel PX1 can be driven by a single signal line to reduce the size of the common photogate CPG.

[0083] Thus, according to the inventive embodiment of the present invention, the power consumption and size of the depth pixel can be reduced by applying the aforementioned common photoelectric gate (CPG).

[0084] Figure 10 This is a block diagram illustrating a time-of-flight (ToF) sensor according to an embodiment of the present invention.

[0085] refer to Figure 10 The ToF sensor 100 includes a sensing unit, a controller 150, and a light source module 200. The sensing unit may include a pixel array 110, an analog-to-digital converter (ADC) unit 120, a row scanning circuit 130, and a column scanning circuit 140.

[0086] Pixel array 110 may include depth pixels that receive light RL reflected from object OBJ after being transmitted by light source module 200 to object OBJ. This reflected light may be referred to as reflected light RL, and the depth pixels may convert the reflected light RL into an electrical signal. The depth pixels may provide information related to the distance from ToF sensor 100 to object OBJ and / or black-and-white image information.

[0087] The pixel array 110 may further include color pixels for providing color image information. In this case, the ToF sensor 100 may be a three-dimensional color image sensor that provides color image information and depth information. According to an embodiment, infrared filters and / or near-infrared filters may be formed on the depth pixels, and color filters (e.g., red, green, and blue filters) may be formed on the color pixels. According to an embodiment, the ratio of the number of depth pixels to the number of color pixels may be varied as needed.

[0088] The ADC unit 120 can convert analog signals output from the pixel array 110 into digital signals. According to one embodiment, the ADC unit 120 can perform column-level analog-to-digital conversion, which uses multiple analog-to-digital converters respectively coupled to multiple column lines to convert analog signals in parallel. According to another embodiment, the ADC unit 120 can perform a single analog-to-digital conversion, which uses a single analog-to-digital converter to sequentially convert analog signals.

[0089] According to an embodiment, the ADC unit 120 may further include a correlated double sampling (CDS) unit for extracting valid signal components. According to an embodiment, the CDS unit may perform an analog double sampling operation that extracts valid signal components based on the difference between an analog reset signal including a reset component and an analog data signal including a signal component. According to an embodiment, the CDS unit may perform digital double sampling that converts the analog reset signal and the analog data signal into two digital signals and extracts valid signal components based on the difference between these two digital signals. According to an embodiment, the CDS unit may perform a dual correlated double sampling operation that performs both analog and digital double sampling operations.

[0090] The line scanning circuit 130 can receive control signals from the controller 150 and can control the line address and line scanning of the pixel array 110. To select a line among multiple line lines, the line scanning circuit 130 can apply a signal to the pixel array 110 to activate the selected line line. According to an embodiment, the line scanning circuit 130 may include a line decoder for selecting line lines of the pixel array 110 and a line driver for applying the signal to activate the selected line line.

[0091] Column scan circuit 140 can receive control signals from controller 150 and can control the column address and column scan of pixel array 110. Column scan circuit 140 can output digital output signals from ADC unit 120 to digital signal processing circuitry and / or an external host. For example, column scan circuit 140 can provide horizontal scan control signals to ADC unit 120 to sequentially select multiple analog-to-digital converters included in ADC unit 120. According to an embodiment, column scan circuit 140 may include a column decoder that selects one of the multiple analog-to-digital converters and a column driver that applies the output of the selected analog-to-digital converter to a horizontal transmission line. The horizontal transmission line may have a bit width corresponding to the bit width of the digital output signal.

[0092] The controller 150 can control the ADC unit 120, the row scanning circuit 130, the column scanning circuit 140, and the light source module 200. The controller 150 can provide control signals, such as clock signals and timing control signals, to the ADC unit 120, the row scanning circuit 130, the column scanning circuit 140, and the light source module 200. According to an embodiment, the controller 150 may include control logic circuitry, a phase-locked loop circuit, a timing control circuit, and a communication interface circuit.

[0093] The light source module 200 can emit light of a desired (or alternatively, predetermined) wavelength. For example, the light source module 200 can emit infrared and / or near-infrared light. The light source module 200 may include a light source 210 and a lens 220. The light source 210 can be controlled by the controller 150 to emit transmitted light TL with a desired intensity and / or characteristics (e.g., periodicity). For example, the intensity and / or characteristics of the transmitted light TL can be controlled so that the transmitted light TL has a waveform such as a pulse wave, a sine wave, a cosine wave, etc. The light source 210 can be implemented by, for example, a light-emitting diode (LED), a laser diode, etc.

[0094] The normal operation of the ToF sensor 100 according to the embodiment will be described below.

[0095] The controller 150 can control the light source module 200 to emit transmitted light TL with periodic intensity. The transmitted light TL emitted by the light source module 200 can be reflected back from the object OBJ to the ToF sensor 100 as reflected light RL. The reflected light RL can be incident on a depth pixel, and the depth pixel can be activated by the row scan circuit 130 to output an analog signal corresponding to the reflected light RL. The ADC unit 120 can convert the analog signal output from the depth pixel into sampled data SDATA. The sampled data SDATA can be provided to the controller 150 by the column scan circuit 140 and / or the ADC 120.

[0096] The controller 150 can calculate the distance from the ToF sensor 100 to the object OBJ, the horizontal position of the object OBJ, the vertical position of the object OBJ, and / or the size of the object OBJ based on the sampled data SDATA. The controller 150 can control the emission angle or projection (or incident) area of ​​the transmitted light TL based on the distance, horizontal position, vertical position, and / or size of the object OBJ. For example, the controller 150 can control the spacing between the light source 210 and the lens 220, the relative position (or arrangement) of the light source 210 and the lens 220 relative to each other, the refractive index of the lens 220, the curvature of the lens 220, etc.

[0097] The transmitted light TL illuminating the object OBJ can be reflected, and the reflected light RL can be incident on the depth pixels in the pixel array 110. The depth pixels can output an analog signal corresponding to the reflected light RL, and the ADC unit 120 can convert the analog signal into digital data or sampled data SDATA. The sampled data SDATA and / or depth information can be provided to the controller 150, digital signal processing circuitry, and / or an external host. According to an embodiment, the pixel array 110 may include color pixels, and color image information and depth information can be provided to the digital signal processing circuitry and / or an external host.

[0098] Figure 11 and Figure 12 This is a diagram illustrating an example of a method for measuring and calculating distances to an object.

[0099] refer to Figure 10 and Figure 11 The transmitted light TL emitted by the light source module 200 can have periodic intensity and / or characteristics. For example, the intensity of the transmitted light TL (e.g., the number of photons per unit area) can have a sinusoidal waveform.

[0100] Transmitted light TL emitted by light source module 200 can be reflected from object OBJ and then incident on pixel array 110 as reflected light RL. Pixel array 110 can periodically sample the reflected light RL. According to an embodiment, during each cycle of the reflected light RL (e.g., corresponding to the cycle of the transmitted light TL), pixel array 110 can perform sampling operations on the reflected light RL, for example, at two sampling points with a phase difference of about 180 degrees, at four sampling points with a phase difference of about 90 degrees, or at more than four sampling points. For example, pixel array 110 can extract four samples A0, A1, A2, and A3 of the reflected light RL each cycle with phases of about 90 degrees, about 180 degrees, about 270 degrees, and about 360 degrees, respectively.

[0101] Due to factors such as background light and noise, the reflected light RL may have an offset B that differs from the offset of the transmitted light TL emitted by the light source module 200. The offset B of the reflected light RL can be calculated using Equation 1.

[0102] [Equation 1]

[0103]

[0104] Here, A0 represents the intensity of the reflected light RL sampled at approximately 90 degrees of the phase of the emitted transmitted light TL, A1 represents the intensity of the reflected light RL sampled at approximately 180 degrees of the phase of the emitted transmitted light TL, A2 represents the intensity of the reflected light RL sampled at approximately 270 degrees of the phase of the emitted transmitted light TL, and A3 represents the intensity of the reflected light RL sampled at approximately 360 degrees of the phase of the emitted transmitted light TL.

[0105] The amplitude A of the reflected light RL may be smaller than the amplitude A of the transmitted light TL emitted by the light source module 200 due to losses (e.g., light loss). The amplitude A of the reflected light RL can be calculated using Equation 2.

[0106] [Equation 2]

[0107]

[0108] Black and white image information about object OBJ can be provided by the amplitude A of the reflected light RL based on the corresponding depth pixels included in pixel array 110.

[0109] The reflected light RL can be delayed by a phase difference Φ relative to the emitted transmitted light TL, which corresponds to, for example, twice the distance between the object OBJ and the ToF sensor 100. The phase difference Φ between the emitted transmitted light TL and the reflected light RL can be calculated using Equation 3.

[0110] [Equation 3]

[0111]

[0112] The phase difference Φ between the emitted transmitted light TL and the reflected light RL can correspond to, for example, the time of flight (TOF). The distance between the object OBJ and the ToF sensor 100 can be calculated using the equation "R = c * TOF / 2", where R represents the distance of the object OBJ and c represents the speed of light. Furthermore, the phase difference Φ between the emitted transmitted light TL and the reflected light RL can also be used to calculate the distance between the object OBJ and the ToF sensor 100 using Equation 4.

[0113] [Equation 4]

[0114]

[0115] Here, f represents the modulation frequency, which is the frequency of the intensity of the transmitted light TL (or the frequency of the intensity of the reflected light RL).

[0116] As described above, the ToF sensor 100 according to the embodiment can use transmitted light TL emitted by the light source module 200 to obtain depth information about the object OBJ. Although Figure 5 The diagram shows a transmitted light TL with a sinusoidal waveform of intensity, but embodiments of the present invention are not limited thereto. For example, in an embodiment, the ToF sensor 100 may use transmitted light TL with various types of waveforms of intensity. Furthermore, the ToF sensor 100 may extract depth information based on, for example, the waveform of the transmitted light TL's intensity, the structure of depth pixels, etc.

[0117] Figure 12 An example of modulation and demodulation timing for a depth pixel with a four-tap structure is shown. The operation of a ToF sensor can be modified differently.

[0118] refer to Figure 12 It can output transmitted light TL from the light source synchronously with the signal provided from the controller 150. It can also generate first, second, third, and fourth demodulated signals DEM1, DEM2, DEM3, and DEM4 synchronously with the signal from the controller 150. The first demodulated signal DEM1 to the fourth demodulated signal DEM4 have phase differences of approximately 0 degrees, 90 degrees, 180 degrees, and 270 degrees, respectively. (Refer to the above...) Figure 11 As described, the four samples A0, A1, A2 and A3 of the reflected light RL can be sampled per cycle with phases of approximately 90 degrees, approximately 180 degrees, approximately 270 degrees and approximately 360 degrees, respectively.

[0119] Figure 12 An example is shown in which the phase of the first demodulated signal DEM1 is consistent with the phase of the transmitted light TL. As will be described below, the first demodulated signal DEM1 through the fourth demodulated signal DEM4 can be applied to the first demodulation transmission gate through the fourth demodulation transmission gate, respectively.

[0120] supply Figure 11 and Figure 12 This describes the principle of using a ToF sensor to measure and calculate the distance to an object, and embodiments of the present invention are not limited thereto. For example, the duty cycle of the transmitted light TL, as well as the number, phase difference, and duty cycle of the demodulated signal, can be varied.

[0121] Figure 13 This is a circuit diagram illustrating a depth pixel with a four-tap structure according to an embodiment of the present invention. Figure 14 This illustrates an embodiment of the concept according to the present invention. Figure 13An example illustration of a layout for depth pixels with a four-tap structure.

[0122] refer to Figure 13 and Figure 14 The depth pixel PX2 may include transistors TMA, TS1, and TT1 corresponding to the first tap TA, transistors TMB, TS1, and TT1 corresponding to the second tap TB, transistors TMC, TS2, and TT2 corresponding to the third tap TC, transistors TMD, TS2, and TT2 corresponding to the fourth tap TD, transistors TRS1, TRS2, TSF1, TSF2, TSL1, and TSL2 corresponding to the readout circuit, and common photogates CPG, overflow gates OG1 and OG2, and photodiode PD corresponding to the shared circuit.

[0123] Each of transistors TMA, TMB, TMC, TMD, TS1, TS2, TT1, TT2, TRS1, and TRS2 may include a gate disposed above a semiconductor substrate and source and drain regions disposed on either side of the gate in the semiconductor substrate. The gates of transistors TMA, TMB, TMC, TMD, TS1, TS2, TT1, TT2, TRS1, and TRS2 correspond to a first demodulation transmission gate TGA, a second demodulation transmission gate TGB, a third demodulation transmission gate TGC, a fourth demodulation transmission gate TGD, memory gates SG1 and SG2, FD transmission gates TG1 and TG2, and reset gates RG1 and RG2.

[0124] The photoelectric gate voltage VPG is applied to the common photoelectric gate CPG, the overflow gate voltage VOG is applied to overflow gates OG1 and OG2, the storage control signal SSG is applied to storage gates SG1 and SG2, the FD transfer control signal STG is applied to FD transfer gates TG1 and TG2, the reset signals SRG1 and SRG2 are applied to reset gates RG1 and RG2 respectively, and the select signals SEL1 and SEL2 are applied to the gates of select transistors TSL1 and TSL2 respectively. First, second, third, and fourth demodulation signals STGA, STGB, STGC, and STGD with different phases are applied to first, second, third, and fourth demodulation transfer gates TGA, TGB, TGC, and TGD respectively.

[0125] For reference Figure 10 As described, under the control of the controller 150, the row scanning circuit 130 can provide photoelectric gate voltage VPG, overflow gate voltage VOG, storage control signal SSG, FD transfer control signal STG, reset signals SRG1 and SRG2, selection signals SEL1 and SEL2, and demodulation signals STGA, STGB, STGC and STGD.

[0126] Storage gates SG1 and SG2 are one of the charge storage structures used to temporarily store the photoelectric charge transferred from the common grating CPG before transferring the photoelectric charge to the floating diffusion regions FDA, FDB, FDC, and FDD. In embodiments, the charge storage structure can be implemented using only storage gates SG1 and SG2. In embodiments, the charge storage structure can be implemented using storage gates SG1 and SG2 and storage diodes formed in the semiconductor substrate below storage gates SG1 and SG2. Using this charge storage structure, true correlated double sampling (CDS) can be performed, and noise in the readout signal can be reduced. According to embodiments, FD transfer gates TGI and TG2 and / or storage gates SG1 and SG2 can be omitted.

[0127] The charge stored in the floating diffusion regions FDA, FDB, FDC, and FDD can be provided as output signals VOUTA, VOUTB, VOUTC, and VOUTD using source follower transistors TSF1 and TSF2 and select transistors TSL1 and TSL2.

[0128] like Figure 14 As shown, a common photogate CPG can be positioned in the central region of the depth pixel PX2, and the demodulation transmission gates TGA, TGB, TGC, and TGD, as well as the overflow gates OG1 and OG2, can form a symmetrical structure about the common photogate CPG. The demodulation transmission gates TGA, TGB, TGC, and TGD are symmetrical about each line of the horizontal line HLX and the vertical line HLY, that is, symmetrical about the central CP of the depth pixel PX2. Similarly, the overflow gates OG1 and OG2 are symmetrical about each line of the horizontal line HLX and the vertical line HLY, that is, symmetrical about the central CP of the depth pixel PX2. This symmetrical structure reduces the deviation in the tap's operational characteristics and improves the sensing accuracy of the depth pixel PX2.

[0129] Figure 15 This illustrates an embodiment of the concept according to the present invention. Figure 13 Timing diagram of an example operation for a depth pixel with a four-tap structure.

[0130] refer to Figures 13 to 15During the integration period TINT, the photogate voltage VPG applied to the common photogate CPG can have a DC voltage level VDC that allows for the collection of photocharge, and the overflow gate voltage VOG applied to the overflow gates OG1 and OG2 can have a turn-off voltage level VOFF that prevents photocharge discharge. Additionally, during the integration period TINT, first to fourth demodulated signals STGA, STGB, STGC, and STGD of different phases are applied to first to fourth demodulated transmission gates TGA, TGB, TGC, and TGD, respectively. The phase of the first demodulated signal STGA can be synchronized with the phase of the transmitted light TL. In an embodiment, the phase difference between the first demodulated signal STGA and the second demodulated signal STGB can be approximately 90 degrees, the phase difference between the first demodulated signal STGA and the third demodulated signal STGC can be approximately 180 degrees, and the phase difference between the first demodulated signal STGA and the fourth demodulated signal STGD can be approximately 270 degrees. The method of measuring distance using demodulated signals of different phases can be compared with a reference... Figures 10 to 12 The methods described are the same.

[0131] During other time periods, such as the reset period TRST that initializes the depth pixel PX1 and the readout period TRD that measures the amount of photocharge collected by the common photogate CPG, the overflow gate voltage VOG can have a turn-on voltage level VON that allows the photocharge collected by the common photogate CPG to be discharged. Thus, a global shutter function can be achieved by using overflow gates OG1 and OG2 to discharge charge during periods other than the integration period TINT.

[0132] In an embodiment, such as Figure 15 As shown, the DC voltage level VDC of the photogate voltage VPG during the reset period TRST and readout period TRD can be approximately equal to the DC voltage level VDC during the integration period TINT. The DC voltage level VDC can be the voltage level between the high voltage level VH and the low voltage level VL of the demodulated signal. In the embodiment, as referenced... Figure 7 The second DC voltage level VDC' of the photogate voltage VPG during the reset period TRST and readout period TRD can be different from the first DC voltage level VDC during the integration period TINT. The first DC voltage level VDC during the integration period TINT can be a voltage level between the high voltage level VH and the low voltage level BL of the demodulated signal. During the reset period TRST and readout period TRD, overflow gates OG1 and OG2 are in the on state, and the second DC voltage level VDC' can be determined based on the potential distribution of the channel formed in the semiconductor substrate. Even if... Figure 7The second DC voltage level VDC' is shown to be higher than the first DC voltage level VDC, but embodiments of the present invention are not limited thereto. For example, in an embodiment, the second DC voltage level VDC' may be lower than the first DC voltage level VDC, depending on the potential distribution of the channel.

[0133] Figure 16 and Figure 17 This is a diagram illustrating an example of the structure of a shared floating diffusion region of depth pixels according to an embodiment of the present invention.

[0134] Besides part of the layout, Figure 16 The depth pixel PX3 is basically with a four-tap structure Figure 13 and Figure 14 The depth pixels PX2 are the same. For ease of explanation, further descriptions of the previously described components and technical aspects can be omitted.

[0135] In the depth pixel PX3, a common photoelectric gate CPG can be located in the central region, and the demodulation transmission gates TGA, TGB, TGC, and TGD, as well as the overflow gates OG1 and OG2, can form a symmetrical structure about the common photoelectric gate CPG. The demodulation transmission gates TGA, TGB, TGC, and TGD can be symmetrical about each line in the horizontal line HLX and the vertical line HLY. In other words, the first demodulation transmission gate TGA and the third demodulation transmission gate TGC can be symmetrical about the central CP of the depth pixel PX3, and the second demodulation gate TGB and the fourth demodulation gate TGD can be symmetrical about the central CP of the depth pixel PX3. Furthermore, the overflow gates OG1 and OG2 can be symmetrical about each line in the horizontal line HLX and the vertical line HLY, that is, symmetrical about the central CP of the depth pixel PX3. This symmetrical structure reduces the deviation in the tap's operational characteristics and improves the sensing accuracy of the depth pixel PX3.

[0136] like Figure 16 As shown, the first floating diffusion region FDA corresponding to the first tap TA and the second floating diffusion region FDB corresponding to the second tap TB can be electrically connected to each other via conductive path LN1, and the third floating diffusion region FDC corresponding to the third tap TC and the fourth floating diffusion region FDD corresponding to the fourth tap TD can be electrically connected to each other via conductive path LN2. Conductive paths LN1 and LN2 may include wires above the semiconductor substrate and vertical contacts such as vias.

[0137] In the case of depth pixel PX3, a demodulated signal with a first phase can be applied to a first demodulation transmission gate TGA and a second demodulation transmission gate TGB, and a demodulated signal with a second phase different from the first phase can be applied to a third demodulation transmission gate TGC and a fourth demodulation transmission gate TGD. In this way, the sensing sensitivity of the depth pixel can be improved by electrically connecting at least two of the multiple floating diffusion regions included in each depth pixel.

[0138] Figure 17 This shows four adjacent depth pixels PXa, PXb, PXc, and PXd in the horizontal direction HLX and the vertical direction HLY. Although Figure 17 For clarity, four depth pixels are shown in the illustration; however, according to an embodiment of the present invention, it is possible to... Figure 10 More pixels are repeatedly arranged in the pixel array 110.

[0139] refer to Figure 17 Four adjacent pixels PXa, PXb, PXc, and PXd can share a floating diffusion region. For example, a second demodulated signal can be applied to four taps adjacent to the floating diffusion region FDB and respectively included in the four adjacent pixels PXa, PXb, PXc, and PXd, and the photocharge collected by the four adjacent pixels PXa, PXb, PXc, and PXd can be pooled into the central floating diffusion region FDB. Thus, depending on the phase of the demodulated signal, the photocharge collected by each of the four adjacent depth pixels can be pooled into the floating diffusion regions FDA, FDB, FDC, and FDD, respectively. This shared floating diffusion region structure can improve the sensing sensitivity of the ToF sensor.

[0140] Figure 18A , Figure 18B , Figure 18C , Figure 19A , Figure 19B and 19C This is a diagram illustrating an example of the layout of depth pixels according to an embodiment of the present invention.

[0141] refer to Figure 18A , 18B And 18C, each of the depth pixels PX4, PX5 and PX6 with a four-tap structure may include a common photoelectric gate CPG, first demodulation transmission gates TGA to fourth demodulation transmission gates TGA, TGB, TGC and TGD corresponding to the first to fourth taps, and an overflow gate OG. For ease of explanation, further descriptions of the previously described components and techniques may be omitted.

[0142] The first to fourth demodulation transmission gates, TGA, TGB, TGC, and TGD, are symmetrical about each line in the horizontal line HLX and the vertical line HLY that pass through the center CP of each depth pixel. Additionally, the overflow gate OG is symmetrical about each line in the horizontal line HLX and the vertical line HLY. This symmetrical structure reduces the deviation in the operating characteristics of the first to fourth taps and improves the sensing accuracy of depth pixels PX4, PX5, and PX6.

[0143] like Figure 18A , 18B As shown in 18C, the shape of the common photoelectric gate CPG can be determined differently. Depending on the shape of the common photoelectric gate CPG, the first demodulation transmission gates to the fourth demodulation transmission gates TGA, TGB, TGC and TGD, as well as the overflow gate OG, can be arranged with a symmetrical structure.

[0144] refer to Figure 19A , 19B In the 19C, each of the depth pixels PX7, PX8, and PX9 with a dual-tap structure may include a common photoelectric gate CPG, a first demodulation transmission gate TGA and a second demodulation transmission gate TGB corresponding to the first and second taps, and an overflow gate OG. For ease of explanation, further descriptions of the previously described components and technical aspects may be omitted.

[0145] The first demodulation transmission gate (TGA) and the second demodulation transmission gate (TGB) can be symmetrical about each of the horizontal line HLX and the vertical line HLY passing through the center CP of each depth pixel, or symmetrical about the center CP. Additionally, the overflow gate (OG) can be symmetrical about each of the horizontal line HLX and the vertical line HLY. This symmetrical structure reduces the deviation in the operating characteristics of the first and second taps and improves the sensing accuracy of depth pixels PX7, PX8, and PX9.

[0146] like Figure 19A , 19B As shown in 19C, the shape of the common photogate CPG can be determined differently. Depending on the shape of the common photogate CPG, the first demodulation transmission gate TGA, the second demodulation transmission gate TGB, and the overflow gate OG can be arranged with a symmetrical structure.

[0147] Figure 20 This is a cross-sectional view showing a depth pixel according to an embodiment of the present invention. Figure 21A and 21B This illustrates an embodiment of the concept according to the present invention. Figure 20A perspective view of an example of a common photogate for depth pixels. For ease of explanation, further descriptions of the previously described elements and technical aspects may be omitted, and the structure of the common photogate CPG according to the embodiment is mainly described.

[0148] refer to Figure 20 , 21A And 21B, the depth pixel PX10 may include a common photoelectric gate CPG and demodulation transmission gates TGA and TGB with the above-described symmetrical structure.

[0149] The common photogate (CPG) may include a horizontal photogate (PPG) and at least one vertical photogate (ZPG). The horizontal photogate (PPG) may be disposed above the upper surface of the semiconductor substrate (SUB) and may extend in a plane substantially parallel to the upper surface of the semiconductor substrate (SUB). The vertical photogate (ZPG) may be connected to the lower surface of the horizontal photogate (PPG) and extends in a vertical direction Z substantially perpendicular to the upper surface of the semiconductor substrate (SUB). The vertical photogate (ZPG) may extend near the photodiode (PD). The vertical photogate (ZPG) may be disposed in a trench (TRC) formed in the upper portion of the semiconductor substrate (SUB). The trench (TRC) may be filled with at least one dielectric material.

[0150] In this way, the collection of photocharge can be enhanced by increasing the surface area of ​​the common photogate (CPG) and extending the vertical photogate (ZPG) near the photodiode (PD). For example, in... Figure 21B In the case of multiple vertical photogates ZPG shown, the electric field between the trench TRCs can be further enhanced to accelerate the collection of photocharge.

[0151] Figure 22 This is a cross-sectional view showing a depth pixel according to an embodiment of the present invention. Figure 23A and 23B This illustrates an embodiment of the concept according to the present invention. Figure 20 A perspective view of an example of a common photoelectric gate with depth pixels.

[0152] refer to Figure 22 , Figure 23A and Figure 23B The depth pixel PX11 may include a common photoelectric gate CPG with the above-described symmetrical structure, as well as demodulation transmission gates TGA and TGB.

[0153] The common photogate (CPG) may include at least one vertical photogate (ZPG). The vertical photogate ZPG may extend in a vertical direction Z, substantially perpendicular to the upper surface of the semiconductor substrate (SUB). The vertical photogate ZPG may extend near the photodiode (PD). The vertical photogate ZPG may be disposed in a trench TRC formed in the upper portion of the semiconductor substrate (SUB). Figure 20 Compared to the PX10's depth pixels, Figure 22 The depth pixel PX11 does not include the horizontal photogate PPG.

[0154] In such Figure 23B In the case of multiple vertical photogates ZPGs shown, the multiple vertical photogates ZPGs can be electrically connected via wires above the semiconductor substrate SUB and vertical contacts such as through holes.

[0155] Figures 24 to 27 This is a diagram illustrating an example of the layout of depth pixels according to an embodiment of the present invention.

[0156] Figure 24 Depth pixels PX21, PX22, PX23, and PX24 with a four-tap structure are shown, such that the common photogate CPG includes a horizontal photogate PPG and one or more vertical photogates ZPG. Figure 25 Depth pixels PX25, PX26, PX27, and PX28 with a dual-tap structure are shown, such that the common photogate CPG includes a horizontal photogate PPG and one or more vertical photogates ZPG.

[0157] Figure 26 The depth pixels PX31, PX32, and PX33 with a four-tap structure are shown, such that the common photogate CPG includes one or more vertical photogates ZPG but no horizontal photogates. Figure 27 The depth pixels PX34, PX35, and PX36 with a double-tap structure are shown, such that the common photogate CPG includes one or more vertical photogates ZPG but no horizontal photogates.

[0158] like Figures 24 to 27 As shown, the shape of the common photogate CPG can be determined differently. Depending on the shape of the common photogate CPG, the first demodulation transmission gates to the fourth demodulation transmission gates TGA, TGB, TGC and TGD, the overflow gate OG0, and different numbers of vertical photogates ZPG can be configured to have a symmetrical structure.

[0159] Figure 28 This is a cross-sectional view showing a depth pixel according to an embodiment of the present invention. Figure 29 This illustrates an embodiment of the concept according to the present invention. Figure 28 A perspective view of an example of a common photogate for depth pixels. For ease of explanation, further descriptions of the previously described components and technical aspects may be omitted, and the structure of the common photogate (CPG) may be described primarily.

[0160] refer to Figure 28 and Figure 29The depth pixel PX41 may include a common photoelectric gate CPG and demodulation transmission gates TGA and TGB with the above-mentioned symmetrical structure.

[0161] The common photogate (CPG) may include a horizontal photogate (PPG). The horizontal photogate (PPG) may be disposed above the upper surface of the semiconductor substrate (SUB), and the horizontal photogate (PPG) may extend in a plane substantially parallel to the upper surface of the semiconductor substrate (SUB).

[0162] like Figure 28 and 29 As shown, the lower surface of the horizontal photogate PPG can have a corrugated CRSTR to induce light reflection and scattering. A corrugated CRSTR can refer to a shape comprising multiple ridges (or protrusions) and grooves (or recesses). For example, a corrugated CRSTR can include multiple ridges (or protrusions) separated from each other by multiple grooves (or recesses). The corrugated CRSTR will be described in further detail below. Using a corrugated CRSTR, light can reside in the semiconductor substrate SUB for a longer period, and the sensing sensitivity of the depth pixel PX41 can be improved.

[0163] Figure 30A , Figure 30B , Figure 30C , Figure 31A , Figure 31B , Figure 31C and Figure 32 This is a cross-sectional view showing a depth pixel according to an embodiment of the present invention. Figure 30A , Figure 30B , Figure 30C , Figure 31A , Figure 31B , Figure 31C and Figure 32 The structure corresponding to backside illumination (BSI) is shown, such that light is incident through the lower surface 12 of the semiconductor substrate SUB.

[0164] refer to Figure 30A , Figure 30B , Figure 30C , Figure 31A , Figure 31B , Figure 31C Each of the depth pixels PX51, PX52, PX53, PX54, PX55 and PX56 may include a common opto-gate CPG configured on the upper surface 11 adjacent to the semiconductor substrate SUB, and a plurality of demodulation transmission gates TGA and TGB having the above-described symmetrical structure.

[0165] like Figure 30A , Figure 30B , Figure 30C , Figure 31A , Figure 31B , Figure 31C As shown, each depth pixel in depth pixels PX51–PX56 may include an anti-reflective layer RFL, a planarization layer PNL, and a microlens MLN. The anti-reflective layer RFL may be positioned adjacent to the lower surface 12 of the semiconductor substrate SUB, through which light is incident. The anti-reflective layer RFL can reflect light scattered and / or reflected within the semiconductor substrate SUB, thus improving sensing sensitivity by allowing light to reside in the semiconductor substrate SUB for a longer period. For example, the anti-reflective layer RFL may have a stacked structure of a fixed charge layer and oxides. The anti-reflective layer RFL may be a high-dielectric-constant insulating film and can be fabricated using an atomic layer deposition (ALD) process. For example, the anti-reflective layer RFL can be implemented using hafnium oxide, aluminum oxide, titanium oxide, strontium titanium oxide, etc.

[0166] The planarization layer PNL can be set as the lower surface adjacent to the antireflective layer RFL. For example, the planarization layer PNL can be implemented using silicon oxide, silicon nitride, silicon oxynitride, etc.

[0167] The microlens MLN can be positioned adjacent to the lower surface of the planarization layer PNL. Light focused by the microlens can be concentrated onto the photodiode PD. For example, the microlens MLN can be implemented using styrene resin, acrylate resin, silicone resin, etc.

[0168] Additionally, each of the depth pixels PX51 to PX56 may include a pixel isolation structure extending in a vertical direction Z substantially perpendicular to the lower surface 12 of the semiconductor substrate SUB, and disposed in the boundary region of the depth pixel to block light from other depth pixels. The pixel isolation structure can block light from other depth pixels.

[0169] In an embodiment, such as Figure 30A As shown, the depth pixel PX51 may include a back-side isolation structure PSSTR1 extending in the vertical direction Z from the lower surface 12 of the semiconductor substrate SUB. A trench TRC1 may be formed to a predetermined depth, and a sidewall SWL1 may be formed in the trench TRC1. The sidewall SWL1 may block light from penetrating to adjacent pixels. For example, the sidewall SWL1 may be implemented using at least one material similar to the material of the anti-reflective layer RFL. The trench TRC1 may be filled with at least one dielectric material.

[0170] In an embodiment, such as Figure 30B As shown, the depth pixel PX52 may include a front isolation structure PSSTR2 extending in the vertical direction Z from the upper surface 11 of the semiconductor substrate SUB. The front isolation structure PSSTR2 includes a trench TRC2 and a sidewall SWL2. In an embodiment, as... Figure 30CAs shown, the depth pixel PX53 may include a fully isolated structure PSSTR3 extending from the upper surface 11 to the lower surface 12 of the semiconductor substrate SUB in the vertical direction Z. The fully isolated structure PSSTR3 includes a trench TRC3 and a sidewall SWL3.

[0171] like Figures 31A to 31C As shown, each of the depth pixels PX54 to PX56 may include a corrugated structure set on the upper surface of the adjacent anti-reflection layer RFL to cause light reflection and scattering.

[0172] like Figure 31A As shown, the corrugated structure CRSTR1 may include a single ridge CR formed in the groove TRC. Figure 31B As shown, the corrugated structure CRSTR2 may include multiple ridges CR1, CR2, and CR3. According to an embodiment, as... Figure 31C As shown, the corrugated structure CRSTR3 may include multiple ridges CR1 to CR3 with different depths from each other. Ribs CR and CR1 to CR3 may also be referred to as protrusions.

[0173] refer to Figure 32 The depth pixel PX61 may include a polarization structure PLSTR, which is configured to selectively allow light along a specific polarization axis to pass through adjacent to the lower surface of the antireflective layer RFL. The polarization structure may be a stacked structure of a metallic pattern PTN1 and a dielectric pattern PTN2.

[0174] Figure 33A and Figure 33B This illustrates an embodiment of the concept according to the present invention. Figure 32 An example illustration of the polarization structure of a depth pixel.

[0175] refer to Figure 33A Four adjacent depth pixels PXa, PXb, PXc, and PXd in the horizontal direction HLX and the vertical direction HLY can each include a polarization structure, causing the polarization pattern PLPTN to be rotated sequentially by approximately 90 degrees. (Reference) Figure 33B In an embodiment, some of the four adjacent depth pixels PXa, PXb, PXc and PXd may include a polarization pattern PLPTN, while the other depth pixels PXb and PXc may not include a polarization pattern PLPTN.

[0176] Figure 34 This is a block diagram illustrating a computing system including a ToF sensor according to an embodiment of the present invention.

[0177] refer to Figure 34The computing system 1000 includes a processor 1010, a memory device 1020, a storage device 1030, an input / output device 1040, a power supply 1050, and / or a ToF sensor 100. In embodiments, the computing system 1000 may also include ports for communicating with electronic devices, such as video cards, sound cards, memory cards, USB devices, etc.

[0178] Processor 1010 can perform specific calculations and / or tasks. For example, processor 1010 can be a microprocessor, a central processing unit (CPU), a digital signal processor, etc. Processor 1010 can communicate with memory device 1020, storage device 1030 and input / output device 1040 via address bus, control bus and / or data bus.

[0179] The processor 1010 can be coupled to an expansion bus, such as a peripheral component interconnect (PCI) bus. The memory device 1020 can store data used to operate the computing system 1000.

[0180] For example, storage device 1020 can be implemented using dynamic random access memory (DRAM), mobile DRAM, static random access memory (SRAM), phase-change random access memory (PRAM), resistive random access memory (RRAM), nanofloating gate memory (NFGM), polymer random access memory (PoRAM), magnetic random access memory (MRAM), ferroelectric random access memory (FRAM), etc. Storage device 1030 may include, for example, a solid-state drive, hard disk drive, CD-ROM, etc. Input / output device 1040 may include input devices such as a keyboard, mouse, keypad, etc., and output devices such as a printer, display device, etc. Power supply 1050 can supply power to computing device 1000.

[0181] The ToF sensor 100 can be coupled to the processor 1010 via a bus or other communication link. As described above, according to embodiments of the present invention, the ToF sensor 100 may include at least one depth pixel having a symmetrical structure centered on a common photogate. The ToF sensor 100 may be integrated with the processor 1010 on the same chip, or the ToF sensor 100 and the processor 1010 may be integrated on separate chips.

[0182] Figure 35 This illustrates an embodiment of the concept according to the present invention. Figure 34 A block diagram illustrating examples of interfaces used in computing systems.

[0183] refer to Figure 35The computing system 1100 may employ or support a MIPI interface and may include an application processor 1110, a ToF sensor 1140, and a display device 1150. The CSI host 1112 of the application processor 1110 may perform serial communication with the CSI device 1141 of the ToF sensor 1140 using a Camera Serial Interface (CSI). In an embodiment, the CSI host 1112 may include a deserializer (DES), and the CSI device 1141 may include a serializer (SER). The DSI host 1111 of the application processor 1110 may perform serial communication with the DSI device 1151 of the display device 1150 using a Display Serial Interface (DSI). In an embodiment, the DSI host 1111 may include a serializer (SER), and the DSI device 1151 may include a deserializer (DES).

[0184] The computing system 1100 may also include a radio frequency (RF) chip 1160, which may include a physical layer PHY 1161 and a DigRF slave controller 1162. The physical layer PHY 1113 of the application processor 1110 may use MIPIDigRF to perform data transmission with the physical layer PHY 1161 of the RF chip 1160. The PHY 1113 of the application processor 1110 may interact (or alternatively, communicate) with the DigRF master controller 1114 to control data transmission with the PHY 1161 of the RF chip 1160.

[0185] The computing system 1100 may also include a Global Positioning System (GPS) 1120, a storage device 1170, a microphone 1180, DRAM 1185, and / or a speaker 1190. The computing system 1100 can communicate with external devices using an Ultra-Wideband (UWB) communication interface 1210, a Wireless Local Area Network (WLAN) communication interface 1220, a World Microwave Access Interoperability (WIMAX) communication interface 1230, etc. However, the embodiments are not limited to this. Figure 34 and 35 The configuration or interface of the computing systems 1000 and 1100 shown.

[0186] As described above, the depth pixel according to the present invention can reduce the size and power consumption of the ToF sensor including the depth pixel by applying a common photogate. Furthermore, the depth pixel according to the embodiment can improve sensing accuracy and sensitivity through symmetrical and modified structures of the common photogate, thereby improving the performance of the ToF sensor including the depth pixel.

[0187] Embodiments of this invention can be applied to any device and system including a ToF sensor. For example, embodiments of this invention can be applied to various systems such as mobile phones, smartphones, personal digital assistants (PDAs), portable multimedia players (PMPs), digital cameras, video recorders, personal computers (PCs), server computers, workstations, laptops, digital TVs, set-top boxes, portable game consoles, navigation systems, wearable devices, Internet of Things (IoT) devices, Internet of Everything (IoE) devices, e-books, virtual reality (VR) devices, augmented reality (AR) devices, etc.

[0188] As is customary in the field of this invention, embodiments are described and illustrated in the accompanying drawings in terms of functional blocks, units, and / or modules. Those skilled in the art will understand that these blocks, units, and / or modules are physically implemented by electronic (or optical) circuitry such as logic circuits, discrete components, microprocessors, hardwired circuitry, memory elements, wiring connections, etc., wherein said electronic (or optical) circuitry can be formed using semiconductor-based manufacturing techniques or other manufacturing techniques. Where blocks, units, and / or modules are implemented by microprocessors, etc., they can be programmed using software (e.g., microcode) to perform the various functions discussed herein, and may optionally be driven by firmware and / or software. Alternatively, each block, unit, and / or module may be implemented by dedicated hardware, or implemented as a combination of dedicated hardware performing some functions and processors performing other functions (e.g., one or more programmed microprocessors and associated circuitry).

[0189] Although the inventive concept has been specifically shown and described with reference to embodiments thereof, those skilled in the art will understand that various changes in form and detail may be made without departing from the spirit and scope of the inventive concept as defined by the appended claims.

Claims

1. A depth pixel of a time-of-flight (ToF) sensor, the depth pixel comprising: A common photogate is located in the central region of the depth pixel; Multiple floating diffusion areas are set in the peripheral area surrounding the central area; Multiple demodulation transmission gates are disposed in the peripheral region and configured to transfer the photocharge collected by the common photogate to the multiple floating diffusion regions. Wherein, the plurality of demodulation transmission gates are symmetrical about each of the horizontal and vertical lines passing through the center of the depth pixel and perpendicular to each other; and Multiple overflow gates are disposed in the peripheral region and configured to discharge the photocharge collected by the common photoelectric gate. The plurality of overflow gates are symmetrical about each of the horizontal and vertical lines. The public photoelectric gate includes: At least one vertical photogate extends in a vertical direction perpendicular to the upper surface of the semiconductor substrate. The vertical photogate is disposed in a trench formed in the upper part of the semiconductor substrate, such that a portion of the vertical photogate is disposed below the upper surface of the semiconductor substrate.

2. The depth pixel according to claim 1, wherein, The photogate voltage applied to the common photogate has a DC voltage level that allows the photocharge to be collected during the integration period, the overflow gate voltage applied to the plurality of overflow gates has a turn-off voltage level that prevents the discharge of the photocharge during the integration period, and a plurality of demodulated signals of different phases are applied to the plurality of demodulated transmission gates during the integration period.

3. The depth pixel according to claim 2, wherein, The overflow gate voltage has an on-state voltage level that discharges the photocharge collected by the common photogate during the reset and readout periods, wherein the depth pixel is initialized during the reset period and the amount of photocharge collected by the common photogate is measured during the readout period.

4. The depth pixel according to claim 2, wherein, The DC voltage level of the photogate voltage during the reset period that initializes the depth pixel and the readout period that measures the amount of photocharge collected by the common photogate is equal to the DC voltage level during the integration period.

5. The depth pixel according to claim 2, wherein, The DC voltage level of the photogate voltage during the reset period that initializes the depth pixel and the readout period that measures the amount of photocharge collected by the common photogate is different from the DC voltage level during the integration period.

6. The depth pixel according to claim 1, wherein, The public photoelectric gate includes: A horizontal photogate is disposed above the upper surface of the semiconductor substrate. The horizontal photogate extends in a plane parallel to the upper surface of the semiconductor substrate.

7. The depth pixel according to claim 6, wherein, The lower surface of the horizontal photogate has a wavy shape that causes light reflection and scattering.

8. The depth pixel according to claim 1, wherein, The public photoelectric gate includes: A horizontal photogate is disposed above the upper surface of the semiconductor substrate. The horizontal photogate extends in a plane parallel to the upper surface of the semiconductor substrate. The at least one vertical photoelectric gate is connected to the lower surface of the horizontal photoelectric gate.

9. The depth pixel according to claim 1, further comprising: Multiple charge storage structures are respectively disposed in the peripheral region between the multiple floating diffusion regions and the multiple demodulation transmission gates, and are configured to temporarily store the photocharge before transmitting the photocharge collected by the common photogate to the multiple floating diffusion regions.

10. The depth pixel according to claim 1, further comprising: An anti-reflective layer is configured adjacent to the lower surface of the semiconductor substrate, wherein light is incident through the lower surface of the semiconductor substrate; A planarization layer is configured to be adjacent to the lower surface of the antireflective layer; Microlenses are configured adjacent to the lower surface of the planarization layer; and A pixel isolation structure extends in the vertical direction perpendicular to the lower surface of the semiconductor substrate and is disposed in the boundary region of the depth pixel. The pixel isolation structure is configured to block light from other depth pixels.

11. The depth pixel according to claim 10, further comprising: A corrugated structure is provided adjacent to the upper surface of the antireflective layer and is configured to cause light reflection and scattering.

12. The depth pixel according to claim 10, further comprising: A polarization structure is provided adjacent to the lower surface of the antireflective layer and is configured to selectively allow light along a specific polarization axis to pass through.

13. The depth pixel according to claim 1, wherein, The depth pixel has a dual-tap structure, such that the plurality of demodulation transmission gates include a first demodulation transmission gate and a second demodulation transmission gate that are centrally symmetrical about the depth pixel. During the integration period, a first demodulated signal is applied to the first demodulation transmission gate, and a second demodulated signal having a 180-degree phase difference with the first demodulated signal is applied to the second demodulation transmission gate.

14. The depth pixel according to claim 1, wherein, The depth pixel has a four-tap structure, such that the plurality of demodulation transmission gates include a first demodulation transmission gate, a second demodulation transmission gate, a third demodulation transmission gate, and a fourth demodulation transmission gate. The first demodulation transmission gate and the third demodulation transmission gate are symmetrical about the center of the depth pixel, and the second demodulation transmission gate and the fourth demodulation transmission gate are also symmetrical about the center of the depth pixel. During the integration period, a first demodulated signal is applied to the first demodulation transmission gate, a second demodulated signal with a 90-degree phase difference relative to the first demodulated signal is applied to the second demodulation transmission gate, a third demodulated signal with a 180-degree phase difference relative to the first demodulated signal is applied to the third demodulation transmission gate, and a fourth demodulated signal with a 270-degree phase difference relative to the first demodulated signal is applied to the fourth demodulation transmission gate.

15. The depth pixel according to claim 1, wherein, At least two of the plurality of floating diffusion regions are electrically connected to each other.

16. A time-of-flight (ToF) sensor, comprising: The light source is configured to illuminate the object with transmitted light; A pixel array, including one or more depth pixels, the one or more depth pixels being configured to provide information about the distance to the object based on reflected light, the reflected light being the transmitted light reflected by the object; as well as The controller is configured to control the light source and the pixel array. The depth pixels include: A common photogate is located in the central region of the depth pixel; Multiple floating diffusion areas are set in the peripheral area surrounding the central area; Multiple demodulation transmission gates are disposed in the peripheral region and configured to transfer the photocharge collected by the common photogate to the multiple floating diffusion regions. Wherein, the plurality of demodulation transmission gates are symmetrical about each of the horizontal and vertical lines passing through the center of the depth pixel and perpendicular to each other; and Multiple overflow gates are disposed in the peripheral region and configured to discharge the photocharge collected by the common photoelectric gate. The plurality of overflow gates are symmetrical about each of the horizontal and vertical lines. The public photoelectric gate includes: At least one vertical photogate extends in a vertical direction perpendicular to the upper surface of the semiconductor substrate. The vertical photogate is disposed in a trench formed in the upper part of the semiconductor substrate, such that a portion of the vertical photogate is disposed below the upper surface of the semiconductor substrate.

17. The ToF sensor according to claim 16, wherein, The depth pixel is one of four adjacent depth pixels, and the four adjacent depth pixels share a floating diffusion region.

18. A depth pixel of a time-of-flight (ToF) sensor, the depth pixel comprising: A common photoelectric gate is located in the central region of the depth pixel. The common photogate includes at least one vertical photogate extending in a vertical direction perpendicular to the upper surface of the semiconductor substrate, and the at least one vertical photogate is disposed in a trench formed in the upper part of the semiconductor substrate, such that a portion of the vertical photogate is disposed below the upper surface of the semiconductor substrate. Multiple floating diffusion areas are set in the peripheral area surrounding the central area; Multiple demodulation transmission gates are disposed in the peripheral region and configured to transfer the photocharge collected by the common photogate to the multiple floating diffusion regions; and Multiple overflow gates are disposed in the peripheral area and configured to discharge the photocharge collected by the common photoelectric gate.

19. The depth pixel according to claim 18, wherein, The plurality of demodulation transmission gates are symmetrical about each of the horizontal and vertical lines that pass through the center of the depth pixel and are perpendicular to each other, and the plurality of overflow gates are symmetrical about each of the horizontal and vertical lines.

Images