Substrate voltage modulation type image sensor pixel unit and array, and operation method

Abstract

The application provides a substrate voltage modulation type image sensor pixel unit, namely array, and an operation method. The pixel unit comprises a field effect tube and a triode, the doping type of the substrate of the field effect tube is the same as the doping type of the base of the triode, but is opposite to the doping type of the source and the drain of the field effect tube; the substrate of the field effect tube is connected with the base of the triode, the emitter of the triode is connected with one of the source and the drain of the field effect tube as the source of the image element, the collector of the triode is connected with the other of the source and the drain of the field effect tube as the drain of the image element, and the gate of the field effect tube is connected with an external voltage as the gate of the image element. The image sensor provided by the application can be applied to submicron pixels, has low dark current, low crosstalk, high signal-to-noise ratio, and the size of the image element can be reduced to 9F 2 and other characteristics.

Description

Technical Field

[0001] This invention relates to the field of photodetectors, and more particularly to the basic principles, operating methods, and device structures of a substrate voltage modulation image sensor pixel unit and pixel array with high integration density, high linearity, high signal-to-noise ratio, and low crosstalk. Background Technology

[0002] Photodetectors are widely used in military, medical, automotive, and mobile device fields. As the performance requirements of image sensors increase in many fields, the optimization and iteration of photodetectors basically follow the characteristics of "Moore's Law", namely, the reduction of the size of a single pixel unit and the improvement of the pixel integration of a single chip.

[0003] Currently, the mainstream photodetectors are charge-coupled devices (CCDs) and CMOS image sensors (CIS). The basic photosensitive unit of a CCD consists of multiple MOS capacitors connected in series. By applying appropriate voltages to the gates of adjacent MOS capacitors, the functions of photoelectric charge collection, pixel isolation, and charge transfer are achieved. Ultimately, the signal charge in the series-connected MOS capacitors is transferred to the readout node stage by stage, realizing the quantization and reset of the photogenerated signal. However, as pixel size shrinks, the gate control capability of the MOS capacitors in a CCD weakens, making it difficult to build potential barriers between MOS capacitors by applying different voltages, thus failing to achieve signal charge isolation. Furthermore, since CCD readout requires all the charge from each stage to be transferred to the readout node, the transfer efficiency limits the integration scale of CCDs. Therefore, current CCD technology is mostly used in scenarios where high imaging resolution is not required, but high dynamic range and signal-to-noise ratio are demanded. Currently, CIS (Computer Image Sensor) systems all employ an active pixel sensor (APS) structure. The photosensitive portion of the pixel is a photodiode. Compared to CCDs, which require multiple photosensitive units to share a single readout circuit, CIS can provide each photodiode with a readout module centered around a source follower (SF), thus avoiding excessive charge transfer. In 2022, Samsung reduced the size of a single CIS pixel to 600nm using vertical transfer gate technology and achieved access to each pixel by using multiple photodiodes sharing a readout module. However, the irregular structure of image sensors composed of CIS places significant pressure on the internal interconnects and photolithography of the device area, making pixel size reduction increasingly difficult.

[0004] In addition to the above, single-transistor or dual-transistor structures are also used to implement the necessary pixel functions. These structures are simple and highly periodic, and can be combined with advanced process technologies to further reduce pixel size. Patent CN101807547A discloses an imaging method using substrate hot electron injection as the core mechanism and a standard floating gate device as a single pixel. From the perspective of layout and process implementation, this imaging device offers the most ideal reduction in size. However, because the storage and readout of optical signals require a programming mechanism, the quantum efficiency is too low, making it unsuitable for imaging under conventional lighting conditions. Patent CN201610592997.3 describes a dual-transistor photodetector that collects photoelectrons in its photosensitive area and then changes the threshold of its readout tube through floating gate coupling to achieve signal reading. The imaging principle of this photodetector is similar to that of CIS, while also possessing the advantage of a simple single-pixel structure. Considering the isolation between pixels and the isolation between the photosensitive area and the readout area within a pixel, the minimum single-pixel size can be reduced to 16F. 2 (F represents the feature size of the process). Furthermore, patent CN108493202A employs an ultra-thin box and body (UTBB) structure as an image sensor solution. This technology has advantages in pixel reduction; however, because the operating state is controlled by the transistor source and drain, and reset requires substrate voltage, image sensors composed of this device as pixels cannot achieve rolling shutter (RS) exposure. Moreover, reset mainly relies on carrier recombination, resulting in low frame rates and high crosstalk.

[0005] The principle of charge modulation device (CMD) image sensors was mentioned as early as 1991, and chip imaging was realized in 2007. However, the imaging device used required two wells for injection to achieve pixel isolation and reset. First, simply using doping to achieve isolation limited the minimum pixel size to the micrometer level. Second, the doped region at the bottom of the pixel used for reset continuously lost photogenerated signals, making this pixel structure only suitable for front-side illumination (FSI) with very low photosensitivity. Summary of the Invention

[0006] In view of the above, the present invention provides a substrate voltage modulation type image sensor pixel unit and its array, and an operation method, which can be applied to image sensors with submicron pixels.

[0007] The technical solution adopted by the pixel unit of this invention is as follows:

[0008] A pixel unit of a substrate voltage modulation image sensor includes a field-effect transistor (FET) and a transistor. The doping type of the FET substrate is the same as that of the base of the transistor, but opposite to that of the source and drain of the FET. The FET substrate is connected to the base of the transistor. The emitter of the transistor is connected to one of the source and drain of the FET, serving as the pixel source. The collector of the transistor is connected to the other of the source and drain of the FET, serving as the pixel drain. An external voltage is applied to the gate of the FET, serving as the pixel gate.

[0009] Furthermore, the transistor is a parasitic transistor, the field-effect transistor substrate serves as the base of the transistor, one of the source and drain of the field-effect transistor serves as the collector of the transistor, and the other of the source and drain of the field-effect transistor serves as the emitter of the transistor.

[0010] Furthermore, the field-effect transistor includes a series structure composed of an address field-effect transistor and a state field-effect transistor. The address field-effect transistor is used to sense photogenerated carriers, and the state field-effect transistor is used for selection. The substrates of both field-effect transistors are connected to the base of the transistor. The source of the address field-effect transistor is connected to one of the emitter and collector of the transistor, serving as the pixel source. The drain of the state field-effect transistor is connected to the other of the emitter and collector of the transistor, serving as the pixel drain. The drain of the address field-effect transistor is connected to the source of the state field-effect transistor. The gate of the address field-effect transistor serves as the pixel gate, and the gate of the state field-effect transistor serves as the pixel state gate.

[0011] This invention also provides an operation method for the pixel unit of the above-mentioned substrate voltage modulation image sensor. This operation method involves the base of the transistor collecting photogenerated carriers and resetting the transistor in conjunction with its emitter and collector. The field-effect transistor reads out the pixel signal through the modulation effect of the substrate voltage. The specific steps are as follows:

[0012] Reset of photogenerated carriers: When a bias voltage is applied to the emitter and collector of the transistor, the majority carriers in the floating base of the transistor are partially discharged, and the emitter and collector of the transistor return to their normal state of near zero bias. Due to the unidirectional conductivity of the two diodes in the transistor, the discharged base majority carriers cannot be replenished from the electrodes, thus completing the reset of photogenerated carriers.

[0013] Exposure and collection of photogenerated carriers: After the base of the transistor is reset, it is in a non-equilibrium state. When exposed to light, one type of carrier in the electron-hole pairs generated is stored as the majority carrier in the base region in the PN junction capacitance formed by the base, emitter, and collector. The other type of carrier flows away from the emitter and collector, thus completing the collection of photogenerated carriers.

[0014] Optical signal readout: After the transistor collects photogenerated carriers, the potential in the region changes accordingly. At the same time, the substrate voltage of the field-effect transistor is equal to the base voltage of the transistor. Therefore, the substrate voltage of the field-effect transistor is related to the number of photogenerated carriers collected. By applying a voltage to the gate of the field-effect transistor and connecting a corresponding load to the source or drain of the field-effect transistor, the number of photogenerated carriers is characterized by the voltage or current at the output terminal of the field-effect transistor, thus completing the optical signal readout.

[0015] Furthermore, when the field-effect transistor includes a series structure composed of an address field-effect transistor and a state field-effect transistor, the state field-effect transistor is used to sense photogenerated carriers, and the address field-effect transistor is used for selection; during the exposure and photogenerated carrier collection process, the address field-effect transistor is turned off; during the readout of the optical signal, both the address field-effect transistor and the state field-effect transistor of the selected pixel are turned on.

[0016] Furthermore, the plurality of pixel units are arranged in an array, wherein the pixel gates of the pixel units in the same row are connected to form the gating word line of the array; the pixel source lines of the pixel units in the same row are connected to form the reset word line of the array; or, the pixel sources of the pixel units in the odd-numbered columns of the same row are connected to form the first reset word line of the array, and the pixel sources of the pixel units in the even-numbered columns of the same row are connected to form the second reset word line of the array; the pixel drains of the pixel units in the same column are connected to form the readout bit line of the array; when the field-effect transistor includes a series structure composed of an address field-effect transistor and a state field-effect transistor, the pixel drains of the pixel units in the same column are connected to form the readout bit line of the array; the pixel state gates of the pixel units in the same row are connected to form the state word line of the array.

[0017] The present invention also provides a device for a pixel unit of a substrate voltage modulation image sensor, the device comprising the pixel unit, a substrate, a pixel fully isolated structure and a field-effect transistor, wherein the pixel fully isolated structure divides the substrate into multiple independent regions, and each independent region is the substrate of the pixel unit.

[0018] Furthermore, the field-effect transistor includes a single bulk silicon transistor, and the pixel fully isolated structure includes a deep trench isolation structure penetrating the substrate in the vertical direction. The deep trench isolation structure includes: a silicon oxide filled structure, or a silicon oxide / air gap composite layer filled structure, or a silicon oxide / silicon nitride / silicon oxide composite layer filled structure.

[0019] Furthermore, the field-effect transistor includes a gate ring transistor and a vertical gate transistor. One of the source and drain of the gate ring transistor is located at the center of the gate ring, and the other is located at the periphery of the gate ring and in contact with the pixel fully isolated structure. The vertical gate transistor includes the pixel fully isolated structure, wherein the pixel fully isolated structure includes a silicon oxide / polycrystalline silicon composite layer filling structure or a silicon oxide / amorphous silicon composite layer filling structure. The pixel source and pixel drain are both located on the front side of the substrate, or they are respectively located on the front and back sides of the substrate.

[0020] Furthermore, a first doped material layer and a second doped material layer are respectively disposed on the front and back sides of the substrate of the pixel unit. The doping type of the first doped material layer is the same as that of the second doped material layer, and opposite to that of the independent substrate. The pixel fully isolated structure includes a silicon oxide / polycrystalline silicon composite layer filling structure or a silicon oxide / amorphous silicon composite layer filling structure. The pixel fully isolated structure includes at least two layers of the silicon oxide / polycrystalline silicon or silicon oxide / amorphous silicon repeating composite layer filling structure along the normal direction of the plane of the independent substrate.

[0021] Compared to existing image sensors, the advantages of this invention are:

[0022] (1) It can realize all the functions of a pixel with a single transistor and achieve excellent performance in important indicators such as dark current, dynamic range, signal-to-noise ratio, and frame rate.

[0023] (2) The substrate voltage modulation image sensor of the present invention adopts pixel full isolation technology and is compatible with back side illumination (BSI) scheme, which has significant advantages in crosstalk and quantum efficiency.

[0024] (3) More importantly, the image sensor of this invention has a simple pixel unit layout structure and strong periodicity of the pixel array, which is more conducive to improving the integration density. Combined with the existing capacitive deep trench isolation (CDTI) technology, the size of a single pixel can be reduced to 9F. 2 . Attached Figure Description

[0025] Figure 1 This is a basic schematic diagram of the pixel unit circuit of a substrate voltage modulation image sensor.

[0026] Figure 2 Schematic diagram of a dual-transistor pixel unit for a substrate voltage modulation image sensor;

[0027] Figure 3 The single-pixel operating timing of a substrate voltage modulation image sensor under readout conditions via a ramp sweep method;

[0028] Figure 4 The substrate voltage modulation image sensor reads out the energy band diagrams of various operating states under different conditions by using a ramp sweep method;

[0029] Figure 5 The single-pixel operating timing of a substrate voltage modulation image sensor under source follower readout conditions;

[0030] Figure 6 The energy band diagrams of various operating states of a substrate voltage modulation image sensor are read out using a source follower method.

[0031] Figure 7 This describes the arrangement and connection method of the pixel array in a substrate voltage modulation image sensor.

[0032] Figure 8 This is a timing diagram of the rolling shutter exposure of the pixel array of a substrate voltage modulation image sensor.

[0033] Figure 9 This is a timing diagram of the rolling shutter exposure in dual sampling mode of the pixel array of a substrate voltage modulation image sensor.

[0034] Figure 10 The arrangement and connection method of the pixel array of a substrate voltage modulation image sensor with dual reset word lines;

[0035] Figure 11 A timing diagram of rolling shutter exposure for a pixel array of a substrate voltage modulation image sensor with dual reset word lines;

[0036] Figure 12 This is the basic device structure of the pixel unit in a substrate voltage modulation image sensor.

[0037] Figure 13 The pixel unit device structure of a substrate voltage modulation image sensor that uses parasitic transistor photosensitive technology;

[0038] Figure 14 This is a substrate voltage modulation image sensor pixel unit device structure that includes a parasitic transistor, a gate-around transistor, and a vertical gate.

[0039] Figure 15 It is a substrate voltage modulation image sensor pixel unit device structure including a parasitic transistor, a gate-around transistor, a vertical gate, and a back-side source-drain;

[0040] Figure 16 This is a pixel unit device structure for a substrate voltage modulation image sensor with an extreme size, including a parasitic transistor, a double-layer vertical gate, and a back-side source / drain.

[0041] Figure 17 for Figure 16 The diagram shows a horizontal cross-section of the device structure at point T.

[0042] Figure 18 for Figure 16 The image shows a horizontal cross-section of the device's pixel structure at point B.

[0043] Figure 19 for Figure 17 The device structure shown is a process flow diagram along AA'.

[0044] Figure 20 for Figure 17 The device structure shown is a process flow diagram along BB'. Detailed Implementation

[0045] The image sensor pixel unit of this invention is, in principle, composed of a transistor and a field-effect transistor connected in parallel. The transistor is used for light signal acquisition and reset, while the field-effect transistor is used for sensing signal charge for reading. Considering that the pixel array needs to possess the most basic rolling shutter exposure function for imaging, this embodiment provides two connection methods for the image sensor pixel array and corresponding operation methods. Furthermore, comprehensively considering the advantages of the image sensor and the current technological level, the embodiment discloses a variety of optional device structures to adapt to fabrication under different process conditions.

[0046] The basic principle of the pixel unit of the substrate voltage modulation image sensor provided in this embodiment is as follows: Figure 1 As shown, a single pixel consists of an N-type doped field-effect transistor (NMOS) and a P-type doped transistor (NPN). The source of the NMOS is connected to the emitter of the NPN, and is referred to as the pixel source; the drain of the NMOS is connected to the collector of the NPN, and is referred to as the pixel drain; the gate voltage of the NMOS is referred to as the pixel gate. In the voltage-modulated image sensor, the substrate of the NMOS is connected to the base of the NPN, serving as the charge collection region of the pixel. The main function of the NPN is to discharge some of the holes in the charge collection region that are in a floating state under the condition of applying a suitable bias voltage to the pixel source and pixel drain, thereby realizing the reset operation of the pixel unit. The main function of the NMOS is that after the pixel undergoes reset and exposure, the charge collection region will have different voltage values ​​depending on the collected light signal, which will affect the threshold voltage of the NMOS by means of the substrate bias voltage, thereby realizing the readout operation of the pixel unit.

[0047] The pixel unit readout methods include two approaches: First, a small bias voltage is applied to the source and drain of the pixel, followed by a ramp voltage on the pixel gate. When the NMOS reaches the threshold voltage, the subsequent comparator flips and records this threshold voltage. Second, a common source follower (SF) method is used, pulling the pixel source up to the power supply voltage and connecting the pixel drain to a stable current source for analog-to-digital conversion (ADC) quantization. The ramp-sweep method places no additional requirements on the pixel unit, and the NMOS operates primarily in a subthreshold state, resulting in low current and low power consumption. However, the readout time of the ramp-sweep method is exponentially related to the number of quantized bits; excessively long readout times affect the image sensor's output frame rate. The following will first discuss the operating voltage and basic principles of the pixel in various operating states using the ramp-sweep readout method. Then, it will be explained that the optimized pixel unit can be well-compatible with the source follower readout method to achieve a high imaging frame rate.

[0048] Figure 2 The timing diagram for the substrate voltage modulation pixel unit in the ramp readout mode is as follows: Initially, the voltages at all three ports of the pixel are maintained at 0V. In the reset state, a reset voltage V of -3V is applied to the pixel gate and pixel source. RST The purpose is to discharge holes from the charge collection region while keeping the NMOS transistor off. After the reset, all port voltages return to 0V, entering the exposure state. In the readout state, a drain readout voltage V of 0.3V is applied to the drain of the pixel. DR A ramp voltage V of 0-3V is applied to the pixel gate. GR Quantize the light signal of the pixel unit.

[0049] Figure 4 The hole band diagram illustrates the reset and exposure of the pixel unit from a semiconductor principle perspective. The base of the transistor collects photogenerated carriers and, together with the emitter and collector of the transistor, achieves reset. The field-effect transistor reads out the pixel signal through the modulation effect of the substrate voltage. The specific steps are as follows: Reset of photogenerated carriers: A bias voltage is applied to the emitter and collector of the transistor, and the majority carriers in the floating base of the transistor are partially discharged. The emitter and collector of the transistor return to their near-zero bias state. Due to the unidirectional conductivity of the two diodes in the transistor, the discharged base majority carriers cannot be replenished from the electrodes, thus completing the reset of photogenerated carriers.

[0050] In the diagram, t0 to t1 represent the pixel entering the reset state. As the source voltage of the pixel decreases, the depletion region of the pixel drain and the charge collection region expands. Correspondingly, some holes recombine with electrons at the pixel source, resulting in hole outflow and resetting of the pixel unit. Furthermore, the amount of reset hole charge Q... RST satisfy,

[0051] Q RST =-C DD V RST

[0052] Among them, Q RST It is the amount of hole charge that has been reset, C DD It is the capacitance between the pixel drain and the charge collection region, V RST It is the reset voltage.

[0053] t1 to t2 represent the period when a pixel transitions from the reset state to the exposure state. The source voltage of the pixel returns to 0V, and at this time, the voltage in the charge collection region cannot maintain the previous V value. RST Instead, it increases accordingly as the source voltage rises. Since there is no source of replenishment for the holes in the charge collection region, the law of hole conservation is satisfied during this transition. After entering the exposure state, the voltage V in the charge collection region... C satisfy,

[0054]

[0055] Among them, V C Q is the voltage of the charge collection region. RST It is the amount of hole charge that has been reset, C DD It is the capacitance between the pixel drain and the charge collection region, C DS It is the capacitance between the pixel source and the charge collection region, V RST It is the reset voltage.

[0056] Exposure and collection of photogenerated carriers: After the base of the transistor completes the reset operation, it is in a non-equilibrium state. When exposed to light, one type of carrier in the electron-hole pairs generated is stored as the majority carrier in the base region in the PN junction capacitance formed by the base, emitter, and collector. The other type of carrier flows away from the emitter and collector, thus completing the collection of photogenerated carriers.

[0057] In the figure, t3 to t4 represent the impact of photogenerated carrier collection on the energy band and voltage of the charge collection region under exposure conditions. hν in the figure represents a photon. After a photon enters the charge collection region, it generates electron-hole pairs. Electrons diffuse and drift out from the source or drain of the pixel, while holes accumulate in the charge collection region, causing the voltage change ΔVC in the charge collection region to satisfy...

[0058]

[0059] Where △V C It is the change in voltage in the charge collection region, ΔQ sigIt is the amount of charge corresponding to the collected photogenerated holes, C DD It is the capacitance between the pixel drain and the charge collection region, C DS It is the capacitance between the pixel source and the charge collection region.

[0060] Optical signal readout: After the transistor collects photogenerated carriers, the potential in the region changes accordingly. At the same time, the substrate voltage of the field-effect transistor is equal to the base voltage of the transistor. Therefore, the substrate voltage of the field-effect transistor is related to the number of photogenerated carriers collected. By applying a voltage to the gate of the field-effect transistor and connecting a corresponding load to the source or drain of the field-effect transistor, the number of photogenerated carriers is characterized by the voltage or current at the output of the field-effect transistor, thus completing the optical signal readout.

[0061] Because the charge of the reverse-biased diode capacitor is provided by the fixed charge in the depletion region, and considering that the doping concentration of the pixel drain and pixel source is much greater than the doping concentration of the charge collection region, and that the doping concentration of each part is uniform, then the pixel drain and pixel source have...

[0062]

[0063]

[0064] Among them, Q D N is the charge amount in the depletion region of the pixel drain and the charge collection region, q is the charge amount of a single electron or hole, and N is the charge amount in the depletion region of the pixel drain and the charge collection region. A It is the acceptor concentration in the charge collection region, W DD A is the depletion width between the pixel drain and the charge collection region. D It is the contact area between the pixel drain and the charge collection region, ∈ s It is the dielectric constant of silicon, V. bi It is the built-in electric field of the pixel drain and the charge collection region, V C This is the voltage of the charge collection region. The parameters of the pixel source are similar.

[0065] Therefore, the total charge is the sum of the charges in the two depletion regions.

[0066]

[0067] Q C A is the total charge collected by the charge collection. T It is the total contact area between the charge collection region and the pixel source / drain.

[0068] For the voltage V of the charge collection region C have,

[0069]

[0070] For the NMOS in the pixel unit, there is...

[0071]

[0072] Among them, V T It is the NMOS threshold voltage, V FB It is the flat-band voltage of the NMOS, φ B It is the Fermi level E in the charge collection region f With the forbidden center E i The potential difference between them, C ox It is the NMOS gate oxide capacitor.

[0073] And 2φ B With V bi These are approximately equal small quantities, combined with the voltage V in the collection region. C The relationship with the total charge in the charge collection region is as follows:

[0074]

[0075]

[0076] Where dV T It is the change in the NMOS threshold voltage, dQ C It is the change in the total charge collected, dQ sig It is the change in the amount of charge of the collected photogenerated holes.

[0077] Therefore, under ideal conditions, the output threshold voltage of the pixel unit of the substrate voltage modulation image sensor is linearly related to the optical signal.

[0078] The above description has clearly explained the working principle and timing of the pixel unit of the substrate voltage modulation image sensor. However, during the reset process, the main component involved in the reset is the pixel drain capacitor C. DD After the reset is completed, with the pull-up of the pixel source electrode and the increase of the pixel source electrode capacitor C... DS The presence of [something] causes a certain rise in the potential of the charge collection region. This does not pose a problem in the ramp-scan readout method, but in the source-following readout scheme, due to the pixel source voltage such as [something], the potential of the charge collection region also rises to a certain extent. This does not cause a problem in the ramp-scan readout method, but in the source-following readout scheme, due to the [something], the potential of the pixel source voltage is [something]. Figure 4 Applying a higher power supply voltage causes the voltage in the charge collection region to exceed that of the pixel drain, resulting in the NMOS being normally on. Therefore, the parameters of the substrate voltage modulation image sensor need to be adjusted accordingly to address this issue, ensuring that the NMOS is closed in the non-selected transition state at 0 gate voltage. This is based on the fundamental principles of the pixel unit and... Figure 4 and Figure 5The timing and band structure of the source-following readout method, and the voltage V after the charge collection region reset operation is completed. C satisfy,

[0079] (V CC -V C C DS +(0-V C C DD =(0-V RST C DD

[0080]

[0081] Among them, V CC The power supply voltage is 1.8V, and the other parameters have the same meaning as those mentioned above.

[0082] Here we set C DD >>C DS ,but

[0083] V C ≈V RST

[0084] That is, the floating voltage of the charge collection region after reset is the same as the reset voltage, and is independent of the pull-up value of the pixel source voltage after reset, thus ensuring that the NMOS channel is always off.

[0085] Under condition C DD >>C DS On this basis, Figure 4 This demonstrates the source-follower readout configuration of a substrate voltage modulation image sensor. Under initialization conditions, all voltage ports are 0V. In the reset state, a reset voltage V of -3V is applied to the pixel gate and pixel source. RST This ensures that the NMOS transistor is turned off. During exposure, the pixel gate returns to 0V, and the pixel source is pulled up to the 1.8V power supply voltage V. CC In read mode, a 2.5V gate voltage V is applied to the pixel gate. GR The pixel drain is connected to a current source, and the pixel drain voltage is read.

[0086] Figure 5 The working principle of the substrate voltage modulation image sensor under source follower readout mode and Figure 3 The principle is the same as that under the ramp readout method. It's just that due to C... DD >>C DS The voltage V of the charge collection region is determined by the given conditions. C The voltage does not increase significantly with the rise of the pixel source voltage, and remains basically stable at the reset voltage V. RST .

[0087] On the other hand, the above explanation of the reset principle mainly considers only the NPN transistor and related diode capacitors. However, in actual operation, the influence of the NMOS gate capacitance cannot be ignored in many cases. Therefore, after the charge collection region completes the reset and enters the exposure state, its floating voltage V C for,

[0088]

[0089] Among them, V ES The pixel source voltage, V, is the voltage at which the image is exposed. EG The pixel gate voltage, C, is the voltage at which the exposure is performed. ox It is the pixel gate capacitance.

[0090] The expression shows that the pixel gate capacitance C ox With the pixel source capacitor C DS Similarly, the floating potential V of the charge collection region after reset is also considered. C These are all negative effects, and could very likely cause the NMOS channel to enter a normally open state. Therefore, as Figure 1 As shown, an additional N-type transistor is introduced and operates in series with the existing NMOS. The substrates of both transistors are connected to the base of the NPN transistor. The source of the existing field-effect transistor is connected to one of the emitter and collector of the existing transistor, serving as the pixel source. The drain of the newly added field-effect transistor is connected to the other of the emitter and collector of the existing transistor, serving as the pixel drain. The drain of the existing field-effect transistor is connected to the source of the newly added field-effect transistor. The existing NMOS is called the address field-effect transistor, used to sense photogenerated carriers, and its gate is called the pixel gate. The newly added NMOS is called the state field-effect transistor, used for selection, and its gate is called the pixel state gate. During exposure and photogenerated carrier collection, the address field-effect transistor is turned off; during the readout of the optical signal, both the address field-effect transistor and the state field-effect transistor of the selected pixel are turned on.

[0091] In the operation of the substrate voltage modulation image sensor, a bias voltage of 3V is applied to the gate of the state field-effect transistor. bias Under the influence of the transistor, the addressing field-effect channel is normally open, while it is normally closed in the non-read-selected state. Because the state field-effect transistor is normally open, the inversion layer of the channel is connected to the pixel drain, forming a depletion capacitance similar to that of a diode with the charge collection region, denoted as C. DST The floating potential V of the charge collection region is then... C In the capacitor C DST Under the influence of, there is

[0092]

[0093] Only when the design of the substrate voltage modulation image sensor image element meets C DST >>Cox and C DST >>C DS Similarly, there are

[0094] V C ≈V RST

[0095] That is, the floating voltage of the charge collection region after reset is the same as the reset voltage, and is independent of the pull-up value of the pixel source voltage and the value of the pixel gate voltage after reset, thus ensuring that the NMOS channel is always off.

[0096] This concludes the explanation of the principle, workflow, and optimization points of a single pixel in the substrate voltage modulation image sensor. The next section will elaborate on the arrangement of the imaging array composed of the image sensor pixels and its basic operating mode.

[0097] Figure 6 This is a schematic diagram of the basic connection method of the pixel array in a substrate voltage modulation image sensor. The pixel unit includes a pixel gate, a pixel source, and a pixel drain. If the pixel unit adopts... Figure 1 The pixel structure having the state transistors is such that a fixed bias voltage of 3V is applied to the state gates of all the pixels in the pixel array. bias Furthermore, since this port does not affect the timing of subsequent pixel array operations, it will not be discussed here. Figure 6 It is not specified in the text. In the pixel array, the pixel gates of the pixel units in the same row are connected, denoted as the gate word line WL, the pixel sources of the pixel units in the same row are connected, denoted as the reset word line RWL; the pixel drains of the pixel units in the same column are connected, denoted as the readout bit line BL.

[0098] Although this invention provides two readout methods for the pixel unit—sweep ramp and source follower—the two differ only in the voltage applied to the pixel unit port and the requirements for some pixel parameters; they do not affect the operating timing of the pixel array. Therefore, only the sweep ramp readout method will be described here; the operating timing of the source follower readout method is the same as that of the sweep ramp.

[0099] Rolling shutter (RS) exposure is a basic function of conventional image sensors. Figure 7 This is a rolling shutter exposure timing diagram of the pixel array of the substrate voltage modulation image sensor. The pixel array is arranged according to... Figure 2The system performs a repetitive, periodic operation of reset, exposure, and readout row by row, based on the pressure conditions given in the diagram. When a pixel unit is in the reset state, the pixel drain extends into the depletion region of the charge collection area, generating an electron current flowing into the pixel. Since pixel readout relies on the pixel drain current, if any pixel in the same column is in the reset state, the remaining pixels cannot be read out normally. Furthermore, because the reset word line RWL and readout bit line BL of the pixel array are orthogonal, if any row of pixels in the array is in the reset state, the pixels in the remaining rows also cannot be read out normally; otherwise, the readout current value will be affected by the electron current of the pixel in the reset state. In summary, after one row completes readout and reset and enters the exposure state, the next row enters the readout and exposure state again, following this pipeline operation to achieve the rolling shutter exposure function of the substrate voltage modulation image sensor pixel array.

[0100] Furthermore, during semiconductor fabrication, fixed pattern noise (FPN) caused by device non-uniformity is unavoidable. Therefore, the field of image sensors often uses double sampling to eliminate a portion of the FPN at the front end to improve imaging performance. Figure 8 This is a timing diagram of the rolling shutter exposure in dual sampling mode of the pixel array of a substrate voltage modulation image sensor. Compared to Figure 7 The reset-exposure-readout operation in the dual-sampling mode is modified by adding an additional reset and readout operation, resulting in a repetitive reset-exposure-readout-reset-readout process. The dual-sampling mode includes two readout results: the second is the initial threshold of the pixel read directly after reset, and the first is the threshold of the pixel containing the light signal. By subtracting the initial pixel value from the first readout value, the threshold change corresponding to the pure light response signal can be obtained. Similarly, it is important to ensure that the readout and reset operations can only proceed sequentially in the next row after the previous row has entered the exposure state.

[0101] Given that one of the advantages of the image sensing technology of this invention is its application to high-sensitivity, small-sized pixels in the sub-micron range, the size limitations often prevent the implementation of a separate peripheral readout circuit module for each readout bit line BL. Instead, a single peripheral readout circuit module is responsible for reading out multiple columns of pixel units. Furthermore, due to the characteristics of the substrate voltage modulation image sensor, pixels in the next row must wait for all pixels in their row to complete readout and reset before they can perform their own readout and reset operations, significantly increasing operation time and reducing the imaging frame rate. Figure 9 and Figure 10The alternative pixel array connection method and timing shown combines the above conditions and problems, providing a method in which different rows can be in readout and reset states simultaneously, shortening the single-cycle operation time of pixels and improving the imaging frame rate. Figure 9 Connecting the source poles of cells in the odd-numbered columns of the pixel array in the same row forms the odd-numbered reset word line RWLo; connecting the source poles of cells in the even-numbered columns of the same row forms the even-numbered reset word line RWLe. In this connection state, when the odd-numbered columns of the pixel array are in the readout state, the even-numbered columns can be reset, and vice versa. Figure 10 As shown. This only applies to... Figure 9 The array structure of the rolling shutter exposure process is demonstrated, and the timing sequence with dual sampling function can be combined with... Figure 8 and Figure 10 The principle is obtained.

[0102] Based on the basic principles of this invention, the substrate voltage modulation image sensor pixel has various structures. The following description will begin with the structure that best matches the circuit schematic and is most intuitive, and then, by utilizing more parasitic effects and combining them with more advanced manufacturing processes, will demonstrate a simpler pixel structure with smaller feature sizes. The basic device structure of the image sensor includes the pixel unit, substrate, pixel fully isolated structure, and field-effect transistor. The pixel fully isolated structure divides the substrate into multiple independent regions, each of which is the substrate of the pixel unit. Figure 11 This is the basic device structure 110 for a pixel unit of a substrate voltage modulation image sensor. A fully deep trench isolation (FDTI) structure 112 made of silicon oxide is used to divide a P-type epitaxial silicon substrate 111 into multiple pixel units. Each pixel unit contains an NMOS transistor and an NPN transistor. The pixel drain 113 is N-type doped and serves as both the source of the NMOS and the emitter of the NPN transistor. The source 114 of the NMOS and the collector 117 of the NPN transistor are both N-type doped and interconnected, serving as the pixel source of the pixel unit. The substrate 115 of the NMOS and the base 118 of the NPN transistor are both P-type doped and interconnected, serving as the charge collection region of the pixel unit. The gate 116 of the NMOS serves as the pixel gate of the pixel unit.

[0103] Furthermore, placing a transistor and a field-effect transistor in each pixel would make the pixel structure overly complex. For a bulk silicon transistor, there is a parasitic transistor between its source / drain and the substrate. Therefore, the field-effect transistor is simplified to a single bulk silicon transistor. The pixel's fully isolated structure includes a deep trench isolation structure penetrating the substrate vertically. This deep trench isolation structure includes: a silicon oxide-filled structure, a silicon oxide / air gap composite layer-filled structure, or a silicon oxide / silicon nitride / silicon oxide composite layer-filled structure. Figure 12 This diagram illustrates a substrate voltage modulation (FDTI) image sensor pixel unit device structure 120 that utilizes a parasitic transistor for photosensitive photosensitivity. The diagram still employs an FDTI structure 122 to divide a P-type epitaxial silicon substrate 111 into multiple pixel units. However, the independent and floating substrate 111 within each pixel serves as the charge collection region for that pixel unit, acting as both the substrate of an NMOS transistor and the base of an NPN transistor. Similarly, the pixel drain 123 is both the drain of an NMOS transistor and the collector of an NPN transistor; the pixel source 124 is both the source of an NMOS transistor and the emitter of an NPN transistor. The pixel gate 125 controls the conduction of the channel between the pixel source 124 and the pixel drain 123.

[0104] Figure 12 The device structure 120 still uses Figure 1 The circuit schematic shows a single transistor connected in parallel with a bipolar junction transistor. However, to improve parameters such as full-well charge, signal-to-noise ratio, and imaging frame rate, substrate voltage modulation image sensors need to employ techniques such as... Figure 2 The circuit schematic includes an addressable field-effect transistor (FET) and a state FET. The device structure provided below in this embodiment includes an addressable FET and a state FET, corresponding respectively to the gate ring transistor and the vertical gate transistor in the embodiments. One of the source and drain terminals of the gate ring transistor is located at the center of the gate ring, and the other is located on the periphery of the gate ring and in contact with the pixel fully isolated structure. The vertical gate transistor includes the pixel fully isolated structure, wherein the pixel fully isolated structure includes a silicon oxide / polysilicon composite layer filling structure or a silicon oxide / amorphous silicon composite layer filling structure.

[0105] Figure 13The pixel unit device structure of the substrate voltage modulation image sensor, including parasitic transistors, gate-around transistors, and vertical gates, is a pixel structure 130 designed to simultaneously address the challenges of supporting source-following readout, increasing full-well charge, and reducing dark current. In the figure, the pixel source 133, pixel drain 134, and pixel gate 135 form a gate-around NMOS, acting as the source, drain, and gate, respectively. The fully isolated structure 132 includes a vertical gate (VG) layer 132-1 made of polycrystalline or amorphous silicon, which, together with the basic fully isolated structure 132, forms a silicon oxide / silicon composite material layer, dividing the epitaxial silicon substrate 131 into multiple pixel units. This silicon oxide / silicon composite material layer is currently referred to as Capacitor Deep Trench Isolation (CDTI) technology. The substrate 131 within each pixel serves as the charge collection region for that pixel unit. The vertical gate layer 132-1 is connected to a fixed 3V bias voltage during use, ensuring that the surface of the fully isolated structure 132 and the charge collection region 131 is in an electron inversion state. At this time, the electron inversion layer is connected to the pixel drain 134, significantly increasing the capacitance CDD of the pixel drain and the charge collection region without consuming planar area. This allows the pixel structure 130 to gain support source follow readout advantages while improving the full-well capacitance and dynamic range of the pixel. Furthermore, since the interface between the isolated structure 132 and the charge collection region 131 is a high-concentration electron inversion layer, the dark current generation rate can be reduced, thereby reducing the dark noise of the pixel structure 130.

[0106] The pixel source and pixel drain can be disposed simultaneously on the front side of the substrate, or separately on the front and back sides of the substrate. Figure 14 The substrate voltage modulation image sensor pixel unit device structure 140, including a parasitic transistor, a gate-around transistor, a vertical gate, and a back-side source / drain, is in... Figure 13 This is an improved structure designed to further reduce the pixel feature size based on the mid-pixel structure 130. The schematic diagram of the pixel structure 140 is as follows: Figure 1 This is a substrate voltage modulation image sensor with pixel state transistors. The pixel gate 145 is the ring gate of the address transistor, and the gate layer 142-2, made of polycrystalline silicon or amorphous silicon, in the fully isolated structure 142 is the vertical gate of the state transistor. The pixel source 143 is located on the front side of the pixel structure 140, and the pixel drain 144 is located on the back side of the pixel 140. Under normal operating conditions, the pixel state gate 142-2 is connected to a fixed 3V voltage V. biasWhen the state transistor channel is turned on, an electron inversion state exists on the surfaces of the fully isolated structure 142 and the charge collection region 141. Since the electron inversion layer and the charge collection region also form the diode-like depletion capacitance CDST, the amount of charge reset, i.e., the full-well charge, is...

[0107] ΔQ max =V RST (C DD +C DST )

[0108] Where ΔQ max It is the full-well charge of the pixel structure 140, VRST is the voltage applied to the source of the pixel in the reset state, C DD It is the capacitance between the pixel drain 144 and the charge collection region 141, C DST It is the capacitance between the inversion layer and the charge collection region 141.

[0109] Compared to pixel structure 130, pixel structure 140 saves two feature sizes in the illustrated direction because the pixel drain surface is moved to the back side, reducing the pixel size from 36F in pixel structure 130. 2 Shrinking to 16F 2 (F represents the characteristic dimension of the process.)

[0110] Furthermore, the planar ring gate structure in the pixel structure 140 can also be made vertically using VG technology. A first doped material layer and a second doped material layer are respectively disposed on the front and back sides of the pixel unit substrate. The doping type of the first doped material layer is the same as that of the second doped material layer, and opposite to the doping type of the independent substrate. The pixel fully isolated structure includes a silicon oxide / polycrystalline silicon composite layer filling structure or a silicon oxide / amorphous silicon composite layer filling structure. The pixel fully isolated structure includes at least two layers of the silicon oxide / polycrystalline silicon or silicon oxide / amorphous silicon repeating composite layer filling structure along the normal direction of the plane of the independent substrate. Figure 15 As shown, in pixel structure 150, pixel fully isolated structure 152 also divides the epitaxial silicon substrate 151 into multiple independent pixels, and the substrate 151 serves as a charge collection region. The fully isolated structure 152 includes two vertical gates made of polycrystalline silicon or amorphous silicon, namely pixel state gate 152-1 and pixel gate 152-2. Pixel source 143 is located on the front side of pixel structure 140, and pixel drain 144 is located on the back side of pixel 140. The operating method of pixel structure 150 and its advantages in imaging metrics such as full-well, dark current, and frame rate are the same as those of pixel structure 140, but the feature size of pixel structure 150 can be reduced to a minimum of 9F. 2 .

[0111] Figure 16 and Figure 17 These are horizontal cross-sectional views of the pixel structure 150 at points T and B, respectively. In cross-sectional view 250 at point T, dashed box 251 represents the range of a single pixel division, 252 is the pixel full isolation structure 152, 253 is the pixel gate 152-2, and 254 is the pixel source 153. In cross-sectional view 350 at point T, dashed box 351 represents the range of a single pixel division, 352 is the pixel full isolation structure 152, 353 is the pixel gate 152-1, and 354 is the pixel drain 154. The pixel gates 253 (152-2) in the same row are connected, enabling row selection functionality in array use; all pixel state gates 353 (152-1) in the array are connected, and a uniform bias voltage V is applied. bias .

[0112] The key technology for realizing pixel structure 150 is a multi-layer vertical gate structure, and for one of the vertical gate structures, it is possible to achieve the connection of the vertical gate structure of the same row of pixels and the electrical isolation of the vertical gate structure of the same layer of pixels in different rows. Figure 18 and Figure 19 These are process flow diagrams for the pixel structure 150 in the horizontal and vertical directions, respectively. The purpose is to illustrate, in conjunction with the process characteristics, that the pixel structure 150 can be reduced to a feature size of 3F in both directions, ultimately achieving 9F. 2 Submicron-sized pixel structures. Figure 19 First, a shallow trench structure with a width of 2F and a period of 3F is photolithographically etched. At this point, the active region without the shallow trench structure has a width of 1F. Next, an oxide layer is grown and polysilicon is deposited, and the pixel gate 253 (152-2) is formed by chemical mechanical polishing. Then, a shallow trench isolation structure (STI) with a width of 1F is etched back at the center of the pixel gate 253 (152-2) with a width of 2F. This is the upper half of the pixel full isolation structure 152, which separates the pixel gates 152-2 that are not in the same row, and completes the ion implantation of the pixel source 153. Immediately afterward, a deep trench structure with a width of 1F is etched at the center of the pixel gate 253 (152-2) with a width of 2F. At this point, the period of the deep trench structure is also 3F, and the active region without the deep trench structure on the back side has a width of 2F. Finally, the pixel state gate 152-1 is grown and deposited, and the ion implantation and annealing of the pixel drain 154 are completed. Figure 18 The process and Figure 19 The process is similar, except that the pixel gate 253 (152-2) does not need to be etched back in the horizontal direction, and the final pixel state gate 152-1 is a grid, meaning that the pixel state gates of all pixel units in the array are interconnected. In summary, the pixel structure 150 in... Figure 18 and Figure 19 With the process steps, the dimensions in both the horizontal and vertical directions are reduced to 3F, so the minimum area of ​​a single pixel can reach 9F. 2 Combined with the relatively mature 55nm node production lines of most domestic foundries, the size of a single pixel can reach the 200nm diffraction limit of visible light, meeting the application requirements of most small-sized visible light sensors.

Claims

1. A pixel unit of a substrate voltage modulation image sensor, comprising a field-effect transistor and a transistor, characterized in that, The doping type of the field-effect transistor substrate is the same as that of the base of the transistor, but opposite to that of the source and drain of the field-effect transistor; the field-effect transistor substrate is connected to the base of the transistor, the emitter of the transistor is connected to one of the source and drain of the field-effect transistor, serving as the pixel source; the collector of the transistor is connected to the other of the source and drain of the field-effect transistor, serving as the pixel drain; the gate of the field-effect transistor is connected to an external voltage, serving as the pixel gate; The transistor is a parasitic transistor, the field-effect transistor substrate serves as the base of the transistor, one of the source and drain of the field-effect transistor serves as the collector of the transistor, and the other of the source and drain of the field-effect transistor serves as the emitter of the transistor. The field-effect transistor includes a series structure consisting of an address field-effect transistor and a state field-effect transistor. The address field-effect transistor is used to sense photogenerated carriers, and the state field-effect transistor is used for selection. The substrates of both field-effect transistors are connected to the base of the transistor. The source of the address field-effect transistor is connected to one of the emitter and collector of the transistor, serving as the pixel source. The drain of the state field-effect transistor is connected to the other of the emitter and collector of the transistor, serving as the pixel drain; the drain of the address field-effect transistor is connected to the source of the state field-effect transistor; the gate of the address field-effect transistor serves as the pixel gate, and the gate of the state field-effect transistor serves as the pixel state gate.

2. The operation method of the pixel unit of the substrate voltage modulation image sensor as described in claim 1, characterized in that, This operation method involves the base of the transistor collecting photogenerated carriers, and the emitter and collector of the transistor achieving reset. The field-effect transistor reads out the pixel signal through the modulation effect of the substrate voltage. The specific steps are as follows: Reset of photogenerated carriers: When a bias voltage is applied to the emitter and collector of the transistor, the majority carriers in the floating base of the transistor are partially discharged, and the emitter and collector of the transistor return to their normal state of near zero bias. Due to the unidirectional conductivity of the two diodes in the transistor, the discharged base majority carriers cannot be replenished from the electrodes, thus completing the reset of photogenerated carriers. Exposure and collection of photogenerated carriers: After the base of the transistor is reset, it is in a non-equilibrium state. When exposed to light, one type of carrier in the electron-hole pairs generated is stored as the majority carrier in the base region in the PN junction capacitance formed by the base, emitter, and collector. The other type of carrier flows away from the emitter and collector, thus completing the collection of photogenerated carriers. Optical signal readout: After the transistor collects photogenerated carriers, the potential in the region changes accordingly. At the same time, the substrate voltage of the field-effect transistor is equal to the base voltage of the transistor. Therefore, the substrate voltage of the field-effect transistor is related to the number of photogenerated carriers collected. By applying a voltage to the gate of the field-effect transistor and connecting a corresponding load to the source or drain of the field-effect transistor, the number of photogenerated carriers is characterized by the voltage or current at the output terminal of the field-effect transistor, thus completing the optical signal readout.

3. The operating method according to claim 2, characterized in that, When the field-effect transistor includes a series structure consisting of an address field-effect transistor and a state field-effect transistor, the state field-effect transistor is used to sense photogenerated carriers, and the address field-effect transistor is used for selection; during the exposure and photogenerated carrier collection process, the address field-effect transistor is turned off; during the readout of the optical signal, both the address field-effect transistor and the state field-effect transistor of the selected pixel are turned on.

4. The array of pixel units of the substrate voltage modulation type image sensor as described in claim 1, characterized in that, Multiple pixel units are arranged in an array, wherein the pixel gates of the pixel units in the same row are connected to form the gating word line of the array; The pixel source lines of the pixel units in the same row are connected to form the reset word line of the array; or, the pixel source poles of the pixel units in the odd-numbered columns of the same row are connected to form the first reset word line of the array, and the pixel source poles of the pixel units in the even-numbered columns of the same row are connected to form the second reset word line of the array. The pixel drains of the pixel units in the same column are connected to form the readout bit line of the array; When the field-effect transistor includes a series structure consisting of an address field-effect transistor and a state field-effect transistor, the drains of the pixel units in the same row are connected to form the readout bit line of the array; the state gates of the pixel units in the same row are connected to form the state word line of the array.

5. The device of the substrate voltage modulation type image sensor pixel unit as described in claim 1, characterized in that, The device includes the pixel unit, a substrate, a pixel fully isolated structure, and a field-effect transistor. The pixel fully isolated structure divides the substrate into multiple independent regions, with each independent region being the substrate of the pixel unit.

6. The device according to claim 5, characterized in that, The field-effect transistor includes a single bulk silicon transistor, and the pixel fully isolated structure includes a deep trench isolation structure that penetrates the substrate in the vertical direction. The deep trench isolation structure includes: a silicon oxide filled structure, or a silicon oxide / air gap composite layer filled structure, or a silicon oxide / silicon nitride / silicon oxide composite layer filled structure.

7. The device according to claim 5, characterized in that, The field-effect transistor includes a gate ring transistor and a vertical gate transistor. One of the source and drain of the gate ring transistor is located at the center of the gate ring, and the other is located at the periphery of the gate ring and in contact with the pixel fully isolated structure. The vertical gate transistor includes the pixel fully isolated structure, wherein the pixel fully isolated structure includes a silicon oxide / polycrystalline silicon composite layer filling structure or a silicon oxide / amorphous silicon composite layer filling structure. The pixel source and pixel drain are both located on the front side of the substrate, or they are located on the front and back sides of the substrate, respectively.

8. The device according to claim 5, characterized in that, The front and back sides of the substrate of the pixel unit are respectively provided with a first doped material layer and a second doped material layer. The doping type of the first doped material layer is the same as that of the second doped material layer, which is opposite to the doping type of the independent substrate. The pixel-wide isolation structure includes a silicon oxide / polycrystalline silicon composite layer filling structure or a silicon oxide / amorphous silicon composite layer filling structure. The pixel-wide isolation structure includes at least two layers of the silicon oxide / polycrystalline silicon or silicon oxide / amorphous silicon repeating composite layer filling structure along the normal direction of the independent substrate plane.

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