Display device

Abstract

A display device includes a substrate including a display area and a non-display area, a light emitting element disposed in the display area, an encapsulation layer covering the light emitting element, and a barrier disposed in the non-display area and surrounding the display area. The barrier includes a plurality of layers, and the plurality of layers includes an organic layer including a portion in which a height decreases and then increases toward an edge of the organic layer.

Description

[0001] This application claims priority to Korean Patent Application No. 10-2020-0087559, filed on July 15, 2020, and all benefits derived therefrom, the contents of which are incorporated herein by reference in their entirety. Technical Field

[0002] Embodiments of the present invention relate to display devices. Background Technology

[0003] Display devices (such as transmitting display devices) include a display panel and a screen on the display panel for displaying images. The display panel is manufactured by forming several layers and elements on a substrate.

[0004] The display panel may include an encapsulation layer that prevents the inflow of moisture or oxygen to protect the components formed on the substrate from external environmental influences. Additionally, the display panel may include an anti-reflective layer to reduce the reflection of external light.

[0005] In recent years, flexible display panels that are lightweight, impact-resistant, and easily deformable using flexible substrates have been developed. Summary of the Invention

[0006] The implementation provides a display device that is thin, lightweight, and capable of improving reliability.

[0007] An embodiment provides a display device comprising: a substrate including a display area and a non-display area; a light-emitting element disposed in the display area; an encapsulation layer covering the light-emitting element; and a baffle disposed in the non-display area and surrounding the display area. The baffle comprises multiple layers, and the multiple layers include an organic layer, the organic layer including a portion whose height decreases towards its edge and then increases.

[0008] In one embodiment, the organic layer may include a black photoresist.

[0009] In an implementation, the organic layer may include a first portion adjacent to the edge and a second portion disposed inside the first portion, and the height of the first portion may be greater than the height of the second portion.

[0010] In one embodiment, the curve defined by the upper surface of the edge portion of the organic layer in the cross-sectional view may include at least two inflection points.

[0011] In an embodiment, the display device may further include power supply voltage transmission lines disposed in a non-display area, and the organic layer may include a portion in contact with the power supply voltage transmission lines.

[0012] In an embodiment, the display device may further include a connecting member that electrically connects the electrodes of the light-emitting element and the power supply voltage transmission line, and the organic layer may include a portion that contacts the connecting member.

[0013] In an embodiment, the display device may further include an insulating layer disposed between the substrate and the power supply voltage transmission line, and the organic layer may include a portion in contact with the insulating layer.

[0014] In one embodiment, the encapsulation layer may include an inorganic layer, which may extend over and contact the organic layer.

[0015] In an embodiment, the display device may further include a black pixel defining layer disposed in the display area and defining an opening therein, and the height of a first portion of the black pixel defining layer adjacent to the edge of the black pixel defining layer for defining the opening may be greater than the height of a second portion disposed further from the opening than the first portion is from the opening.

[0016] In an embodiment, the display device may further include a light-blocking member and a color filter disposed on and overlapping the black pixel defining layer.

[0017] An embodiment provides a display device comprising: a substrate including a display area and a non-display area; a black pixel defining layer disposed in the display area and defining an opening therein; a light-emitting diode disposed in the display area and overlapping the opening; a thin-film encapsulation layer covering the light-emitting diode; and a baffle disposed in the non-display area and surrounding the display area. The baffle may include a first layer and a second layer covering an upper surface and side surfaces of the first layer, and the second layer comprises the same material as the black pixel defining layer.

[0018] In an embodiment, the black pixel defining layer and the second layer may include a black photoresist.

[0019] In an implementation, the second layer may include a first portion adjacent to the edge of the second layer and a second portion disposed inside the first portion, and the height of the first portion may be greater than the height of the second portion.

[0020] In one implementation, the curve defined by the upper and side surfaces of the edge portion of the second layer in the cross-sectional view may include at least three inflection points.

[0021] In one embodiment, the display device may further include a power supply voltage transmission line disposed in a non-display area, and the second layer may include a portion in contact with the power supply voltage transmission line.

[0022] In one embodiment, the display device may further include a connecting member that electrically connects the electrodes of the light-emitting diode and the power supply voltage transmission line, and the second layer may include a portion that contacts the connecting member.

[0023] In an embodiment, the display device may further include an insulating layer disposed between the substrate and the power supply voltage transmission line, and the second layer may include a portion in contact with the insulating layer.

[0024] In one embodiment, the thin-film encapsulation layer may include an inorganic layer, and the inorganic layer may extend over and contact the second layer.

[0025] In an embodiment, the display device may further include a planarization layer disposed between a substrate and a black pixel defining layer, and the first layer may include the same material as the planarization layer.

[0026] In an embodiment, the display device may further include a light-blocking member and a color filter disposed on and overlapping the black pixel defining layer.

[0027] According to the embodiments, a thin and lightweight display device with improved reliability can be provided. Furthermore, although not specifically mentioned, the embodiments can provide advantageous effects that are apparent throughout the specification. Attached Figure Description

[0028] The above and other embodiments, advantages, and features of this disclosure will become more apparent from the accompanying drawings, which describe embodiments of the present disclosure in further detail:

[0029] Figure 1 The illustration shows a schematic top plan view of an embodiment of the display device.

[0030] Figure 2 The diagram illustrates along Figure 1 A schematic cross-sectional view of the implementation method taken along line A-A'.

[0031] Figure 3A The diagram illustrates along Figure 1 A schematic cross-sectional view of the embodiment taken along line B-B', and Figure 3B for Figure 3A A magnified view of part A.

[0032] Figure 4 The diagram illustrates along Figure 1 A schematic cross-sectional view of the implementation method taken along line A-A'.

[0033] Figure 5 The diagram illustrates along Figure 1 A schematic cross-sectional view of the implementation method taken by line B-B'.

[0034] Figure 6 The illustration shows an electron micrograph of the pixel-defining layer in an embodiment of the display panel.

[0035] Figure 7The illustration shows an electron micrograph of the pixel-defining layer in a comparative example of a display panel.

[0036] Figure 8 The diagram illustrates the cone angle of the pixel-defining layer in an embodiment of the display panel and a comparative example of the display panel.

[0037] Figure 9 The diagram illustrates the aperture width of the pixel-defining layer in an embodiment of the display panel and a comparative example of the display panel.

[0038] Figure 10 The illustration shows an electron micrograph of the edge portion of the first baffle in an embodiment of the display panel and a comparative example of the display panel.

[0039] Figure 11 The illustration shows an electron micrograph of the edge portion of the second baffle in an embodiment of the display panel and a comparative example of the display panel.

[0040] Figure 12 The illustration shows an electron micrograph of the edge portion of the first baffle in an embodiment of the display panel.

[0041] Figure 13 The diagram illustrates an equivalent circuit diagram of an embodiment of pixels in a display device.

[0042] Figure 14 The illustration shows a schematic cross-sectional view of an implementation of a pixel area in a display panel. Detailed Implementation

[0043] Embodiments of the invention will be described more fully below with reference to the accompanying drawings, in which embodiments are illustrated.

[0044] Furthermore, for better understanding and ease of description, the dimensions and thicknesses of the constituent elements shown in the accompanying drawings are arbitrarily given.

[0045] It will be understood that when a component, such as a layer, film, region, or substrate, is referred to as being "on" another component, it can be directly on the other component, or there may be intermediate components. In contrast, when a component is referred to as being "directly" on another component, there are no intermediate components.

[0046] In addition, unless explicitly stated otherwise, the word “comprise” and its variations such as “comprises” or “comprising” will be understood to imply inclusion of the stated element, but not exclusion of any other element.

[0047] Additionally, in the specification, “connection” means that two or more components are not only directly connected, but also indirectly connected through other components, physically connected and electrically connected, or it may be referred to by different names depending on location or function, but may include each of the components that are essentially integrated with each other.

[0048] Additionally, in the specification, when a component “includes” a certain component, this means that it may further include other components, unless specifically stated to the contrary.

[0049] In the accompanying drawings, the symbols “x”, “y”, and “z” are used to indicate directions, where x indicates a first direction, y indicates a second direction perpendicular to the first direction, and z indicates a third direction perpendicular to both the first and second directions. The first direction x, the second direction y, and the third direction z may correspond to the horizontal, vertical, and thickness directions of the display device, respectively.

[0050] As used herein, “about” or “approximately” includes stated values ​​and means within an acceptable range of deviation from a particular value, determined by a person skilled in the art taking into account the measurement in question and the errors associated with the measurement of the particular quantity (i.e., limitations of the measurement system). For example, “about” may mean within one or more standard deviations, or within ±30%, ±20%, ±10%, or ±5% of the stated value.

[0051] Unless otherwise described in the specification, “overlap” indicates overlap in a plan view and overlap in a third z-direction.

[0052] Figure 1 The illustration shows a schematic top plan view of an embodiment of the display device.

[0053] refer to Figure 1 The display device includes a display panel 10, a flexible printed circuit film 20 bonded to the display panel 10, and a driving unit including an integrated circuit (“IC”) chip 30, etc.

[0054] The display panel 10 includes a display area DA corresponding to a screen on which an image is displayed, and a non-display area NA. Circuits and / or signal lines for generating and / or transmitting various signals and voltages applied to the display area DA are disposed around the display area DA and are located in the non-display area NA. The non-display area NA may be configured to surround the outer periphery of the display area DA. Figure 1 In the diagram, the inner and outer sides of the boundary line BL correspond to the display area DA and the non-display area NA, respectively.

[0055] Pixels PX are arranged in a matrix in the display area DA of the display panel 10. However, the invention is not limited thereto, and the pixels PX can be arranged in various other shapes. Signal lines, such as scan lines, data lines, drive voltage lines, and initialization voltage lines, can be arranged in the display area DA. Scan lines can extend generally in a first direction x, and data lines and drive voltage lines can extend generally in a second direction y. Initialization voltage lines can include voltage lines extending generally in the first direction x and voltage lines extending generally in the second direction y, and can be arranged in a grid shape. Each pixel PX can be connected to scan lines, data lines, drive voltage lines, and initialization voltage lines, etc., to receive scan signals, data voltages, drive voltages, and initialization voltages from these signal lines. Each pixel PX can also receive a common voltage. In embodiments, the pixels PX can be implemented as light-emitting elements, such as light-emitting diodes.

[0056] Touch sensors for sensing user touch and / or non-contact touch can be located in the display area DA. Although the illustration shows a display area DA with a quadrilateral shape with rounded corners, the display area DA can have various shapes, such as polygonal shapes, circular shapes, and elliptical shapes.

[0057] The pad portion PP, which provides pads for receiving signals from the outside of the display panel 10, may be disposed in the non-display area NA of the display panel 10. The pad portion PP may be configured to extend along one edge of the display panel 10 in a first direction x. A flexible printed circuit film 20 is bonded to the pad portion PP, and the pads of the flexible printed circuit film 20 may be electrically connected to the pads of the pad portion PP.

[0058] A driving unit may be disposed in the non-display area NA of the display panel 10 to generate and / or process various signals for driving the display panel 10. The driving unit includes a data driver for applying data voltages to data lines, a scan driver for applying scan signals to scan lines, and a signal controller for controlling the data driver and the scan driver. Pixels PX may receive data voltages in a predetermined timing sequence according to the scan signals generated by the scan driver. The scan driver may be integrated into the display panel 10 and may be disposed on at least one side of the display area DA. The data driver and signal controller may be provided as an IC chip (also referred to as a driver IC chip) 30, and the IC chip 30 may be disposed (e.g., mounted) in the non-display area NA of the display panel 10. The IC chip 30 may be disposed (e.g., mounted) on a flexible printed circuit film 20, etc., for electrical connection to the display panel 10.

[0059] Display panel 10 may include an encapsulation layer EN that completely covers the display area DA. The encapsulation layer EN covers and seals the display area DA to prevent moisture or oxygen from penetrating into the display panel 10. The edge of the encapsulation layer EN may be disposed between the edge of the display panel 10 and the display area DA. A baffle DM surrounding the display area DA may be disposed in the non-display area NA. The baffle DM prevents materials used to form the encapsulation layer EN (especially organic materials such as monomers) from spilling out to the outside of the display panel 10. Display panel 10 may include at least one baffle DM, and each baffle DM may completely surround the display area DA.

[0060] Display panel 10 may include a curved region BR. The curved region BR may be disposed in a non-display area NA between display area DA and pad portion PP. The curved region BR may be disposed across display panel 10 in a first direction x. Display panel 10 may be curved in the curved region BR about a bending axis parallel to the first direction x with a predetermined radius of curvature. When display panel 10 is a top-emitting type, display panel 10 may be curved such that pad portion PP and flexible printed circuit film 20 may be disposed behind display panel 10, and pad portion PP and flexible printed circuit film 20 are farther from display area DA than curved region BR is from display area DA. When a display device including display panel 10 is applied to an electronic device, display panel 10 may be in a curved state. The curved region BR may be curved about one bending axis, or may be curved about two or more bending axes. In the figures, although the curved region BR is illustrated as being disposed in non-display area NA, the curved region BR may extend across display area DA and non-display area NA, or may be disposed in display area DA.

[0061] Figure 2 The diagram illustrates along Figure 1 A schematic cross-sectional view taken along line A-A' of the implementation method. Figure 3A The diagram illustrates along Figure 1 A schematic cross-sectional view of the embodiment taken along line B-B', and Figure 3B for Figure 3A A magnified view of part A.

[0062] refer to Figure 2 as well as Figure 3A and Figure 3B The diagram schematically illustrates a cross-section near the left edge of the display panel 10. The area near the right edge of the display panel 10 may have a cross-sectional structure that is substantially symmetrical to that near its left edge.

[0063] Display panel 10 includes a substrate 110 and various layers, lines, and elements disposed thereon. Although multiple pixels are arranged in the display area DA of display panel 10, only one pixel will be briefly illustrated to avoid the complexity of the figures to be described. In addition, although each pixel includes a transistor, a capacitor, and a light-emitting diode, the stacked structure of display panel 10 will be described with emphasis on a transistor TR and a light-emitting diode LED connected thereto.

[0064] The substrate 110 may be a flexible substrate. In embodiments, the substrate 110 may include a polymer, such as polyimide, polyamide, polycarbonate, or polyethylene terephthalate. In embodiments, the substrate 110 may have a multilayer structure, which includes, for example, two polymer layers and an insulating layer between them.

[0065] An isolation layer 111 may be disposed on a substrate 110, and a buffer layer 120 may be disposed on the isolation layer 111. The isolation layer 111 prevents moisture and oxygen from penetrating into the display panel 10. The buffer layer 120 blocks impurities that can diffuse from the substrate 110 to the semiconductor layer and reduces the stress applied to the substrate 110 during the process of forming the semiconductor layer.

[0066] The semiconductor layer AL of the transistor TR may be disposed on the buffer layer 120. The semiconductor layer AL may include a channel region overlapping the gate electrode GE and source and drain regions disposed on opposite sides of the channel region. In an embodiment, the semiconductor layer AL may include polycrystalline silicon, amorphous silicon, or oxide semiconductor.

[0067] The first gate insulating layer 141 may be disposed on the semiconductor layer AL.

[0068] A first gate conductor, including the gate electrode GE of a transistor TR, may be disposed on a first gate insulating layer 141. The first gate conductor may be provided from the same material in the same process. A second gate insulating layer 142, which may include electrodes of a storage capacitor, may be disposed on the first gate conductor. The second gate conductor may be provided from the same material in the same process. The second gate conductor may be disposed on the second gate insulating layer 142. An interlayer insulating layer 160 may be disposed on the second gate conductor.

[0069] The buffer layer 120, the first gate insulating layer 141, the second gate insulating layer 142, and the interlayer insulating layer 160 may comprise inorganic insulating materials, such as silicon oxide and silicon nitride. In an embodiment, each of the first gate conductor and the second gate conductor may comprise a metal, such as molybdenum (Mo), copper (Cu), aluminum (Al), silver (Ag), chromium (Cr), tantalum (Ta), titanium (Ti), or an alloy thereof.

[0070] A first data conductor (which may include the source electrode SE and drain electrode DE of transistor TR, drive voltage transmission line DVL, common voltage transmission line CVL, and connection wiring 179) may be disposed on interlayer insulating layer 160. The first data conductor may be provided from the same material in the same process. The source electrode SE and drain electrode DE may be connected to the source and drain regions of semiconductor layer AL through contact holes defined in interlayer insulating layer 160, second gate insulating layer 142, and first gate insulating layer 141. Drive voltage transmission line DVL and common voltage transmission line CVL are power supply voltage transmission lines; drive voltage transmission line DVL may transmit drive voltage ELVDD (see reference). Figure 13 Furthermore, the common voltage transmission line CVL can transmit the common voltage ELVSS (reference). Figure 13 ).

[0071] The gate electrode GE, source electrode SE, and drain electrode DE, together with the semiconductor layer AL, constitute the transistor TR. The transistor TR can be a driving transistor in the pixel PX of an emitting display device, or it can be a transistor electrically connected to the driving transistor. In the illustrated transistor TR, the gate electrode GE is disposed above the semiconductor layer AL, but the transistor structure can be varied.

[0072] A first planarization layer 181 may be disposed on a first data conductor. It may include a data line 171 (see reference). Figure 13 ), drive voltage line 172 (reference) Figure 13 A second data conductor, including the connection electrode LE, may be disposed on the first planarization layer 181. The connection electrode LE may be connected to the drain electrode DE of the transistor TR through a contact hole defined in the first planarization layer 181. The second data conductor may be provided from the same material in the same process. A second planarization layer 182 may be disposed on the second data conductor.

[0073] In embodiments, each of the first and second data conductors may include a metal, such as aluminum (Al), copper (Cu), silver (Ag), gold (Au), platinum (Pt), palladium (Pd), nickel (Ni), molybdenum (Mo), tungsten (W), titanium (Ti), chromium (Cr), or tantalum (Ta), or an alloy thereof. In embodiments, the first and / or second data conductors may be multilayered, such as titanium (Ti) / aluminum (Al) / titanium (Ti).

[0074] Each of the first planarization layer 181 and the second planarization layer 182 may include an organic insulating material, such as an acrylic polymer, a siloxane polymer, or an imide polymer. Each of the first planarization layer 181 and the second planarization layer 182 may be used to eliminate steps and planarize, thereby increasing the luminous efficiency of the light-emitting diode (LED) to be disposed thereon. A passivation layer comprising an inorganic insulating material may be disposed between the first planarization layer 181 and the first data conductor. A passivation layer may be disposed in place of the first planarization layer 181.

[0075] A first electrode E1 of a light-emitting diode (LED) is disposed on a second planarization layer 182. The first electrode E1 can be connected to a connection electrode LE through a contact hole defined in the second planarization layer 182. Because the connection electrode LE is connected to the drain electrode DE, the first electrode E1 can be electrically connected to the drain electrode DE through the connection electrode LE. In another embodiment, the first electrode E1 can be directly connected to the drain electrode DE. The transistor TR to which the first electrode E1 is connected can be a driving transistor or a light-emitting control transistor electrically connected to the driving transistor. The first electrode E1 can include a reflective conductive material or a semi-transparent conductive material, or it can include a transparent conductive material. In an embodiment, the first electrode E1 can include a transparent conductive material, such as indium tin oxide (“ITO”) or indium zinc oxide (“IZO”). In an embodiment, the first electrode E1 can include a metal, such as lithium (Li), calcium (Ca), aluminum (Al), silver (Ag), magnesium (Mg), or gold (Au).

[0076] A connection member 195 connected to the common voltage transmission line CVL may be disposed on the second planarization layer 182. The portions of the first planarization layer 181 and the second planarization layer 182 that overlap with the common voltage transmission line CVL may be removed to connect the connection member 195 and the common voltage transmission line CVL. The connection member 195 may comprise the same material as the first electrode E1, processed in the same way as the first electrode E1.

[0077] A pixel defining layer 360, which defines an opening OP overlapping the first electrode E1, may be disposed on the second planarization layer 182. The pixel defining layer 360 may also be referred to as a partition. The pixel defining layer 360 may comprise an organic insulating material, such as an acrylic polymer, an imide polymer, or an amide polymer. The pixel defining layer 360 may be a black pixel defining layer 360 comprising black pigment or dye. The black pixel defining layer 360 can improve contrast and prevent reflection from the metal layer disposed beneath it.

[0078] The pixel-defining layer 360 can be provided by patterning a black photoresist using a photolithography process. The photoresist can be a photosensitive compound in which a black pigment or dye is dispersed, and the photosensitive compound can include polymers, monomers, and photopolymerization initiators. Negative photoresists can be used as black photoresists.

[0079] The formation of the pixel-defining layer 360 will now be described. A black photoresist is applied onto a second planarization layer 182 (on which the first electrode E1 is disposed), and patterned by selectively irradiating light using a photolithography process (e.g., using a mask) and by developing. Areas of the photoresist not irradiated by light can be removed by a developer, thereby exposing at least a portion of the first electrode E1. The removed areas may correspond to openings OP.

[0080] After photoresist development, curing is typically performed. Curing can also be referred to as baking, burning, or firing. Curing can be carried out in an oven at a predetermined temperature (e.g., from about 230 degrees Celsius to about 250 degrees Celsius) for a predetermined time (e.g., from about 30 minutes to about 60 minutes). During curing, the photoresist may flow back due to the high temperature, allowing it to diffuse into the open-aperture components (OPs), and reducing the width of the OPs. Because the effect of photoresist flow or diffusion is non-uniform across all OPs, the width of the OPs may become dispersed or varied. This dispersion in the width of the OPs can degrade the brightness and color uniformity of the display device.

[0081] Sufficient exposure is performed after development and before curing to improve the flow of the photoresist (which can lead to dispersion in the width of the aperture OP). Sufficient exposure can mean irradiating the photoresist with light (e.g., ultraviolet light) without using a mask. Flow of the photoresist during curing can be particularly problematic with black photoresist, possibly due to insufficient polymerization of the black photoresist during the photolithography process. Sufficient exposure further promotes photopolymerization and photocuring of the photoresist, and the flow of the photoresist can be reduced during curing because the edge portions of the photoresist, which can have a large exposure per unit volume, act as baffles. Even if the pixel-defining layer 360 is an organic insulating layer, by suppressing the flow of the photoresist, the cone angle α at the edge portions of the aperture OP can be about 45° or greater, for example, about 45° to about 65°.

[0082] An emitter layer EL may be disposed on the first electrode E1. In addition to the emitter layer EL, at least one of a hole injection layer, a hole transport layer, an electron transport layer, and an electron injection layer may be disposed on the first electrode E1.

[0083] The second electrode E2 of the light-emitting diode (LED) is disposed on the emitting layer EL. The second electrode E2 can be electrically connected to the common voltage transmission line CVL via the connecting member 195 to receive the common voltage ELVSS. In some embodiments, the second electrode E2 may comprise a transparent conductive material, such as ITO or IZO. In other embodiments, the second electrode E2 may comprise a metal, such as calcium (Ca), barium (Ba), magnesium (Mg), aluminum (Al), or silver (Ag). At least one protective layer or functional layer may be disposed on the second electrode E2.

[0084] The first electrode E1, the emitter layer EL, and the second electrode E2 can constitute a light-emitting diode (LED), which can be an organic light-emitting diode. The first electrode E1 can be the anode, serving as a hole injection electrode, and the second electrode E2 can be the cathode, serving as an electron injection electrode, or vice versa. The first electrode E1 can also be called the pixel electrode, and the second electrode E2 can also be called the common electrode.

[0085] An encapsulation layer EN may be disposed on the second electrode E2. The encapsulation layer EN encapsulates the light-emitting diode (LED) to prevent moisture or oxygen from penetrating from the outside. The encapsulation layer EN may include one or more inorganic layers and one or more organic layers stacked on the second electrode E2. In the illustrated embodiment, the encapsulation layer EN is a thin-film encapsulation layer comprising a first inorganic layer 391, a second inorganic layer 393, and an organic layer 392 between them. The first inorganic layer 391 and the second inorganic layer 393, which covers the side surfaces of the organic layer 392, are wider than the organic layer 392, and the first inorganic layer 391 and the second inorganic layer 393 may contact each other in the edge regions of the encapsulation layer EN. In an embodiment, the organic layer 392 may include acrylic resins, methacrylic resins, polyisoprene, vinyl resins, epoxy resins, urethane resins, cellulose resins, and perylene resins, etc. The encapsulation layer EN may be provided in the form of a substrate.

[0086] The first baffle DM1 and the second baffle DM2 can be disposed in the non-display area NA, above the interlayer insulating layer 160. When the organic layer 392 of the encapsulation layer EN is provided, the first baffle DM1 and the second baffle DM2 can prevent the outflow of organic materials (such as monomers), and therefore, the edge of the organic layer 392 of the encapsulation layer EN can be disposed at least inside the second baffle DM2, that is, between the second baffle DM2 and the display area DA, or between the first baffle DM1 and the display area DA. The first inorganic layer 391 and the second inorganic layer 393 constituting the encapsulation layer EN can extend above the first baffle DM1 and the second baffle DM2. In this case, the contact area between the first inorganic layer 391 and the second inorganic layer 393 can be increased to increase the adhesion between the first inorganic layer 391 and the second inorganic layer 393. The first inorganic layer 391 can contact the surfaces of the first baffle DM1 and the second baffle DM2.

[0087] The first baffle DM1 can be positioned closer to the display area DA than the second baffle DM2. The first baffle DM1 can surround the display area DA, and the second baffle DM2 can surround both the display area DA and the first baffle DM1. The second baffle DM2 can be higher than the first baffle DM1, or vice versa, but is not limited thereto, and the first baffle DM1 and the second baffle DM2 can be substantially the same.

[0088] The first baffle DM1 may include a first layer L11 and a second layer L12. The second layer L12 may completely cover the first layer L11. That is, the second layer L12 may not only cover the upper surface of the first layer L11, but also its side surfaces, and may contact the upper surface and side surfaces of the first layer L11. The first layer L11 may include the same material as the second planarization layer 182 in the same process as the second planarization layer 182. The second layer L12 may include the same material as the pixel defining layer 360 in the same process as the pixel defining layer 360.

[0089] The second baffle DM2 may include a first layer L21, a second layer L22, and a third layer L23. The first layer L21 may include the same material as the first planarization layer 181, processed in the same way as the first planarization layer 181. The second layer L22 may include the same material as the second planarization layer 182, processed in the same way as the second planarization layer 182. The third layer L23 may include the same material as the pixel defining layer 360, processed in the same way as the pixel defining layer 360. The second layer L22 may completely cover the first layer L21. The third layer L23 may completely cover both the second layer L22 and the first layer L21. A connecting member 195 may be disposed between the second layer L22 and the third layer L23.

[0090] When the second layer L12 of the first baffle DM1 is composed of or includes the same material as the pixel defining layer 360 in the same process as the pixel defining layer 360, the second layer L12 can be fully exposed after the photolithography process and before curing. Therefore, the second layer L12 can be provided such that, in areas not overlapping with the first layer L11, the first height h1 of the portion adjacent to its edge can be greater than its internal reference height h0. For convenience, in Figure 3A and Figure 3BIn this embodiment, although the thickness of the second layer L12 is represented by a first height h1 and a reference height h0, the first height h1 and the reference height h0 are intended to be the height from the surface of the substrate 110. In this embodiment, the portion having the first height h1 can be about 1.0 micrometers (μm) away from the edge to about 2.0 μm, and the first height h1 can be about 0.3 μm to about 0.5 μm greater than the reference height h0. The first height h1 can be in the range of about 1.5 μm to about 2.2 μm. As described above, the portion having the first height h1, which is greater than the reference height h0, can be used as an overflow protrusion of the material for forming the organic layer 392 of the encapsulation layer EN, and can effectively prevent the material forming the organic layer 392 from crossing the first baffle DM1.

[0091] The reference height h0 and the first height h1 can be inflection points in the curve defined by the upper surface of the second layer L12 in the cross-sectional view. That is, the second layer L12 can gradually decrease to the reference height h0 along the direction towards the edge, gradually increase to the first height h1 after passing the reference height h0, and gradually decrease after passing the first height h1. In an embodiment, the cone angle of the second layer L12 can be about 45° or greater, for example, about 45° to about 65°.

[0092] When the third layer L23 of the second baffle DM2 is made of the same material as the pixel defining layer 360 in the same process as the pixel defining layer 360, the third layer L23 can be fully exposed after the photolithography process and before curing. The third layer L23 may have the structure and features corresponding to the edge portion of the second layer L12 of the first baffle DM1 described above.

[0093] A crack baffle CD may be positioned near the edge of the display panel 10. When an impact or stress is applied to the edge of the display panel 10, a crack may form in the insulating layer 111, buffer layer 120, first gate insulating layer 141, second gate insulating layer 142, and interlayer insulating layer 160 (these may be inorganic insulating layers) to propagate. At least a portion of the inorganic insulating layer may be removed near the edge of the display panel 10, and the crack baffle CD may cover the removed portion to prevent such crack propagation. The crack baffle CD may be a single layer or multiple layers and may include the same material as the first planarization layer 181, second planarization layer 182, and / or pixel defining layer 360 in the same process as the process of the first planarization layer 181, second planarization layer 182, and / or pixel defining layer 360. When the crack baffle CD is made of the same material as the pixel defining layer 360 in the same process as the pixel defining layer 360, the crack baffle CD may have the structure and features of the second layer L12 corresponding to the first baffle DM1 described above.

[0094] A protective film 50 may be disposed on the rear surface of the substrate 110. The protective film 50 protects the substrate 110 from the effects of physical contact by covering the rear surface of the substrate 110. The protective film 50 may be attached to the rear surface of the substrate 110 by an adhesive, or may be provided by coating the rear surface of the substrate 110 with resin and curing it.

[0095] The bending region BR will now be described. A connection wiring 179 may be provided for electrically connecting a first wiring 128 and a second wiring 129 located on opposite sides of the bending region BR. Therefore, signals output from the IC chip 30 can be transmitted to the display area DA and scan driver, etc., via the second wiring 129, the connection wiring 179, and the first wiring 128. Because the connection wiring 179 bends when the bending region BR bends, the connection wiring 179 may comprise a metal with good flexibility and a small Young's modulus. The connection wiring 179 may comprise the same material as the source electrode SE and drain electrode DE in the same process as the source electrode SE and drain electrode DE. As the flexibility of the connection wiring 179 increases, the stress against strain decreases, thereby reducing the risk of degradation (e.g., cracking) or breakage during bending.

[0096] A first protective layer 165 is disposed in the bending region BR, between the substrate 110 and the connection wiring 179. The first protective layer 165 may include an organic insulating material, such as polyimide, an acrylic polymer, or a siloxane polymer. A second protective layer 183, a third protective layer 185, and / or a fourth protective layer 365 are disposed on the connection wiring 179. The second protective layer 183, the third protective layer 185, and the fourth protective layer 365 may include materials identical to those of the first planarization layer 181, the second planarization layer 182, and the pixel defining layer 360, respectively, processed in the same process as the first planarization layer 181, the second planarization layer 182, and the pixel defining layer 360. A bending protective layer 400 may be disposed on the fourth protective layer 365 to relieve tensile stress and protect the connection wiring 179. The bending protective layer 400 may also be referred to as a stress neutralizing layer. The bending protective layer 400 may include an organic insulating material, such as acrylic resin.

[0097] The isolation layer 111, buffer layer 120, first gate insulation layer 141, second gate insulation layer 142, and interlayer insulation layer 160 (which may be inorganic insulation layers) can be removed from the bending region BR. This is because inorganic insulation layers are prone to cracking when bent, and the wiring can be damaged by the cracks.

[0098] The protective film 50 may be provided to completely cover the rear surface of the substrate 110, but it may not be provided in the bending region BR in order to reduce the bending stress in the bending region BR.

[0099] Figure 4 The diagram illustrates along Figure 1A schematic cross-sectional view of the embodiment taken along line A-A', and Figure 5 The diagram illustrates along Figure 1 A schematic cross-sectional view of the implementation method taken by line B-B'.

[0100] Figure 4 and Figure 5 The implementation method illustrated in the figure is the same as Figure 2 , Figure 3A and Figure 3B The difference in the embodiment illustrated in the diagram lies in the first baffle DM1 and the second baffle DM2. Specifically, the first baffle DM1 may include a first layer L11, a second layer L12, and a third layer L13, and the second baffle DM2 may include a first layer L21, a second layer L22, a third layer L23, and a fourth layer L24. That is, compared with... Figure 2 , Figure 3A and Figure 3B Compared to the first baffle DM1 and the second baffle DM2 shown in the figure, the first baffle DM1 further includes a third layer L13 on the second layer L12, and the second baffle DM2 further includes a fourth layer L24 on the third layer L23.

[0101] The third layer L13 of the first baffle DM1 and the fourth layer L24 of the second baffle DM2 may comprise an organic insulating material, such as an acrylic polymer, an imide polymer, or an amide polymer. The third layer L13 and the fourth layer L24 may comprise the same material as the spacer (not shown) formed on the pixel defining layer 360 in the display area DA, using the same process as that used to form the spacer (not shown) on the pixel defining layer 360 in the display area DA. The spacer may be formed to contact a mask used during the deposition of the emitter layer EL to prevent damage to the previously formed structure. Even though the third layer L13 and the fourth layer L24 are located on the second layer L12 and the third layer L23, respectively, the second layer L12 and the third layer L23 may have structures and features corresponding to those described above for the second layer L12 and the third layer L23.

[0102] Figure 6 The illustration shows an electron micrograph of the pixel-defining layer in an embodiment of the display panel, and Figure 7 The illustration shows an electron micrograph of the pixel-defining layer in a comparative example of a display panel. Figure 8 The diagram illustrates the cone angle of the pixel-defining layer in an embodiment of the display panel and a comparative example of the display panel. Figure 9 The diagram illustrates the width of the opening in the pixel-defining layer in both an embodiment of the display panel and a comparative example of the display panel.

[0103] Figure 6In the embodiment illustrated in the figure, the pixel-defining layer 360 of the display panel is provided by coating a black photoresist and patterning it through a photolithography process, followed by full exposure and curing. Figure 7 The pixel-defining layer of the comparative example display panel illustrated in the middle is provided by coating a black photoresist and patterning it through a photolithography process, followed by curing. This is used to form... Figure 6 In the 360 ​​pixel-limiting layer process, with Figure 7 Compared to the pixel-limiting layer, a full exposure process is added between the photolithography process and the curing process.

[0104] refer to Figure 6 The first height h1 of the portion adjacent to the edge of the opening OP of the defined pixel layer 360 is greater than the reference height h0 of the portion set to be farther from the opening OP than the portion having the first height h1. In contrast, the reference height h0 is greater than the reference height h0. Figure 7 The height gradually increases as the distance from the edge of the pixel-limited layer increases.

[0105] refer to Figure 8 The cone angles of pixel-defining layers #1-1, #1-2, #1-3, and #1-4 in an embodiment of display panel 10 are illustrated on its left side, and the cone angles of pixel-defining layers #2-1, #2-2, #2-3, and #2-4 in a comparative example of display panel are illustrated on its right side. The pixel-defining layers in this embodiment have cone angles ranging from approximately 58° to approximately 61°. The comparative example of pixel-defining layers has cone angles ranging from approximately 22° to 26°. The cone angles of the embodiment of pixel-defining layers are approximately 2.5 times larger than those of the comparative example. This is because, as in this embodiment, the flow rate of photoresist is reduced through sufficient exposure before curing.

[0106] refer to Figure 9 The two left box plots in the four box plots represent the width of the openings in the pixel-defining layer before and after curing in the embodiment of display panel 10, and the two right box plots represent the width of the openings in the pixel-defining layer before and after curing in the comparative example of display panel. In both the embodiment and the comparative example, the width of the openings in the pixel-defining layer is reduced after curing compared to the previous embodiment. This is because the shape of the openings changes due to the flow of photoresist during curing. After curing, the standard deviation of the opening width in the embodiment of pixel-defining layer is 0.16, but the standard deviation of the opening width in the comparative example of pixel-defining layer is 0.32. These results show that by performing sufficient exposure before curing as in the embodiment, the dispersion of the openings in the pixel-defining layer is significantly improved.

[0107] Figure 10The illustration shows electron micrographs of the edge portion of the first baffle in an embodiment of the display panel and a comparative example of the display panel. Figure 11 The illustration shows an electron micrograph of the edge portion of the second baffle in an embodiment of the display panel and a comparative example of the display panel.

[0108] Figure 10 The portion shown in the diagram corresponds to the second layer L12 of the first baffle DM1, and... Figure 11 The portion shown in the diagram corresponds to the third layer L23 of the second baffle DM2. The second layer L12 of the first baffle DM1 and the third layer L23 of the second baffle DM2 are made of the same material as the pixel defining layer 360 in the same process as the pixel defining layer 360. Therefore, the black photoresist is patterned and exposed before curing.

[0109] refer to Figure 10 In a comparative example of the display panel, the height of the second layer of the first baffle gradually decreases towards its edge. In the embodiment of the display panel, the height of the second layer L12 of the first baffle DM1 is substantially constant, and then decreases relatively rapidly along the direction towards its edge. (Reference) Figure 11 In a comparative example of the display panel, the height of the third layer of the second baffle gradually decreases towards its edge. In the embodiment of the display panel, the height of the third layer L23 of the second baffle DM2 is substantially constant, increases slightly, and then decreases relatively rapidly along the direction towards its edge. This morphological characteristic of the first baffle DM1 and the second baffle DM2 is believed to be due to the fact that the photoresist undergoes further photopolymerization and photocuring through sufficient exposure, thereby inhibiting the flow of the photoresist during curing.

[0110] Figure 12 The illustration shows an electron micrograph of the edge portion of the first baffle in an embodiment of the display panel.

[0111] Figure 12 The photomicrographs show Figure 10The micrograph shows the cross-sectional structure of the second layer L12 of the first baffle DM1, but corresponding to the edge portion away from the display area DA. The height of the second layer L12 of the first baffle DM1 gradually decreases, slightly increases, and then rapidly decreases along the direction toward its edge. That is, the second layer L12 includes a portion P0 with a gradually decreasing height, a portion P1 with a gradually increasing height, and a portion P2 with a height that gradually decreases and then rapidly decreases along the direction toward the edge. Due to this height change, the first height h1 of the portion adjacent to the edge (e.g., the boundary between portions P1 and P2) is greater than the reference height h0 of its inner side (e.g., the boundary between portions P0 and P1). Herein, as described above, the first height h1 and the reference height h0 each indicate the height from the surface of the substrate 110. In addition, the second layer L12 includes a portion P3 that is slightly recessed from its side surface. Therefore, there may be three inflection points in the curve defined by the upper surface and side surface of the edge portion of the second layer L12. The cone angle was measured to be 60.8°.

[0112] Figure 13 The diagram illustrates an equivalent circuit diagram of an embodiment of pixels in a display device.

[0113] refer to Figure 13 The pixel PX may include transistors T1 to T7 connected to signal lines 127, 151, 152, 153, 158, 171 and 172, a storage capacitor CS, and a light-emitting diode LED.

[0114] Transistors T1 to T7 include a driving transistor T1, a switching transistor T2, a compensation transistor T3, an initialization transistor T4, an operation control transistor T5, an emitter control transistor T6, and a bypass transistor T7.

[0115] Signal lines 127, 151, 152, 153, 158, 171, and 172 may include initialization voltage line 127, scan line 151, pre-stage scan line 152, transmit control line 153, bypass control line 158, data line 171, and drive voltage line 172.

[0116] Scan line 151 transmits the scan signal GW to switching transistor T2 and compensation transistor T3. Pre-stage scan line 152 transmits the pre-stage scan signal GI to initialization transistor T4. Emit control line 153 transmits the emit control signal EM to operation control transistor T5 and emit control transistor T6. Bypass control line 158 transmits the bypass signal GB to bypass transistor T7. Bypass control line 158 can be connected to pre-stage scan line 152.

[0117] Data line 171 can receive the data voltage Vdat, and drive voltage line 172 and initialization voltage line 127 can receive the drive voltage ELVDD and the initialization voltage Vint, respectively. The initialization voltage Vint can initialize the drive transistor T1.

[0118] Each transistor T1 to T7 includes gate electrodes G1 to G7, source electrodes S1 to S7, and drain electrodes D1 to D7, and the storage capacitor CS includes a first electrode C1 and a second electrode C2. The electrodes of transistors T1 to T7 and the storage capacitor CS can be as follows: Figure 13 The connection is shown in the diagram. The anode of the light-emitting diode (LED), which can be an organic light-emitting diode, is connected to the drain electrode D1 of the driving transistor T1 via the emitter control transistor T6 to receive the drive current Id. The cathode of the LED can receive the common voltage ELVSS.

[0119] In the circuit structure of a pixel PX, various modifications can be made to the number of transistors, the number of capacitors, and the connections between them.

[0120] Reference Figure 14 Describe the cross-sectional structure of the display panel in the embodiment.

[0121] Figure 14 The illustration shows a schematic cross-sectional view of an implementation of a pixel area in a display panel. Although referenced... Figure 2 as well as Figure 3A and Figure 3B The cross-sectional structure is described, but further description will be given focusing on the display area DA.

[0122] refer to Figure 14 The display panel 10 may have a structure in which several layers, wiring and components are stacked on the substrate 110 to configure and drive the pixels PX.

[0123] An isolation layer 111 and a buffer layer 120 may be disposed on the flexible substrate 110. The semiconductor layer AL of the transistor TR may be disposed on the buffer layer 120.

[0124] A first gate insulating layer 141 may be disposed on the semiconductor layer AL. A first gate conductor, including the gate electrode GE of the transistor TR, the bypass control line 158, and the first electrode C1 of the storage capacitor CS, may be disposed on the first gate insulating layer 141. The gate electrode GE may overlap with the channel region of the semiconductor layer AL.

[0125] A second gate insulating layer 142 may be disposed on the first gate conductor. A second gate conductor, which may include a second electrode C2 of a storage capacitor CS, may be disposed on the second gate insulating layer 142. An interlayer insulating layer 160 may be disposed on the second gate conductor.

[0126] A first data conductor, which may include the source electrode SE and drain electrode DE of transistor TR, initialization voltage line 127, scan line 151, pre-stage scan line 152, and emitter control line 153, may be disposed on interlayer insulating layer 160. At least one of initialization voltage line 127, scan line 151, pre-stage scan line 152, and emitter control line 153 may be included in a first gate conductor or a second gate conductor.

[0127] A first planarization layer 181 may be disposed on a first data conductor. A second data conductor, including a data line 171, a drive voltage line 172, and a connection electrode LE, may be disposed on the first planarization layer 181. The data line 171 and / or the drive voltage line 172 may be included in the first data conductor. A second planarization layer 182 may be disposed on the second data conductor.

[0128] The first electrode E1 of the light-emitting diode (LED) is disposed on the second planarization layer 182. The first electrode E1 can be electrically connected to the drain electrode DE via the connecting electrode LE.

[0129] A black pixel defining layer 360, which defines an opening OP overlapping the first electrode E1, may be disposed on the second planarization layer 182. An emission layer EL may be disposed on the first electrode E1, and a second electrode E2 of a light-emitting diode (LED) may be disposed on the emission layer EL. At least one protective layer or functional layer may be disposed on the second electrode E2.

[0130] An encapsulation layer EN may be disposed on the second electrode E2. The encapsulation layer EN may be a thin-film encapsulation layer comprising one or more inorganic layers and one or more organic layers stacked on the second electrode E2. The encapsulation layer EN may be provided in the form of a substrate.

[0131] A touch sensor layer TS, including touch electrodes TE, may be disposed on the encapsulation layer EN. The touch sensor layer TS can be used to sense user contact and / or non-contact touch. The touch electrodes TE may include a metal mesh, a transparent conductive material, or a conductive polymer, etc. The touch sensor layer TS may be disposed on the encapsulation layer EN, or it may be disposed on a separate substrate for attachment to the encapsulation layer EN. An inorganic insulating layer may be disposed between the encapsulation layer EN and the touch sensor layer TS.

[0132] A light-blocking member 220 may be disposed on the touch sensor layer TS. The light-blocking member 220 may include black pigment or dye and may reduce or prevent light reflection caused by the metal layer of the display panel 10, etc. The light-blocking member 220 may be configured not to overlap with the opening OP, which is the emission area. The light-blocking member 220 may also be referred to as a black matrix.

[0133] A color filter 230 may be disposed on the touch sensor layer TS. The color filter 230 may transmit any of red, green, and blue light. Color filters 230 representing different colors may overlap in the area where they overlap with the light-blocking member 220. The color filter 230 and the light-blocking member 220 may be combined to serve as an anti-reflective layer. In this structure, a polarizing layer may not be desired as an anti-reflective layer, and the thickness of the display panel 10 can be reduced. The color filter 230 may include quantum dots or phosphors and may convert light emitted by a light-emitting diode (LED) into red or green light. An outer coating 240 may be disposed on the color filter 230.

[0134] The protective film 50 can be disposed under the substrate 110.

[0135] Although the invention has been described in conjunction with embodiments which are now considered practical, it is to be understood that the invention is not limited to the disclosed embodiments, but rather is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the appended claims.

Claims

1. A display device, comprising: The substrate includes both the display area and the non-display area; A black pixel-limiting layer is provided in the display area; Light-emitting elements disposed in the display area; The encapsulation layer covering the light-emitting element; and A baffle disposed in the non-display area and surrounding the display area. The baffle includes a first organic layer and a second organic layer on the first organic layer. The second organic layer comprises the same material as the black pixel defining layer. The second organic layer includes a portion whose height decreases and then increases towards the edge of the second organic layer. The second organic layer comprises a first portion adjacent to the edge and a second portion disposed inside the first portion. The height of the first portion from the surface of the substrate is 0.3 μm to 0.5 μm greater than the height of the second portion from the surface of the substrate. The curve defined by the upper and side surfaces of the edge portion of the second organic layer in the cross-sectional view includes at least three inflection points.

2. The display device as claimed in claim 1, wherein: The second organic layer comprises a black photoresist.

3. The display device as claimed in claim 1, further comprising: The power supply voltage transmission line is located in the non-display area, and The second organic layer includes a portion that contacts the power supply voltage transmission line.

4. The display device as claimed in claim 3, further comprising: A connecting component that electrically connects the electrodes of the light-emitting element and the power supply voltage transmission line. The second organic layer includes a portion that contacts the connecting member.

5. The display device as claimed in claim 3, further comprising: An insulating layer disposed between the substrate and the power supply voltage transmission line. The second organic layer includes a portion that contacts the insulating layer.

6. The display device as claimed in claim 1, wherein: The encapsulation layer includes an inorganic layer that extends over and contacts the second organic layer.

7. The display device as claimed in claim 1, The black pixel defining layer defines the opening, and The height of a first portion of the black pixel defining layer adjacent to the edge of the black pixel defining layer used to define the opening is greater than the height of a second portion that is set to be farther from the opening than the first portion is from the opening.

8. The display device of claim 7, further comprising: A light-blocking component and a color filter disposed on and overlapping the black pixel defining layer.

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