Three-dimensional packaging structure and packaging method of a superconducting quantum chip

Abstract

The present invention discloses a three-dimensional packaging structure and a packaging method for a superconducting quantum chip. The three-dimensional packaging structure includes: a quantum chip, a control circuit chip, a first connection part, and a second connection part; a first surface of the quantum chip faces a first surface of the control circuit chip and is bonded to the first surface of the control circuit chip through a superconducting material; the first connection part is supported between the first surface of the quantum chip and the first surface of the control circuit chip, and during the bonding process, the dimension of the first connection part in the bonding pressure direction remains unchanged; and either the first surface of the quantum chip or the first surface of the control circuit chip is fixedly connected to one end of the first connection part, the other is fixedly connected to one end of the second connection part, and the first connection part further cooperates with the second connection part to form a fitting structure. The three-dimensional packaging structure for the superconducting quantum chip provided by the present invention can accurately control the distance between the quantum chip and the control circuit chip, and has a high bonding strength.

Description

Technical Field

[0001] The present invention belongs to the technical field of superconducting quantum chip packaging, and particularly relates to a three-dimensional packaging structure and a packaging method for a superconducting quantum chip. Background Art

[0002] With the gradual deepening of the application of quantum computing, quantum chips with more qubits have received attention. Two-dimensional chips can no longer meet the requirements of the layout of qubit arrays and control lines. Three-dimensional packaging can break through the limitation of two-dimensional space, place quantum bits and control circuits on two chips respectively, and use flip-chip bonding to weld the corresponding welding points to form a path, realizing the high-density integration of superconducting quantum chips and promoting the rapid development of quantum computing technology. In this process, it is necessary to precisely control the distance between the two chips and require a high bonding strength.

[0003] In the prior art, generally, silicon pillar bumps are etched on the bottom chip, and then the top chip and the bottom chip are bonded together, and the distance between the two chips is controlled by the silicon pillar bumps. This method has certain defects. One disadvantage is that it can only be realized on a silicon substrate, and there are limitations in use; another disadvantage is that the silicon substrate itself will be damaged during the process of forming silicon pillar bumps by dry etching, affecting the chip performance.

[0004] Therefore, how to provide a three-dimensional packaging structure and a packaging method that can not only precisely control the chip distance but also not affect the performance of the chip itself is an urgent problem to be solved. Summary of the Invention

[0005] The main object of the present invention is to provide a three-dimensional packaging structure and a packaging method for a superconducting quantum chip to overcome the deficiencies of the prior art.

[0006] To achieve the foregoing invention object, the technical solutions adopted by the present invention include:

[0007] An embodiment of the present invention provides a three-dimensional packaging structure for a superconducting quantum chip, which includes: a quantum chip, a control circuit chip, a first connection part, and a second connection part;

[0008] The first surface of the quantum chip faces the first surface of the control circuit chip and is bonded to the first surface of the control circuit chip through a superconducting material;

[0009] The first connection part is supported between the first surface of the quantum chip and the first surface of the control circuit chip. During the bonding process, the dimension of the first connection part in the bonding pressure direction remains unchanged;

[0010] Moreover, either the first side of the quantum chip or the first side of the control circuit chip is fixedly connected to one end of the first connecting portion, and the other is fixedly connected to one end of the second connecting portion, and the first connecting portion further cooperates with the second connecting portion to form a fitting structure.

[0011] An embodiment of the present invention further provides a three-dimensional packaging method for a superconducting quantum chip, which includes:

[0012] Fabricate a first connecting portion on either the first side of the quantum chip or the first side of the control circuit chip, and fabricate a second connecting portion on the other;

[0013] Make the first side of the quantum chip face the first side of the control circuit chip, and make each first connecting portion correspond to a corresponding second connecting portion;

[0014] Apply pressure between the quantum chip and the control circuit chip to bond the quantum chip and the control circuit chip through superconducting materials, and make the first connecting portion support between the first side of the quantum chip and the first side of the control circuit chip, and make each first connecting portion further cooperate with a corresponding second connecting portion to form a fitting structure;

[0015] During the bonding process, the dimension of the first connecting portion in the direction of the pressure remains unchanged.

[0016] Compared with the prior art, the beneficial effects of the present invention are as follows:

[0017] (1) The provided three-dimensional packaging structure of the superconducting quantum chip, by providing a first connecting portion with a hardness greater than that of the superconducting material on either the quantum chip or the control circuit chip, and a second connecting portion on the other, on the one hand, can precisely control the distance between the quantum chip and the control circuit chip by controlling the dimension of the first connecting portion, and on the other hand, form a tight and firm fitting structure through the first connecting portion and the second connecting portion, thereby strengthening the bonding strength between the quantum chip and the control circuit chip and improving the stability and reliability of the packaging structure.

[0018] (2) The provided three-dimensional packaging method for the superconducting quantum chip does not require etching the substrate of the chip or the control circuit chip, and does not affect the performance of the entire superconducting quantum chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings required for the description of the embodiments or the prior art. Obviously, the drawings in the following description are only some embodiments recorded in the present invention. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0020] Figure 1 It is a schematic diagram of a three-dimensional packaging structure of a superconducting quantum chip provided in Embodiment 1 of the present invention;

[0021] Figure 2 It is a schematic diagram of the structure of the three-dimensional packaging structure of the superconducting quantum chip in Embodiment 1 of the present invention before bonding;

[0022] Figures 3A to 3E It is a schematic diagram of the manufacturing process of the second connection part of the three-dimensional packaging structure of the superconducting quantum chip in Embodiment 1 of the present invention;

[0023] Figures 4A to 4E It is a schematic diagram of the manufacturing process of the first connection part of the three-dimensional packaging structure of the superconducting quantum chip in Embodiment 1 of the present invention;

[0024] Figures 5A to 5C They are actual measurement diagrams of the chip pitch at different positions of the three-dimensional packaging structure of the superconducting quantum chip in Embodiment 1 of the present invention respectively;

[0025] Figure 6 It is a schematic diagram of a three-dimensional packaging structure of a superconducting quantum chip provided in Embodiment 2 of the present invention;

[0026] Figure 7 It is a schematic diagram of the structure of the three-dimensional packaging structure of the superconducting quantum chip in Embodiment 2 of the present invention before bonding;

[0027] Figures 8A to 8E It is a schematic diagram of a manufacturing process of the first connection part of the three-dimensional packaging structure of the superconducting quantum chip in Embodiment 2 of the present invention;

[0028] Figures 9A to 9E It is another schematic diagram of the manufacturing process of the first connection part of the three-dimensional packaging structure of the superconducting quantum chip in Embodiment 2 of the present invention;

[0029] Figure 10 It is a physical diagram of the first connection part of the three-dimensional packaging structure of the superconducting quantum chip in Embodiment 2 of the present invention;

[0030] Figure 11 It is a physical diagram of another first connection part of the three-dimensional packaging structure of the superconducting quantum chip in Embodiment 2 of the present invention. Detailed implementation manners

[0031] In view of the deficiencies of the prior art, the inventors of this case have, through long-term research and a large amount of practice, been able to propose the technical solution of the present invention. By fabricating a support structure with a fixed height that is harder than the welding material in the peripheral area of the chip (such as the four corners of the chip), it is possible to precisely control the distance between the two chips during the chip bonding process, and at the same time enhance the bonding strength between the chips without affecting the performance of the chips themselves. The technical solution of the present invention will be clearly and completely described as follows.

[0032] One aspect of an embodiment of the present invention provides a three-dimensional packaging structure for a superconducting quantum chip, which includes: a quantum chip, a control circuit chip, a first connection part, and a second connection part;

[0033] The first surface of the quantum chip faces the first surface of the control circuit chip and is bonded to the first surface of the control circuit chip through a superconducting material;

[0034] The first connection part is supported between the first surface of the quantum chip and the first surface of the control circuit chip. During the bonding process, the dimension of the first connection part in the bonding pressure direction remains unchanged;

[0035] Moreover, either the first surface of the quantum chip or the first surface of the control circuit chip is fixedly connected to one end of the first connection part, and the other is fixedly connected to one end of the second connection part, and the first connection part also cooperates with the second connection part to form a fitting structure.

[0036] Further, one end of the first connection part is fixed to the first surface of the quantum chip, and the other end abuts against the first surface of the control circuit chip. One end of the second connection part is fixed to the first surface of the control circuit chip; or one end of the first connection part is fixed to the first surface of the control circuit chip, and the other end abuts against the first surface of the quantum chip. One end of the second connection part is fixed to the first surface of the quantum chip.

[0037] Further, one end of the second connection part is fixed to the first surface of the control circuit chip, and the other end contacts the first surface of the quantum chip; or one end of the second connection part is fixed to the first surface of the quantum chip, and the other end contacts the first surface of the control circuit chip.

[0038] Further, both the first connection part and the second connection part are multiple and are arranged around the superconducting material, and each first connection part cooperates with a corresponding second connection part.

[0039] Further, the first connecting portion includes a hard material protrusion provided on either the first surface of the quantum chip or the first surface of the control circuit chip, and the second connecting portion includes a ductile material protrusion provided on the other of the first surface of the quantum chip and the first surface of the control circuit chip.

[0040] Further, the hard material includes any one or a combination of tantalum, copper, aluminum, etc., and is not limited thereto.

[0041] In some embodiments, the hard material may also be an inorganic material such as a ceramic material.

[0042] Further, the ductile material includes any one or a combination of indium, tin, etc., and is not limited thereto.

[0043] In some embodiments, the ductile material may also be a polymer organic material that can be patterned and has a certain bonding strength.

[0044] Further, part or all of a first connecting portion is embedded in a corresponding second connecting portion, or part or all of a second connecting portion is embedded in a corresponding first connecting portion.

[0045] In some embodiments, holes or grooves may be formed in the first connecting portion, and the diameter of the opening of the hole or groove is smaller than the inner diameter of the hole or groove, and the second connecting portion is partially or wholly filled in the hole or groove.

[0046] In some other embodiments, the first connecting portion may be a hollow tube with one end open, and the hollow tube is partially or wholly inserted into the second connecting portion.

[0047] Further, the superconducting material includes any one or a combination of indium, aluminum, niobium, tin, titanium, osmium, zinc, molybdenum, tantalum, vanadium, etc., and is not limited thereto.

[0048] Another aspect of the embodiments of the present invention also provides a three-dimensional packaging method for a superconducting quantum chip, which includes:

[0049] Fabricate a first connecting portion on either the first surface of the quantum chip or the first surface of the control circuit chip, and fabricate a second connecting portion on the other;

[0050] Make the first surface of the quantum chip face the first surface of the control circuit chip, and arrange each first connecting portion corresponding to a corresponding second connecting portion;

[0051] Apply pressure between the quantum chip and the control circuit chip, so that the quantum chip and the control circuit chip are bonded through a superconducting material, and the first connecting portion is supported between the first surface of the quantum chip and the first surface of the control circuit chip, and each first connecting portion further cooperates with a corresponding second connecting portion to form a fitting structure;

[0052] During the bonding process, the dimension of the first connecting portion in the pressure direction remains unchanged.

[0053] Further, form the first connecting portion on the first surface of the quantum chip with a hard material, and form the second connecting portion on the first surface of the control circuit chip with a ductile material; or, form the first connecting portion on the first surface of the control circuit chip with a hard material, and form the second connecting portion on the first surface of the quantum chip with a ductile material.

[0054] Wherein, the hard material includes any one or a combination of tantalum, copper, aluminum, etc., and the ductile material includes any one or a combination of indium, tin, etc.

[0055] Further, the three-dimensional packaging method specifically includes:

[0056] Fabricate a first connecting portion with holes or grooves on its surface, the diameter of the mouth of the hole or groove is smaller than the inner diameter of the hole or groove, and make the second connecting portion partially or completely fill the hole or groove under the action of the pressure;

[0057] Or, fabricate a hollow tube with one end open as the first connecting portion, and make the first connecting portion partially or integrally insert into the second connecting portion under the action of the pressure.

[0058] Next, the technical solution of the present invention will be further explained in conjunction with the drawings and several typical embodiments. Unless otherwise specified, the technical means used in the embodiments of the present invention can be well-known to those skilled in the art.

[0059] Embodiment 1

[0060] Please refer to Figure 1-2 , which is a three-dimensional packaging structure of a superconducting quantum chip in this embodiment, including a quantum chip 1 and a control circuit chip 2. The first surface of the quantum chip 1 faces the first surface of the control circuit chip 2 and is bonded to the first surface of the control circuit chip 2 through indium pillars 3.

[0061] Among them, a first connection portion is respectively provided at the four corners of the first surface of the control circuit chip 2, and a second connection portion is respectively provided at the four corners of the first surface of the quantum chip 1. One end of each first connection portion is fixedly connected to the first surface of the control circuit chip 2, and the other end abuts against the first surface of the quantum chip 1. One end of each second connection portion is fixedly connected to the first surface of the quantum chip 1, and the other end is in contact with the first surface of the control circuit chip 2.

[0062] Specifically, the first connection portion is a copper column 4 formed by processing hard material copper, and a hole 41 is provided in the middle of the copper column 4. The aperture of the hole 41 gradually becomes smaller in the direction away from the control circuit chip 2, and the second connection portion is a tin column 5 formed by processing ductile material tin.

[0063] Specifically, when the first surface of the quantum chip 1 is bonded to the first surface of the control circuit chip 2, the copper column 4 supports between the first surface of the quantum chip 1 and the first surface of the control circuit chip 2, and the distance between the first surface of the quantum chip 1 and the first surface of the control circuit chip 2 can be accurately controlled by the size of the copper column 4. The tin column 5 is completely filled in the hole 41 of the copper column 4, so that a tight and firm fitting structure is formed between the tin column 5 and the copper column 4. At the same time, since the diameter of the mouth of the hole 41 is smaller than the inner diameter, the combination between the tin column 5 and the copper column 4 can be enhanced, thereby strengthening the bonding strength between the quantum chip 1 and the control circuit chip 2.

[0064] In the three-dimensional packaging structure of this embodiment, on the one hand, the first connection portion formed by the copper column 4 supports between the quantum chip 1 and the control circuit chip 2, and thus the distance between the quantum chip 1 and the control circuit chip 2 can be accurately controlled; on the other hand, by completely filling the second connection portion formed by the soft tin column 5 into the hole 41 of the copper column 4 to form a tight and firm combination, the bonding strength between the quantum chip 1 and the control circuit chip 2 can be strengthened, and the reliability and stability of the packaging can be improved.

[0065] In addition, this embodiment also provides a three-dimensional packaging method for the superconducting quantum chip, which includes:

[0066] Using hard material copper to process copper columns 4 at the four corners of the first surface of the control circuit chip 2 as the first connection portions, wherein holes 41 are provided on the copper columns 4, and the aperture of the holes 41 gradually becomes smaller in the direction away from the control circuit chip 2;

[0067] Using ductile material tin to process tin columns 5 at the four corners of the first surface of the quantum chip 1 corresponding to the copper columns 4 as the second connection portions;

[0068] Apply pressure between the quantum chip 1 and the control circuit chip 2, so that the quantum chip 1 and the control circuit chip 2 are bonded through indium pillars 3, and make the copper pillars 4 support between the first surface of the quantum chip 1 and the first surface of the control circuit chip 2, and make the tin pillars 5 completely fill the holes 41 of the copper pillars 4 to form an embedded structure. During the bonding process, the size of the copper pillars 4 in the bonding pressure direction remains unchanged.

[0069] Specifically, please refer to Figures 3A-3E , and the process of processing the tin pillars 5 specifically includes:

[0070] Step 1: Spin-coat a negative photoresist 7 on the substrate 6 of the quantum chip 1;

[0071] Step 2: Perform mask exposure on the side of the substrate 6 coated with the negative photoresist 7 through light 8. The mask structure is not shown in the figure. It can be understood that the light 8 represents the light passing through the mask, and no more description will be given here;

[0072] Step 3: Develop the exposed substrate 6 to remove the negative photoresist 7 in the exposed part, and pre-form a gap 9 corresponding to the tin pillar 5;

[0073] Step 4: Evaporate metallic tin on the side of the substrate 6 coated with the negative photoresist 7 to form a metallic tin layer 10 with a fixed thickness on the surface of the negative photoresist 7 and the surface of the substrate 6 corresponding to the tin pillar 5;

[0074] Step 5: Remove the metallic tin layer 10 on the surface of the negative photoresist 7 and the negative photoresist 7 in sequence to complete the production of the tin pillar 5.

[0075] Furthermore, please refer to Figures 4A-4E again, and the process of processing the copper pillars 4 specifically includes:

[0076] Step 1: Spin-coat a positive photoresist 71 on the substrate 11 of the control circuit chip 2;

[0077] Step 2: Perform mask exposure on the side of the substrate 11 coated with the positive photoresist 71 through light 8;

[0078] Step 3: Develop the exposed substrate 11 to remove the positive photoresist 71 in the exposed part, and pre-form a gap 12 corresponding to the copper pillar 4;

[0079] Step 4: Evaporate metallic copper on the side of the substrate 11 coated with the positive photoresist 71 to form a metallic copper layer 13 with a fixed thickness on the surface of the positive photoresist 71 and the surface of the substrate 11 corresponding to the copper pillar 4;

[0080] Step 5: Remove the metallic copper layer 13 on the surface of the positive photoresist 71 and the positive photoresist 71 in sequence to complete the production of the copper pillar 4.

[0081] It should be noted that for the three-dimensional packaging method of the superconducting quantum chip provided in this embodiment, all other specific implementation processes involved adopt technical means well-known to those skilled in the art.

[0082] The three-dimensional packaging structure of the superconducting quantum chip formed by using the three-dimensional packaging method of this embodiment can precisely control the distance between the quantum chip 1 and the control circuit chip 2. For details, please refer to Figures 5A-5C , which are the actual measurement diagrams of the distances at different positions of the three-dimensional packaging structure of the superconducting quantum chip in this embodiment. It can be seen that the distances in each area of the quantum chip 1 and the control circuit chip 2 are basically the same, all about 10 μm.

[0083] In addition, the soft tin column 5 is completely filled into the hole 41 of the copper column 4, and because the hole 41 has a structure that is narrower at the top and wider at the bottom, a more tightly and firmly combined structure can be formed, thereby further strengthening the bonding strength between the quantum chip 1 and the control circuit chip 2 and improving the reliability and stability of the packaging.

[0084] Embodiment 2

[0085] Please refer to Figures 6-7 , which is a three-dimensional packaging structure of a superconducting quantum chip in this embodiment. It is similar to the three-dimensional packaging structure in Embodiment 1, but the difference is that the first connecting part is arranged on the first surface of the quantum chip 1, the second connecting part is arranged on the first surface of the control circuit chip 2, and the first connecting part is a hollow aluminum tube 14 formed by processing hard material aluminum, while the second connecting part is an indium column 15 formed by processing malleable material indium.

[0086] Specifically, when the first surface of the quantum chip 1 and the first surface of the control circuit chip 2 are bonded by the indium column 3, the hollow aluminum tube 14 is supported between the first surface of the quantum chip 1 and the first surface of the control circuit chip 2, and the distance between the first surface of the quantum chip 1 and the first surface of the control circuit chip 2 can be precisely controlled by the size of the hollow aluminum tube 14. At the same time, the whole hollow aluminum tube 14 is inserted into the indium column 15 to form a tightly and firmly fitting structure, thereby strengthening the bonding strength between the quantum chip 1 and the control circuit chip 2.

[0087] In addition, this embodiment also provides a packaging method for a three-dimensional packaging structure of a superconducting quantum chip, which includes:

[0088] Using hard material aluminum to process and form hollow aluminum tubes 14 at the four corners of the first surface of the quantum chip 1 as the first connecting part;

[0089] Using malleable material indium to process and form indium columns 15 at the four corners of the first surface of the control circuit chip 2 corresponding to the hollow aluminum tubes 14 as the second connecting part;

[0090] Apply pressure between the quantum chip 1 and the control circuit chip 2, so that the quantum chip 1 and the control circuit chip 2 are bonded through indium pillars 3, and the hollow aluminum tube 14 is supported between the first surface of the quantum chip 1 and the first surface of the control circuit chip 2, and the hollow aluminum tube 14 is completely inserted into the indium pillar 15 to form an embedded structure. During the bonding process, the size of the hollow aluminum tube 14 in the bonding pressure direction remains unchanged.

[0091] Specifically, please refer to Figures 8A-8E , and the process of processing the hollow aluminum tube 14 specifically includes:

[0092] Step 1: Form a spacer 16 on the substrate 6 of the quantum chip 1, and then spin-coat a negative photoresist 7, where the material of the spacer 6 can be aluminum;

[0093] Step 2: Perform mask exposure on the side of the substrate 6 coated with the negative photoresist 7 through light 8;

[0094] Step 3: Develop the exposed substrate 6 to remove the negative photoresist 7 in the exposed part, and pre-form a gap 17 corresponding to the hollow aluminum tube 14;

[0095] Step 4: Form a metal aluminum layer 18 with a fixed thickness on the surface of the negative photoresist 7 and the inner surface of the gap 17 corresponding to the hollow aluminum tube 14;

[0096] Step 5: Fill the gap 17 corresponding to the hollow aluminum tube 14 with an anti-etching material 19 (such as photoresist), and then use a metal plasma etching method to remove the metal aluminum layer 18 on the surface of the negative photoresist 7;

[0097] Step 6: Remove the remaining photoresist 7 and the anti-etching material 19 filled in the gap 17, and perform plasma cleaning to complete the production of the hollow aluminum tube 14.

[0098] Furthermore, please refer to 9A - 9E again, which is another processing method for the hollow aluminum tube 14, and it specifically includes:

[0099] Step 1: Form a spacer 16 on the substrate 6 of the quantum chip 1, and then spin-coat a negative photoresist 7, where the material of the spacer 6 can be aluminum;

[0100] Step 2: Perform mask exposure on the side of the substrate 6 coated with the photoresist 7 through light 8;

[0101] Step 3: Develop the exposed substrate 6 to remove the photoresist 7 in the exposed part, and pre-form a gap 17 corresponding to the hollow aluminum tube 14;

[0102] Step 4: Deposit metallic aluminum on the side of the substrate 6 coated with photoresist 7 to form a metallic aluminum layer 18 with a fixed thickness on the surface of the photoresist 7 and on the surface of the substrate 6 corresponding to the hollow aluminum tube 14.

[0103] Step 5: Remove the metallic aluminum layer 18 on the surface of the photoresist 7 by means of chemical mechanical polishing, and then remove the photoresist 7 to complete the fabrication of the hollow aluminum tube 14.

[0104] Compared with the first method for processing the hollow aluminum tube 14, since the metallic aluminum layer 18 on the surface of the photoresist 7 is removed by means of chemical mechanical polishing, there is no need to fill the void 17 of the hollow aluminum tube 14, and the process is simple.

[0105] Furthermore, please refer to Figure 10 for the physical diagram of the hollow aluminum tube 14 in this embodiment. It is a cylindrical tubular structure, but in some embodiments, the hollow aluminum tube 14 can also be processed into other shapes with a hollow interior, such as Figure 11 shown.

[0106] In addition, the fabrication process of the indium posts 15 of the second connection part in this embodiment is the same as that of the tin posts 5 in Embodiment 1, and only the corresponding metallic materials need to be changed, so no further description will be given here.

[0107] In addition, the inventor of this case also made tests with other raw materials, process operations, and process conditions described in this specification with reference to the above embodiments, and all obtained relatively ideal results.

[0108] It should be understood that the technical solution of the present invention is not limited to the limitations of the above specific embodiments. Any technical deformation made according to the technical solution of the present invention without departing from the spirit of the present invention and the scope protected by the claims falls within the protection scope of the present invention.

Claims

1. A three-dimensional packaging structure for a superconducting quantum chip, characterized in that it includes a quantum chip, a control circuit chip, a first connection part and a second connection part; The first surface of the quantum chip faces the first surface of the control circuit chip and is bonded to the first surface of the control circuit chip through a superconducting material; The first connection part is supported between the first surface of the quantum chip and the first surface of the control circuit chip. During the bonding process, the dimension of the first connection part in the bonding pressure direction remains unchanged; And, either the first surface of the quantum chip or the first surface of the control circuit chip is fixedly connected to one end of the first connection part, and the other is fixedly connected to one end of the second connection part. The first connection part includes a hard material protrusion provided on either the first surface of the quantum chip or the first surface of the control circuit chip. The second connection part includes a ductile material protrusion provided on the other of the first surface of the quantum chip and the first surface of the control circuit chip. Moreover, part or all of one first connection part is embedded in a corresponding second connection part, or part or all of one second connection part is embedded in a corresponding first connection part. A hole or groove is provided on the first connection part, and the diameter of the opening of the hole or groove is smaller than the internal diameter of the hole or groove. The second connection part is partially or wholly filled in the hole or groove, and the first connection part and the second connection part cooperate to form an interference fit structure.

2. The three-dimensional packaging structure for a superconducting quantum chip according to claim 1, characterized in that, One end of the first connection part is fixed to the first surface of the quantum chip, and the other end abuts against the first surface of the control circuit chip. One end of the second connection part is fixed to the first surface of the control circuit chip; Or, one end of the first connection part is fixed to the first surface of the control circuit chip, and the other end abuts against the first surface of the quantum chip. One end of the second connection part is fixed to the first surface of the quantum chip.

3. The three-dimensional packaging structure for a superconducting quantum chip according to claim 2, characterized in that, One end of the second connection part is fixed to the first surface of the control circuit chip, and the other end is in contact with the first surface of the quantum chip; Or, one end of the second connection part is fixed to the first surface of the quantum chip, and the other end is in contact with the first surface of the control circuit chip.

4. The three-dimensional packaging structure for a superconducting quantum chip according to any one of claims 1-3, characterized in that, Both the first connection part and the second connection part are multiple and are arranged around the superconducting material, and each first connection part cooperates with a corresponding second connection part.

5. The three-dimensional packaging structure for a superconducting quantum chip according to claim 1, characterized in that, The hard material includes any one or a combination of tantalum, copper, aluminum, etc., and the ductile material includes any one or a combination of indium, tin, etc.

6. The three-dimensional packaging structure for a superconducting quantum chip according to claim 1, characterized in that, The first connection part is a hollow tube with an open end, and the hollow tube is partially or wholly inserted into the second connection part.

7. The three-dimensional packaging structure of the superconducting quantum chip according to claim 1, characterized in that, the superconducting material comprises any one or a combination of more than one of indium, aluminum, niobium, tin, titanium, osmium, zinc, molybdenum, tantalum, vanadium.

8. A three-dimensional packaging method for a superconducting quantum chip, characterized in that it includes: forming a first connection part on the first surface of the quantum chip with a hard material, and forming a second connection part on the first surface of the control circuit chip with a ductile material; or, forming a first connection part on the first surface of the control circuit chip with a hard material, and forming a second connection part on the first surface of the quantum chip with a ductile material; making the first surface of the quantum chip face the first surface of the control circuit chip, and arranging each first connection part corresponding to a respective second connection part; applying pressure between the quantum chip and the control circuit chip, so that the quantum chip and the control circuit chip are bonded through a superconducting material, and making the first connection part support between the first surface of the quantum chip and the first surface of the control circuit chip, holes or grooves are formed on the surface of the first connection part, the diameter of the opening of the hole or groove is smaller than the inner diameter of the hole or groove, and making the second connection part partially or completely fill the hole or groove under the action of the pressure; or, the first connection part is a hollow tube with one end open, and making the first connection part partially or integrally insert into the second connection part under the action of the pressure, and each first connection part and a respective second connection part cooperate to form a fitting structure; during the bonding process, the dimension of the first connection part in the pressure direction remains unchanged.

9. The three-dimensional packaging method for a superconducting quantum chip according to claim 8, characterized in that the hard material comprises any one or a combination of more than one of tantalum, copper, aluminum; and / or, the ductile material comprises any one or a combination of more than one of indium, tin.

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