Split-gate flash memory device and manufacturing method thereof

Abstract

The present invention provides a split-gate flash memory device and a manufacturing method thereof, wherein the manufacturing method comprises the following steps: making a charge-trapping dielectric layer; etching and removing the charge-trapping dielectric layer corresponding to a first target area, wherein the first target area is an area corresponding to a middle area of ​​a gate. The present invention provides a new 2-bit / cell charge-trapping split-gate flash memory device structure and a self-manufacturing process thereof. Unlike the NROM of the prior art, the structure removes the charge-trapping dielectric layer by self-aligned etching in the middle of the gate, which can avoid interference caused by lateral movement of stored charges between two bits under the action of an electric field, and introduces a select gate device so that the device can tolerate over-erase operations. In addition, the process is a self-aligned process, which can further reduce the area of ​​the flash memory unit and is not limited by the photolithography process.

Description

Technical Field

[0001] The present invention relates to the technical field of flash memory device manufacturing, and in particular to a split-gate flash memory device and a manufacturing method thereof. Background Art

[0002] The structure of the existing 2-bit / cell charge trap flash memory (also known as NROM: Nitrided ROM) is as follows Figure 1 Its operation is shown in Table 1, where Program means programming, Erase means erasing, Read means reading, Vg means gate voltage, Vd means drain voltage, and Vs means source voltage. The device structure has the following characteristics: the storage medium layer is a charge-trapping material Nitride (nitride), and the characteristic that trapped charges cannot move freely in Nitride is used to enable a single gate structure to form a local charge storage area above the source-drain junction, thereby realizing 2-bit storage (refer to Figure 1 The device is programmed using channel hot electrons, erased using band-to-band tunneling hot holes, and read using reverse read operations (see Table 1).

[0003] Table 1

[0004]

[0005] The device cannot tolerate the over-erase effect. In order to avoid over-erase, a more complex peripheral circuit design is required to assist the device in not causing over-erase operation. Summary of the invention

[0006] The technical problem to be solved by the present invention is to overcome the defect that the charge trapping flash memory device in the prior art cannot withstand over-erasure, and to provide a split-gate flash memory device and a manufacturing method thereof.

[0007] The present invention solves the above technical problems through the following technical solutions:

[0008] The present invention provides a method for manufacturing a split-gate flash memory device, wherein the split-gate flash memory device comprises a two-bit / unit split-gate flash memory device, and the manufacturing method comprises the following steps:

[0009] manufacturing a charge trapping dielectric layer;

[0010] The charge trapping dielectric layer corresponding to the first target area is removed by etching, and the first target area is an area corresponding to the middle area of ​​the gate.

[0011] Preferably, manufacturing the charge trapping dielectric layer includes:

[0012] A first silicon oxide layer is formed, and a first silicon nitride layer is formed on the first silicon oxide layer. The first silicon oxide layer is a bottom gate dielectric layer, and the first silicon nitride layer is a charge trapping dielectric layer.

[0013] Preferably, etching and removing the charge trapping dielectric layer corresponding to the first target area includes:

[0014] S11, forming a second silicon oxide layer and a second silicon nitride layer in sequence on the first silicon nitride layer;

[0015] S12, etching and removing the second silicon nitride layer corresponding to the second target area, where the second target area is an area corresponding to the flash memory cell area, and a width of the second target area is greater than a width of the first target area;

[0016] S13, depositing a polysilicon layer on the second silicon oxide layer corresponding to the second target area and performing anisotropic etching to form a polysilicon sidewall;

[0017] S14, using the polysilicon sidewalls as masks to self-align and sequentially etch the second silicon oxide layer and the first silicon nitride layer corresponding to the first target area.

[0018] Preferably, etching and removing the charge trapping dielectric layer corresponding to the first target area further comprises:

[0019] S15, etching and removing the polysilicon sidewalls by using the second silicon nitride layer, the second silicon oxide layer, the first silicon nitride layer, and the first silicon oxide layer as stop layers.

[0020] Preferably, etching and removing the charge trapping dielectric layer corresponding to the first target area further comprises:

[0021] S16, performing anisotropic etching to remove the second silicon oxide layer corresponding to the second target area and the first silicon oxide layer corresponding to the first target area.

[0022] Preferably, before manufacturing the charge trapping dielectric layer, the manufacturing method further comprises the following steps:

[0023] A P-type well is formed on the substrate, wherein the P-type well is a medium-high voltage P-type well;

[0024] The process of making a charge trapping dielectric layer includes:

[0025] A charge trapping dielectric layer is formed above the P-type well.

[0026] Preferably, after step S16, the manufacturing method further comprises the following steps:

[0027] S21, depositing to form a gate dielectric layer, the gate dielectric layer covers the sidewall of the second silicon nitride layer corresponding to the second target area, the sidewall of the second silicon oxide layer corresponding to the second target area, the upper surface of the first silicon nitride layer corresponding to the second target area, the sidewall of the first silicon nitride layer corresponding to the first target area, and the upper surface of the P-type well corresponding to the first target area;

[0028] S22, forming a selection gate polysilicon layer in the space surrounded by the gate dielectric layer, and doping the selection gate polysilicon layer;

[0029] S23, performing CMP (chemical mechanical polishing) with the second silicon nitride layer as a stop layer, and performing thermal oxidation to form an etching protection oxide layer on the top of the select gate polysilicon layer.

[0030] Preferably, after step S23, the manufacturing method further comprises the following steps:

[0031] S24, removing the second silicon nitride layer;

[0032] S25, using the etching protection oxide layer and the gate dielectric layer as masks, self-aligningly etching the second silicon oxide layer, the first silicon nitride layer, and the first silicon oxide layer in sequence;

[0033] S26, performing LDD (lightly doped drain) / Halo (halo ring) implantation in the P-type well to form a lightly doped drain region, and the lightly doped drain region extends to below the first silicon oxide layer.

[0034] Preferably, after step S26, the manufacturing method further comprises the following steps:

[0035] Depositing and etching to form a first spacer dielectric layer and a second spacer dielectric layer, wherein the first spacer dielectric layer is L-shaped and the second spacer dielectric layer is L-shaped;

[0036] Impurities are implanted below the lightly doped drain region to form a heavily doped source and drain region.

[0037] The present invention provides a split-gate flash memory device, which is a two-bit / unit split-gate flash memory device. The split-gate flash memory device comprises a charge trapping dielectric layer, which comprises a notch, and the notch is arranged in an area corresponding to the middle area of ​​the gate.

[0038] Preferably, the split-gate flash memory device is manufactured by the method for manufacturing a split-gate flash memory device of the present invention.

[0039] The positive and progressive effects of the present invention are as follows: the present invention provides a new 2-bit / cell charge-trapping split-gate flash memory device structure and its self-manufacturing process. Unlike the NROM of the prior art, the structure removes the charge-trapping dielectric layer by self-aligned etching in the middle of the gate, which can avoid the interference caused by the lateral movement of the stored charge between the two bits under the action of the electric field. The introduction of the selection gate device allows the device to tolerate over-erase operations. In addition, the process is a self-aligned process, which can further reduce the area of ​​the flash memory unit and is not limited by the photolithography process.

[0040] Additional aspects and advantages of the present invention will be given in part in the following description and in part will be obvious from the following description, or will be learned through practice of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] Figure 1 It is a schematic diagram of the structure of an NROM in the prior art.

[0042] Figure 2 The present invention is a flowchart of a method for manufacturing a split-gate flash memory device according to a preferred embodiment of the present invention.

[0043] Figure 3 The schematic diagram is a schematic diagram of forming a P-type well in a method for manufacturing a split-gate flash memory device according to a preferred embodiment of the present invention.

[0044] Figure 4 The present invention is a schematic diagram of a method for manufacturing a split-gate flash memory device according to a preferred embodiment of the present invention, in which etching is performed using a polysilicon sidewall as a mask.

[0045] Figure 5 The schematic diagram of the method for manufacturing a split-gate flash memory device after removing the polysilicon sidewall is shown in a preferred embodiment of the present invention.

[0046] Figure 6 The present invention is a schematic diagram of etching the second silicon oxide layer and the first silicon oxide layer in a method for manufacturing a split-gate flash memory device according to a preferred embodiment of the present invention.

[0047] Figure 7 The schematic diagram is a schematic diagram of forming an etching protection oxide layer in the preparation of a method for manufacturing a split-gate flash memory device according to a preferred embodiment of the present invention.

[0048] Figure 8 The schematic diagram is a diagram of forming a lightly doped drain region in a method for manufacturing a split-gate flash memory device according to a preferred embodiment of the present invention.

[0049] Fig. 9 The schematic diagram is a method for manufacturing a split-gate flash memory device according to a preferred embodiment of the present invention for forming heavily doped source and drain regions.

[0050] Fig.10FIG. 1 is a schematic diagram of an Ibl-Vwl curve of a split-gate flash memory device according to a preferred embodiment of the present invention. DETAILED DESCRIPTION

[0051] A preferred embodiment is given below and combined with the accompanying drawings to more clearly and completely illustrate the present invention.

[0052] This embodiment provides a method for manufacturing a split-gate flash memory device. Figure 2 , the manufacturing method at least comprises the following steps:

[0053] S1. Form a P-type well on a substrate. The P-type well is a medium-high voltage P-type well.

[0054] S2. Fabricating a charge trapping dielectric layer.

[0055] S3, etching and removing the charge trapping dielectric layer corresponding to the first target area. The first target area is the area corresponding to the middle area of ​​the gate.

[0056] In the specific implementation, in step S1, refer to Figure 3 , a P-type well 101 is formed by implantation on the substrate, and the P-type well 101 is a medium-high voltage P-type well.

[0057] As an optional implementation, refer to Figure 4 In step S2, a first silicon oxide layer 102 is formed above the P-type well 101, and a first silicon nitride layer 103 is formed above the first silicon oxide layer 102. The first silicon oxide layer 102 is a bottom gate dielectric layer and the first silicon nitride layer 103 is a charge trapping dielectric layer.

[0058] Then, refer to Figure 4 In step S3, a second silicon oxide layer 501 and a second silicon nitride layer 502 are sequentially formed on the first silicon nitride layer 103. Then, the second silicon nitride layer 502 corresponding to the second target area is etched away, and the second target area is the area corresponding to the flash memory cell area, and the width of the second target area is greater than the width of the first target area. In specific implementation, the flash memory cell area is defined by photolithography, and the second silicon nitride layer 502 corresponding to the flash memory cell area is etched away. Next, a polysilicon layer is deposited on the second silicon oxide layer 501 corresponding to the second target area and anisotropic etching is performed to form a polysilicon sidewall 503. Using the polysilicon sidewall 503 as a mask, the second silicon oxide layer 501 and the first silicon nitride layer 103 corresponding to the first target area are etched in sequence in a self-aligned manner.

[0059] Then, refer to Figure 5The polysilicon sidewalls 503 are removed by etching using the second silicon nitride layer 502, the second silicon oxide layer 501, the first silicon nitride layer 103 and the first silicon oxide layer 102 as stop layers. In the specific implementation, the polysilicon sidewalls 503 are removed by wet etching.

[0060] Next, refer to Figure 6 , anisotropic etching is performed to remove the second silicon oxide layer 501 corresponding to the second target area and the first silicon oxide layer 102 corresponding to the first target area.

[0061] Then, refer to Figure 7 , a gate dielectric layer 105 is deposited to form, and the gate dielectric layer 105 covers the side walls of the second silicon nitride layer 502 corresponding to the second target area, the side walls of the second silicon oxide layer 501 corresponding to the second target area, the upper surface of the first silicon nitride layer 103 corresponding to the second target area, the side walls of the first silicon nitride layer 103 corresponding to the first target area, and the upper surface of the P-type well corresponding to the first target area.

[0062] Then, a selection gate polysilicon layer 106 is formed in the space surrounded by the gate dielectric layer 105 , and the selection gate polysilicon layer 106 is doped.

[0063] Next, CMP is performed using the second silicon nitride layer 502 as a stop layer, and thermal oxidation is performed to form an etching protection oxide layer 107 on the top of the select gate polysilicon layer 106 .

[0064] Next, refer to Figure 8 , remove the second silicon nitride layer 502. Then, using the etching protection oxide layer 107 and the gate dielectric layer 105 as masks, the second silicon oxide layer 501, the first silicon nitride layer 103, and the first silicon oxide layer 102 are etched in sequence in a self-aligned manner.

[0065] Then, LDD / Halo implantation is performed in the P-type well to form a lightly doped drain region 109 . The lightly doped drain region 109 extends to below the first silicon oxide layer 102 .

[0066] Next, refer to Fig. 9 , deposit and etch to form a first spacer dielectric layer 104 and a second spacer dielectric layer 108. The first spacer dielectric layer 104 is L-shaped, and the second spacer dielectric layer 108 is L-shaped. Then, impurities are implanted below the lightly doped drain region 109 to form a source-drain heavily doped region 110.

[0067] This embodiment also provides a split-gate flash memory device, referring to Fig. 9The split gate flash memory device is a two-bit / unit split gate flash memory device, the split gate flash memory device includes a charge trapping dielectric layer, the charge trapping dielectric layer includes a notch, and the notch is arranged in an area corresponding to the middle area of ​​the gate. The split gate flash memory device is manufactured by the manufacturing method of the split gate flash memory device of this embodiment.

[0068] Fig.10 The Ibl (bit line current)-Vwl (word line voltage) curves of the simulation results of the split-gate flash memory device are shown, where the horizontal axis represents Vwl in V, the vertical axis represents Ibl in A / um, Program state represents the programming state, and Erase state represents the erased state. The curve shows that the threshold voltage window of the split-gate flash memory device is ~1.7V, and the read currents (Ir01 and Ir10) of the Program state and Erase state in the worst case differ by 6 orders of magnitude.

[0069] The present embodiment proposes a split-gate flash memory device and a manufacturing method thereof, and the split-gate flash memory device belongs to a new 2-bit / cell charge-trapping split-gate flash memory device structure. The structure has two bits / cell and is implemented by a self-alignment process, which improves the integration. Unlike NROM, the split-gate flash memory device of the present embodiment removes the charge-trapping dielectric layer by self-alignment etching in the middle of the gate, which can avoid the interference caused by the lateral movement of the stored charge between the two bits under the action of the electric field, and the introduction of the selection gate device allows the device to tolerate over-erase operations. In addition, the manufacturing method of the split-gate flash memory device of the present embodiment is a self-alignment process during the above-mentioned etching process, which can further reduce the area of ​​the flash memory cell and is not limited by the photolithography process. On the other hand, the manufacturing method of the split-gate flash memory device of the present embodiment uses a sacrificial polysilicon sidewall to achieve a self-alignment structure, which can further reduce the area of ​​the flash memory cell and is not limited by the photolithography process.

[0070] Although the specific embodiments of the present invention are described above, it should be understood by those skilled in the art that this is only for illustration and the protection scope of the present invention is defined by the appended claims. Those skilled in the art may make various changes or modifications to these embodiments without departing from the principles and essence of the present invention, but these changes and modifications all fall within the protection scope of the present invention.

Claims

1. A method for manufacturing a split-gate flash memory device, characterized in that: The split-gate flash memory device comprises a two-bit / unit split-gate flash memory device, and the manufacturing method comprises the following steps: Forming a first silicon oxide layer, and forming a first silicon nitride layer on the first silicon oxide layer, wherein the first silicon oxide layer is a bottom gate dielectric layer, and the first silicon nitride layer is a charge trapping dielectric layer; The charge trapping dielectric layer corresponding to the first target area is removed by etching, wherein the first target area is an area corresponding to the middle area of ​​the gate, comprising the following steps: S11, forming a second silicon oxide layer and a second silicon nitride layer in sequence on the first silicon nitride layer; S12, etching and removing the second silicon nitride layer corresponding to a second target area, where the second target area is an area corresponding to a flash memory cell area, and a width of the second target area is greater than a width of the first target area; S13, depositing a polysilicon layer on the second silicon oxide layer corresponding to the second target area and performing anisotropic etching to form a polysilicon sidewall; S14, using the polysilicon sidewall as a mask to self-align and sequentially etch the second silicon oxide layer and the first silicon nitride layer corresponding to the first target area; S15, using the second silicon nitride layer, the second silicon oxide layer, the first silicon nitride layer, and the first silicon oxide layer as stop layers to etch away the polysilicon sidewalls.

2. The method for manufacturing a split-gate flash memory device according to claim 1, wherein: The etching and removing of the charge trapping dielectric layer corresponding to the first target area further comprises: S16, performing anisotropic etching to remove the second silicon oxide layer corresponding to the second target area and the first silicon oxide layer corresponding to the first target area.

3. The method for manufacturing a split-gate flash memory device according to claim 2, wherein: Before manufacturing the charge trapping dielectric layer, the manufacturing method further comprises the following steps: Forming a P-type well on a substrate, wherein the P-type well is a medium-high voltage P-type well; The manufacturing of the charge trapping dielectric layer comprises: The charge trapping dielectric layer is formed above the P-type well.

4. The method for manufacturing a split-gate flash memory device according to claim 3, wherein: After step S16, the manufacturing method further comprises the following steps: S21, depositing to form a gate dielectric layer, wherein the gate dielectric layer covers the sidewall of the second silicon nitride layer corresponding to the second target area, the sidewall of the second silicon oxide layer corresponding to the second target area, the upper surface of the first silicon nitride layer corresponding to the second target area, the sidewall of the first silicon nitride layer corresponding to the first target area, and the upper surface of the P-type well corresponding to the first target area; S22, forming a selection gate polysilicon layer in the space surrounded by the gate dielectric layer, and doping the selection gate polysilicon layer; S23, performing CMP with the second silicon nitride layer as a stop layer, and performing thermal oxidation to form an etching protection oxide layer on top of the select gate polysilicon layer.

5. The method for manufacturing a split-gate flash memory device according to claim 4, wherein: After step S23, the manufacturing method further comprises the following steps: S24, removing the second silicon nitride layer; S25, using the etching protection oxide layer and the gate dielectric layer as masks, self-aligningly etching the second silicon oxide layer, the first silicon nitride layer, and the first silicon oxide layer in sequence; S26, performing LDD / Halo implantation in the P-type well to form a lightly doped drain region, wherein the lightly doped drain region extends to below the first silicon oxide layer.

6. The method for manufacturing a split-gate flash memory device according to claim 5, wherein: After step S26, the manufacturing method further comprises the following steps: Depositing and etching to form a first spacer dielectric layer and a second spacer dielectric layer, wherein the first spacer dielectric layer is L-shaped and the second spacer dielectric layer is L-shaped; Impurities are implanted below the lightly doped drain region to form a heavily doped source and drain region.

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