Constant offset voltage rail-to-rail operational amplifier

Abstract

The application discloses a constant offset voltage rail-to-rail operational amplifier, which comprises a first input stage operational amplifier unit electrically connected between a power voltage VDD and a reference potential, a first bias enhancement control unit and a first control tube for generating a first control signal and a second control signal, a second input stage operational amplifier unit electrically connected between the power voltage VDD and the reference potential and electrically connected with the first input stage operational amplifier unit, a second bias enhancement control unit and a second control tube for generating a third control signal and a fourth control signal. The rail-to-rail operational amplifier can work in a full swing voltage range and has a constant offset voltage during operation.

Description

Technical Field

[0001] This invention belongs to the field of integrated circuit technology, specifically relating to a constant offset voltage rail-to-rail operational amplifier. Background Technology

[0002] In the design of analog integrated circuits, it is often necessary to add or subtract a fixed voltage to some signals, and sometimes the swing of the signals to be processed is relatively large. This is a major challenge for circuit design, and the implementation circuit is often quite complex.

[0003] The input and output voltage swings of a rail-to-rail operational amplifier are very close to or almost equal to the power supply voltage, which can maintain a high signal-to-noise ratio to a certain extent. However, during the integrated circuit manufacturing process, factors such as process technology and device mismatch will introduce offset voltage, which will directly affect the accuracy of digital-to-analog or analog-to-digital conversion, resulting in a decrease in signal-to-noise ratio.

[0004] Therefore, to address the aforementioned technical problems, it is necessary to provide a constant offset voltage rail-to-rail operational amplifier. Summary of the Invention

[0005] In view of this, the purpose of the present invention is to provide a constant offset voltage rail-to-rail operational amplifier.

[0006] To achieve the above objectives, an embodiment of the present invention provides the following technical solution:

[0007] A constant offset voltage rail-to-rail operational amplifier, the rail-to-rail operational amplifier comprising:

[0008] The first input stage operational amplifier unit is electrically connected between the power supply voltage VDD and the reference potential. It includes several MOS transistors and a first resistor R1, which is used to generate a first offset voltage.

[0009] A first bias enhancement control unit and a first control transistor are used to generate a first control signal and a second control signal, wherein the first control signal is used to control the first control transistor to maintain a first current I flowing through the first resistor R1. R1 The second control signal is used to stabilize the first current I when it cannot be stabilized. R1 The first input stage operational amplifier unit is turned off at that time;

[0010] The second input stage operational amplifier unit is electrically connected between the power supply voltage VDD and the reference potential, and is also electrically connected to the first input stage operational amplifier unit. It includes several MOS transistors and a second resistor R2, which is used to generate a second offset voltage.

[0011] The second bias enhancement control unit and the second control transistor are used to generate a third control signal and a fourth control signal, wherein the third control signal is used to control the second control transistor to maintain the second current I flowing through the second resistor R2. R2 The fourth control signal is used to stabilize the second current I when it cannot be stabilized. R2 The second input stage operational amplifier unit is turned off.

[0012] In one embodiment, the first input stage operational amplifier unit is an NMOS input stage operational amplifier unit, which includes a first NMOS transistor MN1, a second NMOS transistor MN2, a third NMOS transistor MN3, a fourth NMOS transistor MN4, a fifth NMOS transistor MN5, a twelfth NMOS transistor MN12, a thirteenth NMOS transistor MN13, a fourteenth NMOS transistor MN14, a first PMOS transistor MP1, a third PMOS transistor MP3, a fourth PMOS transistor MP4, a sixth PMOS transistor MP6, a first resistor R1, and a first current source I1, wherein:

[0013] The source of the third PMOS transistor MP3 is connected to the power supply voltage VDD, and the gate is connected to the drain. The source of the fourth PMOS transistor MP4 is connected to the power supply voltage VDD, and the gate is connected to the drain.

[0014] The gate of the first NMOS transistor MN1 is connected to the first signal input terminal, and its drain is connected to the drain of the third PMOS transistor MP3. The gate of the second NMOS transistor MN2 is connected to the second signal input terminal, and its drain is connected to the drain of the fourth PMOS transistor MP4. Its source is connected to the first terminal of the first resistor R1.

[0015] The first terminal of the first current source I1 is connected to the source of the first NMOS transistor MN1 and the second terminal of the first resistor R1, and the second terminal is connected to the reference potential.

[0016] The source of the first PMOS transistor MP1 is connected to the power supply voltage VDD, the gate is connected to the gate of the third PMOS transistor MP3, the drain is connected to the drain of the twelfth NMOS transistor MN12, the gate of the twelfth NMOS transistor MN12 is connected to the drain of the twelfth NMOS transistor MN12, and the source is connected to the reference potential.

[0017] The source of the sixth PMOS transistor MP6 is connected to the power supply voltage VDD, the gate is connected to the gate of the fourth PMOS transistor MP4, the drain is connected to the drain of the fifth NMOS transistor MN5, the gate of the fifth NMOS transistor MN5 is connected to the drain of the fifth NMOS transistor MN5, and the source is connected to the reference potential.

[0018] The drain of the fourteenth NMOS transistor MN14 is connected to the second input stage operational amplifier unit, the source is connected to the drain of the thirteenth NMOS transistor MN13, the gate of the thirteenth NMOS transistor MN13 is connected to the gate of the twelfth NMOS transistor NM12, and the source is connected to the reference potential.

[0019] The drain of the third NMOS transistor MN3 is connected to the signal output terminal, its gate is connected to the gate of the fourteenth NMOS transistor MN14, its source is connected to the drain of the fourth NMOS transistor MN4, the gate of the fourth NMOS transistor MN4 is connected to the gate of the fifth NMOS transistor MN5, and its source is connected to the reference potential.

[0020] The second input stage operational amplifier unit is a PMOS input stage operational amplifier unit, which includes a seventh PMOS transistor MP7, an eighth PMOS transistor MP8, a tenth PMOS transistor MP10, an eleventh PMOS transistor MP11, a sixteenth NMOS transistor MN16, a seventeenth NMOS transistor MN17, an eighteenth NMOS transistor MN18, a nineteenth NMOS transistor MN19, a twenty-first NMOS transistor MN21, a twenty-second NMOS transistor MN22, a second resistor R2, and a fourth current source I4, wherein:

[0021] The source of the seventeenth NMOS transistor MN17 is connected to the reference potential, and the gate is connected to the drain. The source of the eighteenth NMOS transistor MN18 is connected to the reference potential, and the gate is connected to the drain.

[0022] The gate of the seventh PMOS transistor MP7 is connected to the second signal input terminal, and its drain is connected to the drain of the seventeenth NMOS transistor MN17. The gate of the eighth PMOS transistor MP8 is connected to the first signal input terminal, its drain is connected to the drain of the eighteenth NMOS transistor MN18, and its source is connected to the first terminal of the second resistor R2.

[0023] The first terminal of the second current source I2 is connected to the reference potential, and the second terminal is connected to the source of the seventh PMOS transistor MP7 and the second terminal of the second resistor R2.

[0024] The source of the tenth PMOS transistor MP10 is connected to the power supply voltage VDD, the gate is connected to the drain, the drain is connected to the drain of the twenty-first NMOS transistor MN21, the drain of the twenty-first NMOS transistor MN21 is connected to the drain of the fourteenth NMOS transistor MN14, the source is connected to the drain of the sixteenth NMOS transistor MN16, the gate of the sixteenth NMOS transistor MN16 is connected to the gate of the seventeenth NMOS transistor MN17, and the source is connected to the reference potential.

[0025] The source of the eleventh PMOS transistor MP11 is connected to the power supply voltage VDD, the gate is connected to the gate of the tenth PMOS transistor MP10, and the drain is connected to the drain of the twenty-second NMOS transistor MN22. The source of the twenty-second NMOS transistor MN22 is connected to the drain of the nineteenth NMOS transistor MN19, and the gate of the nineteenth NMOS transistor MN19 is connected to the gate of the eighteenth NMOS transistor MN18. The source is connected to the reference potential. The drains of the eleventh PMOS transistor MP11 and the twenty-second NMOS transistor MN22 are connected to the signal output terminal.

[0026] In one embodiment, the resistance values ​​of the first resistor R1 and the second resistor R2 are equal, i.e., R1 = R2, and the first offset voltage is V. OS1 =R1*I R1 The second offset voltage is V OS2 =R2*I R2 The current of the first current source I1 is I1 = I0, and the current of the fourth current source I4 is I4 = I0.

[0027] In one embodiment, the first control transistor is the eighth NMOS transistor MN8, the gate of the eighth NMOS transistor MN8 is connected to the first bias enhancement control unit, the source is connected to the reference potential, and the drain is connected to the first terminal of the first current source I1; the second control transistor is the sixteenth PMOS transistor MP16, the gate of the sixteenth PMOS transistor MP16 is connected to the second bias enhancement control unit, the source is connected to the power supply voltage VDD, and the drain is connected to the second terminal of the second resistor R2.

[0028] In one embodiment, the first bias enhancement control unit includes a first sampling unit and a first control unit. The first sampling unit includes a second PMOS transistor MP2, a fifth PMOS transistor MP5, a sixth NMOS transistor MN6, a seventh NMOS transistor MN7, a tenth NMOS transistor MN10, an eleventh NMOS transistor MN11, and a second current source I2. The first control unit includes a ninth NMOS transistor MN9, a third current source I3, and a first Schmitt trigger, wherein:

[0029] The source of the second PMOS transistor MP2 is connected to the power supply voltage VDD, the gate is connected to the gate of the third PMOS transistor MP3, the drain is connected to the drain of the eleventh NMOS transistor MN11, the gate and drain of the eleventh NMOS transistor MN11 are connected, and the source is connected to the reference potential.

[0030] The first terminal of the second current source I2 is connected to the power supply voltage VDD, and the second terminal is connected to the drain of the tenth NMOS transistor MN10. The gate of the tenth NMOS transistor MN10 is connected to the gate of the eleventh NMOS transistor MN11, and the drain is connected to the reference potential.

[0031] The source of the fifth PMOS transistor MP5 is connected to the power supply voltage VDD, the gate is connected to the gate of the fourth PMOS transistor MP4, the drain is connected to the drain of the sixth NMOS transistor MN6, the gate and drain of the sixth NMOS transistor MN6 are connected, and the source is connected to the reference potential.

[0032] The gate of the seventh NMOS transistor MN7 is connected to the gate of the sixth NMOS transistor MN6, and its drain is connected to the gate of the eighth NMOS transistor MN8, the gate of the ninth NMOS transistor MN9, and the drain of the tenth NMOS transistor MN10. Its source is connected to the reference potential.

[0033] The first terminal of the third current source I3 is connected to the power supply voltage VDD, the second terminal is connected to the drain of the ninth NMOS transistor MN9, the gate of the ninth NMOS transistor MN9 is connected to the gate of the eighth NMOS transistor MN8, and the source is connected to the reference potential.

[0034] The input of the first Schmitt trigger is connected to the drain of the ninth NMOS transistor MN9, and the output is connected to the gate of the fourteenth NMOS transistor MN14 and the gate of the third NMOS transistor MN3.

[0035] The second bias enhancement control unit includes a second sampling unit and a second control unit. The second sampling unit includes a ninth PMOS transistor MP9, a twelfth PMOS transistor MP12, a thirteenth PMOS transistor MP13, a fourteenth PMOS transistor MP14, a fifteenth NMOS transistor MN15, a twentieth NMOS transistor MN20, and a fifth current source I5. The second control unit includes a fifteenth PMOS transistor MP15, a sixth current source I6, and a second Schmitt trigger, wherein:

[0036] The source of the ninth PMOS transistor MP9 is connected to the power supply voltage VDD, the gate is connected to the drain, the drain is connected to the drain of the fifteenth NMOS transistor MN15, the gate of the fifteenth NMOS transistor MN15 is connected to the gate of the seventeenth NMOS transistor MN17, and the source is connected to the reference potential.

[0037] The source of the twelfth PMOS transistor MP12 is connected to the power supply voltage VDD, the gate is connected to the gate of the ninth PMOS transistor MP9, and the drain is connected to the first terminal of the fifth current source I5. The source of the thirteenth PMOS transistor MP13 is connected to the power supply voltage VDD, the drain is connected to the first terminal of the fifth current source I5, and the second terminal of the fifth current source I5 is connected to the reference potential.

[0038] The source of the fourteenth PMOS transistor MP14 is connected to the power supply voltage VDD, and its gate is connected to the gate of the thirteenth PMOS transistor MP13. The drain of the fourteenth PMOS transistor MP14 is connected to the gate of the fourteenth PMOS transistor MP14 and the drain of the twentieth NMOS transistor MN20. The gate of the twentieth NMOS transistor MN20 is connected to the gate of the eighteenth NMOS transistor MN18, and its source is connected to the reference potential.

[0039] The source of the fifteenth PMOS transistor MP15 is connected to the power supply voltage VDD, the gate is connected to the gate of the sixteenth PMOS transistor MP16, the drain is connected to the first terminal of the sixth current source I6, and the second terminal of the sixth current source I6 is connected to the reference potential.

[0040] The input of the second Schmitt trigger is connected to the drain of the fifteenth PMOS transistor MP15 and the first terminal of the sixth current source I6, and the output is connected to the gate of the twenty-first NMOS transistor MN21 and the gate of the twenty-second NMOS transistor MN22.

[0041] In one embodiment, the current of the second current source I2 is I2 = I0, the current of the third current source I3 is I3 = I0 / 2, the current of the fifth current source I5 is I5 = I0, and the current of the sixth current source I6 is I6 = I0 / 2.

[0042] In one embodiment, the first sampling unit is used to collect the current flowing through the first NMOS transistor MN1 and the second NMOS transistor MN2, and compare it with the current I2 of the second current source I2 to generate a first control signal to control the gate voltage of the eighth NMOS transistor MN8.

[0043] The second sampling unit is used to collect the current flowing through the seventh PMOS transistor MP7 and the eighth PMOS transistor MP8, and compare it with the current I5 of the fifth current source I5 to generate a second control signal to control the gate voltage of the sixteenth PMOS transistor MP16.

[0044] In one embodiment, the first control unit is used to turn off the first input stage operational amplifier unit when the current of the eighth NMOS transistor MN8 is greater than a first current threshold.

[0045] The second control unit is used to shut down the first input stage operational amplifier unit when the current of the sixteenth PMOS transistor MP16 is less than the second current threshold.

[0046] In one embodiment, in the rail-to-rail operational amplifier, the signal output terminal is connected to the second signal input terminal, and the first signal input terminal receives a voltage signal that increases or decreases linearly.

[0047] In one embodiment, the rail-to-rail operational amplifier:

[0048] At times t1-t2 and t4-t5, both the NMOS input stage operational amplifier unit and the PMOS input stage operational amplifier unit are in operation.

[0049] Between time t2 and t4, the NMOS input stage operational amplifier unit is in the working state, while the PMOS input stage operational amplifier unit is in the non-working state.

[0050] At times t1-t5, the offset voltage VOS of the rail-to-rail operational amplifier is INN-INP and remains constant. INP and INN are the voltage signals at the first signal input terminal and the second signal input terminal, respectively.

[0051] in:

[0052] At time t1, the voltage signal at the first signal input terminal is equal to VGSN, VGSN = Vthn + Vdson, where Vthn is the gate-source voltage threshold of the first NMOS transistor MN1 and the second NMOS transistor MN2, and Vdson is the overdrive voltage.

[0053] At time t2, the voltage signal at the second signal input terminal is equal to VDD-VGSP, VGSP=Vthp+Vdson, Vthp is the gate-source voltage threshold of the seventh PMOS transistor MP7 and the eighth PMOS transistor MP8, and Vdson is the overdrive voltage;

[0054] At time t3, the voltage signal at the first signal input terminal is equal to VDD-VGSP, and the voltage signal at the second signal input terminal is equal to the power supply voltage VDD.

[0055] At time t4, the voltage signal at the second signal input terminal is equal to VDD-VGSP;

[0056] At time t5, the voltage signal at the first signal input terminal is equal to VGSN.

[0057] The present invention has the following beneficial effects:

[0058] The rail-to-rail operational amplifier of the present invention can operate over the full swing voltage range and has a constant offset voltage during operation. Attached Figure Description

[0059] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0060] Figure 1This is the circuit diagram of the constant offset voltage rail-to-rail operational amplifier in the present invention;

[0061] Figure 2 This is the circuit diagram of the constant offset voltage rail-to-rail operational amplifier in a specific embodiment of the present invention;

[0062] Figure 3 This is the timing diagram of the constant offset voltage rail-to-rail operational amplifier in a specific embodiment of the present invention. Detailed implementation manners

[0063] In order to enable those skilled in the art to better understand the technical solutions in the present invention, the following will clearly and completely describe the technical solutions in the embodiments of the present invention with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the scope of protection of the present invention.

[0064] Refer Figure 1 As shown, the present invention discloses a constant offset voltage rail-to-rail operational amplifier, which includes:

[0065] A first input stage operational amplifier unit, electrically connected between the power supply voltage VDD and the reference potential, which includes several MOS transistors and a first resistor R1, and the first resistor R1 is used to generate a first offset voltage;

[0066] A first bias enhancement control unit and a first control transistor, used to generate a first control signal and a second control signal. Among them, the first control signal is used to control the first control transistor to maintain the first current I flowing through the first resistor R1 R1 stable, and the second control signal is used to turn off the first input stage operational amplifier unit when the first current I cannot be stabilized; R1

[0067] A second input stage operational amplifier unit, electrically connected between the power supply voltage VDD and the reference potential, and electrically connected to the first input stage operational amplifier unit, which includes several MOS transistors and a second resistor R2, and the second resistor R2 is used to generate a second offset voltage;

[0068] A second bias enhancement control unit and a second control transistor, used to generate a third control signal and a fourth control signal. Among them, the third control signal is used to control the second control transistor to maintain the second current I flowing through the second resistor R2 R2 stable, and the fourth control signal is used to turn off the second input stage operational amplifier unit when the second current I cannot be stabilized. R2

[0069] Preferably, the reference potential in this invention is illustrated using the ground potential as an example.

[0070] The first input stage operational amplifier unit is an NMOS input stage operational amplifier unit, which includes a first NMOS transistor MN1, a second NMOS transistor MN2, a third NMOS transistor MN3, a fourth NMOS transistor MN4, a fifth NMOS transistor MN5, a twelfth NMOS transistor MN12, a thirteenth NMOS transistor MN13, a fourteenth NMOS transistor MN14, a first PMOS transistor MP1, a third PMOS transistor MP3, a fourth PMOS transistor MP4, a sixth PMOS transistor MP6, a first resistor R1, and a first current source I1, wherein:

[0071] The source of the third PMOS transistor MP3 is connected to the power supply voltage VDD, and the gate is connected to the drain. The source of the fourth PMOS transistor MP4 is connected to the power supply voltage VDD, and the gate is connected to the drain.

[0072] The gate of the first NMOS transistor MN1 is connected to the first signal input terminal, and its drain is connected to the drain of the third PMOS transistor MP3. The gate of the second NMOS transistor MN2 is connected to the second signal input terminal, and its drain is connected to the drain of the fourth PMOS transistor MP4. Its source is connected to the first terminal of the first resistor R1.

[0073] The first terminal of the first current source I1 is connected to the source of the first NMOS transistor MN1 and the second terminal of the first resistor R1, and the second terminal is connected to the reference potential.

[0074] The source of the first PMOS transistor MP1 is connected to the power supply voltage VDD, the gate is connected to the gate of the third PMOS transistor MP3, the drain is connected to the drain of the twelfth NMOS transistor MN12, the gate of the twelfth NMOS transistor MN12 is connected to the drain of the twelfth NMOS transistor MN12, and the source is connected to the reference potential.

[0075] The source of the sixth PMOS transistor MP6 is connected to the power supply voltage VDD, the gate is connected to the gate of the fourth PMOS transistor MP4, the drain is connected to the drain of the fifth NMOS transistor MN5, the gate of the fifth NMOS transistor MN5 is connected to the drain of the fifth NMOS transistor MN5, and the source is connected to the reference potential.

[0076] The drain of the fourteenth NMOS transistor MN14 is connected to the second input stage operational amplifier unit, the source is connected to the drain of the thirteenth NMOS transistor MN13, the gate of the thirteenth NMOS transistor MN13 is connected to the gate of the twelfth NMOS transistor NM12, and the source is connected to the reference potential.

[0077] The drain of the third NMOS transistor MN3 is connected to the signal output terminal, its gate is connected to the gate of the fourteenth NMOS transistor MN14, its source is connected to the drain of the fourth NMOS transistor MN4, the gate of the fourth NMOS transistor MN4 is connected to the gate of the fifth NMOS transistor MN5, and its source is connected to the reference potential.

[0078] In the NMOS input stage operational amplifier unit, the current from the first current source I1 is I1 = I0. The op-amp starts operating when the input signal voltage exceeds one VGS. The first resistor R1 is used to generate the first offset voltage V. OS1 The current I flowing through the first resistor R1 R1 Related, V OS1 =R1*I R1 .

[0079] The second input stage operational amplifier unit is a PMOS input stage operational amplifier unit, which includes the seventh PMOS transistor MP7, the eighth PMOS transistor MP8, the tenth PMOS transistor MP10, the eleventh PMOS transistor MP11, the sixteenth NMOS transistor MN16, the seventeenth NMOS transistor MN17, the eighteenth NMOS transistor MN18, the nineteenth NMOS transistor MN19, the twenty-first NMOS transistor MN21, the twenty-second NMOS transistor MN22, the second resistor R2, and the fourth current source I4, wherein:

[0080] The source of the seventeenth NMOS transistor MN17 is connected to the reference potential, and the gate is connected to the drain. The source of the eighteenth NMOS transistor MN18 is connected to the reference potential, and the gate is connected to the drain.

[0081] The gate of the seventh PMOS transistor MP7 is connected to the second signal input terminal, and its drain is connected to the drain of the seventeenth NMOS transistor MN17. The gate of the eighth PMOS transistor MP8 is connected to the first signal input terminal, its drain is connected to the drain of the eighteenth NMOS transistor MN18, and its source is connected to the first terminal of the second resistor R2.

[0082] The first terminal of the second current source I2 is connected to the reference potential, and the second terminal is connected to the source of the seventh PMOS transistor MP7 and the second terminal of the second resistor R2.

[0083] The source of the tenth PMOS transistor MP10 is connected to the power supply voltage VDD, the gate is connected to the drain, the drain is connected to the drain of the twenty-first NMOS transistor MN21, the drain of the twenty-first NMOS transistor MN21 is connected to the drain of the fourteenth NMOS transistor MN14, the source is connected to the drain of the sixteenth NMOS transistor MN16, the gate of the sixteenth NMOS transistor MN16 is connected to the gate of the seventeenth NMOS transistor MN17, and the source is connected to the reference potential.

[0084] The source of the eleventh PMOS transistor MP11 is connected to the power supply voltage VDD, the gate is connected to the gate of the tenth PMOS transistor MP10, the drain is connected to the drain of the twenty-second NMOS transistor MN22. The source of the twenty-second NMOS transistor MN22 is connected to the drain of the nineteenth NMOS transistor MN19. The gate of the nineteenth NMOS transistor MN19 is connected to the gate of the eighteenth NMOS transistor MN18, and the source is connected to the reference potential. The drain of the eleventh PMOS transistor MP11 and the drain of the twenty-second NMOS transistor MN22 are connected to the signal output terminal.

[0085] In the PMOS input stage operational amplifier unit, the current of the fourth current source I4 is I4 = I0. When the difference between the input signal voltage and the power supply voltage VDD is lower than one VGS or more, the operational amplifier starts to work. The second resistor R2 is used to generate the second offset voltage. The second offset voltage V OS2 is related to the current I R2 flowing through the second resistor R2, and V OS2 = R2 * I R2 , and the resistance values of the first resistor R1 and the second resistor R2 are equal, that is, R1 = R2.

[0086] Specifically, the first control transistor in the present invention is the eighth NMOS transistor MN8. The gate of the eighth NMOS transistor MN8 is connected to the first bias enhancement control unit, the source is connected to the reference potential, and the drain is connected to the first end of the first current source I1; the second control transistor is the sixteenth PMOS transistor MP16. The gate of the sixteenth PMOS transistor MP16 is connected to the second bias enhancement control unit, the source is connected to the power supply voltage VDD, and the drain is connected to the second end of the second resistor R2.

[0087] The first bias enhancement control unit samples the currents flowing through MN1 and MN2, compares them with the reference current, and generates a first control signal to control MN8, so that the sum of the currents of MN1 and MN2 is equal to the reference current, thereby maintaining the current stability of R1 and achieving the purpose of a constant offset voltage. This unit also generates a second control signal EN_NEA. When the input signal voltage is too small to stabilize the current of R1, this control signal EN_NEA turns off the NMOS input stage operational amplifier unit;

[0088] The second bias enhancement control unit samples the currents flowing through MP7 and MP8, compares them with the reference current, and generates a third control signal to control MP16, so that the sum of the currents of MP7 and MP8 is equal to the reference current, thereby maintaining the current stability of R2 and achieving the purpose of a constant offset voltage. This unit also generates a fourth control signal EN_PEA. When the input signal voltage is too large to stabilize the current of R2, this control signal EN_PEA turns off the PMOS input stage operational amplifier unit.

[0089] See Figure 2As shown in a specific embodiment of the present invention, the circuit structures of the first input stage operational amplifier unit and the second input stage operational amplifier unit are exactly the same, and will not be described again here.

[0090] In this embodiment, the first bias enhancement control unit includes a first sampling unit and a first control unit. The first sampling unit includes a second PMOS transistor MP2, a fifth PMOS transistor MP5, a sixth NMOS transistor MN6, a seventh NMOS transistor MN7, a tenth NMOS transistor MN10, an eleventh NMOS transistor MN11, and a second current source I2. The first control unit includes a ninth NMOS transistor MN9, a third current source I3, and a first Schmitt trigger, wherein:

[0091] The source of the second PMOS transistor MP2 is connected to the power supply voltage VDD, the gate is connected to the gate of the third PMOS transistor MP3, the drain is connected to the drain of the eleventh NMOS transistor MN11, the gate and drain of the eleventh NMOS transistor MN11 are connected, and the source is connected to the reference potential.

[0092] The first terminal of the second current source I2 is connected to the power supply voltage VDD, and the second terminal is connected to the drain of the tenth NMOS transistor MN10. The gate of the tenth NMOS transistor MN10 is connected to the gate of the eleventh NMOS transistor MN11, and the drain is connected to the reference potential.

[0093] The source of the fifth PMOS transistor MP5 is connected to the power supply voltage VDD, the gate is connected to the gate of the fourth PMOS transistor MP4, the drain is connected to the drain of the sixth NMOS transistor MN6, the gate and drain of the sixth NMOS transistor MN6 are connected, and the source is connected to the reference potential.

[0094] The gate of the seventh NMOS transistor MN7 is connected to the gate of the sixth NMOS transistor MN6, and its drain is connected to the gate of the eighth NMOS transistor MN8, the gate of the ninth NMOS transistor MN9, and the drain of the tenth NMOS transistor MN10. Its source is connected to the reference potential.

[0095] The first terminal of the third current source I3 is connected to the power supply voltage VDD, the second terminal is connected to the drain of the ninth NMOS transistor MN9, the gate of the ninth NMOS transistor MN9 is connected to the gate of the eighth NMOS transistor MN8, and the source is connected to the reference potential.

[0096] The input of the first Schmitt trigger is connected to the drain of the ninth NMOS transistor MN9, and the output is connected to the gate of the fourteenth NMOS transistor MN14 and the gate of the third NMOS transistor MN3.

[0097] The second bias enhancement control unit includes a second sampling unit and a second control unit. The second sampling unit includes a ninth PMOS transistor MP9, a twelfth PMOS transistor MP12, a thirteenth PMOS transistor MP13, a fourteenth PMOS transistor MP14, a fifteenth NMOS transistor MN15, a twentieth NMOS transistor MN20, and a fifth current source I5. The second control unit includes a fifteenth PMOS transistor MP15, a sixth current source I6, and a second Schmitt trigger, wherein:

[0098] The source of the ninth PMOS transistor MP9 is connected to the power supply voltage VDD, the gate is connected to the drain, the drain is connected to the drain of the fifteenth NMOS transistor MN15, the gate of the fifteenth NMOS transistor MN15 is connected to the gate of the seventeenth NMOS transistor MN17, and the source is connected to the reference potential.

[0099] The source of the twelfth PMOS transistor MP12 is connected to the power supply voltage VDD, the gate is connected to the gate of the ninth PMOS transistor MP9, and the drain is connected to the first terminal of the fifth current source I5. The source of the thirteenth PMOS transistor MP13 is connected to the power supply voltage VDD, the drain is connected to the first terminal of the fifth current source I5, and the second terminal of the fifth current source I5 is connected to the reference potential.

[0100] The source of the fourteenth PMOS transistor MP14 is connected to the power supply voltage VDD, and its gate is connected to the gate of the thirteenth PMOS transistor MP13. The drain of the fourteenth PMOS transistor MP14 is connected to the gate of the fourteenth PMOS transistor MP14 and the drain of the twentieth NMOS transistor MN20. The gate of the twentieth NMOS transistor MN20 is connected to the gate of the eighteenth NMOS transistor MN18, and its source is connected to the reference potential.

[0101] The source of the fifteenth PMOS transistor MP15 is connected to the power supply voltage VDD, the gate is connected to the gate of the sixteenth PMOS transistor MP16, the drain is connected to the first terminal of the sixth current source I6, and the second terminal of the sixth current source I6 is connected to the reference potential.

[0102] The input of the second Schmitt trigger is connected to the drain of the fifteenth PMOS transistor MP15 and the first terminal of the sixth current source I6, and the output is connected to the gate of the twenty-first NMOS transistor MN21 and the gate of the twenty-second NMOS transistor MN22.

[0103] Among them, the current of the second current source I2 is I2 = I0, the current of the third current source I3 is I3 = I0 / 2, the current of the fifth current source I5 is I5 = I0, and the current of the sixth current source I6 is I6 = I0 / 2.

[0104] The first sampling unit is used to collect the current flowing through the first NMOS transistor MN1 and the second NMOS transistor MN2, and compare it with the current I2 of the second current source I2 to generate a first control signal to control the gate voltage of the eighth NMOS transistor MN8.

[0105] The first control unit is used to shut down the first input stage operational amplifier unit when the current of the eighth NMOS transistor MN8 exceeds a first current threshold. The ninth NMOS transistor MN9 mirrors the current of the eighth NMOS transistor MN8. When the current of MN8 exceeds a certain value, it indicates that the input signal is very low. If this signal decreases further, the NMOS input stage operational amplifier unit will not function properly. Therefore, at this time, the control circuit will generate a control signal EN_NEA to shut down the NMOS input stage operational amplifier unit, and the output voltage will be generated by the PMOS input stage operational amplifier unit.

[0106] The second sampling unit is used to collect the current flowing through the seventh PMOS transistor MP7 and the eighth PMOS transistor MP8, and compare it with the current I5 of the fifth current source I5 to generate a second control signal to control the gate voltage of the sixteenth PMOS transistor MP16.

[0107] The second control unit is used to shut down the first input stage operational amplifier unit when the current of the sixteenth PMOS transistor MP16 is less than the second current threshold. The fifteenth PMOS transistor MP15 mirrors the current of the sixteenth PMOS transistor MP16. When the current of MP16 is less than a certain value, it indicates that the input signal is already very high. If this signal increases further, the PMOS input stage operational amplifier unit will not be able to work properly. Therefore, at this time, the control circuit will generate a control signal EN_PEA to shut down the PMOS input stage operational amplifier unit. At this time, the output voltage is generated by the NMOS input stage operational amplifier unit with a constant offset voltage.

[0108] When the signal output terminal OUT of the rail-to-rail operational amplifier is connected to the second signal input terminal INN, the first signal input terminal INP receives a voltage signal that increases or decreases linearly.

[0109] Combination Figure 3 As shown, taking the example of the INP voltage first increasing linearly (from 0 to VDD-VGSP) and then decreasing linearly (from VDD-VGSP back to 0), the corresponding amplifier operation process is as follows:

[0110] At times t1-t2 and t4-t5, both the NMOS input stage operational amplifier unit and the PMOS input stage operational amplifier unit are in operation.

[0111] Between time t2 and t4, the NMOS input stage operational amplifier unit is in the working state, while the PMOS input stage operational amplifier unit is in the non-working state.

[0112] At times t1-t5, the offset voltage VOS of the rail-to-rail operational amplifier is INN-INP and remains constant. INP and INN are the voltage signals at the first signal input terminal and the second signal input terminal, respectively.

[0113] in:

[0114] At time t1, the voltage signal at the first signal input terminal is equal to VGSN, where VGSN is the gate-source voltage threshold of the first NMOS transistor MN1 and the second NMOS transistor MN2.

[0115] At time t2, the voltage signal at the second signal input terminal is equal to VDD-VGSP, where VGSP is the gate-source voltage threshold of the seventh PMOS transistor MP7 and the eighth PMOS transistor MP8.

[0116] At time t3, the voltage signal at the first signal input terminal is equal to VDD-VGSP, and the voltage signal at the second signal input terminal is equal to the power supply voltage VDD.

[0117] At time t4, the voltage signal at the second signal input terminal is equal to VDD-VGSP;

[0118] At time t5, the voltage signal at the first signal input terminal is equal to VGSN.

[0119] When the INP voltage is less than VGSN, MN8 initially has no current flowing through it due to its very low drain voltage. As INP gradually increases, the drain voltage of MN8 begins to increase, and its current also begins to increase. MN1 with I MN2 The current increases accordingly and first stabilizes at the set current I2 value. As the INP voltage further increases, the current I1 gradually increases, and the current MN8 gradually decreases. When INP equals VGSN, EN_NEA goes high, and the NMOS input stage operational amplifier unit starts working. At this time, I... MN1 with I MN2 The current has already reached the set value, so the offset voltage will not change at this time.

[0120] When the INP voltage is between zero and VDD-VGSP, the PMOS input stage operational amplifier unit operates normally, and its offset voltage remains at the set value. When INP rises to a point where I4 cannot operate normally, the current of I4 gradually decreases, while the current of MP16 gradually increases. However, at this time, I... MP7 and I MP8 The current is I4 and I MP16The sum of INN remains unchanged at the set value I0. When INN reaches VDD-VGSP, EN_PEA goes low, and the PMOS input stage operational amplifier unit stops working. After that, the NMOS input stage operational amplifier unit continues to work and maintains the output voltage.

[0121] As can be seen from the above analysis, the rail-to-rail operational amplifier of the present invention has a constant offset voltage and can operate in the full swing voltage range from the reference potential (ground potential) to the power supply voltage VDD. Since its operating state has been established before enabling the NMOS / PMOS input stage operational amplifier unit, its offset voltage VOS = INN - INP will not be affected in any way during the switching of the NMOS / PMOS input stage operational amplifier unit and will remain constant.

[0122] As can be seen from the above technical solutions, the present invention has the following advantages:

[0123] The rail-to-rail operational amplifier of the present invention can operate over the full swing voltage range and has a constant offset voltage during operation.

[0124] It will be apparent to those skilled in the art that the present invention is not limited to the details of the exemplary embodiments described above, and that the invention can be implemented in other specific forms without departing from its spirit or essential characteristics. Therefore, the embodiments should be considered in all respects as exemplary and non-limiting, and the scope of the invention is defined by the appended claims rather than the foregoing description. Thus, all variations falling within the meaning and scope of equivalents of the claims are intended to be included within the present invention. No reference numerals in the claims should be construed as limiting the scope of the claims.

[0125] Furthermore, it should be understood that although this specification describes embodiments, not every embodiment contains only one independent technical solution. This narrative style is merely for clarity. Those skilled in the art should consider the specification as a whole, and the technical solutions in each embodiment can also be appropriately combined to form other embodiments that can be understood by those skilled in the art.

Claims

1. A constant offset voltage rail-to-rail operational amplifier, characterized in that, The rail-to-rail operational amplifier includes: The first input stage operational amplifier unit is electrically connected between the power supply voltage VDD and the reference potential. It includes several MOS transistors and a first resistor R1, which is used to generate a first offset voltage. A first bias enhancement control unit and a first control transistor are used to generate a first control signal and a second control signal, wherein the first control signal is used to control the first control transistor to maintain a first current I flowing through the first resistor R1. R1 The second control signal is used to stabilize the first current I when it cannot be stabilized. R1 The first input stage operational amplifier unit is turned off at that time; The second input stage operational amplifier unit is electrically connected between the power supply voltage VDD and the reference potential, and is also electrically connected to the first input stage operational amplifier unit. It includes several MOS transistors and a second resistor R2, which is used to generate a second offset voltage. The second bias enhancement control unit and the second control transistor are used to generate a third control signal and a fourth control signal, wherein the third control signal is used to control the second control transistor to maintain the second current I flowing through the second resistor R2. R2 The fourth control signal is used to stabilize the second current I when it cannot be stabilized. R2 The second input stage operational amplifier unit is turned off at this time; The first input stage operational amplifier unit is an NMOS input stage operational amplifier unit, which includes a first NMOS transistor MN1, a second NMOS transistor MN2, a third NMOS transistor MN3, a fourth NMOS transistor MN4, a fifth NMOS transistor MN5, a twelfth NMOS transistor MN12, a thirteenth NMOS transistor MN13, a fourteenth NMOS transistor MN14, a first PMOS transistor MP1, a third PMOS transistor MP3, a fourth PMOS transistor MP4, a sixth PMOS transistor MP6, a first resistor R1, and a first current source I1, wherein: The source of the third PMOS transistor MP3 is connected to the power supply voltage VDD, and the gate is connected to the drain. The source of the fourth PMOS transistor MP4 is connected to the power supply voltage VDD, and the gate is connected to the drain. The gate of the first NMOS transistor MN1 is connected to the first signal input terminal, and its drain is connected to the drain of the third PMOS transistor MP3. The gate of the second NMOS transistor MN2 is connected to the second signal input terminal, and its drain is connected to the drain of the fourth PMOS transistor MP4. Its source is connected to the first terminal of the first resistor R1. The first terminal of the first current source I1 is connected to the source of the first NMOS transistor MN1 and the second terminal of the first resistor R1, and the second terminal is connected to the reference potential. The source of the first PMOS transistor MP1 is connected to the power supply voltage VDD, the gate is connected to the gate of the third PMOS transistor MP3, the drain is connected to the drain of the twelfth NMOS transistor MN12, the gate of the twelfth NMOS transistor MN12 is connected to the drain of the twelfth NMOS transistor MN12, and the source is connected to the reference potential. The source of the sixth PMOS transistor MP6 is connected to the power supply voltage VDD, the gate is connected to the gate of the fourth PMOS transistor MP4, the drain is connected to the drain of the fifth NMOS transistor MN5, the gate of the fifth NMOS transistor MN5 is connected to the drain of the fifth NMOS transistor MN5, and the source is connected to the reference potential. The drain of the fourteenth NMOS transistor MN14 is connected to the second input stage operational amplifier unit, the source is connected to the drain of the thirteenth NMOS transistor MN13, the gate of the thirteenth NMOS transistor MN13 is connected to the gate of the twelfth NMOS transistor NM12, and the source is connected to the reference potential. The drain of the third NMOS transistor MN3 is connected to the signal output terminal, its gate is connected to the gate of the fourteenth NMOS transistor MN14, its source is connected to the drain of the fourth NMOS transistor MN4, the gate of the fourth NMOS transistor MN4 is connected to the gate of the fifth NMOS transistor MN5, and its source is connected to the reference potential. The second input stage operational amplifier unit is a PMOS input stage operational amplifier unit, which includes a seventh PMOS transistor MP7, an eighth PMOS transistor MP8, a tenth PMOS transistor MP10, an eleventh PMOS transistor MP11, a sixteenth NMOS transistor MN16, a seventeenth NMOS transistor MN17, an eighteenth NMOS transistor MN18, a nineteenth NMOS transistor MN19, a twenty-first NMOS transistor MN21, a twenty-second NMOS transistor MN22, a second resistor R2, and a fourth current source I4, wherein: The source of the seventeenth NMOS transistor MN17 is connected to the reference potential, and the gate is connected to the drain. The source of the eighteenth NMOS transistor MN18 is connected to the reference potential, and the gate is connected to the drain. The gate of the seventh PMOS transistor MP7 is connected to the second signal input terminal, and its drain is connected to the drain of the seventeenth NMOS transistor MN17. The gate of the eighth PMOS transistor MP8 is connected to the first signal input terminal, its drain is connected to the drain of the eighteenth NMOS transistor MN18, and its source is connected to the first terminal of the second resistor R2. The first terminal of the second current source I2 is connected to the reference potential, and the second terminal is connected to the source of the seventh PMOS transistor MP7 and the second terminal of the second resistor R2. The source of the tenth PMOS transistor MP10 is connected to the power supply voltage VDD, the gate is connected to the drain, the drain is connected to the drain of the twenty-first NMOS transistor MN21, the drain of the twenty-first NMOS transistor MN21 is connected to the drain of the fourteenth NMOS transistor MN14, the source is connected to the drain of the sixteenth NMOS transistor MN16, the gate is connected to the second bias enhancement control unit, the gate of the sixteenth NMOS transistor MN16 is connected to the gate of the seventeenth NMOS transistor MN17, and the source is connected to the reference potential. The source of the eleventh PMOS transistor MP11 is connected to the power supply voltage VDD, the gate is connected to the gate of the tenth PMOS transistor MP10, and the drain is connected to the drain of the twenty-second NMOS transistor MN22. The source of the twenty-second NMOS transistor MN22 is connected to the drain of the nineteenth NMOS transistor MN19, and the gate is connected to the second bias enhancement control unit. The gate of the nineteenth NMOS transistor MN19 is connected to the gate of the eighteenth NMOS transistor MN18, and the source is connected to the reference potential. The drains of the eleventh PMOS transistor MP11 and the twenty-second NMOS transistor MN22 are connected to the signal output terminal.

2. The constant offset voltage rail-to-rail operational amplifier according to claim 1, characterized in that, The resistance values ​​of the first resistor R1 and the second resistor R2 are equal, i.e., R1 = R2, and the first offset voltage is V. OS1 = R1*I R1 The second offset voltage is V OS2 =R2*I R2 The current of the first current source I1 is I1=I0, and the current of the fourth current source I4 is I4=I0.

3. The constant offset voltage rail-to-rail operational amplifier according to claim 1, characterized in that, The first control transistor is the eighth NMOS transistor MN8. The gate of the eighth NMOS transistor MN8 is connected to the first bias enhancement control unit, the source is connected to the reference potential, and the drain is connected to the first terminal of the first current source I1. The second control transistor is the sixteenth PMOS transistor MP16. The gate of the sixteenth PMOS transistor MP16 is connected to the second bias enhancement control unit, the source is connected to the power supply voltage VDD, and the drain is connected to the second terminal of the second resistor R2.

4. The constant offset voltage rail-to-rail operational amplifier according to claim 3, characterized in that, The first bias enhancement control unit includes a first sampling unit and a first control unit. The first sampling unit includes a second PMOS transistor MP2, a fifth PMOS transistor MP5, a sixth NMOS transistor MN6, a seventh NMOS transistor MN7, a tenth NMOS transistor MN10, an eleventh NMOS transistor MN11, and a second current source I2. The first control unit includes a ninth NMOS transistor MN9, a third current source I3, and a first Schmitt trigger, wherein: The source of the second PMOS transistor MP2 is connected to the power supply voltage VDD, the gate is connected to the gate of the third PMOS transistor MP3, the drain is connected to the drain of the eleventh NMOS transistor MN11, the gate and drain of the eleventh NMOS transistor MN11 are connected, and the source is connected to the reference potential. The first terminal of the second current source I2 is connected to the power supply voltage VDD, and the second terminal is connected to the drain of the tenth NMOS transistor MN10. The gate of the tenth NMOS transistor MN10 is connected to the gate of the eleventh NMOS transistor MN11, and the drain is connected to the reference potential. The source of the fifth PMOS transistor MP5 is connected to the power supply voltage VDD, the gate is connected to the gate of the fourth PMOS transistor MP4, the drain is connected to the drain of the sixth NMOS transistor MN6, the gate and drain of the sixth NMOS transistor MN6 are connected, and the source is connected to the reference potential. The gate of the seventh NMOS transistor MN7 is connected to the gate of the sixth NMOS transistor MN6, and its drain is connected to the gate of the eighth NMOS transistor MN8, the gate of the ninth NMOS transistor MN9, and the drain of the tenth NMOS transistor MN10. Its source is connected to the reference potential. The first terminal of the third current source I3 is connected to the power supply voltage VDD, the second terminal is connected to the drain of the ninth NMOS transistor MN9, the gate of the ninth NMOS transistor MN9 is connected to the gate of the eighth NMOS transistor MN8, and the source is connected to the reference potential. The input of the first Schmitt trigger is connected to the drain of the ninth NMOS transistor MN9, and the output is connected to the gate of the fourteenth NMOS transistor MN14 and the gate of the third NMOS transistor MN3. The second bias enhancement control unit includes a second sampling unit and a second control unit. The second sampling unit includes a ninth PMOS transistor MP9, a twelfth PMOS transistor MP12, a thirteenth PMOS transistor MP13, a fourteenth PMOS transistor MP14, a fifteenth NMOS transistor MN15, a twentieth NMOS transistor MN20, and a fifth current source I5. The second control unit includes a fifteenth PMOS transistor MP15, a sixth current source I6, and a second Schmitt trigger, wherein: The source of the ninth PMOS transistor MP9 is connected to the power supply voltage VDD, the gate is connected to the drain, the drain is connected to the drain of the fifteenth NMOS transistor MN15, the gate of the fifteenth NMOS transistor MN15 is connected to the gate of the seventeenth NMOS transistor MN17, and the source is connected to the reference potential. The source of the twelfth PMOS transistor MP12 is connected to the power supply voltage VDD, the gate is connected to the gate of the ninth PMOS transistor MP9, and the drain is connected to the first terminal of the fifth current source I5. The source of the thirteenth PMOS transistor MP13 is connected to the power supply voltage VDD, the drain is connected to the first terminal of the fifth current source I5, and the second terminal of the fifth current source I5 is connected to the reference potential. The source of the fourteenth PMOS transistor MP14 is connected to the power supply voltage VDD, and its gate is connected to the gate of the thirteenth PMOS transistor MP13. The drain of the fourteenth PMOS transistor MP14 is connected to the gate of the fourteenth PMOS transistor MP14 and the drain of the twentieth NMOS transistor MN20. The gate of the twentieth NMOS transistor MN20 is connected to the gate of the eighteenth NMOS transistor MN18, and its source is connected to the reference potential. The source of the fifteenth PMOS transistor MP15 is connected to the power supply voltage VDD, the gate is connected to the gate of the sixteenth PMOS transistor MP16, the drain is connected to the first terminal of the sixth current source I6, and the second terminal of the sixth current source I6 is connected to the reference potential. The input of the second Schmitt trigger is connected to the drain of the fifteenth PMOS transistor MP15 and the first terminal of the sixth current source I6, and the output is connected to the gate of the twenty-first NMOS transistor MN21 and the gate of the twenty-second NMOS transistor MN22.

5. The constant offset voltage rail-to-rail operational amplifier according to claim 4, characterized in that, The current of the second current source I2 is I2=I0, the current of the third current source I3 is I3=I0 / 2, the current of the fifth current source I5 is I5=I0, and the current of the sixth current source I6 is I6=I0 / 2.

6. The constant offset voltage rail-to-rail operational amplifier according to claim 4, characterized in that, The first sampling unit is used to collect the current flowing through the first NMOS transistor MN1 and the second NMOS transistor MN2, and compare it with the current I2 of the second current source I2 to generate a first control signal to control the gate voltage of the eighth NMOS transistor MN8. The second sampling unit is used to collect the current flowing through the seventh PMOS transistor MP7 and the eighth PMOS transistor MP8, and compare it with the current I5 of the fifth current source I5 to generate a second control signal to control the gate voltage of the sixteenth PMOS transistor MP16.

7. The constant offset voltage rail-to-rail operational amplifier according to claim 6, characterized in that, The first control unit is used to turn off the first input stage operational amplifier unit when the current of the eighth NMOS transistor MN8 is greater than the first current threshold. The second control unit is used to shut down the first input stage operational amplifier unit when the current of the sixteenth PMOS transistor MP16 is less than the second current threshold.

8. The constant offset voltage rail-to-rail operational amplifier according to claim 7, characterized in that, In the rail-to-rail operational amplifier, the signal output terminal is connected to the second signal input terminal, and the first signal input terminal receives a voltage signal that increases or decreases linearly.

9. The constant offset voltage rail-to-rail operational amplifier according to claim 8, characterized in that, The rail-to-rail operational amplifier: At times t1-t2 and t4-t5, both the NMOS input stage operational amplifier unit and the PMOS input stage operational amplifier unit are in operation. Between time t2 and t4, the NMOS input stage operational amplifier unit is in the working state, while the PMOS input stage operational amplifier unit is in the non-working state. At times t1-t5, the offset voltage VOS of the rail-to-rail operational amplifier is INN-INP and remains constant. INP and INN are the voltage signals at the first signal input terminal and the second signal input terminal, respectively. At time t1, the voltage signal at the first signal input terminal is equal to VGSN, VGSN=Vthn+Vdson, where Vthn is the gate-source voltage threshold of the first NMOS transistor MN1 and the second NMOS transistor MN2, and Vdson is the overdrive voltage. At time t2, the voltage signal at the second signal input terminal is equal to VDD-VGSP, VGSP=Vthp+Vdson, Vthp is the gate-source voltage threshold of the seventh PMOS transistor MP7 and the eighth PMOS transistor MP8, and Vdson is the overdrive voltage; At time t3, the voltage signal at the first signal input terminal is equal to VDD-VGSP, and the voltage signal at the second signal input terminal is equal to the power supply voltage VDD. At time t4, the voltage signal at the second signal input terminal is equal to VDD-VGSP; At time t5, the voltage signal at the first signal input terminal is equal to VGSN.

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