A low voltage high speed dynamic comparator structure
By employing a dual-tailed dynamic comparator and a voltage pull-down structure at low voltage, the problem of slow switching speed of traditional dynamic comparators at low voltage is solved, achieving high-speed latching function and expanding the power supply and process applicability range of SAR ADC.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- SHANGHAI HUALI INTEGRATED CIRCUIT CORP
- Filing Date
- 2021-10-29
- Publication Date
- 2026-07-10
AI Technical Summary
Traditional low-voltage high-speed dynamic comparators malfunction and have slow switching speeds because the input common-mode level is lower than the threshold voltage of the NMOS transistor, which affects the performance of high-speed SAR ADCs.
It adopts a dual-tailed dynamic comparator structure, combined with a voltage pull-down structure and logic control circuit. By pulling the input signal to a negative voltage instantaneously in the pre-amplification stage, the gate-source voltage of the input pair transistors is increased, thereby achieving high-speed latching function.
Achieving high-speed latching at low supply voltage expands the power supply application range of SAR ADCs, improving the competitiveness of the circuit and its application environment.
Smart Images
Figure CN114024530B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of semiconductor technology, and in particular to a high-speed dynamic comparator structure operating at low voltage. Background Technology
[0002] In communication products, A / D converters are crucial, and their performance significantly impacts the overall performance of these systems. Within an A / D converter, the comparator is a core unit, and its accuracy, power consumption, speed, and other specifications have a significant influence on the overall performance of the A / D converter.
[0003] Dynamic comparators are widely used in high-speed, low-power SAR ADCs due to their low power consumption and high speed. Traditional double-tailed dynamic comparators, such as... Figure 1 As shown, Figure 1 The diagram shows a schematic of an existing dual-tailed dynamic comparator circuit. The first stage (10) is a pre-amplification stage that amplifies the input signal, and the second stage (20) is a latching stage that latches the comparison result. The simplest structure of a dynamic comparator is the latch structure, also known as a regenerative comparator. Its main principle is to use positive voltage feedback to compare the input signal. Because of this positive feedback, the latch circuit is very fast, making it suitable for high-speed SAR ADC designs.
[0004] However, with the development of integrated circuit technology, process dimensions and doping concentrations have decreased proportionally, leading to a reduction in power supply voltage. Meanwhile, the threshold voltage of transistors has not decreased proportionally with the power supply voltage. Simultaneously, the widespread use of portable instruments has further driven down the operating voltage of circuits. Therefore, the design difficulty of analog circuits has increased significantly, and circuit performance has decreased accordingly, including the design of dynamic comparators in high-speed SAR ADCs.
[0005] In the design of SAR ADC, as the power supply voltage decreases, the output common-mode level of the DAC also decreases, which means the input common-mode level of the comparator decreases. This presents a new challenge for traditional double-tail comparator amplifier stages that use NMOS transistors as input pairs. Specifically, the input common-mode level is lower than the threshold voltage Vth of the NMOS transistor, causing the comparator to malfunction, resulting in slow switching speed or even failure to switch, leading to functional problems. Summary of the Invention
[0006] In view of the shortcomings of the prior art described above, the purpose of this invention is to provide a high-speed dynamic comparator structure for low-voltage operation, which solves the problem that the switching speed of the high-speed dynamic comparator for low-voltage operation in the prior art is slow, resulting in malfunction.
[0007] To achieve the above and other related objectives, the present invention provides a high-speed dynamic comparator structure operating at low voltage, comprising at least:
[0008] Dual-tailed dynamic comparator; voltage pull-down structure; logic control circuit;
[0009] The dual-tailed dynamic comparator includes a pre-amplification stage and a latching stage; the pre-amplification stage pre-amplifies the differential input signals VINN and VINP and then outputs them differentially to the latching stage;
[0010] The voltage pull-down structure includes: a seventh NMOS transistor, the gate of which is supplied with the logic clock signal CLOCK; the drain of the seventh NMOS transistor outputs a signal VY to the source of the NMOS transistor NM0 in the pre-amplification stage; the gate of the NMOS transistor NM0 in the pre-amplification stage is supplied with a clock signal CLOCKB that is opposite to the logic clock signal CLOCK; the voltage pull-down structure pulls down the signal VY input to the source of the NMOS transistor NM0 in the pre-amplification stage to a negative voltage at the instant the dual-tailed dynamic comparator starts working by inputting the logic clock signal CLOCK to the gate of the seventh NMOS transistor;
[0011] The logic control circuit includes a first inverter and a second inverter connected in series with the first inverter; wherein the input terminal of the first inverter is connected to the logic clock signal CLOCK; the clock signal CLOCKB output by the first inverter is connected to the input terminal of the second inverter; and the second inverter outputs a clock signal CLOCKBB that is the same as the logic clock signal CLOCK.
[0012] Preferably, the latch stage includes a PMOS transistor PMO, a first PMOS, a second PMOS, and a first to a fourth NMOS; the source of the PMOS transistor PMO is connected to the power supply voltage VDD, its gate is connected to the clock signal CLOCKBB, and its drain is connected to the source of the first and second PMOS; the gates of the first PMOS and the first NMOS are connected to the drain of the second PMOS, the drain of the second NMOS, and the drain of the fourth NMOS; the gates of the second PMOS and the second NMOS are connected to the drain of the first PMOS, the drain of the first NMOS, and the drain of the third NMOS.
[0013] Preferably, the gate of the second PMOS is connected to the drain of the first PMOS to form an output node VOUTN; the gate of the first PMOS is connected to the drain of the second PMOS to form an output node VOUTP.
[0014] Preferably, the sources of the first to fourth NMOS are grounded.
[0015] Preferably, the pre-amplification stage further includes third and fourth PMOS; fifth and sixth NMOS; wherein the source of the third and fourth PMOS is connected to the power supply voltage VDD; the gate of the third and fourth PMOS is connected to the clock signal CLOCKB; the drain of the third PMOS is connected to the drain of the fifth NMOS and the gate of the third NMOS; the drain of the fourth PMOS is connected to the drain of the sixth NMOS and the gate of the fourth NMOS.
[0016] Preferably, the gate of the fifth NMOS is connected to the differential input signal VINN; the gate of the sixth NMOS is connected to the differential input signal VINP; the pre-amplification stage pre-amplifies the differential input signals VINN and VINP, and then performs the differential output on the gates of the third and fourth NMOS in the latching stage, the differential output signals corresponding to signals P and Q respectively.
[0017] Preferably, the drain of the third PMOS and the drain of the fifth NMOS are connected to the upper plate of the first capacitor, and the lower plate of the first capacitor is grounded; the drain of the fourth PMOS and the drain of the sixth NMOS are connected to the upper plate of the second capacitor, and the lower plate of the second capacitor is grounded.
[0018] Preferably, the drain output signal VX of the NMOS transistor NM0 in the pre-amplification stage is sent to the source of the fifth and sixth NMOS transistors.
[0019] Preferably, the voltage pull-down structure further includes: a fifth PMOS and a third capacitor; the gate of the fifth PMOS is connected to the clock signal CLOCKB; the source of the fifth PMOS is connected to the power supply voltage VDD; the drain of the fifth PMOS and the upper plate of the third capacitor are connected to the clock signal CLOCKBB; the lower plate of the third capacitor is connected to the source of the NMOS transistor NMO and the drain of the seventh NMOS; the source of the seventh NMOS is grounded.
[0020] As described above, the low-voltage operation high-speed dynamic comparator structure of the present invention has the following beneficial effects: the present invention enables the dynamic comparator to operate effectively in the low power supply range, realize the high-speed latching function, and does not increase its inherent bias; the circuit structure of the present invention has a faster latching function, which can expand the power supply application range and process range of high-speed SAR ADC, improve IP competitiveness, and increase its application environment range. Attached Figure Description
[0021] Figure 1 The diagram shows the existing dual-tailed dynamic comparator circuit structure.
[0022] Figure 2 The diagram shows a schematic of the high-speed dynamic comparator circuit structure for low-voltage operation according to the present invention.
[0023] Figure 3 The image shows the Virtuoso simulation results of a traditional dual-tailed dynamic comparator.
[0024] Figure 4 The figure shown is a Virtuoso simulation result of the high-speed dynamic comparator operating at low voltage according to the present invention. Detailed Implementation
[0025] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.
[0026] Please see Figures 2 to 4 It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the drawings only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.
[0027] This invention provides a high-speed dynamic comparator structure for low-voltage operation, such as... Figure 2 As shown, Figure 2 The diagram shows a schematic of a high-speed dynamic comparator circuit structure operating at low voltage according to the present invention. This structure includes at least:
[0028] Dual-tailed dynamic comparator 10; voltage pull-down structure 20; logic control circuit 30;
[0029] The dual-tailed dynamic comparator 10 includes a pre-amplification stage and a latching stage; the pre-amplification stage pre-amplifies the differential input signals VINN and VINP and then outputs them differentially to the latching stage;
[0030] The voltage pull-down structure 20 includes: a seventh NMOS (NM7), the gate of which is supplied with the logic clock signal CLOCK; the drain of the seventh NMOS (NM7) outputs a signal VY to the source of the NMOS transistor NM0 in the pre-amplification stage; the gate of the NMOS transistor NM0 in the pre-amplification stage is supplied with a clock signal CLOCKB opposite to the logic clock signal CLOCK; the voltage pull-down structure 20 pulls down the signal VY input to the source of the NMOS transistor NM0 in the pre-amplification stage to a negative voltage at the instant the dual-tailed dynamic comparator 10 starts working by inputting the logic clock signal CLOCK to the gate of the seventh NMOS (NM7);
[0031] The logic control circuit 30 includes a first inverter INV (04) and a second inverter INV (05) connected in series with the first inverter INV; wherein the input terminal of the first inverter INV is connected to the logic clock signal CLOCK; the clock signal CLOCKB output by the first inverter INV is connected to the input terminal of the second inverter INV; the second inverter INV outputs a clock signal CLOCKBB that is the same as the logic clock signal CLOCK.
[0032] In a further embodiment of the present invention, the latch stage includes a PMOS transistor PM0, a first PMOS transistor (PM1), a second PMOS transistor (PM2), and first to fourth NMOS transistors (PM1 to PM4). The source of the PMOS transistor PM0 is connected to the power supply voltage VDD, its gate is connected to the clock signal CLOCKBB, and its drain is connected to the source of the first and second PMOS transistors. The gates of the first PMOS transistor (PM1) and the first NMOS transistor (NM1) are connected to the drain of the second PMOS transistor (PM2), the drain of the second NMOS transistor (NM2), and the drain of the fourth NMOS transistor (NM4). The gates of the second PMOS transistor (PM2) and the second NMOS transistor (NM2) are connected to the drain of the first PMOS transistor (PM1), the drain of the first NMOS transistor (NM1), and the drain of the third NMOS transistor (NM3).
[0033] In a further embodiment of the present invention, the gate of the second PMOS (PM2) is connected to the drain of the first PMOS to serve as the output node VOUTN; the gate of the first PMOS (PM1) is connected to the drain of the second PMOS to serve as the output node VOUTP.
[0034] Furthermore, in this embodiment, the sources of the first to fourth NMOS are grounded.
[0035] Furthermore, in this embodiment, the pre-amplification stage further includes a third PMOS (PM3), a fourth PMOS (PM4), a fifth NMOS (NM5), and a sixth NMOS (NM6); wherein the sources of the third and fourth PMOS are connected to the power supply voltage VDD; the gates of the third PMOS (PM3) and the fourth PMOS (PM4) are connected to the clock signal CLOCKB; the drain of the third PMOS (PM3) is connected to the drain of the fifth NMOS (NM5) and the gate of the third NMOS (NM3); and the drain of the fourth PMOS (PM4) is connected to the drain of the sixth NMOS (NM6) and the gate of the fourth NMOS (NM4).
[0036] In a further embodiment of the present invention, the gate of the fifth NMOS (NM5) is connected to the differential input signal VINN; the gate of the sixth NMOS (NM6) is connected to the differential input signal VINP; the pre-amplification stage pre-amplifies the differential input signals VINN and VINP, and then performs the differential output on the gates of the third NMOS (NM3) and the fourth NMOS (NM4) in the latching stage, and the differential output signals correspond to signals P and Q, respectively.
[0037] In a further embodiment of the present invention, the drain of the third PMOS (PM3) and the drain of the fifth NMOS (NM5) are connected to the upper plate of the first capacitor O1, and the lower plate of the first capacitor O1 is grounded; the drain of the fourth PMOS and the drain of the sixth NMOS are connected to the upper plate of the second capacitor O2, and the lower plate of the second capacitor O2 is grounded.
[0038] Furthermore, in this embodiment, the drain output signal VX of the NMOS transistor NM0 in the pre-amplification stage is sent to the source of the fifth NMOS (NM5) and the sixth NMOS (NM6).
[0039] Furthermore, the voltage pull-down structure in this embodiment further includes: a fifth PMOS (PM5) and a third capacitor O3; the gate of the fifth PMOS is connected to the clock signal CLOCKB; the source of the fifth PMOS is connected to the power supply voltage VDD; the drain of the fifth PMOS and the upper plate of the third capacitor O3 are jointly connected to the clock signal CLOCKBB; the lower plate of the third capacitor is connected to the source of the NMOS transistor NMO and the drain of the seventh NMOS; the source of the seventh NMOS is grounded.
[0040] like Figure 2As shown, the working principle of the circuit structure of the present invention is as follows: by controlling the voltage pull-down structure 20 through logic, the signal VY is pulled down to a negative voltage at the moment the dual-tailed dynamic comparator starts to work, thereby increasing the gate-source voltage (Vgs) of the input to the fifth NMOS (NM5) and the sixth NMOS (NM6), so that it can achieve the function of high-speed latching under low power supply voltage conditions without increasing its inherent offset.
[0041] Figure 2 The 10 preamplifier stages and latch stages together constitute the dual-tailed dynamic comparator. The preamplifier preamplifies the differential input signals VINP / VINN, and P and Q are differential outputs. The CLOCK signal and the CLOCKB signal are out of phase, while the CLOCK signal and the CLOCKBB signal are in phase. CLOCKBB is generated by delaying CLOCK through two inverters. When CLOCK is high, it is the reset phase. The NMOS transistor NM0 below the input pair NM5 and NM6 is turned off, PM3 and PM4 are turned on, and nodes P and Q (i.e., signals P and Q) are precharged to the power supply voltage. NM7 is turned on, and VY is pulled low. When NM3 and NM4 are turned on, CLOCKBB is high, PM0 is turned off, and the latch outputs VOUTP and VOUTN are 0. The latch stage does not work during this phase. When the CLOCK signal goes low, it's the comparison phase. PM3 and PM4 are off, NM0 is on, and P and Q begin to discharge. At this time, CLOCKBB changes from high to low, the voltage pull-down structure starts working, PM5 is off, and the voltage on the left plate of the capacitor jumps from high to low, causing a certain degree of pull-down to a negative voltage for VY, increasing the input voltage of NM5 and NM6 to Vgs, thereby accelerating the discharge speed of P and Q. At this time, latch stage 10 also starts working. Because the output level of the first stage decreases at different rates, the latch will lock the comparison result.
[0042] The specific workflow is as follows: The input transistors (NM3 / NM4) of the dynamic comparator 10 are sequentially turned off. When the gate voltage of the faster-turning transistor falls below the threshold voltage Vth of the latch input transistor, it will turn off the corresponding input transistor (NM3 / NM4) first. Simultaneously, CLOCKBB is low, and PM0 is turned on. When the output node voltage VOUTP / VOUTN rises to the threshold voltage of NM1 / NM2, the positive feedback begins to act. Depending on the discharge rate, the positive feedback quickly pulls one output terminal down to ground and the other terminal up to VDD. The dynamic comparator operates essentially as a charging and discharging process; there is no continuously conducting path from power supply to ground, and therefore no static power consumption.
[0043] like Figure 3 , Figure 4 As shown, Figure 3 The image shows the Virtuoso simulation results of a traditional dual-tailed dynamic comparator. Figure 4The image shown is a Virtuoso simulation result of the high-speed dynamic comparator operating at low voltage according to the present invention. It can be seen that the present invention enables the dynamic comparator to operate effectively in the low power supply range, achieving high-speed latching without increasing its inherent offset. The results are compared when the operating voltage is 0.9V. Figure 4 The design of P and Q discharge rates is relatively... Figure 3 The design is about twice as fast. Figure 3 The setup time for a traditional dual-tailed dynamic comparator is 1.68 ns. Figure 4 The dynamic comparator has a setup time of 0.534 ns, which shows that this design has a faster latching function and can be applied to SAR ADC designs with relatively higher speeds.
[0044] In summary, this invention enables the dynamic comparator to operate effectively in a low power supply range, achieving high-speed latching without increasing its inherent bias. The circuit structure of this invention provides even faster latching, expanding the power supply and process range of high-speed SAR ADCs, enhancing IP competitiveness, and broadening its application environment. Therefore, this invention effectively overcomes the various shortcomings of existing technologies and possesses high industrial applicability.
[0045] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.
Claims
1. A high-speed dynamic comparator structure operating at low voltage, characterized in that, At least including: Dual-tailed dynamic comparator; voltage pull-down structure; Logic control circuit; The dual-tailed dynamic comparator includes a pre-amplification stage and a latching stage; The pre-amplification stage pre-amplifies the differential input signals VINN and VINP and then outputs them differentially to the latching stage. The voltage pull-down structure includes a seventh NMOS, a fifth PMOS, and a third capacitor. A logic clock signal CLOCK is applied to the gate of the seventh NMOS. The drain of the seventh NMOS outputs a signal VY to the source of the NMOS transistor NM0 in the pre-amplification stage. A clock signal CLOCKB, opposite to the logic clock signal CLOCK, is applied to the gate of the NMOS transistor NM0 in the pre-amplification stage. The gate of the fifth PMOS is connected to the clock signal CLOCKB. The source of the fifth PMOS is connected to the power supply voltage VDD. The drain of the fifth PMOS and the upper plate of the third capacitor are both connected to the clock signal CLOCKBB. The lower plate of the third capacitor is connected to the source of the NMOS transistor NM0 and the drain of the seventh NMOS. The source of the seventh NMOS is grounded. The voltage pull-down structure, by inputting the logic clock signal CLOCK to the gate of the seventh NMOS, pulls the signal VY input to the source of the NMOS transistor NM0 in the pre-amplification stage to a negative voltage at the instant the dual-tailed dynamic comparator starts operating. The logic control circuit includes a first inverter and a second inverter connected in series with the first inverter; wherein the input terminal of the first inverter is connected to the logic clock signal CLOCK; the clock signal CLOCKB output by the first inverter is connected to the input terminal of the second inverter; and the second inverter outputs a clock signal CLOCKBB that is the same as the logic clock signal CLOCK.
2. The high-speed dynamic comparator structure for low-voltage operation according to claim 1, characterized in that: The latch stage includes a PMOS transistor PMO, a first PMOS, a second PMOS, and a first to a fourth NMOS. The source of the PMOS transistor PMO is connected to the power supply voltage VDD, its gate is connected to the clock signal CLOCKBB, and its drain is connected to the source of the first and second PMOS. The gates of the first PMOS and the first NMOS are connected to the drain of the second PMOS, the drain of the second NMOS, and the drain of the fourth NMOS. The gates of the second PMOS and the second NMOS are connected to the drain of the first PMOS, the drain of the first NMOS, and the drain of the third NMOS.
3. The high-speed dynamic comparator structure for low-voltage operation according to claim 2, characterized in that: The gate of the second PMOS is connected to the drain of the first PMOS, serving as the output node VOUTN; the gate of the first PMOS is connected to the drain of the second PMOS, serving as the output node VOUTP.
4. The high-speed dynamic comparator structure for low-voltage operation according to claim 2, characterized in that: The sources of the first to fourth NMOS transistors are grounded.
5. The high-speed dynamic comparator structure for low-voltage operation according to claim 2, characterized in that: The pre-amplification stage further includes a third and a fourth PMOS; a fifth and a sixth NMOS; wherein the source of the third and fourth PMOS is connected to the power supply voltage VDD; the gate of the third and fourth PMOS is connected to the clock signal CLOCKB; the drain of the third PMOS is connected to the drain of the fifth NMOS and the gate of the third NMOS; the drain of the fourth PMOS is connected to the drain of the sixth NMOS and the gate of the fourth NMOS.
6. The high-speed dynamic comparator structure for low-voltage operation according to claim 5, characterized in that: The gate of the fifth NMOS is connected to the differential input signal VINN; the gate of the sixth NMOS is connected to the differential input signal VINP; the pre-amplification stage pre-amplifies the differential input signals VINN and VINP, and then performs the differential output on the gates of the third and fourth NMOS in the latching stage, which correspond to signals P and Q respectively.
7. The high-speed dynamic comparator structure for low-voltage operation according to claim 6, characterized in that: The drain of the third PMOS and the drain of the fifth NMOS are connected to the upper plate of the first capacitor, and the lower plate of the first capacitor is grounded; the drain of the fourth PMOS and the drain of the sixth NMOS are connected to the upper plate of the second capacitor, and the lower plate of the second capacitor is grounded.
8. The high-speed dynamic comparator structure for low-voltage operation according to claim 7, characterized in that: The drain output signal VX of the NMOS transistor NM0 in the pre-amplification stage is sent to the source of the fifth and sixth NMOS transistors.