Memory array and method for forming a memory array including strings of memory cells

Abstract

A memory array comprising strings of memory cells includes laterally spaced memory blocks, each comprising a vertical stack including alternating insulating and conductive layers. Strings of operative channel material for the memory cells extend through the insulating and conductive layers. Insulating pillars are laterally positioned between laterally adjacent memory blocks and longitudinally spaced along the laterally adjacent memory blocks. The pillars directly abut against the conductive material of conductive lines in the conductive layers. Other arrays and methods are disclosed.

Description

Technical Field

[0001] The embodiments disclosed herein relate to memory arrays and methods for forming memory arrays comprising strings of memory cells. Background Technology

[0002] Memory is a type of integrated circuit system used in computer systems to store data. Memory can be manufactured as one or more arrays of individual memory cells. Memory cells can be written to or read from using digital lines (also called bit lines, data lines, or sense lines) and access lines (also called word lines). Sense lines electrically interconnect memory cells along columns of the array, and access lines electrically interconnect memory cells along rows of the array. Each memory cell can be uniquely addressed by a combination of sense lines and access lines.

[0003] Memory cells can be volatile, semi-volatile, or non-volatile. Non-volatile memory cells can store data for extended periods without power. Non-volatile memory is typically specified as memory with a retention time of at least approximately 10 years. Volatile memory dissipates and is therefore refreshed / rewritten to maintain data storage. Volatile memory can have retention times of milliseconds or less. In any case, memory cells are configured to retain or store memory in at least two distinct optional states. In binary systems, states are considered to be "0" or "1". In other systems, at least some individual memory cells can be configured to store information in more than two levels or states.

[0004] A field-effect transistor (FET) is a type of electronic component that can be used in memory cells. These transistors include a pair of conductive source / drain regions with a semi-conductive channel between them. A conductive gate is adjacent to the channel region and separated from it by a thin gate insulator. Applying a suitable voltage to the gate allows current to flow through the channel region from one of the source / drain regions to the other. When the voltage is removed from the gate, current flow through the channel region is greatly prevented. FETs may also include additional structures, such as a reversible programmable charge storage region as part of the gate construction between the gate insulator and the conductive gate.

[0005] Flash memory is a type of memory widely used in modern computers and devices. For example, modern personal computers store the BIOS on flash memory chips. As another example, it is increasingly common for computers and other devices to use flash memory, in the form of solid-state drives, instead of traditional hard disk drives. As yet another example, flash memory is prevalent in wireless electronic devices because it enables manufacturers to support new communication protocols as they become standardized, and allows manufacturers to provide the ability to remotely upgrade devices for enhanced features.

[0006] NAND can be a basic architecture for integrated flash memory. A NAND cell device includes at least one selection device series-coupled with a series combination of memory cells (and said series combination is generally referred to as a NAND string). NAND architectures can be configured in a three-dimensional arrangement, comprising vertically stacked memory cells, each vertically stacked memory cell individually including a reversibly programmable vertical transistor. Control components or other circuitry may be formed beneath the vertically stacked memory cells. Other volatile or non-volatile memory array architectures may also include vertically stacked memory cells individually including transistors.

[0007] Memory arrays can be arranged in memory pages, memory blocks, and portions of blocks (e.g., sub-blocks), as well as memory planes, as shown and described, for example, in any of U.S. Patent Application Publications Nos. 2015 / 0228659, 2016 / 0267984, and 2017 / 0140833, which are hereby fully incorporated herein by reference, and aspects thereof can be used in some embodiments of the invention disclosed herein. A memory block can at least partially define the longitudinal profile of individual word lines in an individual word line level of vertically stacked memory cells. Connections to these word lines can occur in a so-called “step structure” at the ends or edges of the array of vertically stacked memory cells. The step structure includes individual “steps” (alternatively referred to as “steps” or “staircases”) defining contact areas for individual word lines, with vertically extending conductive vias contacting said contact areas to provide electrical access to the word lines. Attached Figure Description

[0008] Figure 1 Is it through Figure 2 The diagram shows a cross-sectional view of a portion of a substrate under processing according to an embodiment of the present invention, taken by line 1-1.

[0009] Figure 2 Is it through Figure 1 A schematic diagram of the cross-section taken from line 2-2 in the diagram.

[0010] Figure 3-21 This is a process according to some embodiments of the present invention. Figure 1 and 2 A sequential cross-section and / or enlarged schematic diagram of the structure or its parts. Detailed Implementation

[0011] Some aspects of the present invention aim to overcome the problems associated with so-called “block bending” (the lateral tilting / tilting of a block stack relative to its longitudinal orientation during manufacturing), but the invention is not limited thereto.

[0012] Embodiments of the present invention cover methods for forming memory arrays, such as arrays of NAND or other memory cells having a peripheral control circuitry system (e.g., under-array CMOS) below the array. Embodiments of the present invention cover so-called "back-gate" or "replacement gate" processes, so-called "front-gate" processes, and other processes, whether existing or future-developed, that are independent of the formation timing of transistor gates. Embodiments of the present invention also cover memory arrays (e.g., NAND architectures) independent of the manufacturing method. Reference Figure 1-21 The described example method embodiments can be considered as a "post-gate" or "replacement gate" process.

[0013] Figure 1 and 2 The diagram illustrates a configuration 10 having an array or array region 12 in which vertically extending strings of transistors and / or memory cells will be formed. Configuration 10 includes a substrate 11 having any one or more of the following materials: conductive / conductive / conductive, semiconductive / semiconductor / semiconductive, or insulating / insulator / insulator (i.e., electrically) materials. Various materials are vertically formed above the substrate 11. The materials may... Figure 1 and 2 The material depicted is adjacent to, vertically inward, or vertically outward. For example, components of other parts or all of the integrated circuit system may be provided somewhere above, around, or inside the base substrate 11. Control and / or other peripheral circuitry systems for operating components within an array (e.g., array 12) of vertically extending strings of memory cells may also be fabricated, and said systems may or may not be entirely or partially within the array or subarray. Furthermore, multiple subarrays may be fabricated and operated relatively independently of each other, sequentially, or otherwise. In this document, "subarray" may also be considered as an array.

[0014] A conductive layer 16, comprising conductive material 17, is formed above the substrate 11. The conductive layer 16 may include portions of a control circuitry (e.g., peripheral array under-circuit system and / or common source line or board) for controlling read and write access to transistors and / or memory cells to be formed within the array 12. A stack 18, comprising vertically alternating insulating layers 20 and conductive layers 22, is formed above the conductive layer 16. Examples of the thickness of each of layers 20 and 22 are 22 to 60 nanometers. Only a small number of layers 20 and 22 are shown; the stack 18 is more likely to comprise tens, hundreds, or more layers 20 and 22. Other circuitry, which may or may not be portions of the peripheral and / or control circuitry, may be situated between the conductive layer 16 and the stack 18. For example, multiple vertically alternating layers of conductive and insulating material of such circuitry may be below the lowermost conductive layer 22 and / or above the uppermost conductive layer 22. For example, one or more select gate layers (not shown) may be between conductor layer 16 and the lowermost conductive layer 22, and one or more select gate layers may be above the uppermost conductive layer 22. In any case, conductive layer 22 (alternatively referred to as the first layer) may not include conductive material, and insulating layer 20 (alternatively referred to as the second layer) may not include insulating material or may be insulating when combined with the process of the "back gate" or "alternate gate" example method embodiment described herein. Example conductive layer 22 includes a first material 26 (e.g., silicon nitride) that may be completely or partially sacrificed. Example insulating layer 20 includes a second material 24 (e.g., silicon dioxide) that has a different composition from the first material 26 and may be completely or partially sacrificed.

[0015] A channel opening 25 is formed through the insulating layer 20 and the conductive layer 22 to the conductor layer 16 (e.g., by etching). In some embodiments, the channel opening 25 may partially extend into the conductive material 17 of the conductor layer 16 as shown, or may terminate on top (not shown). Alternatively, as an example, the channel opening 25 may terminate on top of or inside the lowermost insulating layer 20. The reason for extending the channel opening 25 at least to the conductive material 17 of the conductor layer 16 is to ensure that, when such a connection is desired, the subsequently formed channel material (not shown) is directly electrically coupled to the conductor layer 16 without the use of alternative processes and structures. An etch-stopping material (not shown) may be inside or on top of the conductive material 17 of the conductor layer 16 to facilitate the termination of etching of the channel opening 25 relative to the conductor layer 16 when such a requirement is desired. Such an etch-stopping material may be sacrificial or non-sacrificial. For example, and for simplicity only, the channel openings 25 are shown as groups or columns arranged in staggered rows of four and five openings 25 per row, and arranged in laterally spaced memory block regions 58, which will comprise laterally spaced memory blocks 58 in the finished circuit system construction. In this document, "block" generally includes "sub-block". The memory block regions 58 and the resulting memory blocks 58 (not shown) can be considered as longitudinally elongated and oriented, for example, along direction 55. The memory block regions 58 may be indistinguishable at this processing point. Any alternative existing or future-developed arrangements and constructions may be used.

[0016] Transistor channel material can be formed vertically along insulating and conductive layers in individual channel openings, thus including individual channel material strings directly electrically coupled to conductive material in the conductive layer. Individual memory cells of an example memory array in formation may include a gate region (e.g., a control gate region) and a memory structure laterally positioned between the gate region and the channel material. In one such embodiment, the memory structure is formed to include a charge-blocking region, a storage material (e.g., a charge storage material), and an insulating charge-transfer material. The storage material of the individual memory cell (e.g., a floating gate material, such as doped or undoped silicon, or a charge-trapping material, such as silicon nitride, metal dots, etc.) is formed vertically along the individual charge-blocking region within the charge-blocking region. The insulating charge-transfer material (e.g., a bandgap-engineered structure having a nitrogen-containing material (e.g., silicon nitride) sandwiched between two insulating oxides (e.g., silicon dioxide) is laterally positioned between the channel material and the storage material.

[0017] Figure 3 , 3AFigures 4 and 4A illustrate an embodiment in which charge-blocking material 30, storage material 32, and charge-transfer material 34 are vertically formed in individual channel openings 25 along insulating layer 20 and conductive layer 22. Transistor materials 30, 32, and 34 (e.g., memory cell materials) can be formed, for example, by depositing corresponding thin layers of the transistor materials above stack 18 and within individual channel openings 25 and subsequently planarizing such transistor materials back at least to the top surface of stack 18. Channel material 36 is also vertically formed in channel openings 25 along insulating layer 20 and conductive layer 22, thereby comprising individual operative channel material strings 53. Due to proportions, materials 30, 32, 34, and 36 in Figure 3 and 4 The material 37 is shown and designated only in the examples. Example channel material 36 comprises a suitably doped crystalline semiconductor material, such as one or more silicon, germanium, and so-called Group III / V semiconductor materials (e.g., GaAs, InP, GaP, and GaN). The thickness of each of materials 30, 32, 34, and 36 is typically 25 to 100 angstroms. Punch etching can be performed to remove materials 30, 32, and 34 from the substrate at the channel opening 25 to expose the conductor layer 16, such that the channel material 36 directly abuts the conductor material 17 of the conductor layer 16. Such punch etching can occur individually with respect to each of materials 30, 32, and 34 (as shown), or it can occur jointly with respect to all materials after the deposition of material 34 (not shown). Alternatively, and only by way of example, punch etching may not be performed, and the channel material 36 may be directly electrically coupled to the conductor material 17 of the conductor layer 16 via separate conductive interconnects (not shown). The channel opening 25 is shown to include a radially centered solid dielectric material 38 (e.g., spin-coated dielectric, silicon dioxide, and / or silicon nitride). Alternatively, and by way of example only, the radially centered portion within the channel opening 25 may include void spaces (not shown) and / or may not contain solid material (not shown). A conductive plug (not shown) may be formed on top of the channel material string 53 for better conductive connection to the overlying circuitry (not shown).

[0018] refer to Figure 5 and 6 In the stack 18, horizontally elongated trenches 40 are formed (e.g., by anisotropic etching) to form laterally spaced memory block regions 58. The horizontally elongated trenches 40 may have a corresponding bottom (as shown) directly abutting the conductive material 17 of the conductor layer 16 (e.g., top or interior), or may have a corresponding bottom (not shown) above the conductive material 17 of the conductor layer 16.

[0019] The above process illustrates forming and filling the channel opening 25 before forming the groove 40. This process can be reversed. Alternatively, the groove 40 can be formed between forming and filling the channel opening 25 (which is not ideal).

[0020] refer to Figure 7 and 8 A filler material 57 has been formed in a horizontally elongated trench 40. If such material is to be retained in the finished circuit system construction, then such material should be non-conductive at least at and along the outermost lateral edge of the trench 40. If it is entirely sacrificial, then any material can be used regardless of conductivity. Examples of insulating materials include silicon dioxide, aluminum dioxide, hafnium silicate, etc. If the process is performed according to post-gate formation, then the filler material 57 should have a composition different from that of material 26, such that material 26 can be selectively etched relative to the filler material 57. If, for example, material 26 comprises a composition other than silicon nitride, then the filler material 57 may comprise silicon nitride. Alternatively, by way of example only, if the process is gate-first, then the filler material 57 may comprise silicon nitride. If gate-first, then a horizontally elongated trench is formed through the conductive material (not shown) across the conductive layer 22.

[0021] refer to Figure 9 and 10 Vertically extending holes 60 have been formed (e.g., by photolithography and anisotropic dry etching) into the filler material 57. The holes 60 are longitudinally spaced along the laterally adjacent memory block regions 58. In one embodiment, the holes 60 are formed vertically or within a vertical 10°. In one embodiment, the holes 60 are in a horizontal cross-section (e.g., Figure 9The hole 60 has a circular shape in its cross-section. Regardless, all holes 60 extend laterally across individual horizontally elongated grooves 40 and form insulating struts 61 laterally positioned between and longitudinally spaced along the adjacent memory block regions 58, which are longitudinally positioned between the holes 60. Ideally, the holes 60 are formed through all alternating insulating layers 20 and conductive layers 22. Example struts 61 have a quadrilateral shape in their horizontal cross-section. However, in one embodiment, struts 61 include a pair of laterally opposing concave sides 66 in their horizontal cross-section. In one embodiment, the concave sides 66 are curved, end-to-end curved in the horizontal cross-section in one such embodiment, and have a constant radius in the horizontal cross-section in a later such embodiment, as shown. Alternatively, the concave sides 66 may not have curved portions (e.g., squares, rectangles, triangles, etc., not shown) or may include a combination of curved and straight portions (not shown). In one embodiment, struts 61 include a pair of laterally opposing flat sides 64 in their horizontal cross-section. In one such embodiment, the laterally opposed flat sides 64 are oriented parallel to the longitudinal orientation of their laterally adjacent memory block region 58 (e.g., along direction 55). In one embodiment, the strut 61 extends through all alternating insulating layers 20 and conductive layers 22, respectively. In one embodiment, at least a major (greater than 50% and comprising 100%) composition of the strut 61 is the same as the composition of the insulating layer 20, and in another embodiment, at least a major composition is different from the composition of the insulating layer 20. In one embodiment, the strut 61 is vertical or within 10° of vertical.

[0022] Figure 9 and 10 An example embodiment is shown in which the hole 60 is formed to extend laterally beyond the filling material 57. Figure 11 and 12An example alternative embodiment construction 10a is shown, comprising an array 12a including memory block regions 58a, wherein the aperture 60a does not extend laterally beyond the filling material 57. The same reference numerals as those used in the embodiments described above are used where appropriate, with the suffix "a" or different reference numerals indicating certain construction differences. The example aperture 60a is shown as having the same width as the trench 40 and, by way of example only, a quadrilateral (e.g., rectangular) shape. In one embodiment and as shown, the aperture 60a has laterally opposed flat sides 64 that directly abut against the insulating material 24 of the insulating layer 20 and, in one embodiment, directly against the material 26 of the conductive layer 22. The sides 66a of the pillar 61a are shown as flat, and thus include another pair of laterally opposed flat sides 66a in the horizontal cross-section in addition to the pair of laterally opposed flat sides 64. The example laterally opposed flat sides 66a are oriented orthogonally longitudinally (e.g., orthogonal to direction 55) to the memory block region 58 to which they are laterally adjacent. Any other properties or aspects as shown and / or described herein with respect to other embodiments may be used.

[0023] refer to Figure 13-15 In one embodiment, material 26 (not shown) of the conductive layer 22 is removed, for example, by isotropically etching it through the aperture 60 with a preference for other exposed materials (e.g., using liquid or gaseous H3PO4 as the primary etchant, where material 26 is silicon nitride and other materials include one or more oxides or polysilicon). In an exemplary embodiment, material 26 in the conductive layer 22 is sacrificial and replaced with conductive material 48, and is subsequently removed from the aperture 60, thus forming individual conductive lines 29 (e.g., word lines) and vertically extending strings 49 of individual transistors and / or memory cells 56. The conductive material 48 may be laterally recessed within the conductive layer 22 from laterally opposite edges of the aperture 60 (not shown) and may also be laterally recessed from laterally opposite edges of material 57 (not shown) to ensure that the individual conductive lines 29 are vertically separated from each other. A thin insulating liner (e.g., Al2O3, not shown) may be formed prior to the formation of the conductive material 48. The general orientation of the transistors and / or memory cells 56 is as follows: Figure 15 Parentheses are used to indicate this, while some are in Figure 13 and 14The transistors and / or memory cells 56 are shown in a dashed outline, where they are substantially ring-shaped in the depicted example. Alternatively, the transistors and / or memory cells 56 may not completely surround the individual channel openings 25, such that each channel opening 25 may have two or more vertically extending strings 49 (e.g., in an individual conductive layer, multiple transistors and / or memory cells surround an individual channel opening, where there may be multiple word lines per channel opening in an individual conductive layer, and these are not shown). The conductive material 48 can be considered as having ends 50 corresponding to control gate regions 52 of the individual transistors and / or memory cells 56. Figure 15 In the depicted embodiment, the control gate region 52 includes individual portions of individual conductive lines 29. Materials 30, 32, and 34 can be considered as a memory structure 65 laterally located between the control gate region 52 and the channel material 36. In one embodiment, and as shown with respect to the example of “back gate” processing, the conductive material 48 of the conductive layer 22 is formed after the formation of the vias 60 / 60a. Alternatively, for example with respect to “front gate” processing, the conductive material of the conductive layer may be formed before the formation of the vias 60 / 60a and / or before the formation of the trench 40 (not shown).

[0024] A charge-blocking region (e.g., charge-blocking material 30) is located between the storage material 32 and each control gate region 52. The charge-blocking element in the memory cell may function to prevent charge carriers from flowing out of the storage material (e.g., floating gate material, charge trapping material, etc.) to the control gate in programming mode, and to prevent charge carriers from flowing from the control gate into the charge storage material in erase mode. Therefore, the charge block can be used to block charge migration between the control gate region and the storage material of an individual memory cell. As illustrated, the charge-blocking region includes an insulating material 30. By other examples, the charge-blocking region may include a lateral (e.g., radial) outer portion of the storage material (e.g., material 32), wherein this storage material is insulating (e.g., in the absence of any different compositional materials between the insulating storage material 32 and the conductive material 48). In any case, as an additional example, the interface between the storage material and the conductive material of the control gate may be sufficient to act as a charge-blocking region in the absence of any single-component insulating material 30. Furthermore, the interface between the conductive material 48 and the insulating material 30 (if present) can together serve as a charge-blocking region, and alternatively or additionally serve as a lateral outer region of an insulating storage material (e.g., silicon nitride material 32). Example material 30 is one or more of hafnium oxide and silicon dioxide.

[0025] Figure 16 and 17 A similar process is shown for the construction 10a that forms the example conductive line 29a.

[0026] The insulating post 61 (not shown) can be removed, and the remaining volume of the trench 40 is subsequently filled with insulating material. Alternatively, and as... Figure 18-21 As shown, the holes 60 / 60a have been filled with insulating material 71, thus forming insulating pillars 63 / 63a. The insulating material 71 may have the same or different composition as the insulating pillars 61 / 61a and the insulating material 24. Example pillar 63 has a circular shape in horizontal cross-section, while example pillar 63a has a quadrilateral shape in horizontal cross-section. Example pillar 63 includes a pair of laterally opposed concave sides 66 in horizontal cross-section. In any case, and in one embodiment, as shown, the pillar 63 is laterally projected onto the side surface 73 of the conductive material 48 of the conductive line 29. In one embodiment, example conductive lines 29 in individual conductive layers 22 include laterally opposed side surfaces 73. Figure 18 The laterally opposed sides 73 individually include longitudinally spaced concave regions 75. In one embodiment, the concave regions 75 are curved from end to end, and in one such embodiment, for example, as shown, the curved concave regions 75 have a constant radius. Alternatively, the concave regions 75 may not have curved portions (e.g., are squares, rectangles, triangles, etc., and not shown) or may include a combination of curved and straight portions (not shown). Any other properties or aspects as shown and / or described herein with respect to other embodiments may be used.

[0027] In one embodiment, memory block 58 has been formed to individually include laterally opposed sides 59. Figure 19 The laterally opposite sides 59 individually include recessed areas 77 spaced vertically along the longitudinal direction of the stack 18. For clarity, in Figure 19 Only two sides 59 and two regions 77 are specified. In one such embodiment, such concave regions 77 are curved from end to end, and in one such embodiment, such curved concave regions 77 have a constant radius. Alternatively, concave regions 77 may not have curved portions (e.g., are squares, rectangles, triangles, etc., and not shown) or may include a combination of curved and straight portions (not shown). Any other properties or aspects as shown and / or described herein with respect to other embodiments may be used.

[0028] Embodiments of the present invention cover memory arrays independent of manufacturing methods. Nevertheless, such memory arrays may have any of the properties described herein in the method embodiments. Similarly, the method embodiments described above may be incorporated into and form any of the properties described with respect to the apparatus embodiments.

[0029] Embodiments of the invention include memory arrays (e.g., 12 and / or 12a) comprising strings of memory cells (e.g., 49). Such embodiments include laterally spaced memory blocks (e.g., 58 and / or 58a), each comprising a vertical stack (e.g., 18) comprising alternating insulating layers (e.g., 20) and conductive layers (e.g., 22). Strings (e.g., 53) of operative channel material for memory cells (e.g., 56) extend through the insulating and conductive layers.

[0030] In one embodiment, insulating struts (e.g., 61 / 61a and / or 63 / 63a) are laterally positioned between laterally adjacent memory blocks and longitudinally spaced along the laterally adjacent memory blocks. The struts directly abut against the conductive material (e.g., 48) of the conductive lines (e.g., 29) in the conductive layer. In one embodiment, the struts (e.g., 63) are larger than the channel material string at all points in their horizontal cross-section. Any other properties or aspects as shown and / or described herein with respect to other embodiments may be used.

[0031] In one embodiment, insulating struts (e.g., 61 / 61a and / or 63a) are laterally positioned between laterally adjacent memory blocks and longitudinally spaced along the laterally adjacent memory blocks. The struts include a pair of laterally opposed flat sides (e.g., 64) in a horizontal cross-section. Any other properties or aspects as shown and / or described herein with respect to other embodiments may be used.

[0032] In one embodiment, insulating struts (e.g., 61) are laterally positioned between laterally adjacent memory blocks and longitudinally spaced along the laterally adjacent memory blocks. The struts include a pair of laterally opposing concave sides (e.g., 66) in a horizontal cross-section. Any other properties or aspects as shown and / or described herein with respect to other embodiments may be used.

[0033] In one embodiment, the conductive lines in individual conductive layers (e.g., 29, 29a) individually include laterally opposed sides (e.g., 73), which individually include longitudinally spaced concave regions (e.g., 75). Any other properties or aspects as shown and / or described herein with respect to other embodiments may be used.

[0034] In one embodiment, the memory block individually includes laterally opposed sides (e.g., 59), which individually include recessed regions (e.g., 77) spaced vertically along the stack longitudinal direction. Any other properties or aspects as shown and / or described herein with respect to other embodiments may be used.

[0035] The above-described processing or construction can be viewed as an array of components formed as a single stack or group of such components, or within a single stack or group, which is above or part of a bottom-side substrate (but a single stack / group may have multiple layers). Control and / or other peripheral circuitry for operating or accessing components within the array may also be formed anywhere as part of the finished construction, and in some embodiments may be under the array (e.g., under-array CMOS). In any case, one or more additional such stacks / groups may be provided or fabricated above and / or below the stacks / groups shown in the diagram or described above. Furthermore, the arrays of components may be the same or different relative to each other in different stacks / groups, and the different stacks / groups may have the same or different thicknesses relative to each other. Intermediate structures may be disposed between vertically adjacent stacks / groups (e.g., additional circuitry and / or dielectric layers). And, the different stacks / groups may be electrically coupled relative to each other. Multiple stacks / groups can be manufactured individually and sequentially (e.g., one on top of another), or two or more stacks / groups can be manufactured substantially simultaneously.

[0036] The assemblies and structures discussed above can be used in integrated circuit / circuit systems and incorporated into electronic systems. Such electronic systems can be used in, for example, memory modules, device drivers, power modules, communication modems, processor modules, and application-specific modules, and can contain multi-layered, multi-chip modules. Electronic systems can be any of the following wide range of systems: for example, cameras, wireless devices, displays, chipsets, set-top boxes, games, lighting systems, vehicles, clocks, televisions, cellular phones, personal computers, automobiles, industrial control systems, aircraft, etc.

[0037] In this document, unless otherwise indicated, “vertical,” “higher,” “upper,” “lower,” “top,” “top,” “bottom,” “above,” “below,” “under,” “upward,” and “downward” generally refer to the vertical direction. “Horizontal” refers to a generally relative direction (i.e., within 10 degrees) along the surface of the main substrate, where the substrate is processed during manufacturing, and which is generally orthogonal to vertical. “Just horizontal” is a generally relative direction (i.e., not at an angle) along the surface of the main substrate. Furthermore, “vertical” and “horizontal” as used herein are generally perpendicular to each other and independent of the orientation of the substrate in three-dimensional space. Additionally, “vertically extending” and “vertically extending” refer to a direction deviating at least 45° from just horizontal. Furthermore, “vertically extending,” “vertically extending,” “horizontally extending,” “horizontally extending,” etc., relative to a field-effect transistor, refer to the orientation of the transistor’s channel length along which current flows between the source / drain regions during operation. For bipolar junction transistors, terms such as "vertically extending," "vertically extending," "horizontally extending," and "horizontally extending" refer to the orientation of the substrate length along which current flows between the emitter and collector during operation. In some embodiments, any vertically extending component, feature, and / or region extends vertically or within a vertical 10°.

[0038] Furthermore, "directly above," "directly below," and "directly below" require that the two stated areas / materials / components have at least some lateral overlap (i.e., horizontally) relative to each other. Moreover, using "above" without the preceding "direct" only requires that a portion of the stated area / material / component above the other stated area / material / component extends vertically outward from the other stated area / material / component (i.e., regardless of whether there is any lateral overlap between the two stated areas / materials / components). Similarly, using "below" and "under" without the preceding "direct" only requires that a portion of the stated area / material / component below / under the other stated area / material / component extends vertically inward from the other stated area / material / component (i.e., regardless of whether there is any lateral overlap between the two stated areas / materials / components).

[0039] Any of the materials, regions, and structures described herein may be homogeneous or non-homogeneous, and in any event may be continuous or discontinuous over any material covering them. When one or more example compositions are provided for any material, the material may comprise, consist primarily of, or consist of such one or more compositions. Furthermore, unless otherwise stated, any suitable existing or future-developed techniques may be used to form each material, with atomic layer deposition, chemical vapor deposition, physical vapor deposition, epitaxial growth, diffusion doping, and ion implantation being examples.

[0040] Additionally, the term "thickness" used alone (without a directional adjective) is defined as the average straight-line distance perpendicular to the nearest surface of adjacent materials or regions with different compositions, passing through a given material or region. Furthermore, the various materials or regions described herein may have substantially constant thickness or variable thickness. If variable thickness is present, then unless otherwise indicated, the thickness refers to the average thickness, and the material or region will have a minimum thickness and a maximum thickness due to the variable thickness. As used herein, "different compositions" only requires that the portions of two stated materials or regions that can directly contact each other are chemically and / or physically different, for example, in cases where such materials or regions are not homogeneous. If two stated materials or regions are not directly contacting each other, then in cases where such materials or regions are not homogeneous, "different compositions" only requires that the portions of two stated materials or regions that are closest to each other are chemically and / or physically different. In this document, one material, region, or structure "directly contacts" another material, region, or structure when there is at least some physical contact between the stated materials, regions, or structures. In contrast, the words "over," "on," "near," "along," and "against" without the preceding "positive" encompass "direct contact" and constructions in which the intervening material, area, or structure causes the stated material, area, or structure to have no physical contact with each other.

[0041] In this text, if, during normal operation, current can flow continuously from one region-material-component to another, and this flow is primarily accomplished by the movement of said subatomic positive and / or negative charges when sufficient subatomic positive and / or negative charges are generated, then the region-material-components are “electrically coupled” relative to each other. Another electronic component may be electrically coupled between and to the region-material-components. In contrast, when region-material-components are referred to as “directly electrically coupled,” there are no intervening electronic components (e.g., no diodes, transistors, resistors, transducers, switches, fuses, etc.) between directly electrically coupled region-material-components.

[0042] Any use of the terms "row" and "column" in this document is for the convenience of distinguishing one series or orientation of features from another series or orientation of features, and for which components have been or may be formed along said "row" and "column". "Row" and "column" are used synonymously with any series of areas, components, and / or features, regardless of function. In any case, rows may be straight and / or curved and / or parallel and / or non-parallel relative to each other, and columns may be the same. Furthermore, rows and columns may intersect each other at 90° or at one or more other angles.

[0043] The components of any of the conductive / conductor / conductive materials mentioned herein may be metallic materials and / or conductive-doped semiconducting / semiconductor / semiconductive materials. "Metallic material" means any elemental metal, any mixture or alloy of two or more elemental metals, and any one or more conductive metallic compounds.

[0044] In this document, any use of “selective” in relation to etching, removal, deposition, formation, and / or shaping is an action in which a stated material is performed relative to another stated material at a volume ratio of at least 2:1. Additionally, any use of selective deposition, selective growth, or selective formation is the deposition, growth, or formation of one material relative to one or more stated materials at a volume ratio of at least 2:1 for a depth of at least 75 angstroms.

[0045] Unless otherwise indicated, the use of "or" in this document covers either one or both.

[0046] in conclusion

[0047] In some embodiments, the memory array comprising strings of memory cells includes laterally spaced memory blocks, each of which individually comprises a vertical stack comprising alternating insulating and conductive layers. Strings of operative channel material for the memory cells extend through the insulating and conductive layers. Insulating struts are laterally positioned between laterally adjacent memory blocks and longitudinally spaced along the laterally adjacent memory blocks. The struts directly abut against the conductive material of conductive lines in the conductive layers.

[0048] In some embodiments, the memory array comprising strings of memory cells includes laterally spaced memory blocks, each of which individually comprises a vertical stack comprising alternating insulating and conductive layers. Strings of operative channel material for the memory cells extend through the insulating and conductive layers. Insulating struts are laterally positioned between laterally adjacent memory blocks and longitudinally spaced along the laterally adjacent memory blocks. Each strut comprises a pair of laterally opposing flat sides in a horizontal cross-section.

[0049] In some embodiments, the memory array comprising strings of memory cells includes laterally spaced memory blocks, each of which individually comprises a vertical stack comprising alternating insulating and conductive layers. Strings of operative channel material for the memory cells extend through the insulating and conductive layers. Insulating struts are laterally positioned between laterally adjacent memory blocks and longitudinally spaced along the laterally adjacent memory blocks. Each strut includes a pair of laterally opposing concave sides in a horizontal cross-section.

[0050] In some embodiments, the memory array including strings of memory cells includes laterally spaced memory blocks, each of which individually includes a vertical stack comprising alternating insulating and conductive layers. Strings of operative channel material for the memory cells extend through the insulating and conductive layers. Conductive lines in individual conductive layers of the conductive layers individually include laterally opposed sides, each of which individually includes longitudinally spaced concave regions.

[0051] In some embodiments, the memory array comprising strings of memory cells includes laterally spaced memory blocks, each of which individually includes a vertical stack comprising alternating insulating and conductive layers. Strings of operative channel material for the memory cells extend through the insulating and conductive layers. Each memory block individually includes laterally opposed sides, each of which individually includes recessed regions spaced vertically along the longitudinal direction of the stack.

[0052] In some embodiments, a method for forming a memory array comprising strings of memory cells includes forming a stack comprising vertically alternating first and second layers. Horizontally elongated trenches are formed in the stack to form laterally spaced memory block regions. A filler material is formed in the horizontally elongated trenches. Vertically extending holes are formed in the filler material and longitudinally spaced along laterally adjacent memory block regions. All holes extend laterally across individual horizontally elongated trenches and form insulating struts laterally located between and longitudinally spaced along laterally adjacent memory block regions, the memory block regions being longitudinally located between the holes.

Claims

1. A memory array comprising strings of memory cells, comprising: Horizontally spaced memory blocks, each comprising a vertical stack, the vertical stack including alternating insulating and conductive layers, with strings of operative channel material for memory cells extending through the insulating and conductive layers; and An insulating pillar, which is laterally positioned between the laterally adjacent memory blocks and longitudinally spaced along the laterally adjacent memory blocks, directly abuts against the conductive material of the conductive wires in the conductive layer. The conductive line is located in an individual conductive layer of the conductive layer, the conductive line individually including laterally opposed sides, the laterally opposed sides individually including longitudinally spaced concave areas into which the insulating pillar extends laterally, the insulating pillar extending through all alternating insulating layers and conductive layers, and including a vertical and centrally located insulating core extending through all alternating insulating layers and conductive layers.

2. The memory array of claim 1, wherein the concave region is curved from end to end.

3. The memory array of claim 2, wherein the curved concave region has a constant radius.

4. The memory array of claim 1, wherein the insulating pillars are horizontal and uniform from top to bottom.

5. The memory array according to claim 1, comprising NAND.

6. The memory array of claim 1, wherein the concave region does not have a curved portion.

7. The memory array of claim 1, wherein the concave region has a combination of curved portions and straight portions.

8. A memory array comprising a string of memory cells, comprising: Horizontally spaced memory blocks, each comprising a vertical stack, the vertical stack comprising alternating insulating and conductive layers, with strings of operational channel material for memory cells extending through the insulating and conductive layers; An insulating pillar is laterally positioned between the laterally adjacent memory blocks and longitudinally spaced along the laterally adjacent memory blocks, the insulating pillar directly abutting the conductive material of the conductive wires in the conductive layer; The conductive lines are located in individual conductive layers of the conductive layers, each conductive line individually including laterally opposed sides, each laterally opposed side individually including longitudinally spaced concave regions, the concave regions not being end-to-end curved in a horizontal cross-section, the insulating struts extending through all alternating insulating layers and conductive layers, and including a vertical and centrally located insulating core extending through all alternating insulating layers and conductive layers.

9. The memory array of claim 8, wherein the concave region does not have a curved portion.

10. The memory array of claim 8, wherein the concave region has a combination of curved portions and straight portions.

11. The memory array of claim 8, wherein the insulating pillars are horizontal and uniform from top to bottom.

12. A memory array comprising a string of memory cells, comprising: Horizontally spaced memory blocks, each comprising a vertical stack, the vertical stack including alternating insulating and conductive layers, with strings of operative channel material for memory cells extending through the insulating and conductive layers; and A pair of first insulating pillars are laterally positioned between the laterally adjacent memory blocks and longitudinally spaced by a second insulating pillar along the laterally adjacent memory blocks. The first insulating pillars and the second insulating pillars directly abut against the conductive material of the conductive wires in the conductive layer. The first insulating pillars and the second insulating pillars have different compositions and directly abut against each other. The first insulating pillars are uniformly oriented horizontally throughout their horizontal cross-section.

13. The memory array of claim 12, wherein the first insulating pillar is uniform from top to bottom.

14. The memory array of claim 12, wherein the second insulating pillar is uniformly distributed horizontally throughout the horizontal cross-section.

15. The memory array of claim 14, wherein the first insulating pillar is uniform from top to bottom.

16. A method for forming a memory array comprising strings of memory cells, comprising: This forms a stack consisting of alternating vertical first and second layers; Horizontally elongated trenches are formed into the stack to form laterally spaced memory block regions; A filling material is formed in the horizontally elongated groove; and Vertically extending holes are formed in the filling material, the vertically extending holes being longitudinally spaced along the laterally adjacent memory block regions. All the holes extend laterally across individual horizontally elongated grooves in the horizontally elongated grooves and form insulating pillars. The insulating pillars are laterally positioned between the laterally adjacent memory block regions and are longitudinally spaced along the laterally adjacent memory block regions, which are longitudinally positioned between the holes. In the completed circuit configuration, the insulating pillars directly abut against the conductive material of the conductive lines in the first layer. The insulating pillars extend through all alternating first and second layers and include a vertically positioned and centrally located insulating core extending through all alternating first and second layers.

17. The method of claim 16, wherein the sacrificial material in the first layer is etched isotropically through the hole and replaced with the conductive material of the individual conductive lines in the conductive lines.

18. The method of claim 16, further comprising forming individual memory cells of the memory cell string to include channel material of an operational channel material string in the memory block region, a gate region as a portion of a conductive line in an individual first layer of the first layer, and a memory structure laterally situated between the gate region and the channel material of the operational channel material string in the individual first layer, the conductive material of the first layer being formed after the via is formed.

19. The method of claim 16, further comprising forming individual memory cells of the memory cell string to include channel material of an operational channel material string in the memory block region, a gate region as a portion of a conductive line in an individual first layer, and a memory structure laterally situated between the gate region and the channel material of the operational channel material string in the individual first layer, wherein forming the horizontally elongated trench is through the conductive material of the first layer.

20. The method of claim 16, further comprising forming an operational channel material string through the second layer and the first layer in the memory block region prior to forming the horizontally elongated trench.

21. The method of claim 16, further comprising forming an operational channel material string through the insulating layer and the first layer in the memory block region after forming the horizontally elongated trench.

22. The method of claim 16, further comprising forming the hole as vertical or within 10° of vertical.

23. The method of claim 16, further comprising filling the holes with an insulating material.

24. The method of claim 16, further comprising forming the hole as extending laterally beyond the filler material.

25. The method of claim 24, further comprising forming the hole into a circular shape in a horizontal cross-section.

26. The method of claim 24, further comprising forming the hole into a quadrilateral shape in a horizontal cross-section.

27. The method of claim 16, further comprising forming the hole so that it does not extend laterally beyond the filler material.

28. The method of claim 27, further comprising forming the hole as having laterally opposed flat sides directly abutting the insulating material of the second layer.

29. The method of claim 27, further comprising forming the hole as having laterally opposed flat sides that directly abut against the material of the first layer.

30. A method for forming a memory array comprising strings of memory cells, comprising: This forms a stack consisting of alternating vertical first and second layers; Horizontally elongated trenches are formed into the stack to form laterally spaced memory block regions; A filling material is formed in the horizontally elongated groove; and Vertically extending holes are formed in the filler material, the vertically extending holes being longitudinally spaced along the laterally adjacent memory block regions, the holes extending laterally completely spanning individual horizontally elongated grooves, and the remaining filler material forming a pair of first insulating pillars, the pair of first insulating pillars being laterally positioned between the laterally adjacent memory block regions and being longitudinally spaced along the laterally adjacent memory block regions by one of the holes; The holes are filled with insulating material to form second insulating supports in individual holes within the holes; as well as In the completed circuit configuration, the first insulating pillar and the second insulating pillar directly abut against the conductive material of the conductive wire in the first layer. The first insulating pillar and the second insulating pillar have different compositions and directly abut against each other. The first insulating pillar is uniformly oriented horizontally throughout its horizontal cross-section.

31. The method of claim 30, wherein the first insulating post is uniform from top to bottom.

32. The method of claim 30, wherein the second insulating post is uniformly distributed horizontally throughout the horizontal cross-section.

33. The method of claim 32, wherein the first insulating post is uniform from top to bottom.

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