Distributed fet reverse bias network

Abstract

Electronic circuits and methods including RF switches comprising a plurality of serially coupled (stacked) integrated circuit (IC) SOI MOSFETs with a distributed reverse bias network structure having a set of substrate contacts coupled to a bias voltage source through a resistive ladder. The distributed reverse bias network structure sets a common IC substrate voltage at a fixed DC bias, but resistively decouples the set of MOSFETs with respect to RF voltage, such that the voltage dividing properties of the MOSFET stack are maintained. The distributed reverse bias network structure increases the voltage handling capability of each MOSFET and improves the maximum RF voltage at which a particular MOSFET functions as a switching device, while mitigating losses, leakage, cross-talk, and distortion. RF switches according to the invention are particularly useful as antenna switches.

Description

[0001] Cross Reference to Related Applications

[0002] This application claims priority to U.S. Patent Application No. 16 / 441,623, filed June 14, 2019, entitled “Distributed FET Back-Bias Network,” the contents of which are incorporated by reference in their entirety. BACKGROUND (1) TECHNICAL FIELD

[0004] The present invention relates to electronic circuits, and more particularly to systems and methods for back-biased field effect transistors for use in radio frequency electronic switching circuits. (2) BACKGROUND

[0006] Radio frequency (RF) communication systems such as cellular telephones and WiFi and Bluetooth connected devices have become the backbone of modern life. The demand for such communication systems forces more users into a crowded spectrum, increasing interference between all signals. In response, system designers and regulators have increased the number of frequency bands and user density within the bands. As a result, communication systems have become more complex and sophisticated to overcome problems such as increased inter signal interference.

[0007] In RF communication systems, many system-wide approaches have been used to increase the total bandwidth and data transfer rate, and in cellular systems these are commonly referred to as generations (e.g., 3G, 4G). Each generation has required increasing levels of complexity, bandwidth, and linearity, and this trend is expected to continue. For example, the next generation of cellular systems, 5G, is the most sophisticated and complex cellular system to date, and will introduce antenna arrays that can direct both transmitted and received signals toward the intended receiver and away from other interferers.

[0008] In order for modern cellular communication systems to function properly, multiple antennas must be able to operate relatively independently and be able to handle voltages much higher than the target power of the power amplifiers. Antennas are typically constrained to a small volume inside a cellular phone to save space, and can only be located in a limited number of places. This spatial constraint can result in cross-talk and interference coupling that can significantly reduce data rates.

[0009] These factors drive the need for antenna switches and tuning devices with higher levels of power handling and linearity. It is apparent that antennas need to handle the transmit power set by the particular standard. However, since antennas are constrained by space and cost, they often mismatch, which wastes power and, ironically, results in increased power reflections that they must handle. Since antenna switches are directly attached to the antennas, such switches must handle such high voltages while maintaining linearity.

[0010] In modern systems, antenna switches include multiple MOSFETs connected in series in a "stack" to withstand high voltage RF signals by dividing the voltage across the MOSFETs of the switch stack. For example, FIG. 1 is a schematic diagram of a prior art switch 100 including a stack of MOSFETs M1-Mn. The MOSFETs M1-Mn are coupled drain-to-source, and their respective gates are coupled to a control voltage Vctrl through respective gate resistors Rg. The MOSFETs M1-Mn making up the switch 100 are turned on or off as a group by Vctrl, and thus function as a single-pole, single-throw switch.

[0011] The MOSFET switch stack can be used in series with an RF signal line, for example, to selectively block or conduct RF signals between an antenna and a transceiver circuit. The MOSFET switch stack can also be used in a shunt configuration between an RF signal and a reference potential (e.g., RF circuit ground), for example, to selectively isolate a node of the RF signal line from significantly affecting other circuits.

[0012] Ideally, the MOSFETs should not significantly alter or affect the RF signal. However, integrated circuit MOSFETs, particularly in RF circuits, do not function as ideal switches having no resistance in the on (on) state and infinite impedance and no RF coupling in the off (off) state. For example, a MOSFET in the on state exhibits some resistance R ON to a conducted signal, while a MOSFET in the off state exhibits a very high (but not infinite) resistance R OFF to a conducted signal, as well as some capacitance C OFF Additionally, the integrated circuit area and associated interconnect circuitry forming the MOSFET exhibit significant parasitic capacitance, inductance, and resistance, particularly for RF signals, which can adversely affect power handling and linearity, while causing distortion, insertion loss, current leakage, etc.

[0013] For example, referring to FIG. 1, the applied RF signal is ensured to be divided between the gate and source / drain of each MOSFET by the drain-gate and source-gate capacitive coupling of the parasitic capacitance Cp within the MOSFETs M1-Mn. The gate resistors Rg block the RF signal from the control node Vctrl, enabling a DC voltage to turn on and off the MOSFETs. However, the parasitic capacitance Cp disrupts the voltage division along the stack, causing some MOSFETs to experience too much voltage. This reduces the power handling and linearity of the switch 100, which in turn can require a greater number of MOSFETs in the stack and a related increase in insertion loss of the switch 100.

[0014] Another issue with MOSFETs is that the drain-source voltage a single MOSFET can withstand without breakdown is typically limited to a few volts. While stacking MOSFETs separates the applied drain-source voltage, ensuring that the voltage across any single MOSFET is less than its drain-source breakdown voltage, the overall increase in Rs of the series-coupled MOSFETs adds to the overall resistance of the stacked switches. ON .

[0015] The circuit shown in Figure 1 does not fully capture the problems inherent in the interactions within a MOSFET. As mentioned above, the integrated circuit regions forming the MOSFET and the associated interconnect circuitry exhibit significant parasitic capacitance, inductance, and resistance, especially for RF signals. For example, Figure 2A is a cross-sectional view of a typical prior art silicon-on-insulator (SOI) MOSFET 200 of the type that can be used in antenna switches. The MOSFET shown includes a substrate 202 on which a buried oxide (BOX) layer 204 and an active layer 206 are sequentially formed in a known manner. The active layer 206 is typically a thin layer of suitably doped silicon (but may be other materials known in the art) on which and within which various active devices can be formed. In the example shown, the primary MOSFET device includes a gate 208 formed on an insulator 210 between the source and drain. The gate 208 defines a body 212 between the source and drain. As is known in the art, the substrate 202 can be formed from a variety of materials, including silicon, ceramics (e.g., silicon nitride, silicon carbide), crystalline or polycrystalline materials (e.g., diamond or sapphire), or other insulating or semi-insulating materials.

[0016] As is common practice known in the art (and as...) Figure 3A As shown below, the upper structure 214 can contain various elements, regions, and structures, which can be fabricated in a known manner on, above, or even through the active layer 206 to achieve specific functions. For example, the upper structure 214 may include conductive interconnects and / or external contacts from the illustrated MOSFET 100 to active and passive components (including other MOSFETs), passivation layers and regions, and protective coatings. The conductive interconnects may be, for example, copper or other suitable metals or conductive materials (e.g., polysilicon).

[0017] Generally for SOI, and particularly for RF circuits, the substrate 202 preferably has a high resistivity in the range of about 3,000 to about 20,000 or higher ohm-cm. High resistivity substrates, when used in RF SOI IC structures, are able to reduce substrate losses. However, such substrates are highly susceptible to another phenomenon known as parasitic surface conduction. The problem of parasitic surface conduction arises because, although the substrate 202 with high resistivity is able to terminate the field lines, the thin surface region of the substrate 202 can form an inversion or accumulation region due to the influence of the signal voltage in the active layer 206 on the charge carriers. The signal in the active layer 206 directly changes the degree to which the charge carriers in the thin surface region are displaced. As a result, the capacitance between the high resistivity substrate 202 and the active layer 206, as seen by the active layer 206, is dependent on the applied voltage, resulting in non-linearity and loss of signal purity. In addition, the applied voltage can invert the interface on the high resistivity substrate 202 side and create a channel-like layer within the thin surface region, where, despite the fact that the substrate layer 202 is high resistivity, the charges can easily move in the lateral direction (e.g., to an adjacent MOSFET). Thus, this effect also causes signal degradation cross-talk in the RF communication circuit.

[0018] Parasitic surface conduction can be greatly mitigated by forming a trap-rich layer 216 on top of the substrate 202. The trap-rich layer 216 is typically formed as an amorphous or polysilicon layer on the top surface of the substrate 202 and significantly reduces the carrier lifetime and mobility of the charge carriers in the thin top surface region of the substrate 202. The trap-rich layer 216 also pins the Fermi level of the surface silicon, thereby suppressing inversion at the BOX / substrate interface. Since the carriers cannot travel too far, the effective high resistance of the substrate 202 is preserved, and the capacitance as seen by the active layer 206 is no longer dependent on the signal in the active layer 206. The improved RF performance of SOI IC substrates with the trap-rich layer 216 is so significant that wafers with this configuration are commercially available and widely used.

[0019] Another problem with SOI MOSFETs is the presence of a parasitic back channel FET with respect to the body 212 of the primary MOSFET device. The structure of the parasitic back channel FET is formed by the source, the substrate 202, the BOX layer 204, and the drain. The substrate 202 acts as the gate of the parasitic back channel FET (i.e., the substrate 202 underneath the MOSFET device as a whole acts as a secondary gate of the device). FIG. 2B is an equivalent schematic diagram of the FET structure shown in FIG. 2A, showing the parasitic back channel FET 220 coupled in parallel to the primary MOSFET 222. The parasitic back channel FET 220 adversely affects the leakage current Id OFF and threshold voltage V THThis also adversely affects the so-called harmonic kick-off point (HKP) of the MOSFET. The HKP of a MOSFET is the RF power that significantly increases the distortion or nonlinearity of the applied RF signal. HKP effectively represents the maximum power (or more precisely, the maximum RF voltage) at which a particular MOSFET functions as a switching device.

[0020] Another undesirable side effect of the parasitic back-channel FET 220 is that it may be strongly affected by an electric field generated by back-channel charges present at or near the interface between the substrate 202 and the BOX layer 204, as well as by trapped charges within the BOX layer 204. Such charges can originate from many sources, but are primarily due to charging effects related to the substrate construction, the fabrication process associated with the FET device itself, or exposure of the FET device to high-energy radiation (e.g., high-energy plasma, X-rays, gamma rays, and / or cosmic radiation).

[0021] The adverse characteristics of parasitic back-channel FETs can be mitigated by altering the behavior of the MOSFET by connecting its substrate 200 to a fixed voltage (such as circuit ground or a bias voltage). For example, applying a negative substrate voltage (“reverse bias” voltage) will increase the threshold voltage and HKP of the N-type MOSFET.

[0022] In another example of the interrelationships in MOSFET structures, while the rich trap layer 216 alleviates one type of problem, it introduces another. Referring again to Figures 1 and 2A, the BOX layer 204 dielectrically isolates all FETs M1 to Mn, thereby achieving the voltage division of the stack shown in Figure 1. However, while the rich trap layer 216 enables the substrate 202 to function as a standard semiconductor at DC and low frequencies, it also enables the substrate 202 to function as a dielectric material at RF frequencies. Therefore, at RF frequencies, each FET M1 to Mn is capacitively coupled to a nearby ground node via the BOX 204 and the substrate 202, representing the parasitic capacitance of the voltage division upon which the switching 100 handles high RF voltages. As described above, the rich trap layer 216 prevents the formation of a charge layer at the BOX-substrate interface that would alter coupling and cause nonlinearity.

[0023] As should be apparent from the above, the inherent non-ideal characteristics of MOSFETs in integrated circuits pose challenges to the design of transistor devices and circuits using such devices in order to minimize losses, leakage, crosstalk, and distortion while improving linearity and voltage handling capability. One object of the present invention is to provide a MOSFET-based RF switch that has increased voltage handling capability and improved HKP for each MOSFET, while mitigating losses, leakage, crosstalk, and distortion. The RF switch according to the invention is particularly useful as an antenna switch. Summary of the Invention

[0024] This invention includes an RF switch comprising a plurality of series-coupled (stacked) SOI MOSFETs with a distributed reverse bias network structure, the distributed reverse bias network structure including a group of substrate contacts coupled to a bias voltage via resistive steps. The distributed reverse bias network structure sets a common IC substrate voltage at a fixed DC bias, but resistively disconnects the group of MOSFETs relative to the RF voltage, thereby maintaining the voltage divider characteristics of the MOSFET stack. The distributed reverse bias network structure increases the voltage handling capability of each MOSFET and improves the HKP of each MOSFET, while mitigating losses, leakage, crosstalk, and distortion. The RF switch according to the invention is particularly useful as an antenna switch.

[0025] The added HKP of the MOSFET biased by the distributed reverse bias network structure according to the present invention can be used by designers in a variety of ways. For example, the added HKP characteristic will improve the linearity and power handling capability of the existing MOSFET stack size compared to a MOSFET stack lacking such a network. Alternatively, the added HKP characteristic can be used to reduce the height of the MOSFET stack while maintaining the same linearity and power handling capability as a MOSFET stack lacking such a network.

[0026] Details of one or more embodiments of the invention are set forth in the accompanying drawings and the following description. Other features, objects, and advantages of the invention will become apparent from the specification, the drawings, and the claims. Attached Figure Description

[0027] Figure 1 is a schematic diagram of a prior art switch including a stack of MOSFETs M1 to Mn.

[0028] Figure 2A is a cross-sectional view of a typical prior art silicon-on-insulator (SOI) MOSFET of the type that can be used in antenna switches.

[0029] Figure 2B is an equivalent schematic diagram of the FET structure shown in Figure 2A, illustrating the parasitic back-channel FET coupled in parallel to the primary MOSFET.

[0030] Figure 3A This is a cross-sectional view of a silicon-on-insulator (SOI) MOSFET switch including an S-contact as part of a distributed reverse bias network structure.

[0031] Figure 3B This is a top view of an SOI MOSFET switch that includes an S-contact as part of a distributed reverse bias network structure.

[0032] Figure 4This is a top view of an SOI MOSFET switch that includes multiple stacks of MOSFETs and multiple bias networks.

[0033] Figure 5 This is a plan view of an IC die with a die seal (not to scale).

[0034] Figure 6 This is a process flow diagram illustrating one method for manufacturing integrated circuits with increased power handling capabilities.

[0035] Figure 7 This is a process flow diagram illustrating one method for manufacturing a radio frequency switch.

[0036] The same reference numerals and names in each figure indicate the same elements. Detailed Implementation

[0037] This invention includes an RF switch comprising a plurality of series-coupled (stacked) integrated circuit (IC) SOI MOSFETs having a distributed reverse bias network structure. This distributed reverse bias network structure includes a group of substrate contacts (also referred to as "through-BOX contacts" or TBCs) coupled to a bias voltage via resistive steps. The distributed reverse bias network structure sets a common IC substrate voltage at a fixed DC bias, but resistively disconnects the group of MOSFETs relative to the RF voltage, thereby maintaining the voltage divider characteristics of the MOSFET stack. The distributed reverse bias network structure increases the voltage handling capability of each MOSFET and improves the maximum RF voltage at which a particular MOSFET functions as a switching device, while mitigating losses, leakage, crosstalk, and distortion. The RF switch according to the invention is particularly useful as an antenna switch.

[0038] Increase voltage handling capability and HKP

[0039] MOSFET-based switches—particularly antenna switches—are designed to operate using all the MOSFETs in a stack that operate below their respective HKP (Hypervoltage Limiting). By biasing the secondary gate of the back-channel FET of the MOSFET with an appropriate reverse bias voltage, the HKP of each MOSFET in the stack can be increased, thus increasing the voltage handling capability of the switch. (The threshold voltage will also increase slightly, which will increase the RV of the MOSFET.) ON And it slightly increases the insertion loss of the RF switch, which is a valuable trade-off for achieving higher voltage handling capability in many applications. A negative DC reverse bias voltage will increase the threshold voltage and voltage (RF power) handling capability of the N-type MOSFET. A positive DC reverse bias voltage will increase the threshold voltage and voltage (RF power) handling capability of the P-type MOSFET.

[0040] However, as described in more detail below, applying a reverse bias voltage to the IC substrate at a single point, such as the TBC, or even through several points, adversely affects the RF voltage divider characteristics of the MOSFET stack and the startup time of the switching circuit.

[0041] To overcome these problems, embodiments of the present invention apply a DC reverse bias voltage to multiple substrate regions of an integrated circuit near the stack of MOSFETs via substrate contacts (S-contacts, also known as TBCs, which are used interchangeably in this disclosure). An S-contact is a conductive structure formed from the top structure of the MOSFET through the active layer and the BOX layer to (or near) the IC substrate. Previous uses of S-contacts include mitigating accumulated charge effects that adversely affect FETs, shielding, and / or for thermal conduction. Examples of the applicant’s application of S-contacts are set forth in U.S. Patent No. 9,837,412, entitled “S-Contact for SOI”, published December 5, 2017; U.S. Patent No. 9,960,098, entitled “Systems and Methods for Thermal Conduction Using S-Contacts”, published May 1, 2018; and U.S. Patent Application No. 15 / 600,588, entitled “Managed Substrate Effects for Stabilized SOI FETs”, filed May 19, 2017, the entire contents of which are incorporated herein by reference.

[0042] However, embodiments of the present invention apply S-contacts in a novel configuration and circuit including a resistive ladder. The resulting combination of S-contacts and resistive ladders sets the common IC substrate voltage to a fixed DC bias voltage, but resistively disconnects the MOSFET stack relative to the RF voltage, thereby preserving the voltage divider characteristics of the MOSFET stack.

[0043] Bias network configuration

[0044] Figure 3A This is a cross-sectional view of a silicon-on-insulator (SOI) MOSFET switch 300, including S-contacts as part of a distributed reverse bias network structure. The background shows (along...) Figure 3BLine AA (as described below) consists of three MOSFETs 302a to 302c, which are similar in type to those shown in Figure 2A and are configured to be connected in series via upper structure 214 (e.g., source S of MOSFET 302a to drain D of MOSFET 302b, and source S of MOSFET 302b to drain D of MOSFET 302c) (connections not shown to avoid clutter). In the example shown, RF IN The signal will be applied to the drain D of MOSFET 302a, and the source S of MOSFET 302c will be connected as an RF converter. OUT Simultaneous operation of all MOSFETs 302a to 302c will block RF transmission. IN To RF OUT The current (off state) or the current (on state) from RF IN Conducted to RF OUT Therefore, it can be used as an RF switch.

[0045] exist Figure 3A In the foreground (along) Figure 3B The line BB (described below) is an S-contact 304, which comprises a conductive material formed in a known manner from the upper structure 214 through the active layer 206 and the BOX layer 204 and through or into the trap-rich layer 216 (if present) to (or near) the substrate 202. Each S-contact 304 penetrates a corresponding isolation region 306 within the active layer 206. The material used for the S-contact 304 can be any relatively low resistivity conductive material, such as polysilicon and various metals (e.g., tungsten, copper, etc.). Particularly in the case of SOI devices, the isolation region 306 can be a shallow trench isolation (STI) region made in a known manner. Because it penetrates the isolation region 306 within the active layer 206, the S-contact 304 remains isolated from direct contact with other active regions or elements on or within the active layer 206. Note that other S-contacts (not shown) may be included, and these other S-contacts are configured to perform independent functions, such as mitigating accumulated charge effects that are detrimental to the FET, shielding, and / or for thermal conduction.

[0046] Figure 3A The resistor 310 forming a resistance step is schematically shown in the diagram, which extends from the RF of the switch 300. IN Lateral to RF OUTA group of one or more S-contacts 304 is connected in series. In some applications, the group may include two or more S-contacts 304 connected by a low-resistance conductor (e.g., metal) and a higher-resistance resistor 310 connecting the group. The resistor 310 may be formed of polysilicon, for example, in one or more layers of the upper structure 214 or in the active layer 206, and each resistor may have the same or different resistance values. As discussed in more detail below, the resistor 310 should have a sufficiently high resistance value to provide the desired level of RF isolation between the groups of S-contacts 304.

[0047] The conductive group of S-contact 304 and resistor 310 together form a distributed reverse bias network structure 320 (referred to as the "bias network"). A bias voltage Vbias can be applied at one or both ends of the bias network 320. The bias voltage Vbias is typically a fixed DC voltage (e.g., -3V) that will bias the substrate 202 at a fixed DC voltage level, at least near the MOSFETs 302a to 302c. However, in some applications, Vbias can be a variable or pulsed voltage. For example, Vbias can be negative when the MOSFETs 302a to 302c are off (thus increasing HKP), but positive when the MOSFETs 302a to 302c are on to reduce the on-resistance R. ON In some applications, since the SOI substrate 202 is highly resistive and therefore can have local potentials, selected areas of the substrate 202 can be biased with different DC voltages by using independent bias networks (e.g., in RF or analog circuits).

[0048] Figure 3B This is a top view of a portion 350 of an SOI MOSFET switch, which includes an S-contact as part of a distributed reverse bias network structure. In this figure, line AA corresponds to the cross-sectional view of the background MOSFETs 302a to 302c in Figure 3, and line BB corresponds to... Figure 3A A cross-sectional view of the foreground S-contact 304. Three MOSFETs 302a to 302c are connected in series in the RF... IN With RF OUT (For clarity, the connection between the source S and drain D of adjacent MOSFETs is omitted, but the connection could be, for example, a metal conductor within the upper structure 214). In the example shown, the gates G of MOSFETs 302a to 302c are coupled to the control voltage Vctrl via gate resistors Rg.

[0049] exist Figure 3BIn the example, the bias network 320 of the S-contact 304 and resistor 310 is offset to the side of MOSFETs 302a to 302c and is aligned and aligned in the direction in which the RF signal flows through MOSFETs 302a to 302c. The S-contact 304 has an end sufficiently close (including actual contact) to the substrate 202 beneath MOSFETs 302a to 302c to apply an applied bias voltage sufficient to increase the power handling capability of at least one of the MOSFETs 302a to 302c over a region of substrate 202. A second end of the S-contact 304 provides access to connections in the upper structure 204 of the integrated circuit; more specifically, pairs of one or more S-contacts 304 are connected via corresponding resistors 310. Although Figure 3A and Figure 3B A relatively small number of S-contacts 304 are shown for each MOSFET 302x, but it should be understood that the ratio of S-contacts 304 to MOSFET 302x is a design choice.

[0050] Figure 4 This is a top view of an SOI MOSFET switch 400 comprising multiple stacks of MOSFETs 302 and multiple bias networks 320. The example shown illustrates three rows of five MOSFETs 302 connected in series, where the bias networks 320 divide or separate the rows of MOSFETs 302; also, for clarity, the connection between the source S and drain D of adjacent MOSFETs 302 is omitted. In some applications, the number of MOSFETs 302 connected in series can exceed 30 devices, and the number of rows of MOSFETs 302 can be more than three or less. In some applications, some or all rows can be connected in parallel to function as a single switch with high current capacity. In some applications, some rows (or groups of rows) can be connected independently to provide multiple switching ports.

[0051] In the example shown, at switch 400 RF OUT The side—which is at a low common voltage—includes one or more optional auxiliary S-contacts 402 as Vbias electrical conduits to the substrate 202. Although the auxiliary S-contacts 402 are shown as multiple S-contacts, a single large busbar structure can also be used. Since the auxiliary S-contacts 402 do not experience any significant RF voltage gradient, they do not need to be resistively coupled to Vbias.

[0052] The effective total resistance of all parallel S-contacts 304, 402 to substrate 302 can be designed to range from high to very low, for example from several thousand ohms to sub-ohm levels; a typical value in a process is typically at least 100 ohms. This is generally a desirable characteristic because the resistance of individual S-contacts 304, 402 can vary, for example, due to minute differences in the cross-sectional area of ​​the etched holes forming the S-contacts 304. In contrast, the resistance of resistor 310 can be set quite precisely during the IC manufacturing process. Therefore, if a large number of S-contacts 304 are connected in parallel (through conductors or resistors), the resistance of bias network 320 can be determined primarily by the value of inter-group resistor 310. In some implementations for specific RF applications, the inter-group resistor 310 of the resistance ladder can have approximately 3 to approximately 10 times the combined resistance of the S-contacts 304, 402. In one example implementation, for a switch designed for RF signals in the range of about 0.5 GHz to about 6 GHz, the inter-group resistor 310 has a value in the range of about 10 K ohms to 40 K ohms.

[0053] Operational aspects of bias networks

[0054] As should be understood from the above description, applying an appropriate bias voltage Vbias to the bias network 320 can apply a charge to the substrate 202 near the MOSFET 302, a charge sufficient to increase the HKP of each MOSFET 302 in the nearby stack, and thus increase the voltage handling capability of the switch 400. As mentioned above, a negative Vbias will be used for the N-type MOSFET (e.g., about -3V), while a positive Vbias will be used for the P-type MOSFET (e.g., about +3V).

[0055] A key aspect of the bias network 320 is that resistors 310, placed between groups of one or more S-contacts 304, provide basic RF isolation between the groups. RF isolation is required because the different MOSFETs 302 in the stack of MOSFETs 302 are exposed to RF interference. IN To RF OUT The substrate 202 beneath the different MOSFETs 302 in the stack will experience different levels of RF voltage. Therefore, the substrate 202 beneath the different MOSFETs 302 in the stack will see different levels of RF voltage. If from RF... IN To RF OUTSince all S-contacts 304 are coupled to Vbias via low-resistance conductors, the capacitively coupled RF voltage will reduce the voltage divider characteristics of the MOSFET 302 when all back-channel gates of the MOSFET 302 are biased with the same DC voltage. Therefore, the significant benefit of the bias networks 320 described above is that they provide a constant DC voltage across all stacked MOSFETs 302—thus increasing their respective HKP—while reducing RF coupling between the MOSFETs 302.

[0056] By utilizing numerous S-contacts 304, the substrate 202 will be rapidly charged to a static DC voltage upon device startup. Once charged, there is no significant current flow, so the Vbias voltage can be provided using an existing power supply. For example, a negative voltage is used in N-MOSFET-based RF switches to ensure that the MOSFET remains off when a high-power RF signal is applied. These negative power supplies are typically generated on-chip using a low-current charge pump. As long as any charging current remains within the design limits of the charge pump circuitry, the negative bias voltage Vbias can be tapped from this existing negative voltage.

[0057] The resistance value of resistor 310 (which need not all be the same) also sets the response time of the substrate bias circuit, which can be set to the maximum value of resistor 310. More specifically, bias network 320 is indispensable for the RC time constant, which is essentially set by multiplying the capacitance between the FET in active layer 206 and the substrate 202 (including the trap-rich layer 216) directly below the FET by the value of resistor 310. In most applications, the value of resistor 310 in bias network 320 is preferably adjusted to produce an optimal time constant. The optimal time constant should balance RF coupling (a longer time constant is better) with the startup time for charging bias network 320 (a shorter time constant is better). If the startup time is too long, the RF system may apply a high-power RF voltage before the substrate potential reaches its target value, and therefore before the MOSFET HKP increase has been achieved (due to the reverse bias provided by bias network 320). Therefore, the optimal time constant can be a time constant that prevents excessive RF coupling but allows the initial startup time to meet system requirements.

[0058] Another reason for appropriately adjusting the size of resistor 310 is to handle the RF coupling between the long MOSFET stack and the long traces of the bias network 320 structure. The bias network 320 is typically connected to the bias voltage Vbias via a conductive material (e.g., a metal trace), which in turn couples the RF power emitted from the MOSFET stack. This RF power coupled into the bias network 320 structure then loads the RF signal and affects the voltage division along the MOSFET stack. Such coupling with the low-impedance array of the bias network 320 can be significant enough to offset the increased HKP due to the bias network 320. Therefore, resistor 310 should have sufficient resistance to substantially block such RF power coupling.

[0059] Another advantage of the bias network 320 structure is that the bias of the substrate 202 can be achieved entirely through the contacts on the upper structure 214 side of the switching IC. Therefore, it is not necessary to access the back side of the substrate 202.

[0060] In summary, the problems to be solved by the embodiments of the present invention and the aspects of the embodiments themselves include the following:

[0061] • It is advantageous to allow the potential of the substrate 202 directly below the MOSFET 302 to follow the potential of the MOSFET portion directly above it. For example, on top of a stack of MOSFETs designed to withstand a 100V RF signal when turned off, the corresponding substrate 202 region should be allowed to follow ±100V.

[0062] For SOI ICs, substrate 202 has a very high resistivity. Applying or changing the bias voltage to the secondary back gate of the MOSFET involves charging a low-frequency capacitance between substrate 202 and the MOSFET. The MOSFET stack can be quite large (e.g., 400 μm × 500 μm), so the capacitance can be significant. To keep the RC time constant consistent with switching and startup specifications, the substrate contacts should be numerous and close to the MOSFET stack.

[0063] The substrate 202 that is close to or in contact with the S-contact 304 of the bias network 320 will be at or near the potential of the S-contact 304.

[0064] • In the absence of S-contact 304, the substrate 202 near the location of S-contact 304 will experience considerable RF oscillation. S-contacts 304 shorted together and maintained at DC voltage will suppress this oscillation, but a strong potential gradient is generated near and when in contact with S-contact 304. As a result, when a positive potential gradient is applied, S-contact 304 injects charge carriers (electrons) into the substrate.

[0065] Regardless of charge injection, the nearby S-contacts 304, the substrate 202 in contact with all S-contacts 304, and the low-resistance conductor (e.g., metal) connected to the top of the S-contacts 304 form a capacitor together with the MOSFET stack. This increases the parasitic capacitance of the MOSFET stack, which affects the voltage division and input capacitance.

[0066] To mitigate the effects of charge injection and increased parasitic capacitance of the S-contacts, embodiments of the present invention connect a group of one or more S-contacts 304 to a resistance ladder comprising one or more high-value resistors 310 connected in series, such as... Figure 3B As illustrated in the example, with high-value resistors 310 between the groups of S-contacts 304, each group of S-contacts 304 is sufficiently isolated to "follow" the RF swing of the underlying substrate 202 rather than suppress it, which essentially eliminates the possibility of charge injection. Furthermore, the parasitic impedance exerted on the MOSFET stack by the S-contacts 304 is the impedance of the parasitic capacitance from the MOSFET stack to the S-contacts 304, connected in series with the impedance of the resistors 310 in the connection resistor ladder. By appropriately adjusting the dimensions of the resistors 310, the reduction in RF coupling can be balanced with the specifications for startup time and switching.

[0067] The bias network 320, constructed as described above, provides a suitable reverse bias to the switching stack of MOSFETs 302, sufficient to provide a significant increase in the MOSFET stack's HKP, and thus an increase in switching power handling capability. A related benefit is that (due to the increased threshold voltage V...) TH )R ON The linearity of the switch increases even with very small degradation in insertion loss. Furthermore, in analog circuit design, the degradation due to V... TH Any effect of offset on non-RF analog circuits.

[0068] The increased HKP of the MOSFETs biased by one or more bias networks 320 according to the present invention can be used by designers in a variety of ways. For example, the increased HKP characteristic will improve the linearity and power handling capability of the existing MOSFET stack size compared to a MOSFET stack lacking bias networks 320. Alternatively, the increased HKP characteristic can be used to reduce the height of the MOSFET stack (i.e., the number of MOSFETs connected in series) while maintaining the same linearity and power handling capability as a MOSFET stack lacking bias networks 320. Any trade-offs made to reduce the stack height can also reduce insertion loss, compensating for the slightly higher Vo of the MOSFETs biased by bias networks 320. TH .

[0069] bare die seal assembly

[0070] In the manufacture of integrated circuit (IC) dies, it is advantageous in many cases to use die seals around the edges of individual dies (also known as "chips"). Die seals provide protection for the IC die substrate (and associated circuitry) from damage, and particularly protect the IC die substrate and internal circuitry from the structural stresses that occur when dicing a semiconductor wafer into an IC die. Die seals are typically formed by depositing metal lines in all metal layers surrounding the die's periphery to prevent the propagation of die cracks and contaminants. As an example, Figure 5 This is a plan view (not to scale) of an IC die 500 with a die seal 502. Typically, most or all of the microelectronic circuitry is located inside the die seal 502. In some cases, S-contacts 304 with different metal layers of the die seal 502 are provided for electrical and mechanical connections (e.g., as shown above). Figure 3A (Described S-contact).

[0071] Further discussion of die seals, particularly broken or “broken” die seals, can be found in U.S. Patent Application No. 16 / 252,396, filed January 18, 2019, entitled “Method and Apparatus for Reducing Noise on Integrated Circuit using Broken Die Seal,” which is incorporated herein by reference.

[0072] A die seal is typically a complete loop around the die, allowing induced current to circulate around the conductive die seal. This can lead to induced noise in circuits fabricated on the die, especially when the die seal is grounded, thus creating a path for these currents to couple into IC circuitry. As discussed in U.S. Patent Application 16 / 252,396, it is known to use one or more straight slots or gaps 504 to interrupt or “break” the die seal 502 for electrical isolation, in order to mitigate or eliminate induced currents through the die seal 502. To ensure that cracks that may form during a cutting operation do not propagate through the straight gap 504, at least a portion of a parallel conductor strip (not shown) is positioned adjacent to (meaning close but spaced apart from) and overlapping the straight gap 504, such that a segment of the die seal always blocks any direct path from the die edge. However, providing such parallel conductor strips within the die seal 502 reduces the area available for fabricating circuits on the die, and providing such parallel conductor strips outside the die seal 502 requires a larger die to accommodate the additional conductor strips. Therefore, both parallel conductor strip solutions increase the manufacturing cost of the IC.

[0073] As taught in U.S. Patent Application No. 16 / 252,396, a die seal comprising a conductor strip formed on each conductor layer can be interrupted or broken in at least one place, such that no current can flow around the entire periphery of the die. In some embodiments, an angled gap 506 is provided in the original die seal, such as Figure 5 As shown. In such an embodiment, the plurality of metal layers forming such angled gaps can be vertically aligned. In other embodiments, one or more straight (rather than angled) but vertically staggered gaps 508 can be provided. In the vertically staggered straight gaps 508, the plurality of metal layers forming such gaps are offset relative to the other conductive layers, such that each gap in each conductive layer has at least one conductor on its top and / or bottom to ensure that the die seal will perform its desired protective function.

[0074] This invention allows for an alternative method for ensuring the presence of a segment of the die seal that blocks any direct path from the die edge. When manufacturing an IC including the bias network 320 as described above, in some applications and / or manufacturing processes, it may be desirable or necessary to utilize the straight gap 504 of the die seal 502 through the IC without vertical staggered gaps. As described above, the bias network 320 includes a conductive group of S-contacts 304 and a resistor 310. Figure 3A As shown in the example, the S-contact 304 comprises a conductive material formed from the upper structure 214 through the active layer 206 and the BOX layer 204 and through or into the trap-rich layer 216 (if present) to (or near) the substrate 202. Therefore, the S-contact 304 exhibits substantially the same physical properties as the segment of the die seal 502 while being electrically isolated from the die seal 502. Thus, as... Figure 5 As shown, if the bias network 320 is located inside the die seal 502, such that the segments of the S-contacts 304 overlap with the corresponding straight gaps 504, the active die seal is preserved relative to any direct path from the die edge without requiring a large IC die 500 or unnecessarily consuming additional IC area within the periphery of the die seal 502. The spacing and size of the segments of the S-contacts 304 can be adjusted so that they serve the dual purpose of a die seal and a distributed reverse bias network structure 320 (note that the FET associated with the bias network 320 is from...). Figure 5 (omitted to avoid clutter).

[0075] like Figure 5As shown, combining aspects of the present invention with the teachings of U.S. Patent Application No. 16 / 252,396 allows for the use of angled gaps 506 and non-interlaced straight gaps 504 (i.e., without vertical interlacing) through the die seal 502 of the IC die 500. Additionally, other teachings of U.S. Patent Application No. 16 / 252,396 can be applied, such as those including vertically interlaced straight gaps (…). Figure 5 (Not shown in the image). Furthermore, although... Figure 5 The bias network 320 is shown with S-contacts 304 adjacent to and overlapping with non-interlaced straight gaps 504, but such S-contacts 304 may also be adjacent to and overlapping with angled gaps 506 and / or perpendicularly interlaced straight gaps 508.

[0076] method

[0077] Another aspect of the invention includes a method for manufacturing an integrated circuit (including an improved RF switch) with increased power handling capability. For example, Figure 6 This is a process flow diagram 600 illustrating a method for manufacturing an integrated circuit with increased power handling capability. The method includes: fabricating a plurality of series-coupled MOSFETs on a silicon-on-insulator substrate (box 602); fabricating a plurality of substrate contacts, each substrate contact having a first terminal sufficiently close to the substrate to apply a reverse bias voltage sufficient to increase the power handling capability of at least one of the MOSFETs over a region of the substrate, and having a second terminal that allows access to connections in the upper structure of the integrated circuit (box 604); and fabricating resistors between the second terminals of the plurality of substrate contacts in pairs, each resistor being configured to provide basic radio frequency isolation between the pairs (box 606).

[0078] As another example, Figure 7 This is a process flow diagram 700 illustrating a method for manufacturing an RF switch. The method includes: fabricating a plurality of series-coupled MOSFETs on a silicon-on-insulator substrate, the plurality of series-coupled MOSFETs being configured to be coupled to an RF input signal (box 702); and fabricating a reverse bias network comprising (a) a plurality of groups, each group including one or more substrate contacts, each substrate contact having a first terminal sufficiently close to the substrate to apply a reverse bias voltage over a region of the substrate sufficient to increase the power handling capability of at least one of the MOSFETs, and a second terminal for accessing connections in an overstructure of an integrated circuit; and (b) and at least one resistor, each resistor coupled to the second terminal of a pair of substrate contacts in the group and configured to provide basic RF isolation between the groups (box 704).

[0079] The above-described method and circuit may further include one or more of the following: wherein the MOSFET is an N-type MOSFET and the applied bias voltage is a negative bias voltage; wherein the MOSFET is a P-type MOSFET and the applied bias voltage is a positive bias voltage; wherein each resistor provides at least 10K ohms of resistance between paired groups; further comprising configuring a plurality of substrate contacts into at least a first group and a second group of one or more substrate contacts, and configuring at least a first group and a second group of one or more substrate contacts to selectively apply at least two different reverse bias voltages to corresponding different regions of the substrate; further comprising... A group of one or more substrate contacts is configured to selectively apply at least two different reverse bias voltages to corresponding different regions of the substrate; a plurality of series-coupled MOSFETs are linearly arranged on the substrate, and a group of one or more substrate contacts and resistors are offset toward the MOSFETs, and a group of one or more substrate contacts and resistors are arranged and aligned in the direction in which the radio frequency signal flows through the MOSFETs; and a plurality of series-coupled MOSFETs are linearly arranged on the substrate, and a reverse bias network is offset toward the linearly arranged MOSFETs, and a reverse bias network is arranged and aligned in the direction in which the radio frequency signal flows through the MOSFETs.

[0080] Manufacturing technology and options

[0081] As used in this disclosure, the term "MOSFET" includes any field-effect transistor (FET) having an insulated gate with conductivity of its voltage-determining transistor and includes an insulated gate having a metal or metalloid, insulator, and / or semiconductor structure. The terms "metal" or "metalloid" include at least one conductive material (e.g., aluminum, copper, or other metals, or highly doped polycrystalline silicon, graphene, or other conductors), "insulator" includes at least one insulating material (e.g., silicon oxide or other dielectric material), and "semiconductor" includes at least one semiconductor material.

[0082] Regarding the accompanying drawings referenced in this disclosure, it should be noted that the dimensions of the various elements are not drawn to scale; for clarity or emphasis, some dimensions have been significantly enlarged vertically and / or horizontally. Furthermore, references to orientation and direction (e.g., “top,” “bottom,” “above,” “below,” “lateral,” “vertical,” “horizontal,” etc.) are relative to the example drawings and are not necessarily absolute orientations or directions.

[0083] As used in this disclosure, the term "radio frequency" (RF) refers to an oscillation rate in the range of about 3 kHz to about 300 GHz. The term also includes frequencies used in wireless communication systems. RF frequencies can be the frequencies of electromagnetic waves or the frequencies of alternating voltage or current in a circuit.

[0084] Various embodiments of the invention can be implemented to meet various specifications. Unless otherwise stated above, the selection of suitable component values ​​is a matter of design choice. Various embodiments of the invention can be implemented using any suitable integrated circuit (IC) technology (including, but not limited to, MOSFET structures) or in hybrid or discrete circuit form. Integrated circuit embodiments can be fabricated using any suitable substrate and process, including, but not limited to, silicon-on-insulator (SOI) or other combinations of silicon-on-semiconductor. However, embodiments of the invention are particularly useful when fabricated using SOI-based processes or processes with similar characteristics. Fabrication in CMOS using SOI or SOS processes enables circuits to have low power consumption, the ability to withstand high power signals during operation due to FET stacking, good linearity, and high-frequency operation (i.e., radio frequencies up to and exceeding 50 GHz). Monolithic IC implementations are particularly useful because parasitic capacitance can generally be kept low (or minimized, consistent across all cells, thus allowing for compensation of parasitic capacitance) through careful design.

[0085] Depending on specific specifications and / or implementation technologies (e.g., NMOS, PMOS, or CMOS, and enhancement-mode or depletion-mode transistor devices), voltage levels and / or the polarity of voltage and / or logic signals can be adjusted. The voltage, current, and power handling capabilities of components can be adjusted as needed, for example, by adjusting device size, "stacking" components (especially FETs) in series to handle higher voltages, and / or using multiple components in parallel to handle higher currents. Additional circuit components can be added to enhance the capabilities of the disclosed circuit and / or provide additional functionality without significantly altering the function of the disclosed circuit.

[0086] Summarize

[0087] Many embodiments of the invention have been described. It should be understood that various modifications can be made without departing from the spirit and scope of the invention. For example, some of the steps described above may be order-independent and therefore may be performed in a different order than described. Furthermore, some of the steps described above may be optional. The various actions described with respect to the methods identified above may be performed repeatedly, sequentially, or in parallel.

[0088] It should be understood that the foregoing description is intended to illustrate, not limit, the scope of the invention, which is defined by the scope of the appended claims, and other embodiments are within the scope of the claims. In particular, the scope of the invention includes any and all possible combinations of one or more of the processes, machines, manufactures, or compositions of matter set forth in the appended claims. (Note that the bracketed designations of claim elements are for easy reference to such elements and do not in themselves indicate a particular order of requirements or an enumeration of elements; furthermore, such designations may be repeated in dependent claims to refer to additional elements without being considered as a sequence of designations that begins to conflict with each other.)

Claims

1. A reverse bias network configured to be coupled to a stack of series-coupled MOSFETs, the stack of series-coupled MOSFETs being fabricated as an integrated circuit on a silicon-on-insulator substrate, the reverse bias network comprising: (a) A plurality of groups of more than one substrate contact, positioned to apply a reverse bias voltage to a plurality of regions of a respective MOSFET in a stack of series-coupled MOSFETs on the substrate, each substrate contact including a conductive structure formed through an active layer and a buried oxide layer of the integrated circuit to or near the substrate. as well as (b) A resistance ladder comprising a plurality of resistors, each resistor being coupled between corresponding groups of more than one substrate contact, the resistance ladder being configured to be coupled to a bias voltage source.

2. The reverse bias network according to claim 1, wherein, The MOSFET is an N-type MOSFET, and the reverse bias voltage is a negative bias voltage.

3. The reverse bias network according to claim 1, wherein, The MOSFET is a P-type MOSFET, and the reverse bias voltage is a forward bias voltage.

4. The reverse bias network according to claim 1, wherein, The resistance ladder provides a resistance of at least 10K ohms between the groups of more than one substrate contact.

5. The reverse bias network according to claim 1, wherein, The reverse bias network is configured to selectively apply a first reverse bias voltage to a first region of the substrate, and further includes a second reverse bias network configured to selectively apply a second reverse bias voltage to a second region of the substrate.

6. The reverse bias network according to claim 1, wherein, The integrated circuit includes a die seal having at least one gap, having an interior, and wherein at least one of the more than one substrate contacts is located within the interior of the die seal, adjacent to and overlapping the at least one gap.

7. A reverse bias network configured to be coupled to a stack of series-coupled MOSFETs, the stack of series-coupled MOSFETs being fabricated as an integrated circuit on a silicon-on-insulator substrate, the reverse bias network comprising: (a) A plurality of groups, each group comprising one or more substrate contacts, and at least one group comprising more than one substrate contact, each substrate contact comprising a conductive structure formed through an active layer and a buried oxide layer of the integrated circuit to or near the substrate, and each substrate contact having a first end and a second end, the first end being positioned to apply a reverse bias voltage over a region of the substrate, and the second end being capable of accessing a connection in the superstructure of the integrated circuit, each group being positioned near a corresponding MOSFET within a stack of the series-coupled MOSFETs; as well as (b) A resistor coupled between pairs of groups to a second end of a substrate contact of the pairs of groups; The reverse bias network is also configured to be coupled to a bias voltage source.

8. The reverse bias network according to claim 7, wherein, The MOSFET is an N-type MOSFET, and the bias voltage source provides a negative bias voltage to the group when coupled.

9. The reverse bias network according to claim 7, wherein, The MOSFET is a P-type MOSFET, and the bias voltage source provides a positive bias voltage to the group when coupled.

10. The reverse bias network according to claim 7, wherein, Each resistor provides a resistance of at least 10K ohms between the pairs.

11. The reverse bias network according to claim 7, wherein, The reverse bias network is configured to selectively apply a first reverse bias voltage to a first region of the substrate, and further includes a second reverse bias network configured to selectively apply a second reverse bias voltage to a second region of the substrate.

12. The reverse bias network according to claim 7, wherein, The integrated circuit includes a die seal having at least one gap, having an interior, and wherein at least one substrate contact is located within the interior of the die seal, adjacent to and overlapping the at least one gap.

13. An integrated circuit fabricated on a silicon-on-insulator substrate and having increased power handling capability, the integrated circuit comprising: (a) A plurality of series-coupled MOSFETs fabricated on the substrate; (b) A plurality of groups, each group comprising one or more substrate contacts and at least one group comprising more than one substrate contact, each substrate contact comprising a conductive structure formed through an active layer and a buried oxide layer of the integrated circuit to or near the substrate, and each substrate contact having a first end and a second end, the first end being positioned to apply a reverse bias voltage over a region of the substrate, and the second end being capable of accessing a connection in the superstructure of the integrated circuit, each group being positioned near a corresponding MOSFET within the plurality of series-coupled MOSFETs; (c) A resistor coupled between each pair of adjacent groups to the second end of the substrate contact of the pair of adjacent groups; as well as (d) A bias voltage source coupled to at least one of the plurality of groups.

14. The integrated circuit according to claim 13, wherein, The MOSFET is an N-type MOSFET, and the bias voltage source provides a negative bias voltage to the group.

15. The integrated circuit according to claim 13, wherein, The MOSFET is a P-type MOSFET, and the bias voltage source provides a positive bias voltage to the group.

16. The integrated circuit according to claim 13, wherein, Each resistor provides at least 10K ohms of resistance between the pairs of adjacent groups.

17. The integrated circuit according to claim 13, wherein, The group is configured to selectively apply at least two different reverse bias voltages to corresponding different regions of the substrate.

18. The integrated circuit according to claim 13, wherein, The plurality of series-coupled MOSFETs are linearly arranged on the substrate, and the group and the resistors are offset to the side of the MOSFETs and arranged and aligned in the direction in which the radio frequency signal flows through the MOSFETs.

19. The integrated circuit according to claim 13, wherein, The integrated circuit includes a die seal having at least one gap, having an interior, and wherein at least one substrate contact is located within the interior of the die seal, adjacent to and overlapping the at least one gap.

20. The integrated circuit according to claim 13, wherein, The integrated circuit includes a radio frequency switch.

21. A radio frequency switch, comprising: (a) A plurality of series-coupled MOSFETs, said plurality of series-coupled MOSFETs being fabricated as an integrated circuit on a silicon-on-insulator substrate and configured to selectively conduct or block coupled radio frequency input signals; (b) Inverse bias network, including: (1) A plurality of groups, each group comprising one or more substrate contacts and at least one group comprising more than one substrate contact, each substrate contact comprising a conductive structure formed to or near the substrate through an active layer and a buried oxide layer of the integrated circuit, and each substrate contact having a first end and a second end, the first end being positioned to apply a reverse bias voltage over a region of the substrate, and the second end being accessible to a connection in the upper structure of the integrated circuit, each group being positioned near a corresponding MOSFET of the plurality of series-coupled MOSFETs; and (2) At least one resistor, each resistor being coupled to a second end of a pair of substrate contacts; and (c) A bias voltage source coupled to at least one of the plurality of groups.

22. The radio frequency switch according to claim 21, wherein, The MOSFET is an N-type MOSFET, and the bias voltage source provides a negative bias voltage to the group.

23. The radio frequency switch according to claim 21, wherein, The MOSFET is a P-type MOSFET, and the bias voltage source provides a positive bias voltage to the group.

24. The radio frequency switch according to claim 21, wherein, Each resistor provides a resistance of at least 10K ohms.

25. The radio frequency switch according to claim 21, wherein, The group is configured to selectively apply at least two different reverse bias voltages to corresponding different regions of the substrate.

26. The radio frequency switch according to claim 21, wherein, The plurality of series-coupled MOSFETs are linearly arranged on the substrate, and the group and the resistors are offset to the side of the MOSFETs and arranged and aligned in the direction in which the radio frequency signal flows through the MOSFETs.

27. The radio frequency switch according to claim 21, wherein, The integrated circuit includes a die seal having at least one gap, having an interior, and wherein at least one substrate contact is located within the interior of the die seal, adjacent to and overlapping the at least one gap.

28. A method for manufacturing an integrated circuit with increased power handling capability, comprising: (a) Fabricating multiple series-coupled MOSFETs on a silicon-on-insulator substrate; (b) Fabricating a plurality of substrate contacts, each substrate contact including a conductive structure formed through an active layer and a buried oxide layer of the integrated circuit to or near the substrate, and each substrate contact having a first end and a second end, the first end being positioned to apply a reverse bias voltage over a region of the substrate, and the second end being able to access a connection in the upper structure of the integrated circuit, wherein a group of more than one of the plurality of substrate contacts is positioned close to a corresponding MOSFET within the plurality of series-coupled MOSFETs; (c) A resistor is fabricated between the second ends of the plurality of substrate contacts in pairs, each resistor being configured to be coupled to a bias voltage source.

29. The method according to claim 28, wherein, The MOSFET is an N-type MOSFET, and the reverse bias voltage is a negative bias voltage.

30. The method according to claim 28, wherein, The MOSFET is a P-type MOSFET, and the reverse bias voltage is a forward bias voltage.

31. The method according to claim 28, wherein, Each resistor provides a resistance of at least 10K ohms between the pairs.

32. The method according to claim 28, wherein, Also includes: At least a first group and a second group of substrate contacts are configured to selectively apply at least two different reverse bias voltages to corresponding different regions of the substrate.

33. The method of claim 28, further comprising: (a) The plurality of series-coupled MOSFETs are linearly arranged on the substrate; (b) Offset the assembly of the substrate contacts and the resistor toward the side of the MOSFET; as well as (c) The group of substrate contacts and the resistor are arranged and aligned in the direction in which the radio frequency signal flows through the MOSFET.

34. The method of claim 28, further comprising providing a die seal to the integrated circuit, the die seal having at least one gap and having an interior, and further comprising positioning at least one of the plurality of substrate contacts within the interior of the die seal, adjacent to and overlapping the at least one gap.

35. A method for manufacturing a radio frequency switch, comprising: (a) A plurality of series-coupled MOSFETs are fabricated on a silicon-on-insulator substrate, the plurality of series-coupled MOSFETs being fabricated as an integrated circuit on the silicon-on-insulator substrate and configured to selectively conduct or block coupled radio frequency input signals. as well as (b) Fabricating a reverse bias network, the reverse bias network comprising: (1) A plurality of groups, each group including one or more substrate contacts, and at least one group of the groups including more than one substrate contact, each substrate contact including a conductive structure formed through an active layer and a buried oxide layer of the integrated circuit to or near the substrate, and each substrate contact having a first end and a second end, the first end being positioned to apply a reverse bias voltage over a region of the substrate, and the second end being able to access a connection in the superstructure of the integrated circuit, each group being positioned near a corresponding MOSFET within the plurality of series-coupled MOSFETs; as well as (2) At least one resistor, each resistor being coupled to the second end of a pair of substrate contacts.

36. The method according to claim 35, wherein, The MOSFET is an N-type MOSFET, and the reverse bias voltage is a negative bias voltage.

37. The method of claim 35, wherein, The MOSFET is a P-type MOSFET, and the reverse bias voltage is a forward bias voltage.

38. The method according to claim 35, wherein, Each resistor provides a resistance of at least 10K ohms between the pairs.

39. The method of claim 35, further comprising configuring the group to selectively apply at least two different reverse bias voltages to corresponding different regions of the substrate.

40. The method of claim 35, further comprising: (a) The plurality of series-coupled MOSFETs are linearly arranged on the substrate; (b) Shift the reverse bias network toward the side of the linearly arranged MOSFETs; as well as (c) The reverse bias network is arranged and aligned in the direction in which the radio frequency signal flows through the MOSFET.

41. A reverse bias network configured to be coupled to a stack of series-coupled MOSFETs, the stack of series-coupled MOSFETs being fabricated as an integrated circuit on a silicon-on-insulator substrate, the reverse bias network comprising: (a) A plurality of groups of substrate contacts, each substrate contact including a conductive structure formed to or near the substrate through an active layer and a buried oxide layer of the integrated circuit, each group including one or more substrate contacts, wherein a group of more than one of the one or more substrate contacts is positioned to apply a reverse bias voltage to a region of a corresponding MOSFET in a stack of series-coupled MOSFETs on the substrate; and (b) A resistance ladder comprising a plurality of resistors, each resistor being coupled between a corresponding group of one or more substrate contacts, the resistance ladder being configured to be coupled to a bias voltage source.

42. The reverse bias network according to claim 41, wherein, The MOSFET is an N-type MOSFET, and the reverse bias voltage is a negative bias voltage.

43. The reverse bias network according to claim 41, wherein, The MOSFET is a P-type MOSFET, and the reverse bias voltage is a forward bias voltage.

44. The reverse bias network according to claim 41, wherein, The resistance step provides a resistance of at least 10K ohms between one or more groups of substrate contacts.

45. The reverse bias network according to claim 41, wherein, The reverse bias network is configured to selectively apply a first reverse bias voltage to a first region of the substrate, and further includes a second reverse bias network configured to selectively apply a second reverse bias voltage to a second region of the substrate.

46. ​​The reverse bias network according to claim 41, wherein, The integrated circuit includes a die seal having at least one gap, having an interior, and wherein at least one of the substrate contacts is located within the interior of the die seal, adjacent to and overlapping the at least one gap.

47. The reverse bias network according to claim 41, wherein, The reverse bias network is configured to selectively apply pulsed reverse bias voltages to regions of the substrate.

48. The reverse bias network according to claim 41, wherein, The reverse bias network is configured to selectively apply forward and reverse bias voltages to regions of the substrate.

49. The reverse bias network according to claim 41, wherein, The reverse bias network is configured to selectively apply forward and reverse bias voltages to a region of the substrate when the MOSFET is in the ON state.

50. The reverse bias network according to claim 41, wherein, The reverse bias network is configured to selectively apply a negative reverse bias voltage to a region of the substrate.

51. The reverse bias network according to claim 41, wherein, The reverse bias network is configured to selectively apply a negative reverse bias voltage to a region of the substrate when the MOSFET is in the off state.

52. The reverse bias network according to claim 41, wherein, The reverse bias network is configured to selectively apply positive and reverse bias voltages to a region of the substrate when the MOSFET is in the ON state, and to selectively apply negative reverse bias voltages to a region of the substrate when the MOSFET is in the OFF state.

53. The reverse bias network according to claim 41, wherein, The reverse bias network is configured to selectively apply positive and reverse bias voltages to a region of the substrate at a first time, and to selectively apply negative reverse bias voltages to a region of the substrate at a second time.

54. The reverse bias network according to claim 41, wherein, The reverse bias network is configured to selectively apply positive and negative bias voltages to a first region of the substrate and selectively apply negative reverse bias voltages to a second region of the substrate.

55. The reverse bias network according to claim 41, wherein, The reverse bias network is coupled to a stack of series-coupled MOSFETs, which is fabricated as an integrated circuit on a silicon-on-insulator substrate and configured as a radio frequency switch.

56. A reverse bias network configured to be coupled to a stack of series-coupled MOSFETs, the stack of series-coupled MOSFETs being fabricated as an integrated circuit on a silicon-on-insulator substrate, the reverse bias network comprising: (a) A plurality of groups of more than one substrate contact, positioned to apply a reverse bias voltage to a plurality of corresponding regions of a respective MOSFET in a stack of series-coupled MOSFETs on the substrate, wherein each substrate contact includes a conductive structure extending from the upper structure of the integrated circuit through the active layer and insulating buried oxide layer of the integrated circuit to or near the substrate; and (b) A resistance ladder formed within the upper structure of the integrated circuit and comprising a plurality of resistors, each resistor being coupled between corresponding groups of more than one substrate contact, the resistance ladder being configured to be coupled to a bias voltage source.

57. The reverse bias network according to claim 56, wherein, The MOSFET is an N-type MOSFET, and the reverse bias voltage is a negative bias voltage.

58. The reverse bias network according to claim 56, wherein, The MOSFET is a P-type MOSFET, and the reverse bias voltage is a forward bias voltage.

59. The reverse bias network according to claim 56, wherein, The resistance ladder provides a resistance of at least 10K ohms between the groups.

60. The reverse bias network according to claim 56, wherein, The reverse bias network is configured to selectively apply a first reverse bias voltage to a first region of the substrate, and further includes a second reverse bias network configured to selectively apply a second reverse bias voltage to a second region of the substrate.

61. The reverse bias network according to claim 56, wherein, The integrated circuit includes a die seal having at least one gap, having an interior, and wherein at least one of the more than one substrate contacts is located within the interior of the die seal, adjacent to and overlapping the at least one gap.

62. A reverse bias network configured to be coupled to a stack of series-coupled MOSFETs, the stack of series-coupled MOSFETs being fabricated as an integrated circuit on a silicon-on-insulator substrate, the reverse bias network comprising: (a) A plurality of groups, each group comprising one or more substrate contacts, and at least one group comprising more than one substrate contact, wherein each substrate contact comprises a conductive structure extending from the superstructure of the integrated circuit through the active layer and insulating buried oxide layer of the integrated circuit to or near the substrate, each substrate contact having a first end and a second end, the first end being positioned to apply a reverse bias voltage over a region of the substrate, and the second end being accessible to a connection in the superstructure of the integrated circuit, each group being positioned near a corresponding MOSFET within a stack of the series-coupled MOSFETs; and (b) A resistor coupled between pairs of groups to a second end of a substrate contact of the pairs of groups; The reverse bias network is also configured to be coupled to a bias voltage source.

63. The reverse bias network according to claim 62, wherein, The MOSFET is an N-type MOSFET, and the bias voltage source provides a negative bias voltage to the group when coupled.

64. The reverse bias network according to claim 62, wherein, The MOSFET is a P-type MOSFET, and the bias voltage source provides a positive bias voltage when coupled.

65. The reverse bias network according to claim 62, wherein, Each resistor provides a resistance of at least 10K ohms between the pairs.

66. The reverse bias network according to claim 62, wherein, The reverse bias network is configured to selectively apply a first reverse bias voltage to a first region of the substrate, and further includes a second reverse bias network configured to selectively apply a second reverse bias voltage to a second region of the substrate.

67. The reverse bias network according to claim 62, wherein, The integrated circuit includes a die seal having at least one gap, having an interior, and wherein at least one substrate contact is located within the interior of the die seal, adjacent to and overlapping the at least one gap.

68. An integrated circuit fabricated on a silicon-on-insulator substrate and having increased power handling capability, the integrated circuit comprising: (a) A plurality of series-coupled MOSFETs fabricated on the substrate; (b) A plurality of groups, each group comprising one or more substrate contacts and at least one group comprising more than one substrate contact, wherein each substrate contact comprises a conductive structure extending from the superstructure of the integrated circuit through the active layer and insulating buried oxide layer of the integrated circuit to or near the substrate, each substrate contact having a first end and a second end, the first end being positioned to apply a reverse bias voltage over a region of the substrate, and the second end being capable of accessing a connection in the superstructure of the integrated circuit, each group being positioned near a corresponding MOSFET within the plurality of series-coupled MOSFETs; (c) A resistor coupled between each pair of adjacent groups to the second end of the substrate contact of the pair of adjacent groups; and (d) A bias voltage source coupled to at least one of the plurality of groups.

69. The integrated circuit according to claim 68, wherein, The MOSFET is an N-type MOSFET, and the bias voltage source provides a negative bias voltage to the group.

70. The integrated circuit according to claim 68, wherein, The MOSFET is a P-type MOSFET, and the bias voltage source provides a positive bias voltage to the group.

71. The integrated circuit according to claim 68, wherein, Each resistor provides at least 10K ohms of resistance between the pairs of adjacent groups.

72. The integrated circuit according to claim 68, wherein, The group is configured to selectively apply at least two different reverse bias voltages to corresponding different regions of the substrate.

73. The integrated circuit according to claim 68, wherein, The plurality of series-coupled MOSFETs are linearly arranged on the substrate, and the group and the resistors are offset to the side of the MOSFETs and arranged and aligned in the direction in which the radio frequency signal flows through the MOSFETs.

74. The integrated circuit according to claim 68, wherein, The integrated circuit includes a die seal having at least one gap, having an interior, and wherein at least one substrate contact is located within the interior of the die seal, adjacent to and overlapping the at least one gap.

75. A radio frequency switch, comprising: (a) A plurality of series-coupled MOSFETs, said plurality of series-coupled MOSFETs being fabricated as an integrated circuit on a silicon-on-insulator substrate and configured to be coupled to a radio frequency input signal; (b) Inverse bias network, including: (1) A plurality of groups, each group comprising one or more substrate contacts, each substrate contact having a first end and a second end, the first end being sufficiently close to the substrate to apply a reverse bias voltage on a region of the substrate sufficient to increase the power handling capability of at least one of the MOSFETs, the second end being capable of accessing a connection in the superstructure of the integrated circuit, wherein each substrate contact includes a conductive structure extending from the superstructure of the integrated circuit through the active layer and insulating buried oxide layer of the integrated circuit to or near the substrate; and (2) At least one resistor, each resistor being coupled to a second end of a pair of substrate contacts and configured to provide basic radio frequency isolation between the pairs; and (c) A bias voltage source coupled to at least one of the plurality of groups.

76. The radio frequency switch according to claim 75, wherein, The MOSFET is an N-type MOSFET, and the bias voltage source provides a negative bias voltage to the group of one or more substrate contacts.

77. The radio frequency switch according to claim 75, wherein, The MOSFET is a P-type MOSFET, and the bias voltage source provides a positive bias voltage to the group of one or more substrate contacts.

78. The radio frequency switch according to claim 75, wherein, Each resistor provides a resistance of at least 10K ohms.

79. The radio frequency switch according to claim 75, wherein, The group of one or more substrate contacts is configured to selectively apply at least two different reverse bias voltages to corresponding different regions of the substrate.

80. The radio frequency switch according to claim 75, wherein, The plurality of series-coupled MOSFETs are linearly arranged on the substrate, and the group of one or more substrate contacts and the resistor are offset toward the side of the MOSFETs and arranged and aligned in the direction in which the radio frequency signal flows through the MOSFETs.

81. The radio frequency switch according to claim 75, wherein, The integrated circuit includes a die seal having at least one gap, having an interior, and wherein at least one substrate contact is located within the interior of the die seal, adjacent to and overlapping the at least one gap.

82. A method for manufacturing an integrated circuit with increased power handling capability, comprising: (a) Fabricating multiple series-coupled MOSFETs on a silicon-on-insulator substrate; (b) Fabricating a plurality of substrate contacts, each substrate contact having a first end and a second end, the first end being close enough to the substrate to apply a reverse bias voltage on a region of the substrate sufficient to increase the power handling capability of at least one of the MOSFETs, the second end being able to access a connection in the superstructure of the integrated circuit, wherein each substrate contact includes a conductive structure extending from the superstructure of the integrated circuit through the active layer and insulating buried oxide layer of the integrated circuit to or near the substrate; (c) A resistor is fabricated between the second ends of the plurality of substrate contacts in pairs, each resistor being configured to provide basic radio frequency isolation between the pairs.

83. The method according to claim 82, wherein, The MOSFET is an N-type MOSFET, and the reverse bias voltage is a negative bias voltage.

84. The method according to claim 82, wherein, The MOSFET is a P-type MOSFET, and the reverse bias voltage is a forward bias voltage.

85. The method according to claim 82, wherein, Each resistor provides a resistance of at least 10K ohms between the pairs.

86. The method of claim 82, further comprising: The plurality of substrate contacts are configured into at least a first group and a second group of one or more substrate contacts, and the at least first group and the second group of one or more substrate contacts are configured to selectively apply at least two different reverse bias voltages to corresponding different regions of the substrate.

87. The method of claim 82, further comprising: (a) The plurality of series-coupled MOSFETs are linearly arranged on the substrate; (b) Offset a group of one or more substrate contacts and the resistor toward the side of the MOSFET; as well as (c) The group of one or more substrate contacts and the resistor are arranged and aligned in the direction in which the radio frequency signal flows through the MOSFET.

88. The method of claim 82, further comprising providing a die seal to the integrated circuit, the die seal having at least one gap and having an interior, and further comprising positioning at least one of the plurality of substrate contacts within the interior of the die seal, adjacent to and overlapping the at least one gap.

89. A method for manufacturing a radio frequency switch, comprising: (a) A plurality of series-coupled MOSFETs are fabricated on a silicon-on-insulator substrate, the plurality of series-coupled MOSFETs being fabricated as an integrated circuit on the silicon-on-insulator substrate and configured to be coupled to a radio frequency input signal; as well as (b) Fabricating a reverse bias network, the reverse bias network comprising: (1) A plurality of groups, each group comprising one or more substrate contacts, each substrate contact having a first end and a second end, the first end being sufficiently close to the substrate to apply a reverse bias voltage on a region of the substrate sufficient to increase the power handling capability of at least one of the MOSFETs, the second end being capable of accessing a connection in the superstructure of the integrated circuit, wherein each substrate contact includes a conductive structure extending from the superstructure of the integrated circuit through the active layer and insulating buried oxide layer of the integrated circuit to or near the substrate; and (2) At least one resistor, each resistor being coupled to a second end of a pair of substrate contacts and configured to provide basic radio frequency isolation between the pairs.

90. The method according to claim 89, wherein, The MOSFET is an N-type MOSFET, and the reverse bias voltage is a negative bias voltage.

91. The method according to claim 89, wherein, The MOSFET is a P-type MOSFET, and the reverse bias voltage is a forward bias voltage.

92. The method according to claim 89, wherein, Each resistor provides a resistance of at least 10K ohms between the pairs.

93. The method of claim 89, further comprising configuring the group of one or more substrate contacts to selectively apply at least two different reverse bias voltages to corresponding different regions of the substrate.

94. The method of claim 89, further comprising: (a) The plurality of series-coupled MOSFETs are linearly arranged on the substrate; (b) Shift the reverse bias network toward the side of the linearly arranged MOSFETs; as well as (c) The reverse bias network is arranged and aligned in the direction in which the radio frequency signal flows through the MOSFET.

Images