FPGA Integrated Circuit Layout-Based High-Fanout Net Optimization Method and Optimization System

Abstract

The present disclosure provides a layout-based high-fanout wire network optimization method and system for FPGA integrated circuits. Each wire network includes multiple connection lines connected between a driving device and multiple output devices. The optimization method includes: marking the timing criticality at the output ends of the multiple connection lines respectively; setting cluster control parameters for each timing criticality respectively; obtaining the timing criticality of the wire network and determining whether it is a high-fanout wire network that needs to be split according to the cluster control parameters; for the wire network that needs to be split, using a clustering algorithm to split the multiple output devices into multiple clusters according to the cluster control parameters; replicating multiple copies of the driving device and allocating them to the multiple clusters as the driving devices therein. The optimization method and system define the timing criticality and set the cluster control parameters accordingly, split the wire network based on these parameters, with high internal correlation within the clusters, improved device transmission performance, accurate and fast algorithms, improved splitting efficiency and reduced costs, and simplified wire network layout.

Description

Technical Field

[0001] The present invention relates to the field of integrated circuits, and particularly to a method and system for optimizing high-fanout nets based on layout for FPGA integrated circuits. Background Art

[0002] An FPGA (Field Programmable Gate Array) is a logic device composed of many logic units, with rich hardware resources and powerful parallel processing capabilities, and has been widely used in many fields such as data processing and communication. After the physical positions of the logic units in the FPGA integrated circuit are determined, the actual physical connection of signal lines for the connection relationships of the logic units begins. It is necessary to establish a connection net between the driving device and the output devices. If the fanout of the net is too high, that is, the driving device needs to drive too many output devices, then the net will be particularly complex. The longer the net length of the net with a larger fanout is usually after layout, and the greater the error between the half-perimeter wire length (HPWL, Half-Perimeter Wire Length) commonly used by the layout algorithm to estimate the net wire length and the wire length of the net after actual wiring; and the high-fanout net (HFN, High Fanout Net) has a long wiring time and is prone to topological detours, which often lead to a large timing delay of the high-fanout net, thus affecting the timing quality of the chip design. Therefore, the optimization of high-fanout nets is an important part of the FPGA integrated circuit automatic design software.

[0003] Currently, the existing optimization method for high-fanout nets is to divide the output devices of the high-fanout net into multiple groups according to the proximity of the layout positions, and insert registers into each group to drive multiple output devices to reduce the net load. Such a division method is too single and does not consider the timing influence between devices, and the device performance of each group is poor after grouping. Therefore, the currently used optimization method for high-fanout nets has great limitations and cannot meet the requirements of high integration and fast signal processing of integrated circuits. Summary of the Invention

[0004] In view of this, embodiments of the present invention provide a method and system for optimizing high-fanout nets based on layout for FPGA integrated circuits, and split the high-fanout nets to solve the problems in the prior art.

[0005] According to a first aspect of the present invention, there is provided a method for optimizing high-fanout nets based on layout for FPGA integrated circuits. The FPGA integrated circuit includes multiple nets, and each net includes multiple connection lines connected between a driving device and multiple output devices. Wherein, for each net, the optimization method includes:

[0006] Mark the timing criticality at the output ends of the multiple connection lines respectively, where the timing criticality characterizes the timing transmission performance on the corresponding connection lines;

[0007] Set cluster control parameters for each cluster corresponding to the timing criticality respectively;

[0008] Obtain the timing criticality of the net according to the multiple timing criticalities of the multiple connection lines, and judge whether the net is a high fan-out net that needs to be split according to the cluster control parameters;

[0009] For the high fan-out net that needs to be split, use the clustering algorithm to split the multiple output devices into multiple clusters according to the cluster control parameters;

[0010] Based on the driving device, replicate multiple copies and allocate the multiple copies to the multiple clusters as the driving devices therein.

[0011] Optionally, before the step of marking the timing criticality at the output ends of the multiple connection lines respectively, it further includes:

[0012] Conduct timing analysis on the net to obtain the timing margin at the output end of each connection line, where the timing margin is the difference between the set transmission time and the actual transmission time;

[0013] Sort all the connection lines in ascending order of the timing margin, and calculate the timing criticality at the output end of each connection line according to the sorting result.

[0014] Optionally, the timing criticality is distributed in a stepwise manner from large to small according to the sorting of the timing margin, and the greater the timing criticality, the worse the timing transmission performance.

[0015] Optionally, the timing criticality at the output end of the connection lines ranked in the top 1% is 6;

[0016] The timing criticality at the output end of the connection lines ranked from 1% to 5% is 5;

[0017] The timing criticality at the output end of the connection lines ranked from 5% to 10% is 4;

[0018] The timing criticality at the output end of the connection lines ranked from 10% to 20% is 3;

[0019] The timing criticality at the output end of the connection lines ranked from 20% to 40% is 2;

[0020] The timing criticality at the output end of the connection lines ranked after 40% is 1;

[0021] The timing criticality at the output end of the connection lines without timing constraints is 0.

[0022] Optionally, after the step of replicating multiple copies based on the driving device and allocating the multiple copies to the multiple clusters as the driving devices therein, the method further includes:

[0023] Invoking an incremental layout algorithm to adjust the layout positions of the multiple copies and re-layout the netlist.

[0024] Optionally, the timing criticality of the netlist is the maximum timing criticality among the multiple timing criticalities of the multiple connection lines; the timing criticality of the cluster is the maximum timing criticality among the timing criticalities corresponding to all the connection lines in the cluster.

[0025] Optionally, the cluster control parameters include a cluster size and a cluster radius. The cluster size is the number of output devices included in the cluster, and the cluster radius is the maximum distance between the output device and the cluster center point.

[0026] Optionally, the steps of obtaining the timing criticality of the netlist according to the multiple timing criticalities of the multiple connection lines and determining whether the netlist is a high fan-out netlist that needs to be split according to the cluster control parameters include:

[0027] Obtaining the maximum timing criticality among the multiple timing criticalities corresponding to the multiple connection lines in the netlist as the timing criticality of the netlist;

[0028] Obtaining the cluster control parameters corresponding to the timing criticality of the netlist;

[0029] When the number of output devices and the cluster radius included in the netlist conform to the cluster control parameters, the netlist is a netlist that does not need to be split;

[0030] When the number of output devices or the cluster radius included in the netlist is greater than the cluster control parameters, the netlist is a high fan-out netlist that needs to be split.

[0031] Optionally, the upper limit of the cluster size corresponding to a cluster with a timing criticality of 6 is 10, and the upper limit of the cluster radius is 10;

[0032] The upper limit of the cluster size corresponding to a cluster with a timing criticality of 5 is 20, and the upper limit of the cluster radius is 10;

[0033] The upper limit of the cluster size corresponding to a cluster with a timing criticality of 4 is 30, and the upper limit of the cluster radius is 10;

[0034] The upper limit of the cluster size corresponding to a cluster with a timing criticality of 3 is 50, and the upper limit of the cluster radius is 20;

[0035] The upper limit of the cluster scale corresponding to the clusters with a timing criticality of 2 is 80, and the upper limit of the cluster radius is 30;

[0036] The upper limit of the cluster scale corresponding to the clusters with a timing criticality of 1 is 120, and the upper limit of the cluster radius is 50;

[0037] There are no restrictions on the cluster scale and the cluster radius corresponding to the clusters with a timing criticality of 0.

[0038] Optionally, the step of splitting multiple output devices into multiple clusters according to the cluster control parameters for the high fan-out wire nets that need to be split by using the clustering algorithm includes:

[0039] Calculating the clustering score of each target cluster and other clusters according to the clustering formula and putting it into the priority queue. Each cluster includes at least one output device, and the initial number of the output devices included in each cluster is 1;

[0040] Taking out the pair of clusters with the smallest clustering score from the priority queue. When the clustering score is valid, merging all the output devices in the pair of clusters into one target cluster;

[0041] Judging whether the parameters of the merged target cluster conform to the cluster control parameters;

[0042] For the target cluster whose parameters conform to the cluster control parameters, repeatedly executing the steps of calculating the clustering score of each target cluster and other clusters according to the clustering formula until judging whether the parameters of the merged target cluster conform to the cluster control parameters, until the parameters do not conform to the cluster control parameters, and taking the target cluster as a group.

[0043] Optionally, the clustering formula uses the distribution distance of the output devices, the difference in timing criticality, and the cluster scale as control factors.

[0044] According to the second aspect of the present invention, there is provided an FPGA integrated circuit layout-based high fan-out wire net optimization system. The FPGA integrated circuit includes multiple wire nets, and each wire net includes multiple connection lines connected between a driving device and multiple output devices. Among them, the optimization system includes:

[0045] A timing analysis unit for performing timing analysis on the wire nets to obtain the timing margin at the output end of each connection line. The timing margin is the difference between the set transmission time and the actual transmission time;

[0046] A timing criticality calculation unit for sorting all the connection lines in ascending order of the timing margin and calculating the timing criticality at the output end of each connection line according to the sorting result;

[0047] A marking unit, which is used to respectively mark the timing criticality at the output ends of the multiple connection lines, and the timing criticality characterizes the timing transmission performance on the corresponding connection lines;

[0048] A control parameter setting unit, which is used to respectively set cluster control parameters for each cluster corresponding to the timing criticality;

[0049] A judgment unit, which is used to obtain the timing criticality of the net according to the multiple timing criticalities of the multiple connection lines, and judge whether the net is a high fan-out net that needs to be split according to the cluster control parameters;

[0050] A clustering grouping unit, which is used to adopt a clustering algorithm for the high fan-out net that needs to be split to split the multiple output devices into multiple clusters according to the cluster control parameters;

[0051] An allocation unit, which is used to replicate multiple copies based on the driving device and allocate the multiple copies to the multiple clusters as the driving devices therein;

[0052] A layout unit, which is used to call an incremental layout algorithm to adjust the layout positions of the multiple copies and re-layout the net.

[0053] Optionally, the cluster control parameters include a cluster scale and a cluster radius. The cluster scale is the number of the output devices included in the cluster, and the cluster radius is the maximum distance between the output device and the cluster center point.

[0054] The embodiments of the present invention have the following advantages or beneficial effects: The FPGA integrated circuit based on-layout high fan-out net optimization method and optimization system according to the embodiments of the present invention set the timing criticality for all output ends of the net, then set the cluster control parameters for the corresponding clusters according to the timing criticality, and then judge whether the net needs to be split according to these parameters. For the high fan-out net that needs to be split, a clustering algorithm is adopted to classify the multiple output devices, and the cluster control parameters are added at the same time, so as to consider the influence of the timing criticality and the cluster control parameters on the grouping. For the grouped clusters, multiple copies are replicated based on the driving device, and one copy is allocated to each cluster as the driving device to complete the splitting and re-layout of the net. The FPGA integrated circuit based on-layout high fan-out net optimization method and optimization system split the net based on the timing criticality and the cluster control parameters, so that the correlation degree of the output devices inside the split clusters is high and the timing transmission performance is quite the same, avoiding the increase in cost caused by directly using the timing margin for grouping; moreover, the clustering algorithm is adopted for grouping, which can optimize the distribution of the output devices and simplify the wiring difficulty of the net; the adopted algorithm is accurate and fast, without multiple iterations, can flexibly control the scale of the cluster, improve the splitting efficiency and reduce the splitting cost. Description of the Drawings

[0055] The above and other objects, features, and advantages of the present invention will become more apparent from the following description of the embodiments of the present invention with reference to the accompanying drawings. In the drawings:

[0056] Figure 1 A simplified flowchart of a layout-based high-fanout wire network optimization method for an FPGA integrated circuit according to an embodiment of the present invention is shown;

[0057] Figure 2 An optimized flowchart of a layout-based high-fanout wire network optimization method for an FPGA integrated circuit according to an embodiment of the present invention is shown;

[0058] Figure 3 An overall flowchart of a layout-based high-fanout wire network optimization method for an FPGA integrated circuit according to an embodiment of the present invention is shown;

[0059] Figure 4 A schematic flowchart of a clustering algorithm in an FPGA integrated circuit according to an embodiment of the present invention is shown;

[0060] Figure 5 A structural diagram of a layout-based high-fanout wire network optimization system for an FPGA integrated circuit according to an embodiment of the present invention is shown. Detailed Embodiments

[0061] The present invention will be described below based on embodiments, but the present invention is not limited to these embodiments. In the following detailed description of the present invention, some specific details are described in detail. Those skilled in the art can fully understand the present invention without the description of these details. In order to avoid obscuring the essence of the present invention, well-known methods, processes, and flows are not described in detail. Additionally, the accompanying drawings are not necessarily drawn to scale.

[0062] Figure 1 A simplified flowchart of a layout-based high-fanout wire network optimization method for an FPGA integrated circuit according to an embodiment of the present invention is shown, and the specific steps include S101 - S105.

[0063] When routing integrated circuits, some optimization methods for high - fan - out nets are usually adopted to reduce the load of high - fan - out nets. For example, the K - Center clustering algorithm is used to divide output devices into multiple clusters according to similar timing margins and layout positions, and then buffer registers (Buffers) are inserted into each cluster to drive the output devices to optimize the net. However, this clustering algorithm needs to pre - select the "seeds" of clustering, has a long algorithm time, and the number of clusters and the number of output devices in the clusters need to be iterated and converged repeatedly, making the control relatively difficult. The present invention provides a layout - based high - fan - out net optimization method applied to FPGA integrated circuits. Specifically, it provides a method for physically optimizing high - fan - out nets based on the preliminary circuit layout results, using the Best - Choice clustering algorithm, which has a fast algorithm speed and can flexibly control the number of devices in the cluster and the maximum distance between output devices according to the timing criticality of the devices in the cluster. The following combines Figure 1 the respective steps to introduce in detail the optimization method of the high - fan - out net in this embodiment.

[0064] In step S101, timing criticalities are respectively marked at the output ends of multiple connection lines, and the timing criticality characterizes the timing transmission performance of the corresponding connection line.

[0065] In this step, the FPGA integrated circuit includes multiple nets, each net includes at least one driving device and multiple output devices, and multiple connection lines connecting the driving device and the multiple output devices. On each connection line, a timing path is formed from the signal output end to the signal output end, and the signal input end and output end are respectively called the source end and the drain end. In this embodiment, first, timing criticalities are respectively marked at the output ends (drain ends) of each connection line in a net. The timing criticality is a quantity used to characterize the timing transmission performance of the connection line. Then, the timing criticalities corresponding to the drain ends of each connection line are not completely the same. According to the marked timing criticalities, it can be known how fast each timing path transmits.

[0066] In step S102, cluster control parameters are respectively set for each cluster corresponding to the timing criticality.

[0067] In this step, the timing criticalities corresponding to multiple connection lines are obtained. The timing criticalities of connection lines with similar transmission performances can be regarded as the same value. Then, the number of timing criticalities corresponding to a net is limited. According to the timing criticality, cluster control parameters can be respectively set for each cluster corresponding to the timing criticality. For example, the cluster control parameter of the cluster where the first timing criticality is located is set to the first value, and the cluster control parameter of the cluster where the second timing criticality is located is set to the second value, and the first value is different from the second value, and so on, to complete the setting of the cluster control parameters for each cluster corresponding to the timing criticality.

[0068] Further, the cluster control parameters include the cluster size and the cluster radius. The cluster size is the number of output devices included in the cluster, and the cluster radius is the maximum distance between the output device and the cluster center point (in the unit of the average row and column size of the logic array of the FPGA integrated circuit). The cluster size and the cluster radius corresponding to different timing criticalities are not exactly the same. The set cluster control parameters are used as constraint conditions when splitting high fan-out nets. When the timing criticality of a cluster is determined, the corresponding cluster size and cluster radius need to conform to the corresponding cluster control parameters.

[0069] In step S103, the timing criticality of the net is obtained according to the timing criticalities of multiple connection lines, and it is judged whether the net is a high fan-out net that needs to be split according to the cluster control parameters.

[0070] In this step, for a selected net, it is first necessary to judge whether it is a high fan-out net and whether it needs to be split. Then, it is necessary to first obtain the timing criticality of the net, and then judge whether the net is a high fan-out net that needs to be split according to the timing criticality of the net and the corresponding set cluster control parameters. Specifically, this step includes: obtaining the maximum timing criticality among the multiple timing criticalities corresponding to the multiple connection lines in the net as the timing criticality of the net; obtaining the cluster control parameters corresponding to the timing criticality of the net; when the number of output devices and the cluster radius included in the net conform to the cluster control parameters, the net is a net that does not need to be split; and when the number of output devices or the cluster radius included in the net is greater than the cluster control parameters, the net is a high fan-out net that needs to be split. The timing criticality of the net is the maximum timing criticality among the multiple timing criticalities corresponding to all the connection lines in the net. For example, when the maximum timing criticality in the net is the second timing criticality mentioned in the previous step, it is necessary to judge whether the number of output devices and the cluster radius of the net conform to the second value.

[0071] In step S104, the high fan-out net that needs to be split is split into multiple clusters according to the cluster control parameters by using the clustering algorithm.

[0072] In this step, when it is determined that the selected wire net is a high fan-out wire net to be split, a certain algorithm needs to be used to split the wire net, and multiple output devices are divided into multiple groups. Commonly, the clustering algorithm is used for grouping. For example, the Best-Choice clustering algorithm is used. In the obtained grouping, multiple output devices are closely clustered with each other. When using the clustering algorithm to group the high fan-out wire net, the cluster control parameter needs to be used as a constraint condition. The multiple groups divided, that is, multiple clusters, need to conform to the cluster control parameter corresponding to the cluster. In this step, when using the clustering algorithm to divide multiple output devices into multiple clusters, the timing criticality of each cluster needs to be obtained, and then the corresponding cluster control parameter is found according to the timing criticality, so that both the cluster size and the cluster radius of the cluster after grouping are within the range specified by the cluster control parameter. The criticality of the cluster in this embodiment is the maximum timing criticality among the timing criticalities corresponding to all the connection lines in the cluster.

[0073] Therefore, the optimization method for the high fan-out wire net in this embodiment is to set the cluster control parameter according to the timing criticality, and use the cluster control parameter as a constraint condition for the clustering algorithm to control the size of the cluster and the output devices included after the clustering grouping.

[0074] In step S105, multiple copies of the driving device are replicated and distributed to multiple clusters as the driving devices therein.

[0075] In this step, the method of replicating the driving device is used to optimize the layout of the high fan-out wire net. By replicating the original signal driving device in the wire net, the number of driving devices is increased to form multiple copies, and then multiple copies are used as driving devices to drive the output devices of multiple clusters respectively, that is, a copy is assigned to each cluster as a driving device, and the driving device of each cluster is responsible for driving all the output devices under the cluster. In this way, all the output devices originally driven by one driving device are driven by multiple replicated copies respectively, so as to achieve the purpose of reducing the fan-out of the wire net.

[0076] The high fan-out wire net can be optimized at all stages of the integrated circuit automated design (such as after front-end circuit synthesis, back-end chip layout or wiring). The optimization method for the high fan-out wire net in this embodiment is applicable to the layout stage of the circuit. Based on the layout position and timing criticality of the output devices, first, all the output devices of the high fan-out wire net are divided into several clusters by using the clustering algorithm, and then the driving device of the wire net is replicated to drive the output devices of each cluster, so as to achieve the purpose of simplifying the complex wire net.

[0077] The method for optimizing high-fanout nets based on layout in the FPGA integrated circuit according to the embodiment of the present invention sets the timing criticality for all signal output terminals of the net, then sets the cluster control parameters of the cluster according to the timing criticality, and then determines whether the net needs to be split according to these parameters. For the high-fanout nets that need to be split, the clustering algorithm is used to classify multiple output devices, and the cluster control parameters are added at the same time, so as to consider the influence of the timing criticality and the cluster control parameters on the grouping. For the clusters after grouping, the driving device is replicated, and a driving device is assigned to each cluster to complete the splitting and re-layout of the net. The method for optimizing high-fanout nets based on layout in the FPGA integrated circuit and the optimization system split the net based on the timing criticality and the cluster control parameters, so that the correlation degree of the output devices inside the cluster after splitting is high, and the timing transmission performance is quite the same, avoiding the increase in cost caused by directly using the timing margin for grouping; moreover, the clustering algorithm is used for grouping, which can optimize the distribution of the output devices and simplify the wiring difficulty of the net; the algorithm adopted is accurate and fast, without multiple iterations, and can flexibly control the scale of the cluster, improve the splitting efficiency and reduce the splitting cost.

[0078] Figure 2 The optimization flowchart of the method for optimizing high-fanout nets based on layout in the FPGA integrated circuit according to the embodiment of the present invention is shown.

[0079] As Figure 2 shown, this embodiment is the Figure 1 optimization scheme of the embodiment, which specifically includes steps S201-S208. Among them, steps S203-S207 are the same as Figure 1 steps S101-S105 of the embodiment, and the same parts will not be described again.

[0080] In step S201, a timing analysis is performed on the net to obtain the timing margin of the output terminal of each connection line. The timing margin is the difference between the set transmission time and the actual transmission time.

[0081] In this step, for the FPGA integrated circuit after preliminary layout or basically completed layout, first select a net, and then perform a timing analysis on it to obtain the timing margin of the signal output terminal (drain terminal) of each connection line. The timing margin is the difference between the set transmission time and the actual transmission time on the timing path. The smaller the value of the timing margin, the longer the actual transmission time, and the closer it is to the set transmission time; while the larger the value of the timing margin, the shorter the actual transmission time and the better the timing transmission performance. When the timing margin is negative, it especially means that the actual transmission time has exceeded the set transmission time and the timing transmission performance is poor.

[0082] In step S202, all connection lines are sorted in ascending order of the timing margin, and the timing criticality of the output terminal of each connection line is calculated according to the sorting result.

[0083] In this step, according to the timing analysis results, all the leakage ends of the wire network are sorted in ascending order of timing margin, and then the timing criticality of each leakage end is calculated. The ascending order here also includes the sorting of negative values. The timing criticality is set according to the sorting of the timing margin. For example, the timing criticality shows a stepped distribution from large to small in ascending order of the timing margin. For example, it can be shown in percentage form: the timing criticality of the output end of the connection line ranked in the top 1% is 6; the timing criticality of the output end of the connection line ranked from 1% to 5% is 5; the timing criticality of the output end of the connection line ranked from 5% to 10% is 4; the timing criticality of the output end of the connection line ranked from 10% to 20% is 3; the timing criticality of the output end of the connection line ranked from 20% to 40% is 2; the timing criticality of the output end of the connection line ranked after 40% is 1; the timing criticality of the output end of the connection line without timing constraints is 0. Correspondingly, the greater the timing criticality, the worse the timing transmission performance, and the wire network distribution corresponding to it needs to be adjusted emphatically.

[0084] In addition, the stepped calculation method of the timing criticality can be flexibly adjusted according to the requirements of high fan-out wire network optimization. For example, if more high fan-out wire networks with the most critical timing need to be optimized, the percentage of the leakage ends with a timing criticality of 6 can be adjusted to >1%, that is, the number of output devices with a larger timing criticality is increased.

[0085] Next, execute steps S203 - S207, which Figure 1 is the same as steps S101 - S105.

[0086] In step S203, mark the timing criticality at the output ends of multiple connection lines respectively, and the timing criticality characterizes the timing transmission performance of the corresponding connection line.

[0087] In step S204, set cluster control parameters for each cluster corresponding to the timing criticality respectively.

[0088] In this step, corresponding cluster control parameters are set according to the timing criticality of the clusters. Combining with step S202, this step includes: setting the upper limit of the cluster size corresponding to the cluster with a timing criticality of 6 to 10, and the upper limit of the cluster radius to 10; similarly, the upper limit of the cluster size corresponding to the cluster with a timing criticality of 5 is 20, and the upper limit of the cluster radius is 10; the upper limit of the cluster size corresponding to the cluster with a timing criticality of 4 is 30, and the upper limit of the cluster radius is 10; the upper limit of the cluster size corresponding to the cluster with a timing criticality of 3 is 50, and the upper limit of the cluster radius is 20; the upper limit of the cluster size corresponding to the cluster with a timing criticality of 2 is 80, and the upper limit of the cluster radius is 30; the upper limit of the cluster size corresponding to the cluster with a timing criticality of 1 is 120, and the upper limit of the cluster radius is 50; there are no restrictions on the cluster size and cluster radius corresponding to the cluster with a timing criticality of 0. In this way, the cluster sizes and cluster radii corresponding to different timing criticalities are limited. Then, when grouping later, the corresponding cluster control parameters can be obtained according to the timing criticality of the clusters, and the number and layout positions of the output devices included in the clusters can be well controlled according to the cluster control parameters.

[0089] Of course, the above cluster control parameters corresponding to different timing criticalities can be flexibly adjusted according to the requirements of high fan-out wire net optimization. For example, if it is necessary to weaken the optimization of high fan-out wire nets that are not critical to timing, the upper limit of the cluster size corresponding to the cluster with a timing criticality of 1 can be adjusted to >120, that is, the wire nets corresponding to the output devices that are not critical to timing (with good timing transmission performance) can be adjusted less.

[0090] In step S205, the timing criticality of the wire net is obtained according to the multiple timing criticalities of multiple connection lines, and it is judged whether the wire net is a high fan-out wire net that needs to be split according to the cluster control parameters.

[0091] In this step, the timing criticality of the wire net is the maximum timing criticality corresponding to all the leakage ends of the wire net. The corresponding cluster control parameters can be obtained according to the timing criticality of the wire net, and then it is judged whether the wire net is a high fan-out according to the number of output devices of the wire net, and it is decided whether to split the wire net. Moreover, when grouping the output devices of the wire net, it is also necessary to adaptively control the size and radius of the cluster according to the timing criticality of the cluster.

[0092] In step S206, for the high fan-out wire nets that need to be split, the clustering algorithm is used to split multiple output devices into multiple clusters according to the cluster control parameters.

[0093] In this step, a clustering algorithm is used to split the high fan-out wire networks according to the cluster control parameters in groups, and multiple output devices are split into multiple clusters. This step mainly includes: calculating the clustering scores of each target cluster and other clusters according to the clustering formula and putting them into a priority queue. Each cluster includes at least one output device, and the initial number of output devices included in each cluster is 1. Take out the pair of clusters with the smallest clustering score from the priority queue. When the clustering score is valid, merge all the output devices in the pair of clusters into a target cluster. Determine whether the parameters of the merged target cluster meet the cluster control parameters. For the target cluster whose parameters meet the cluster control parameters, repeat the steps of calculating the clustering scores of each target cluster and other clusters according to the clustering formula until the parameters of the merged target cluster do not meet the cluster control parameters, and then take the target cluster as a group.

[0094] This clustering algorithm is the Best-Choice algorithm, which is an algorithm for selecting the cluster or output device that best matches a cluster or output device. At the beginning of the algorithm, calculate the minimum clustering scores of each target output device and other output devices to obtain multiple score pairs and put them into a priority queue. Then select the pair with the smallest score from it, merge these two output devices into a target cluster, and then obtain the corresponding cluster control parameters according to the timing criticality of this target cluster. When it is determined that this target cluster is a suitable group, continue to calculate the minimum clustering scores of this target cluster and other clusters or output devices, and select the pair with the smallest score in the priority queue again to merge the clusters or output devices until the cluster size or cluster radius of the merged target cluster exceeds the corresponding cluster control parameters and then end the merge operation. This target cluster is taken as a group. This clustering algorithm will be introduced in detail in the subsequent Figure 4 There will be a detailed introduction.

[0095] In step S207, multiple copies are replicated based on the driving device and the multiple copies are assigned to multiple clusters as the driving devices therein.

[0096] In this step, in order to avoid increasing the logic levels of the timing path, multiple copies are replicated based on the driver of the wire network, and the replicated copies have the same input signals and logic functions as the original driving device. Then modify the connection of the output wire ends corresponding to the replicated driving devices to drive the output devices in each cluster.

[0097] In step S208, call the incremental placement algorithm to adjust the placement positions of the multiple copies and re-place the wire network.

[0098] In this step, an incremental placement algorithm is called to select the initial placement positions of the replicated driving devices according to the placement density map. The incremental placement algorithm uses the center position of the cluster as the reference position, and the area between the reference position and the driving devices of the high-fanout nets as the search range. Starting from the reference position, it searches for positions with a placement density lower than a given threshold to place the replicated driving devices. Finally, after all the optimizations of the high-fanout nets are completed, the placement positions of all the newly generated devices are further optimized according to the incremental placement algorithm.

[0099] The method for optimizing high-fanout nets based on placement in the FPGA integrated circuit optimized in this embodiment splits the high-fanout nets based on the placement positions and timing criticalities of the output devices of the nets during the process of optimizing the existing net placement. Since the timing criticalities of the nets are defined and the cluster control parameters for optimizing the high-fanout nets are set according to the timing criticalities, it is more convenient to merge the output devices with comparable timing transmission performance into the same cluster, reducing the control pressure and avoiding the problem of increasing the clustering cost due to excessive timing differences between the output devices caused by directly using the timing margins for grouping. In addition, by using the Best-Choice clustering algorithm to divide the output devices of the high-fanout nets into several clusters based on the placement positions and timing criticalities, the scale and radius of the clusters can be flexibly controlled adaptively, without the need for multiple iterative convergences, and the algorithm is fast.

[0100] Figure 3 The overall flowchart of the method for optimizing high-fanout nets based on placement in the FPGA integrated circuit according to an embodiment of the present invention is shown.

[0101] As Figure 3 shown, the method for optimizing high-fanout nets based on placement in the FPGA integrated circuit of this embodiment mainly includes steps S301 - S307, which is mainly a method for analyzing and placing all the nets on the FPGA integrated circuit and is an embodiment of the placement method in practical applications.

[0102] In step S301, timing analysis.

[0103] In this step, timing analysis is performed on all the nets of the FPGA integrated circuit respectively to obtain the timing margins and timing criticalities of all the sink terminals of each net, and then multiple different cluster control parameters are set for each net according to the timing criticality. The specific steps can refer to the embodiments of Figure 1 and Figure 2 this invention.

[0104] In step S302, it is judged whether there are high-fanout nets that need to be split. If so, steps S303 - S304 are executed; otherwise, step S305 is executed.

[0105] In this step, based on the timing analysis results obtained in step S301, each net is analyzed one by one. All the nets are traversed in sequence. For each net, the upper limit of the scale of the net is obtained according to the timing criticality of the net and the above cluster control parameters. If the number of output devices of the net is greater than the upper limit, the net is split and optimized. In this step, all the nets of the integrated circuit are analyzed, and each is analyzed one by one. If there are high fan-out nets that need to be split, steps S303 - S304 are executed to split the nets.

[0106] In step S303, Best-Choice clustering grouping is performed.

[0107] In this step, the high fan-out nets that need to be split are clustered and grouped.

[0108] In step S304, the net is split and the driver is copied.

[0109] In this step, multiple output devices of the net are split into multiple clusters according to the grouping result, and then the driver devices are copied and assigned to each cluster. After step S304 is executed, step S302 is returned to execute, forming a loop. This loop is because the FPGA integrated circuit contains multiple nets, and each clustering grouping is a layout adjustment for one of the nets, so it is necessary to judge one by one whether multiple nets need to be split. Through the judgment in step S302, all the high fan-out nets that need to be split on the integrated circuit can be selected, and each is clustered and grouped and the net is split until there are no nets that need to be split on the integrated circuit. At this time, step S305 is executed.

[0110] In step S305, it is judged whether the number of split high fan-out nets is greater than 0. When the number of split nets is greater than 0, step S306 is executed; otherwise, step S307 is executed.

[0111] In step S306, the layout is incremented.

[0112] Through the judgment in step S305, when the number of split high fan-out nets is greater than 0, that is, when there are nets that have been split, the incremental layout algorithm is called to optimize the layout of the nets.

[0113] In step S307, the process ends.

[0114] Through the judgment in step S305, when the number of split high fan-out nets is equal to 0, that is, when there are no nets that have been split, the process ends.

[0115] The layout-based high-fanout wire network optimization method for the FPGA integrated circuit in this embodiment is a wiring optimization for the entire integrated circuit. It comprehensively adjusts the grouping of output devices based on the timing criticality and cluster control parameters, thereby optimizing the wiring layout and improving the optimization efficiency of the wire network.

[0116] Figure 4 FIG. shows a schematic flowchart of the clustering algorithm in the FPGA integrated circuit according to an embodiment of the present invention, which specifically includes the following steps.

[0117] The layout-based high-fanout wire network optimization method for the FPGA integrated circuit in this embodiment adopts the Best-Choice clustering algorithm. The algorithm is fast and can flexibly control the number of devices in the cluster and the maximum distance between devices in the cluster according to the timing criticality of the devices in the cluster. Specifically:

[0118] In step S401, all output devices create a KD-Tree according to their positions.

[0119] When clustering and grouping all output devices of the high-fanout wire network, various factors need to be considered. For example, try to select output devices with similar layout positions to form a cluster and drive them with one driving device to reduce the total wiring length after splitting the wire network; the timing of the wire network is determined by the most timing-critical device in the wire network. Therefore, the timing-critical output devices and the non-timing-critical output devices should be separated into different clusters as much as possible to facilitate the subsequent processing of the timing-critical wire network; try to reduce the number of required groups to reduce the number of driving devices that need to be replicated, that is, reduce the increase in device area. This embodiment comprehensively considers these factors and proposes the Best-Choice clustering algorithm. First, in this step, a KD-Tree (k-dimensional tree) is created for each output device according to its position to establish the relationship between each output device from the spatial layout.

[0120] In step S402, the KD-Tree is used to calculate the minimum clustering score of each output device with other output devices and put it into the priority queue.

[0121] In this step, the clustering score of each target cluster (target output device) with other clusters (other output devices) is calculated according to the clustering formula and put into the priority queue. The clustering formula uses the distribution distance, the difference in timing criticality, and the cluster size of the output devices as positive control factors. Specifically, the calculation formula for the minimum clustering score of cluster u and cluster v in the algorithm is as follows:

[0122] s(u, v) = dist(u, v) * pow(α, Δ crit) * (size(u) + size(v)).

[0123] In the formula, dist(u, v) is the Manhattan distance between the central points of clusters u and v; Δcrit is the difference in the timing criticality between clusters u and v; α is a control parameter; size(u) and size(v) are the sizes of clusters u and v respectively. This clustering formula comprehensively considers the influences of layout position, the difference in timing criticality, and cluster size, that is, the smaller the minimum clustering score between two clusters with closer distance, smaller difference in timing criticality, and smaller cluster size.

[0124] Put the minimum clustering score corresponding to each pair of clusters into a priority queue. The initial number of output devices for each cluster is 1, and the number of output devices in the merged clusters will increase gradually later.

[0125] In step S403, determine whether the priority queue is non-empty. When the priority queue is non-empty, execute step S404; otherwise, the process ends.

[0126] In this step, when the priority queue is empty, it means that all clusters have been merged, indicating that the grouping is completed, and the process ends at this time; while when the priority queue is non-empty, the next step needs to be executed.

[0127] In step S404, take out the top cluster pair (u, v) from the priority queue.

[0128] In this step, take out the pair of clusters with the smallest clustering score, that is, the cluster pair at the top of the priority queue.

[0129] In step S405, determine whether the minimum clustering score of cluster u is valid. When the clustering score is valid, execute step S406; otherwise, execute step S409.

[0130] In this step, after taking out the pair of clusters with the smallest clustering score, determine whether the clustering score is valid. Only when the clustering score is valid does it mean that the two clusters can be merged; otherwise, the minimum clustering score needs to be recalculated. In this step, a delayed calculation method is adopted for the clustering score to improve the algorithm speed. It can tolerate invalid scores temporarily stored in the queue to reduce the real-time calculation amount. In addition, during the clustering process, if the cluster v corresponding to the minimum clustering score of cluster u has been merged with other clusters, the clustering score becomes invalid. The invalid minimum clustering score and the cluster pair (u, v) will only be recalculated when they are taken out at the top of the priority queue.

[0131] In step S406, merge cluster u = Merge(u, v).

[0132] In this step, merge the two cluster pairs taken out from the top of the priority queue and use them as a new cluster. After merging, the target cluster u is formed.

[0133] In step S407, it is determined whether cluster u meets the cluster control parameters. If it meets the cluster control parameters, step S409 is executed; otherwise, step S408 is executed.

[0134] In this step, when calculating the minimum clustering score of cluster u and the corresponding cluster v, the algorithm checks whether the scale and radius upper limits corresponding to the maximum timing criticality of clusters u and v are violated after the merger of clusters u and v. It is determined whether the scale and radius of the merged cluster meet the cluster control parameters. Only when they meet can the minimum clustering score be calculated again for further merging; otherwise, further calculation and merging cannot be continued.

[0135] In step S408, the grouping ends. In this step, since it has been determined that cluster u does not meet the cluster control parameters, it may be that the cluster scale or cluster radius of cluster u has reached the corresponding upper limit. At this time, the grouping ends, and cluster u is output as a group. Subsequently, multiple output devices of the netlist are divided based on this group (all output devices in cluster u are taken as a group).

[0136] In step S409, the minimum clustering score of cluster u and the corresponding cluster v are recalculated and placed in the priority queue.

[0137] In this step, the target cluster u is already the merged cluster. The minimum clustering score of this cluster u is recalculated and placed in the priority queue. Then, it returns to execute step S403 to determine whether the new priority queue is empty, and starts the loop of subsequent steps, so as to cluster each output device to form multiple clusters (groups).

[0138] In this embodiment, the layout-based high fan-out netlist optimization method for FPGA integrated circuits is further optimized. The Best-Choice clustering strategy is adopted, and the output devices of the high fan-out netlist are divided into several clusters based on the layout position and timing criticality. During the clustering process, according to the cluster timing criticality, the scale and radius of the cluster are adaptively and flexibly controlled; there is no need for multiple iterative convergences, and the algorithm is fast.

[0139] Figure 5 The structure diagram of a layout-based high fan-out netlist optimization system for FPGA integrated circuits according to an embodiment of the present invention is shown.

[0140] As Figure 5 shown, the layout-based high fan-out netlist optimization system 500 for FPGA integrated circuits includes a timing analysis unit 501, a timing criticality calculation unit 502, a marking unit 503, a control parameter setting unit 504, a judgment unit 505, a clustering and grouping unit 506, an allocation unit 507, and a layout unit 508. The FPGA integrated circuit includes multiple netlists, and each netlist includes multiple connection lines connected between a driving device and multiple output devices.

[0141] The timing analysis unit 501 is used to perform timing analysis on the wire network to obtain the timing margin of the output end of each connection line. The timing margin is the difference between the set transmission time and the actual transmission time. The timing criticality calculation unit 502 is used to sort all the connection lines in ascending order of the timing margin, and calculate the timing criticality of the output end of each connection line according to the sorting result. The marking unit 503 is used to mark the timing criticality at the output ends of multiple connection lines respectively. The timing criticality characterizes the timing transmission performance on the corresponding connection line. The control parameter setting unit 504 is used to set cluster control parameters for each cluster corresponding to the timing criticality. The judgment unit 505 is used to obtain the timing criticality of the wire network according to the multiple timing criticalities of multiple connection lines, and judge whether the wire network is a high fan-out wire network that needs to be split according to the cluster control parameters. The clustering and grouping unit 506 is used to use the clustering algorithm to split multiple output devices into multiple clusters for the high fan-out wire network that needs to be split according to the cluster control parameters. The allocation unit 507 is used to replicate multiple copies based on the driving device and allocate the multiple copies to multiple clusters as the driving devices therein. The layout unit 508 is used to call the incremental layout algorithm to adjust the layout positions of the multiple copies and re-layout the wire network. The cluster control parameters include the cluster size and the cluster radius. The cluster size is the number of the output devices included in the cluster, and the cluster radius is the maximum distance between the output device and the cluster center point.

[0142] In this embodiment, the high fan-out wire network optimization system 500 based on the layout of the FPGA integrated circuit obtains the timing margin of the output end of each connection line and the corresponding set timing criticality through the timing analysis unit 501, the timing criticality calculation unit 502, and the marking unit 503. Then, the control parameter setting unit 504 sets the cluster control parameters corresponding to each cluster according to the timing criticality, so as to provide control parameters when the clustering and grouping unit 506 groups the output devices. The clusters divided according to the control parameters have high compactness, small differences in the timing criticality of the output devices, close positions, appropriate cluster sizes, reasonable layouts of the entire grouping, simplified wire network distribution, accurate and efficient algorithms, and can complete wiring accurately and concisely. Further optimizing the positions of the driving devices through the layout unit 508 can make the distribution of the wire network more reasonable, reduce the area, and improve the transmission speed between the devices.

[0143] Furthermore, the present invention provides a wiring device for an FPGA integrated circuit, which includes a processor, a memory, and an input / output device connected through a bus. The memory includes a read-only memory (ROM) and a random access memory (RAM). Various computer instructions and data required for executing system functions are stored in the memory. The processor reads various computer instructions from the memory to perform various appropriate actions and processes. The input / output device includes an input part such as a keyboard and a mouse; an output part including a cathode ray tube (CRT), a liquid crystal display (LCD), etc. and a speaker; a storage part including a hard disk, etc.; and a communication part including a network interface card such as a LAN card and a modem. The memory also stores the following computer instructions to complete the operations specified by the layout-based high-fan-out wire network optimization method for the FPGA integrated circuit of the embodiment of the present invention: respectively mark the timing criticality for the output end of each connection line, and the timing criticality characterizes the timing transmission performance on the connection line; respectively set cluster control parameters according to multiple timing criticalities; determine whether a wire network is a high-fan-out wire network that needs to be split according to the timing criticality of the wire network and the corresponding cluster control parameters; for the high-fan-out wire network that needs to be split, use a clustering algorithm to group according to the cluster control parameters, and split multiple output devices into multiple clusters; copy the driving device and assign one driving device to each cluster.

[0144] Correspondingly, an embodiment of the present invention provides a computer-readable storage medium, which stores computer instructions, and when the computer instructions are executed, the operations specified by the above-mentioned layout-based high-fan-out wire network optimization method for the FPGA integrated circuit are implemented.

[0145] It can be understood that the flowcharts and block diagrams in the drawings illustrate the possible system frameworks, functions, and operations of the systems and methods of the embodiments of the present invention. The blocks in the flowcharts and block diagrams may represent a module, a program segment, or just a piece of code, and the module, program segment, and code are all executable instructions for implementing the specified logical functions. The blocks in the drawings and the order of the blocks are only used to better illustrate the processes and steps of the embodiments, and should not be used as a limitation to the invention itself.

[0146] Each module or unit of the system can be implemented by hardware, firmware, or software. Software includes, for example, coding programs formed by various programming languages such as JAVA, C / C++ / C#, and SQL. Although the steps and the order of the steps are given in the method and the method illustration of the embodiment of the present invention, the executable instructions for implementing the specified logical functions of the steps can be recombined to generate new steps. The order of the steps should not be limited only to the order of the steps in the method and the method illustration, and can be adjusted at any time according to the needs of the function. For example, some of the steps can be executed in parallel or in the reverse order.

[0147] The above are only the preferred embodiments of the present invention and are not intended to limit the present invention. For those skilled in the art, the present invention may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included within the protection scope of the present invention.

Claims

1. A layout-based high-fanout net optimization method for FPGA integrated circuits, the FPGA integrated circuit including a plurality of nets, each net including a plurality of connection lines connected between a driving device and a plurality of output devices, wherein, For each net, the optimization method includes: Mark the timing criticality at the output ends of the multiple connecting lines respectively, where the timing criticality characterizes the timing transmission performance of the corresponding connecting line; Set cluster control parameters for each cluster corresponding to the timing criticality; Obtain the timing criticality of the net according to the multiple timing criticalities of the multiple connecting lines, and determine whether the net is a high fan-out net that needs to be split according to the cluster control parameters; For the high fan-out net that needs to be split, use the clustering algorithm to split the multiple output devices into multiple clusters according to the cluster control parameters; Based on the driving device, replicate multiple copies and allocate the multiple copies to the multiple clusters as the driving devices therein; Wherein, the cluster control parameters include the cluster scale and the cluster radius, the cluster scale is the number of the output devices included in the cluster, and the cluster radius is the maximum distance between the output device and the cluster center point.

2. The layout-based high-fanout wire network optimization method for FPGA integrated circuits according to claim 1, wherein, Before the step of marking the timing criticality at the output ends of the multiple connecting lines respectively, it further includes: Perform timing analysis on the net to obtain the timing margin at the output end of each connecting line, where the timing margin is the difference between the set transmission time and the actual transmission time; Sort all the connecting lines in ascending order of the timing margin, and calculate the timing criticality at the output end of each connecting line according to the sorting result.

3. The FPGA integrated circuit layout-based high-fanout wire network optimization method according to claim 2, wherein, The timing criticality is distributed in a stepped manner from large to small according to the sorting of the timing margin. The greater the timing criticality, the worse the timing transmission performance.

4. The FPGA integrated circuit layout-based high fan-out net optimization method according to claim 3, wherein The timing criticality at the output end of the connecting line ranked in the top 1% is 6; The timing criticality at the output end of the connecting line ranked from 1% to 5% is 5; The timing criticality at the output end of the connecting line ranked from 5% to 10% is 4; The timing criticality at the output end of the connecting line ranked from 10% to 20% is 3; The timing criticality at the output end of the connecting line ranked from 20% to 40% is 2; The timing criticality at the output end of the connecting line ranked after 40% is 1; The timing criticality at the output end of the connecting line without timing constraints is 0.

5. The layout-based high-fanout wire network optimization method for FPGA integrated circuits according to claim 1, wherein, After the step of replicating multiple copies based on the driving device and allocating the multiple copies to the multiple clusters as the driving devices therein, it further includes: Call the incremental placement algorithm to adjust the layout positions of the multiple copies and re-layout the net.

6. The method for optimizing high-fanout wire networks based on layout of FPGA integrated circuits according to claim 1, wherein, The timing criticality of the net is the maximum timing criticality among the multiple timing criticalities of the multiple connecting lines; The timing criticality of the cluster is the maximum timing criticality among the timing criticalities corresponding to all the connecting lines in the cluster.

7. The layout-based high-fanout wire network optimization method for FPGA integrated circuits according to claim 1, wherein, The step of obtaining the timing criticality of the net according to the multiple timing criticalities of the multiple connecting lines and determining whether the net is a high fan-out net that needs to be split according to the cluster control parameters includes: Obtain the maximum timing criticality among the multiple timing criticalities corresponding to the multiple connection lines in the wire network as the timing criticality of the wire network; Obtain the cluster control parameter corresponding to the timing criticality of the wire network; When the number of output devices and the cluster radius included in the wire network conform to the cluster control parameter, the wire network is a wire network that does not need to be split; When the number of output devices or the cluster radius included in the wire network is greater than the cluster control parameter, the wire network is a high fan-out wire network that needs to be split.

8. The method for optimizing high fan-out wire networks based on layout of FPGA integrated circuits according to claim 1, wherein, The upper limit of the cluster scale corresponding to the cluster with a timing criticality of 6 is 10, and the upper limit of the cluster radius is 10; The upper limit of the cluster scale corresponding to the cluster with a timing criticality of 5 is 20, and the upper limit of the cluster radius is 10; The upper limit of the cluster scale corresponding to the cluster with a timing criticality of 4 is 30, and the upper limit of the cluster radius is 10; The upper limit of the cluster scale corresponding to the cluster with a timing criticality of 3 is 50, and the upper limit of the cluster radius is 20; The upper limit of the cluster scale corresponding to the cluster with a timing criticality of 2 is 80, and the upper limit of the cluster radius is 30; The upper limit of the cluster scale corresponding to the cluster with a timing criticality of 1 is 120, and the upper limit of the cluster radius is 50; There are no restrictions on the cluster scale and the cluster radius corresponding to the cluster with a timing criticality of 0.

9. The FPGA integrated circuit layout-based high-fanout wire network optimization method according to claim 1, wherein, The steps of splitting multiple output devices into multiple clusters according to the cluster control parameter for the high fan-out wire network that needs to be split by using the clustering algorithm include: Calculate the clustering score of each target cluster and other clusters according to the clustering formula, and put it into the priority queue. Each cluster includes at least one output device, and the initial number of the output devices included in each cluster is 1; Take out the cluster pair with the smallest clustering score from the priority queue. When the clustering score is valid, merge all the output devices in the cluster pair into one target cluster; Judge whether the parameters of the merged target cluster conform to the cluster control parameter; For the target cluster whose parameters conform to the cluster control parameter, repeat the steps of calculating the clustering score of each target cluster and other clusters according to the clustering formula until judging whether the parameters of the merged target cluster conform to the cluster control parameter until the parameters do not conform to the cluster control parameter, and take the target cluster as a group.

10. The FPGA integrated circuit layout-based high-fanout wire network optimization method according to claim 9, wherein, The clustering formula uses the distribution distance of output devices, the difference in timing criticality, and the cluster scale as control factors.

11. A layout-based high-fanout net optimization system for FPGA integrated circuits, the FPGA integrated circuit comprising a plurality of nets, each net including a plurality of connecting lines connected between a driving device and a plurality of output devices, wherein, The optimization system includes: A timing analysis unit for performing timing analysis on the wire network to obtain the timing margin of the output end of each connection line, where the timing margin is the difference between the set transmission time and the actual transmission time; A timing criticality calculation unit for sorting all the connection lines in ascending order of the timing margin, and calculating the timing criticality of the output end of each connection line according to the sorting result; A marking unit for respectively marking the timing criticality at the output ends of the multiple connection lines, where the timing criticality characterizes the timing transmission performance on the corresponding connection lines; A control parameter setting unit for respectively setting cluster control parameters for each cluster corresponding to the timing criticality; A judgment unit for obtaining the timing criticality of the net according to the multiple timing criticalities of the multiple connection lines, and judging whether the net is a high fan-out net to be split according to the cluster control parameters; A clustering and grouping unit for splitting the multiple output devices into multiple clusters for the high fan-out net to be split by using a clustering algorithm according to the cluster control parameters; An allocation unit for replicating multiple copies based on the driving device and allocating the multiple copies to the multiple clusters as the driving devices therein; A layout unit for calling an incremental layout algorithm to adjust the layout positions of the multiple copies and re-layout the net, wherein the cluster control parameters include a cluster scale and a cluster radius, the cluster scale is the number of the output devices included in the cluster, and the cluster radius is the maximum distance between the output device and the cluster center point.

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