Electronic device and method of manufacturing the same

Abstract

An electronic device and a method of manufacturing the same are provided. The electronic device includes a display panel including a display area and an electronic module, the display area including a first display area and a second display area having a transmittance higher than that of the first display area, the electronic module being under the second display area of the display panel, wherein the display panel includes a base layer, a plurality of first pixel electrodes on the base layer and in the first display area, a plurality of second pixel electrodes on the base layer and in the second display area, a common electrode on the plurality of first pixel electrodes and the plurality of second pixel electrodes, and a plurality of openings being defined in the common electrode, and a barrier pattern spaced apart from the common electrode and having a plurality of transmission portions overlapping the plurality of openings, and the plurality of second pixel electrodes being interposed between the barrier pattern and the common electrode.

Description

[0001] This application claims priority to and the benefit of Korean Patent Application No. 10-2020-0090310, filed on July 21, 2020, in the Korean Intellectual Property Office, the entire contents of which are incorporated herein by reference. TECHNICAL FIELD

[0002] Aspects of some embodiments of the disclosure relate to an electronic device and a method for manufacturing an electronic device. BACKGROUND

[0003] An electronic device can be a device having various electronic components such as a display panel and an electronic module. The electronic module can include a camera, an infrared sensing sensor, a proximity sensor, etc. The electronic module can be located under the display panel. The transmittance of some areas of the display panel can be higher than the transmittance of other areas of the display panel. The electronic module can receive an external input through some areas of the display panel, or can provide an output through some areas of the display panel.

[0004] The above information disclosed in this Background section is only for enhancing the understanding of the background of the disclosure, therefore, it can not necessarily be construed as the prior art that is already known to those skilled in the art. SUMMARY

[0005] Aspects of some embodiments of the disclosure relate to an electronic device and a method for manufacturing an electronic device. According to some embodiments, the electronic device can have a display panel with relatively improved transmittance of some areas.

[0006] Aspects of some embodiments of the disclosure include an electronic device having a display panel with improved transmittance of some areas.

[0007] Aspects of some embodiments of the disclosure further include a method for manufacturing an electronic device having a display panel with relatively improved transmittance of some areas.

[0008] According to some embodiments of the inventive concept, an electronic device includes a display panel including a display area, the display area including a first display area and a second display area, the second display area having a transmittance higher than that of the first display area; and an electronic module under the second display area of the display panel. According to some embodiments, the display panel can include a base layer; a plurality of first pixel electrodes on the base layer and in the first display area; a plurality of second pixel electrodes on the base layer and in the second display area; a common electrode on the plurality of first pixel electrodes and the plurality of second pixel electrodes, and a plurality of openings defined in the common electrode; and a barrier pattern spaced apart from the common electrode with the plurality of second pixel electrodes interposed therebetween, and a plurality of transmissive portions defined in the barrier pattern superposed with the plurality of openings.

[0009] According to some embodiments, the display panel can further include a plurality of first pixel circuits electrically connected to the plurality of first pixel electrodes, respectively; and a plurality of second pixel circuits electrically connected to the plurality of second pixel electrodes, respectively, wherein each of the plurality of first pixel circuits and the plurality of second pixel circuits can include a transistor including a gate, an active region, a source, and a drain; and a capacitor including a first electrode electrically connected to the transistor and a second electrode facing the first electrode.

[0010] According to some embodiments, the barrier pattern can include a first barrier pattern and a second barrier pattern on the first barrier pattern, wherein the first barrier pattern can be on the same layer as the gate and include the same material as that of the gate, and the second barrier pattern can be on the same layer as the second electrode and include the same material as that of the second electrode.

[0011] According to some embodiments, the barrier pattern can further include a third barrier pattern under the first barrier pattern.

[0012] According to some embodiments, the display panel can further include a barrier layer on the base layer and a buffer layer on the barrier layer, wherein the barrier layer can include a first sub-barrier layer on the base layer and a second sub-barrier layer on the first sub-barrier layer, and the third barrier pattern can be between the barrier layer and the buffer layer, or can be between the first sub-barrier layer and the second sub-barrier layer.

[0013] According to some embodiments, a plurality of first transmissive portions, a plurality of second transmissive portions, and a plurality of third transmissive portions can be defined in the first barrier pattern, the second barrier pattern, and the third barrier pattern, respectively, superposed with the plurality of openings of the common electrode.

[0014] According to some embodiments, the barrier pattern can be on the same layer as the gate or the second electrode, and can include the same material as that of the gate or the second electrode.

[0015] According to some embodiments, the display panel can further include a peripheral area adjacent to the display area. The plurality of first pixel circuits can be in the first display area, and the plurality of second pixel circuits can be in the peripheral area.

[0016] According to some embodiments, the display panel can further include a plurality of connection lines electrically connecting the plurality of second pixel electrodes and the plurality of second pixel circuits, respectively, and each of the plurality of connection lines can include a transparent conductive material.

[0017] According to some embodiments, the display area can further include a third display area defined between the first display area and the second display area, and the plurality of second pixel circuits can be in the third display area.

[0018] According to some embodiments, the display panel can further include a plurality of third pixel electrodes on the base layer and in the third display area, and a plurality of third pixel circuits in the third display area and electrically connected to the plurality of third pixel electrodes, respectively, wherein a number of the first pixel electrodes in the first area among the plurality of first pixel electrodes can be greater than each of a number of the second pixel electrodes in a second area having a same size as a size of the first area among the plurality of second pixel electrodes and a number of the third pixel electrodes in a third area having a same size as the size of the first area among the plurality of third pixel electrodes.

[0019] According to some embodiments, the plurality of openings and the plurality of transmissive portions can be defined in the second display area.

[0020] According to some embodiments, the plurality of transmissive portions and the plurality of openings can be spaced apart from the plurality of second pixel electrodes when viewed in a thickness direction of the display panel.

[0021] According to some embodiments of the inventive concept, an electronic device includes a display panel in which a display area is defined, and an electronic module under the display area of the display panel, wherein the display panel includes a light emitting element including a pixel electrode in the display area, a light emitting layer on the pixel electrode, and a common electrode on the light emitting layer, a barrier pattern under the light emitting element, and in which a transmissive portion is defined in a region spaced apart from the pixel electrode when viewed in a thickness direction of the display panel, a pixel circuit spaced apart from the pixel electrode and electrically connected to the light emitting element, and a connection line electrically connecting the pixel circuit and the pixel electrode and including a transparent conductive material, wherein a portion of the common electrode overlapping the transmissive portion can be removed when viewed in the thickness direction of the display panel.

[0022] According to some embodiments, the display panel can further include a peripheral area adjacent to the display area. The pixel circuit can be in the peripheral area.

[0023] According to some embodiments, the pixel circuit can include a transistor including a gate, an active region, a source, and a drain, and a capacitor including a first electrode electrically connected to the transistor and a second electrode facing the first electrode, and the barrier pattern can include a first barrier pattern and a second barrier pattern on the first barrier pattern, wherein the first barrier pattern can be on the same layer as the gate and can include the same material as a material of the gate, and the second barrier pattern can be on the same layer as the second electrode and can include the same material as a material of the second electrode.

[0024] According to some embodiments of the inventive concept, a method for manufacturing an electronic device includes the steps of: providing a base layer; providing a circuit layer on the base layer, the circuit layer including a barrier pattern in which a transmission part is defined; providing a light emitting element including a pixel electrode on the circuit layer, a light emitting layer on the pixel electrode, and a common electrode on the light emitting layer; and removing a portion of the common electrode overlapping the transmission part by irradiating laser in a direction from the base layer toward the common electrode.

[0025] According to some embodiments, the step of providing the circuit layer can further include providing a transistor including a gate, an active region, a source, and a drain, and providing a capacitor including a first electrode electrically connected to the transistor and a second electrode facing the first electrode, wherein the pixel electrode can be spaced apart from the transistor.

[0026] According to some embodiments, the step of providing the circuit layer including the barrier pattern can include a step of providing a first barrier pattern and a step of providing a second barrier pattern on the first barrier pattern, wherein the first barrier pattern can be provided in the same process as the gate, and the second barrier pattern can be provided in the same process as the second electrode.

[0027] According to some embodiments, the step of providing the circuit layer can further include a step of providing a connection line electrically connecting the transistor and the pixel electrode, wherein the connection line can include a transparent conductive material. BRIEF DESCRIPTION OF DRAWINGS

[0028] The accompanying drawings are included to provide a further understanding of the inventive concept, and are incorporated in and constitute a part of this specification. The drawings illustrate aspects of some embodiments of the inventive concept and, together with the description, serve to explain principles of the inventive concept. In the drawings:

[0029] FIG. 1 is a perspective view of an electronic device according to some embodiments of the inventive concept;

[0030] FIG. 2 is an exploded perspective view of some components of an electronic device according to some embodiments of the inventive concept;

[0031] FIG. 3Ais a sectional view of a display panel according to some embodiments of the inventive concept;

[0032] FIG. 3B is a sectional view of a display panel according to some embodiments of the inventive concept;

[0033] FIG. 3C is a sectional view of a display panel according to some embodiments of the inventive concept;

[0034] FIG. 4 is a plan view of a display panel according to some embodiments of the inventive concept;

[0035] FIG. 5 is an equivalent circuit diagram of a pixel according to some embodiments of the inventive concept;

[0036] FIG. 6 is a sectional view of a display layer according to some embodiments of the inventive concept;

[0037] FIG. 7 is a plan view showing an enlarged view of the area AA' of FIG. 4 ;

[0038] FIG. 8 is a sectional view taken along the line I-I' shown in FIG. 7 ;

[0039] FIG. 9 is a sectional view of a display layer according to some embodiments of the inventive concept;

[0040] FIG. 10A is a plan view showing some enlarged components of a display layer according to some embodiments of the inventive concept;

[0041] FIG. 10B is a plan view showing some enlarged components of a display layer according to some embodiments of the inventive concept;

[0042] FIG. 10C is a plan view showing some enlarged components of a display layer according to some embodiments of the inventive concept;

[0043] FIG. 10D is a plan view showing some enlarged components of a display layer according to some embodiments of the inventive concept;

[0044] FIG. 11A is a sectional view of a display layer according to some embodiments of the inventive concept;

[0045] FIG. 11B is a sectional view of a display layer according to some embodiments of the inventive concept;

[0046] FIG. 11C is a sectional view of a display layer according to some embodiments of the inventive concept;

[0047] FIG. 11D is a cross-sectional view of a display layer according to some embodiments of the inventive concept;

[0048] FIG. 12 is a plan view of a display panel according to some embodiments of the inventive concept;

[0049] FIG. 13 is a plan view of an enlarged view of the area BB' of FIG. 12

[0050] FIG. 14 is a cross-sectional view taken along the line III-III' shown in FIG. 13

[0051] FIG. 15A FIG. 15B FIG. 15C are diagrams for describing a method for manufacturing an electronic device according to some embodiments of the inventive concept. DETAILED DESCRIPTION

[0052] In the present disclosure, when an element (or region, layer, part, etc.) is referred to as being “on” another element, “connected to” or “joined to” another element, it can be directly located / connected / joined to the other element or a third element can be located therebetween.

[0053] The same reference numerals refer to the same elements throughout the specification. Also, in the drawings, the thickness, proportions, and dimensions of elements can be exaggerated for effective description of the technical content.

[0054] The term “and / or” includes all combinations of one or more of the associated terms.

[0055] It will be understood that, although the terms “first,” “second,” etc. can be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, a first element could be termed a second element, and, similarly, a second element could be termed a first element, without departing from the scope of example embodiments of the inventive concept. The singular forms “a,” “an,” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise.

[0056] In addition, terms such as “below,” “under,” “above,” “over,” and the like, are used herein to describe relationships of elements in the drawings. These terms are used as relative concepts and are described with reference to the directions indicated in the drawings.

[0057] ​​​​Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the inventive concept belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

[0058] It will be understood that the terms "comprises" or "has" are intended to denote the presence of stated features, integers, steps, operations, elements, components, or combinations thereof, but does not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, or combinations thereof.

[0059] Hereinafter, aspects of some embodiments of the inventive concept will be described in more detail with reference to the accompanying drawings.

[0060] FIG. 1 is a perspective view of an electronic device according to some embodiments of the inventive concept.

[0061] Referring to FIG. 1 , the electronic device 1000 can be a device activated according to an electrical signal. For example, the electronic device 1000 can be a mobile phone, a tablet computer, a car navigation system, a game console, or a wearable device, but embodiments of the inventive concept are not limited thereto. In FIG. 1 , the electronic device 1000 is illustrated as a mobile phone as an example, but embodiments are not limited thereto, and the electronic device 1000 can include any other suitable electronic device.

[0062] The electronic device 1000 can display an image through a display area 1000A. The display area 1000A can include a plane (e.g., a display surface or a main display surface) defined by a first direction DR1 and a second direction DR2. The display area 1000A can further include curved surfaces curved from at least two edges of the plane, respectively. However, the shape of the display area 1000A is not limited thereto. For example, the display area 1000A can include only a plane, and the display area 1000A can further include four curved surfaces curved from at least two edges (e.g., four edges) of the plane, respectively.

[0063] In the display area 1000A of the electronic device 1000, a sensing area 1000SA can be defined. FIG. 1 An example of one sensing area 1000SA is illustrated, but the number of sensing areas 1000SA is not limited thereto. The sensing area 1000SA can be a part of the display area 1000A. Accordingly, the electronic device 1000 can display an image through the sensing area 1000SA.

[0064] In a region overlapping the sensing area 1000SA, an electronic module, such as a camera module, a proximity illuminance sensor, or the like, can be disposed. The electronic module can receive an external input transmitted through the sensing area 1000SA, or can provide an output through the sensing area 1000SA.

[0065] A thickness direction of the electronic device 1000 can be parallel to a third direction DR3 crossing the first direction DR1 and the second direction DR2. Accordingly, a front surface (or an upper surface) and a rear surface (or a lower surface) of components constituting the electronic device 1000 can be defined based on the third direction DR3.

[0066] FIG. 2 is an exploded perspective view of some components of an electronic device according to some embodiments of the inventive concept.

[0067] Referring to FIG. 2 , the electronic device 1000 can include a display panel 100 and an electronic module 200. The display panel 100 can be a component configured to generate an image and sense an input (e.g., a touch input) applied from the outside. The electronic module 200 is located below the display panel 100 and can be, for example, a camera module.

[0068] In the display panel 100, a display area 100A and a peripheral area 100N can be defined. The display area 100A can correspond to the display area 1000A shown in FIG. 1 . Some regions of the display panel 100 can have a higher transmittance than other regions of the display panel 100. For example, a sensing area 100SA of the display panel 100 can have a higher transmittance than other portions of the display area 100A around the sensing area 100SA. The sensing area 100SA can be a portion of the display area 100A. That is, the sensing area 100SA displays an image and can transmit an external input received by the electronic module 200 or an output from the electronic module 200.

[0069] FIG. 3A is a cross-sectional view of a display panel according to some embodiments of the inventive concept.

[0070] Referring to FIG. 3A , the display panel 100 can include a display layer 110, a sensor layer 120, an anti-reflection layer 130, and an optical layer 140.

[0071] The display layer 110 can be a component that generates an image. The display layer 110 can be a light-emitting type display layer. For example, the display layer 110 can be an organic light-emitting display layer, a quantum dot display layer, or a micro-LED display layer.

[0072] The display layer 110 can include a base layer 111, a circuit layer 112, a light emitting element layer 113, and an encapsulation layer 114.

[0073] The base layer 111 can be a member that provides a base surface on which the circuit layer 112 is positioned. The base layer 111 can be a glass substrate, a metal substrate, or a polymer substrate. However, embodiments of the inventive concept are not limited thereto, and the base layer 111 can be an inorganic layer, an organic layer, or a composite material layer.

[0074] The base layer 111 can have a multi-layer structure. For example, the base layer 111 can include a first synthetic resin layer, a silicon oxide (SiO x ) layer positioned on the first synthetic resin layer, an amorphous silicon (a-Si) layer positioned on the silicon oxide layer, and a second synthetic resin layer positioned on the amorphous silicon layer. The silicon oxide layer and the amorphous silicon layer can be referred to as a base barrier layer.

[0075] Each of the first synthetic resin layer and the second synthetic resin layer can include a polyimide-based resin. In addition, each of the first synthetic resin layer and the second synthetic resin layer can include at least one of an acrylate-based resin, a methacrylate-based resin, a polyisoprene-based resin, a vinyl-based resin, an epoxy-based resin, a polyurethane-based resin, a cellulose-based resin, a siloxane-based resin, a polyamide-based resin, and a perylene-based resin. Meanwhile, in the present disclosure, the "~~" based resin refers to a functional group including "~~".

[0076] The circuit layer 112 can be positioned on the base layer 111. The circuit layer 112 can include an insulating layer, a semiconductor pattern, a conductive pattern, a signal line, etc. The insulating layer, the semiconductor layer, and the conductive layer are formed on the base layer 111 by coating, deposition, etc., after which the insulating layer, the semiconductor layer, and the conductive layer can be selectively patterned by performing a photolithography process multiple times. Thereafter, the semiconductor pattern, the conductive pattern, and the signal line, all of which are included in the circuit layer 112, can be formed.

[0077] The light emitting element layer 113 can be positioned on the circuit layer 112. The light emitting element layer 113 can include a light emitting element. For example, the light emitting element layer 113 can include an organic light emitting material, a quantum dot, a quantum rod, or a micro LED.

[0078] The encapsulation layer 114 can be positioned on the light emitting element layer 113. The encapsulation layer 114 can protect the light emitting element layer 113 from foreign substances such as moisture, oxygen, and dust particles.

[0079] The sensor layer 120 can be positioned on the display layer 110. The sensor layer 120 can sense an external input applied from the outside. The external input can be a user input. The user input includes various forms of external input such as a part of a user's body, light, heat, a pen, and pressure.

[0080] The sensor layer 120 can be formed on the display layer 110 through a series of processes. In this case, the sensor layer 120 can be denoted as being directly on the display layer 110. Directly on can mean that a third component is not located between the sensor layer 120 and the display layer 110. That is, according to some embodiments, a separate adhesive member can not be located between the sensor layer 120 and the display layer 110.

[0081] Optionally, the sensor layer 120 and the display layer 110 can be combined with each other through an adhesive member. The adhesive member can include a typical adhesive or a pressure sensitive adhesive.

[0082] The anti-reflection layer 130 can be located on the sensor layer 120. The anti-reflection layer 130 can reduce the reflectance of external light incident from the outside of the display panel 100. The anti-reflection layer 130 can be formed on the sensor layer 120 through a series of processes. The anti-reflection layer 130 can include a color filter. The color filter can have a certain arrangement (e.g., a set or predetermined arrangement). For example, the color filter can be arranged in consideration of the light emission color of the pixels included in the display layer 110. In addition, the anti-reflection layer 130 can further include a black matrix adjacent to the color filter.

[0083] The optical layer 140 can be located on the anti-reflection layer 130. The optical layer 140 can be formed on the anti-reflection layer 130 through a series of processes. The optical layer 140 can improve the front surface brightness of the display panel 100 by controlling the direction of light incident from the display layer 110. For example, the optical layer 140 can include an organic insulating layer in which openings corresponding to light emission areas of the pixels included in the display layer 110 are defined, and a high refractive layer covering the organic insulating layer and filled in the openings. The high refractive layer can have a refractive index higher than that of the organic insulating layer.

[0084] The organic insulating layer can include at least one of an acrylate-based resin, a methacrylate-based resin, a polyisoprene, a vinyl-based resin, an epoxy-based resin, a polyurethane-based resin, a cellulose-based resin, a siloxane-based resin, a polyimide-based resin, a polyamide-based resin, and a perylene-based resin. The high refractive layer can include a siloxane-based resin. In addition to the siloxane-based resin, the high refractive layer can include at least one of zirconium oxide particles, aluminum oxide particles, and titanium oxide particles.

[0085] Light emitted from the pixels can be provided to the optical layer 140. According to the difference in refractive index between the high refractive layer and the organic insulating layer, the light can be reflected from the side surface of the organic insulating layer in which the openings are defined. The light can be reflected from the side surface of the organic insulating layer in which the openings are defined, so that the moving direction of the light can be controlled, and thus, the front surface brightness of the display panel 100 can be improved.

[0086] According to some embodiments of the inventive concept, at least one of the anti-reflection layer 130 and the optical layer 140 can be omitted. In addition, the structural relationship can be changed differently from the structural relationship shown in FIG. 1A. FIG. 3A For example, the optical layer 140 can be disposed by being included in the sensor layer 120, and in addition, the anti-reflection layer 130 can be disposed by being included in the sensor layer 120. In this case, the function of the anti-reflection layer 130 or the optical layer 140 can be implemented by using an insulating layer constituting the sensor layer 120.

[0087] FIG. 3B is a cross-sectional view of a display panel according to some embodiments of the inventive concept.

[0088] Referring to FIG. 3B , the display panel 100_1 can include a display layer 110, a sensor layer 120, an optical layer 140_1, and an anti-reflection layer 130_1. When comparing FIG. 3B the display panel 100_1 and FIG. 3A the display panel 100, there is a difference in the stacking order of the optical layer 140_1 and the anti-reflection layer 130_1.

[0089] The optical layer 140_1 can be located on the sensor layer 120. The optical layer 140_1 can be formed on the sensor layer 120 through a series of processes. The optical layer 140_1 can improve the front surface luminance of the display panel 100_1 by controlling the direction of light incident from the display layer 110.

[0090] The anti-reflection layer 130_1 can be located on the optical layer 140_1. The anti-reflection layer 130_1 can reduce the reflectance of external light incident from the outside of the display panel 100_1. The anti-reflection layer 130_1 can include a polarizing film, and the polarizing film can include a phase retarder and / or a polarizer. According to some embodiments, the anti-reflection layer 130_1 can be bonded to the optical layer 140_1 through an adhesive layer. The adhesive layer can be a transparent adhesive layer such as a pressure sensitive adhesive film (PSA), an optically clear adhesive film (OCA), or an optically clear resin (OCR).

[0091] According to some embodiments of the inventive concept, at least one of the anti-reflection layer 130_1 and the optical layer 140_1 can be omitted. Alternatively, the optical layer 140_1 can be disposed by being included in the sensor layer 120. In this case, a layer implementing the function of the optical layer 140_1 can be disposed by using an insulating layer constituting the sensor layer 120.

[0092] FIG. 3C is a cross-sectional view of a display panel according to some embodiments of the inventive concept.

[0093] Referring to FIG. 3CThe display panel 100_2 can include a display layer 110_1 and a sensor layer 120_1. The display layer 110_1 can include a base substrate 111_1, a circuit layer 112_1, a light emitting element layer 113_1, an encapsulation substrate 114_1, and a bonding member 115_1.

[0094] Each of the base substrate 111_1 and the encapsulation substrate 114_1 can be a glass substrate, a metal substrate, a polymer substrate, or the like, but embodiments of the inventive concept are not particularly limited thereto.

[0095] The bonding member 115_1 can be located between the base substrate 111_1 and the encapsulation substrate 114_1. The bonding member 115_1 can bond the encapsulation substrate 114_1 to the base substrate 111_1 or the circuit layer 112_1. The bonding member 115_1 can include an inorganic material or an organic material. For example, the inorganic material can include a glass frit seal, and the organic material can include a photocurable resin or a photoplastic resin. However, the material constituting the bonding member 115_1 is not limited to the above examples.

[0096] The sensor layer 120_1 can be directly located on the encapsulation substrate 114_1. Directly located can mean that a third component is not located between the sensor layer 120_1 and the display layer 110_1. That is, a separate bonding member can not be located between the sensor layer 120_1 and the display layer 110_1. However, embodiments of the inventive concept are not limited thereto. An adhesive layer can also be located between the sensor layer 120_1 and the encapsulation substrate 114_1.

[0097] FIG. 4 is a plan view of a display panel according to some embodiments of the inventive concept.

[0098] Referring to FIG. 4 The display area 100A can include a first display area 100A1 and a second display area 100A2. The electronic module 200 can be located below the second display area 100A2. That is, a sensing area 100SA (see FIG. 2 ) can be included in the second display area 100A2.

[0099] In the display area 100A, a plurality of pixels PX (hereinafter, pixels) can be positioned. Each of the pixels PX can include a light emitting element and a pixel circuit electrically connected to the light emitting element. The pixels PX can include first pixels PX1 located in the first display area 100A1 and second pixels PX2 located in the second display area 100A2.

[0100] The transmittance of the first display area 100A1 and the transmittance of the second display area 100A2 can be different from each other. For example, the transmittance of the second display area 100A2 can be higher than the transmittance of the first display area 100A1.

[0101] In order to increase the transmittance of the second display region 100A2 to be higher than that of the first display region 100A1, at least some components located in the second display region 100A2 can be omitted, or can be moved to another region other than the second display region 100A2 and positioned therein.

[0102] The density of the second pixels PX2 located in the second display region 100A2 can be lower than the density of the first pixels PX1 located in the first display region 100A1. In this case, the resolution of the second display region 100A2 can be lower than that of the first display region 100A1, but the transmittance of the second display region 100A2 can be higher than that of the first display region 100A1.

[0103] The light emitting element of each of the second pixels PX2 can be located in the second display region 100A2, and the pixel circuit of each of the second pixels PX2 can be located in the peripheral region 100N. In this case, the transmittance of the second display region 100A2 can be further improved compared to the transmittance of the second display region 100A2 in the case where the pixel circuit of each of the second pixels PX2 is located in the second display region 100A2.

[0104] The second display region 100A2 can have a quadrilateral shape. At least three sides of the second display region 100A2 can be in contact with the first display region 100A1. However, embodiments according to the inventive concept are not limited thereto. For example, the second display region 100A2 can be completely surrounded by the first display region 100A1 according to the position of the electronic module 200.

[0105] The maximum width WT11 of the second display region 100A2 in the first direction DR1 can be smaller than the maximum width WT21 of the first display region 100A1 in the first direction DR1. In addition, the maximum width WT12 of the second display region 100A2 in the second direction DR2 can be smaller than the maximum width WT22 of the first display region 100A1 in the second direction DR2. The maximum width WT21 of the first display region 100A1 is the maximum width of the display region 100A in the first direction DR1, and the maximum width WT22 of the first display region 100A1 can be the maximum width of the display region 100A in the second direction DR2. The maximum width in the first direction DR1 refers to the maximum width parallel to the first direction DR1, and the maximum width in the second direction DR2 refers to the maximum width parallel to the second direction DR2.

[0106] FIG. 5 is an equivalent circuit diagram of a pixel according to some embodiments of the inventive concept.

[0107] Reference FIG. 5 A pixel PX may include a light-emitting element (LD) and a pixel circuit (CC). The light-emitting element (LD) may be included in... FIG. 3A The components in the light-emitting element layer 113, and the pixel circuit CC may be included in FIG. 3A Components in circuit layer 112.

[0108] The pixel circuit CC may include multiple transistors T1, T2, T3, T4, T5, T6, and T7, as well as a capacitor CP. The pixel circuit CC can control the amount of current flowing through the light-emitting element LD in response to a data signal. The light-emitting element LD can emit light with a certain brightness (e.g., a set or predetermined brightness) corresponding to the amount of current supplied from the pixel circuit CC. For this purpose, the level of the first power ELVDD can be set higher than the level of the second power ELVSS.

[0109] A pixel (PX) can be electrically connected to multiple signal lines. Among these signal lines, FIG. 5 Example scan lines SLi, SLi-1, and SLi+1, data line DL, first power line PL1, second power line PL2, initialization power line VL, and light emission control line ECLi are shown. However, this is merely an example, and embodiments according to this disclosure are not limited thereto. Pixels PX according to some embodiments of the inventive concept may be additionally connected to various other signal lines, and some of the signal lines shown may be omitted.

[0110] Each of the plurality of transistors T1, T2, T3, T4, T5, T6, and T7 may include an input electrode (or source), an output electrode (or drain), and a control electrode (or gate). In this specification, for convenience, one of the input electrode and the output electrode may be referred to as the first electrode, and the other of the input electrode and the output electrode may be referred to as the second electrode.

[0111] The first electrode of the first transistor T1 can be connected to the first power line PL1 via the fifth transistor T5. The first power line PL1 can be a line providing the first power ELVDD. The second electrode of the first transistor T1 is connected to the pixel electrode (or anode) of the light-emitting element LD via the sixth transistor T6. In this specification, the first transistor T1 can be referred to as the driving transistor.

[0112] The first transistor T1 can control the amount of current flowing in the light-emitting element LD by corresponding to the voltage applied to the control electrode of the first transistor T1.

[0113] The second transistor T2 is connected between the data line DL and the first electrode of the first transistor T1. In addition, the control electrode of the second transistor T2 is connected to the i-th scan line SLi. When the i-th scan signal is supplied to the i-th scan line SLi, the second transistor T2 is turned on to electrically connect the data line DL and the first electrode of the first transistor T1.

[0114] The third transistor T3 is connected between the second electrode of the first transistor T1 and the control electrode of the first transistor T1. The control electrode of the third transistor T3 is connected to the i-th scan line SLi. When the i-th scan signal is supplied to the i-th scan line SLi, the third transistor T3 is turned on to electrically connect the second electrode of the first transistor T1 and the control electrode of the first transistor T1. Accordingly, when the third transistor T3 is turned on, the first transistor T1 is connected in a diode form.

[0115] The fourth transistor T4 is connected between the node ND and the initialization power line VL. In addition, the control electrode of the fourth transistor T4 is connected to the (i-1)-th scan line SLi-1. The node ND can be a node to which the control electrode of the first transistor T1 and the fourth transistor T4 are connected. When the (i-1)-th scan signal is supplied to the (i-1)-th scan line SLi-1, the fourth transistor T4 is turned on to supply the initialization voltage Vint to the node ND.

[0116] The fifth transistor T5 is connected between the first power line PL1 and the first electrode of the first transistor T1. The sixth transistor T6 is connected between the second electrode of the first transistor T1 and the pixel electrode of the light emitting element LD. The control electrode of the fifth transistor T5 and the control electrode of the sixth transistor T6 are connected to the i-th light emission control line ECLi.

[0117] The seventh transistor T7 is connected between the initialization power line VL and the pixel electrode of the light emitting element LD. In addition, the control electrode of the seventh transistor T7 is connected to the (i+1)-th scan line SLi+1. When the (i+1)-th scan signal is supplied to the (i+1)-th scan line SLi+1, the seventh transistor T7 is turned on to supply the initialization voltage Vint to the pixel electrode of the light emitting element LD.

[0118] The seventh transistor T7 can improve the black expression capability of the pixel PX. For example, when the seventh transistor T7 is turned on, a parasitic capacitor of the light emitting element LD is discharged. Then, when black luminance is achieved, the light emitting element LD does not emit light due to the drain current from the first transistor T1, and thus the black expression capability can be improved.

[0119] FIG. 5The control electrode of the seventh transistor T7 is shown connected to the i+1th scan line SLi+1, but embodiments of the inventive concept are not limited thereto. According to some embodiments of the inventive concept, the control electrode of the seventh transistor T7 can be connected to the i-1th scan line SLi-1 or the i-th scan line SLi.

[0120] Although FIG. 5 Various transistors shown as PMOS are shown as examples, but embodiments of the inventive concept are not limited thereto. According to some embodiments of the inventive concept, the pixel circuit CC can be formed of one or more NMOS transistors, as will be appreciated by one of ordinary skill in the art. According to some embodiments of the inventive concept, the pixel circuit CC can be formed of a combination of NMOS transistors and PMOS transistors. That is, according to some embodiments, the pixel circuit CC can utilize any suitable combination of NMOS transistors and PMOS transistors.

[0121] The capacitor CP is positioned between the first power line PL1 and the node ND. The capacitor CP stores a voltage corresponding to a data signal. When the fifth transistor T5 and the sixth transistor T6 are turned on, an amount of current flowing through the first transistor T1 can be determined according to the voltage stored in the capacitor CP.

[0122] The light emitting element LD can be electrically connected to the sixth transistor T6 and the second power line PL2. The light emitting element LD can receive the second power ELVSS through the second power line PL2.

[0123] The light emitting element LD can emit light with a voltage corresponding to a difference between a signal transmitted through the sixth transistor T6 and the second power ELVSS received through the second power line PL2.

[0124] The equivalent circuit of the pixel circuit CC is not limited to FIG. 5 the equivalent circuit shown in FIG. 7. According to some embodiments of the inventive concept, the pixel circuit CC can be modified in various forms to cause the light emitting element LD to emit light. According to some embodiments, the pixel circuit CC can include additional electronic components or fewer electronic components without departing from the spirit and scope of embodiments according to the present disclosure.

[0125] FIG. 6 is a cross-sectional view of a display layer according to some embodiments of the inventive concept.

[0126] Referring to FIG. 6The display layer 110 can include a plurality of insulating layers, semiconductor patterns, conductive patterns, signal lines, and the like. The insulating layers, semiconductor layers, and conductive layers are formed by coating, deposition, or the like. Thereafter, the insulating layers, semiconductor layers, and conductive layers can be selectively patterned by photolithography. The semiconductor patterns, conductive patterns, signal lines, and the like included in the circuit layer 112 and the light emitting element layer 113 are formed in the above-described manner. Thereafter, the encapsulation layer 114 covering the light emitting element layer 113 can be formed.

[0127] At least one inorganic layer is formed on an upper surface of the base layer 111. The inorganic layer can include at least one of aluminum oxide, titanium oxide, silicon oxide, silicon nitride, silicon oxynitride, zirconium oxide, and hafnium oxide. The inorganic layer can be formed as a multilayer inorganic layer. The multilayer inorganic layer can constitute the barrier layer 112br and / or the buffer layer 112bf.

[0128] The barrier layer 112br can be located on the base layer 111. The barrier layer 112br can include at least one of silicon oxide, silicon nitride, and silicon oxynitride. The buffer layer 112bf can be located on the barrier layer 112br. The buffer layer 112bf can improve the bonding force between the base layer 111 and the semiconductor pattern. The buffer layer 112bf can include at least one of silicon oxide, silicon nitride, and silicon oxynitride. For example, the buffer layer 112bf can include a structure in which a silicon oxide layer and a silicon nitride layer are alternately stacked.

[0129] The semiconductor pattern can be located on the buffer layer 112bf. The semiconductor pattern can include polysilicon. However, embodiments of the inventive concept are not limited thereto. The semiconductor pattern can include amorphous silicon or an oxide semiconductor.

[0130] FIG. 6 Only a portion of the semiconductor pattern is shown, and the semiconductor pattern can also be located in another region. The semiconductor pattern can be arranged across pixels according to specific rules. The semiconductor pattern can have different electrical properties according to whether the semiconductor pattern is doped. The semiconductor pattern can include a first region having a high conductivity and a second region having a low conductivity. The first region can be doped with an N-type dopant or a P-type dopant. A P-type transistor can include a doped region that has been doped with a P-type dopant, and an N-type transistor can include a doped region that has been doped with an N-type dopant. The second region can be an undoped region or a region doped to a lower concentration than the concentration of the first region.

[0131] The conductivity of the first region can be greater than the conductivity of the second region, and the first region can substantially function as an electrode or a signal line. The second region can substantially correspond to an active region (or a channel) of a transistor. In other words, a portion of the semiconductor pattern can be an active region of a transistor, another portion of the semiconductor pattern can be a source or a drain of a transistor, and another portion of the semiconductor pattern can be a connection electrode or a connection signal line.

[0132] FIG. 6 An example of the sixth transistor T6_1 and the light emitting element 100PE_1 included in the pixel is shown. FIG. 6 is a cross-sectional view of the first display region 100A1.

[0133] The source SE, the active region AC, and the drain DE of the sixth transistor T6_1 can be formed of a semiconductor pattern. The source SE and the drain DE can extend in opposite directions from the active region AC in a cross section.

[0134] The first insulating layer 10 can be located on the buffer layer 112bf. The first insulating layer 10 is generally superposed with a plurality of pixels, and can cover the semiconductor pattern. The first insulating layer 10 can be an inorganic layer and / or an organic layer, and can have a single-layer structure or a multi-layer structure. The first insulating layer 10 can include at least one of aluminum oxide, titanium oxide, silicon oxide, silicon nitride, silicon oxynitride, zirconium oxide, and hafnium oxide. According to some embodiments, the first insulating layer 10 can be a single-layer silicon oxide layer. Not only the first insulating layer 10 but also the insulating layers to be described of the circuit layer 112 can be an inorganic layer and / or an organic layer, and can have a single-layer structure or a multi-layer structure. The inorganic layer can include at least one of the above-described materials, but embodiments of the present inventive concept are not limited thereto.

[0135] The gate GT of the sixth transistor T6_1 is located on the first insulating layer 10. The gate GT can be part of a metal pattern. The gate GT is superposed with the active region AC. The gate GT can be used as a mask in a process of doping the semiconductor pattern.

[0136] The second insulating layer 20 is located on the first insulating layer 10, and can cover the gate GT. The second insulating layer 20 can be an inorganic layer and / or an organic layer, and can have a single-layer structure or a multi-layer structure. The second insulating layer 20 can include at least one of silicon oxide, silicon nitride, and silicon oxynitride. According to some embodiments, the second insulating layer 20 can have a multi-layer structure including a silicon oxide layer and a silicon nitride layer.

[0137] The capacitor CP can include a first electrode E1 and a second electrode E2 facing the first electrode E1. The first electrode E1 is located on the same layer as the gate GT, and can include the same material as that of the gate GT. For example, the first electrode E1 can be located between the first insulating layer 10 and the second insulating layer 20. The second electrode E2 can be located on the second insulating layer 20. The position of the capacitor CP is not limited to the example shown in FIG. 1A. For example, the capacitor CP can be located on the first transistor T1 (see FIG. 6 FIG. 5 ). That is, the capacitor CP can be superposed with the first transistor T1 (see FIG. 5 ). In this case, it can be ensured that a pixel circuit CC (see​FIG. 5 ) of the region or space.

[0138] The third insulating layer 30 can be located on the second insulating layer 20, and the third insulating layer 30 can cover the second electrode E2. The third insulating layer 30 can have a single layer structure or a multi-layer structure. For example, the third insulating layer 30 can have a multi-layer structure including a silicon oxide layer and a silicon nitride layer. The first connection electrode CNE1 can be located on the third insulating layer 30. The first connection electrode CNE1 can be connected to the drain DE of the sixth transistor T6_1 through a contact hole passing through the first insulating layer 10, the second insulating layer 20, and the third insulating layer 30.

[0139] The fourth insulating layer 40 can be located on the third insulating layer 30. The fourth insulating layer 40 can be an organic layer.

[0140] The second connection electrode CNE2 can be located on the fourth insulating layer 40. The second connection electrode CNE2 can be connected to the first connection electrode CNE1 through a contact hole passing through the fourth insulating layer 40.

[0141] The fifth insulating layer 50 is located on the fourth insulating layer 40 and can cover the second connection electrode CNE2. The fifth insulating layer 50 can be an organic layer.

[0142] The light emitting element layer 113 including the light emitting element 100PE_1 can be located on the circuit layer 112. The light emitting element 100PE_1 can include the first pixel electrode AE_1, the light emitting layer EL, and the common electrode CE.

[0143] The first pixel electrode AE_1 can be located on the fifth insulating layer 50. The first pixel electrode AE_1 can be connected to the second connection electrode CNE2 through a contact hole passing through the fifth insulating layer 50.

[0144] The pixel definition film 60 is located on the fifth insulating layer 50 and can cover a portion of the first pixel electrode AE_1. In the pixel definition film 60, an opening 60op is defined. The opening 60op of the pixel definition film 60 exposes at least a portion of the first pixel electrode AE_1.

[0145] The light emitting layer EL can be located on the first pixel electrode AE_1. The light emitting layer EL can be located in a region corresponding to the opening 60op. That is, the light emitting layer EL can be divided and formed in each of the pixels. When the light emitting layer EL is divided and formed in each of the pixels, each of the light emitting layers EL can emit light of at least one color among blue, red, and green. However, embodiments of the inventive concept are not limited thereto, and the light emitting layer EL can be connected to the pixels and provided commonly. In this case, the light emitting layer EL can provide blue light or white light.

[0146] The common electrode CE can be located on the light-emitting layer EL. The common electrode CE has an integrated shape and can be commonly located in a plurality of pixels.

[0147] According to some embodiments, a hole control layer can be located between the first pixel electrode AE_1 and the light-emitting layer EL. The hole control layer includes a hole transport layer and can further include a hole injection layer. An electron control layer can be located between the light-emitting layer EL and the common electrode CE. The electron control layer includes an electron transport layer and can further include an electron injection layer. The hole control layer and the electron control layer can be commonly formed in a plurality of pixels using an opening mask.

[0148] The encapsulation layer 114 can be located on the light-emitting element layer 113. The encapsulation layer 114 can include an inorganic layer 114a, an organic layer 114b, and an inorganic layer 114c, which are sequentially stacked, but the layers constituting the encapsulation layer 114 are not limited thereto.

[0149] The inorganic layers 114a and 114c can protect the light-emitting element layer 113 from moisture and oxygen, and the organic layer 114b can protect the light-emitting element layer 113 from foreign matter such as dust particles. The inorganic layers 114a and 114c can include a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, an aluminum oxide layer, or the like. The organic layer 114b can include an acrylic organic layer, but is not limited thereto.

[0150] FIG. 7 is a plan view showing an enlarged view of the region AA' of FIG. 4 .

[0151] Referring to FIG. 7 , a plurality of first pixel electrodes AE_1 (hereinafter, first pixel electrodes), a plurality of second pixel electrodes AE_2 (hereinafter, second pixel electrodes), a plurality of first pixel circuits CC_1 (hereinafter, first pixel circuits), and a plurality of second pixel circuits CC_2 (hereinafter, second pixel circuits) are shown.

[0152] The first pixel electrodes AE_1 can be located in the first display area 100A1, and the second pixel electrodes AE_2 can be located in the second display area 100A2. The resolution of the first display area 100A1 can be higher than the resolution of the second display area 100A2. The density of the first pixel electrodes AE_1 can be higher than the density of the second pixel electrodes AE_2. The number of the first pixel electrodes AE_1 located in the first area ARAl among the first pixel electrodes AE_1 (or the first number of the first pixel electrodes AE_1) can be greater than the number of the second pixel electrodes AE_2 located in the second area AR A2 among the second pixel electrodes AE_2 (or the second number of the second pixel electrodes AE_2). The first area ARAl and the second area AR A2 can be defined to have the same size and the same shape.

[0153] Each of the first pixel circuit CC_1 and the second pixel circuit CC_2 can have the same equivalent circuit as that of the pixel circuit CC described with reference to FIG. 1. FIG. 5 The equivalent circuit of the pixel circuit CC described with reference to FIG. 1 is the same as that of the pixel circuit CC described with reference to FIG. 2. FIG. 5 The first pixel circuit CC_1 can be electrically connected to the first pixel electrode AE_1, respectively, and the second pixel circuit CC_2 can be electrically connected to the second pixel electrode AE_2, respectively.

[0154] The first pixel circuit CC_1 can be located in the first display area 100A1. The second pixel circuit CC_2 can be spaced apart from the second pixel electrode AE_2. For example, the second pixel circuit CC_2 can be located in the peripheral area 100N. When viewed in the third direction DR3 (for example, from a direction or a plan view perpendicular or orthogonal to the plane of the display surface), the first pixel circuit CC_1 can be superposed with the first pixel electrode AE_1, respectively, and the second pixel circuit CC_2 can not be superposed with the second pixel electrode AE_2.

[0155] The display panel 100 described with reference to FIG. 1 can further include a plurality of connection lines CL (hereinafter, connection lines). The connection lines CL can electrically connect the second pixel electrode AE_2 and the second pixel circuit CC_2, respectively. For example, one connection line CL can electrically connect one second pixel electrode AE_2 and one second pixel circuit CC_2. One connection line CL can correspond to the line connecting the sixth transistor T6 (see FIG. 1) and the light emitting element LD (see FIG. 1) illustrated in FIG. 1. FIG. 2 FIG. 5 FIG. 5 FIG. 5

[0156] A portion of each of the connection lines CL is also located in the second display area 100A2. Since the second display area 100A2 is an area superposed with the electronic module 200 (see FIG. 2), the portion of each of the connection lines CL can include a transparent conductive material. Accordingly, degradation of the transmittance of the second display area 100A2 caused by the connection lines CL can be reduced or minimized. FIG. 2

[0157] The transparent conductive material can include a transparent conductive oxide such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium tin zinc oxide (ITZO), or the like. In addition, the transparent conductive material can include a conductive polymer such as PEDOT, a metal nanowire, graphene, or the like, but embodiments of the inventive concept are not particularly limited thereto.

[0158] FIG. 8 is a cross-sectional view taken along the line I-I' illustrated in FIG. 1. FIG. 7 FIG. 8 ​​​​​​is a cross-sectional view of the second display region 100A2 and the peripheral region 100N.

[0159] Referring to FIG. 7 and FIG. 8 , an example of the sixth transistor T6_2 and the light emitting element 100PE_2 included in the pixel is shown. Because the sixth transistor T6_2 is included in the second pixel circuit CC_2, the sixth transistor T6_2 can be located in the peripheral region 100N.

[0160] The second display region 100A2 can include a first sub-region 100A2P and a second sub-region 100A2T. The first sub-region 100A2P can be a region in which the light emitting element 100PE_2 is located, and the second sub-region 100A2T can be a region in which the light emitting element 100PE_2 is not located. According to some embodiments of the inventive concepts, a portion of the common electrode CE that overlaps the second sub-region 100A2T can be removed. Thus, in the common electrode CE, an opening CEo can be defined, and the opening CEo can correspond to the second sub-region 100A2T. When the common electrode CE is removed from the second sub-region 100A2T, the transmittance of the second sub-region 100A2T can be improved. For reference, in FIG. 8 , an indication line indicating the opening CEo is shown on a sidewall defining the opening CEo.

[0161] The light emitting element 100PE_2 can include a second pixel electrode AE_2, a light emitting layer EL, and a common electrode CE. The second pixel electrode AE_2 can be electrically connected to the second pixel circuit CC_2. For example, the second pixel electrode AE_2 can be electrically connected to the sixth transistor T6_2 through a connection line CL.

[0162] According to some embodiments of the inventive concepts, the connection line CL can include a first connection portion CL1 and a second connection portion CL2. The second pixel electrode AE_2 can be electrically connected to the second connection portion CL2 through a second connection electrode CNE2_2.

[0163] The first connection portion CL1 can be located in the peripheral region 100N. The first connection portion CL1 can be in electrical contact with the first connection electrode CNE1. The first connection portion CL1 is on the same layer as the second connection electrode CNE2 (see FIG. 6 ) and can include the same material as the material of the second connection electrode CNE2 (see FIG. 6 ).

[0164] The second connection portion CL2 can be located in the peripheral area 100N and the second display area 100A2. The second connection portion CL2 can be located on the same layer as the first connection electrode CNE1. For example, the second connection portion CL2 can be located between the third insulating layer 30 and the fourth insulating layer 40. The second connection portion CL2 is located on the same layer as the first connection electrode CNE1, but the second connection portion CL2 can include a material different from that of the first connection electrode CNE1. For example, the second connection portion CL2 can include a transparent conductive material. Accordingly, even when the second connection portion CL2 is located in the second display area 100A2, deterioration in transmittance of the second display area 100A2 caused by the second connection portion CL2 can be small.

[0165] In contrast to what is shown in FIG. 1B, the connection line CL can be composed of only the second connection portion CL2. In this case, the second connection portion CL2 can be in contact with the first connection electrode CNE1. FIG. 8

[0166] Under the second pixel electrode AE_2, a barrier pattern BP can be positioned. The barrier pattern BP can be spaced apart from the common electrode CE, and the second pixel electrode AE_2 is interposed between the barrier pattern BP and the common electrode CE. The barrier pattern BP can be a pattern used as a mask when an opening CEo is formed in the common electrode CE. The barrier pattern BP can include an opaque metal. The barrier pattern BP can be referred to as a barrier layer.

[0167] The barrier pattern BP can include a first barrier pattern BP1 and a second barrier pattern BP2. The second barrier pattern BP2 can be located on the first barrier pattern BP1, and the second barrier pattern BP2 can be located between the first barrier pattern BP1 and the second pixel electrode AE_2. The first barrier pattern BP1, the second barrier pattern BP2, and the second pixel electrode AE_2 can be stacked on each other when viewed in the third direction DR3.

[0168] The first barrier pattern BP1 can be located between the first insulating layer 10 and the second insulating layer 20. For example, the first barrier pattern BP1 is located on the same layer as the gate GT, and can include the same material as that of the gate GT.

[0169] The second barrier pattern BP2 can be located between the second insulating layer 20 and the third insulating layer 30. For example, the second barrier pattern BP2 is located on the same layer as the second electrode E2 (see FIG. 6 ) of the capacitor CP (see FIG. 6 ), and can include the same material as that of the second electrode E2 (see FIG. 6 ).

[0170] ​In the first block pattern BP1, a first transmission part BP1o is defined, and in the second block pattern BP2, a second transmission part BP2o can be positioned. During a process of manufacturing the display panel 100 (see FIG. 2 ), portions of the common electrode CE overlapped with the first transmission part BP1o and the second transmission part BP2o are removed, so that an opening CEo of the common electrode CE can be formed. Therefore, the first transmission part BP1o, the second transmission part BP2o and the opening CEo of the common electrode CE can all be overlapped in the third direction DR3.

[0171] FIG. 9 is a sectional view of a display layer according to some embodiments of the inventive concept. In the description FIG. 9 of the display layer, components that are the same as those described with reference to FIG. 8 are denoted by the same reference numerals, and a description thereof is omitted.

[0172] With reference to FIG. 9 , the second pixel electrode AE_2 can be electrically connected to the sixth transistor T6_2 by the first connection line CLa. According to some embodiments, another second pixel electrode located in the second display area 100A2 can be electrically connected to the sixth transistor corresponding to the other second pixel electrode by the second connection line CLb.

[0173] According to some embodiments of the inventive concept, the first connection line CLa can include a first connection part CLa1 and a second connection part CLa2. The second connection part CLa2 can be located in the peripheral area 100N and the second display area 100A2. For example, the first connection part CLa1 is located on the same layer as the second connection electrode CNE2 (see FIG. 6 ) and can include the same material as the material of the second connection electrode CNE2 (see FIG. 6 ). The first connection part CLa1 and the second connection part CLa2 are located on the same layer and can include different materials. The second connection part CLa2 can include a transparent conductive material. In addition, the second connection line CLb can also include a transparent conductive material.

[0174] According to some embodiments, as shown in FIG. 9 , the connection line located in the second display area 100A2 and including a transparent conductive material can be provided to have at least two layers. The second pixel electrode located in the second display area 100A2 can be electrically connected to the pixel circuit located in the peripheral area 100N by using the connection line including a transparent conductive material.

[0175] Under the second pixel electrode AE_2, a barrier pattern BP can be positioned. The barrier pattern BP can be spaced apart from the common electrode CE, and the second pixel electrode AE_2 is positioned between the barrier pattern BP and the common electrode CE. The barrier pattern BP can be a pattern used as a mask when forming an opening CEo in the common electrode CE.

[0176] FIG. 10A is a plan view showing some enlarged components of a display layer according to some embodiments of the inventive concept.

[0177] FIG. 4 and FIG. 10A The second pixel electrode AE_2, the barrier pattern BP, and the common electrode CE positioned in the second display area 100A2 are shown. In the barrier pattern BP, a plurality of transmission portions BPo (hereinafter, transmission portions) can be defined. The transmission portions BPo can be spaced apart from the second pixel electrode AE_2 when viewed in the third direction DR3. That is, the transmission portions BPo can not be overlapped with the second pixel electrode AE_2.

[0178] The barrier pattern BP can be a pattern used as a mask in a process of removing a portion of the common electrode CE. A portion of the common electrode CE overlapped with the barrier pattern BP can not be removed, and a portion of the common electrode CE overlapped with the transmission portions BPo of the barrier pattern BP can be removed. In the portion of the common electrode CE overlapped with the transmission portions BPo, a plurality of openings CEo can be defined. The barrier pattern BP can be used during a process of patterning the common electrode CE. This will be described in detail below.

[0179] According to some embodiments of the inventive concept, because a portion of the common electrode CE is removed, the transmittance in the second display area 100A2 can be increased, and the aperture ratio in the second display area 100A2 can also be improved.

[0180] Taking the case in which the electronic module 200 is a camera as an example, because the openings CEo are defined in the common electrode CE in the second display area 100A2, the haze (or light smear) of an image captured by the electronic module 200 can be reduced. In addition, because the transmittance in the second display area 100A2 is improved, the image quality of an image captured by the electronic module 200 in a low-illuminance environment can be improved.

[0181] The second pixel electrode AE_2 can include a red pixel electrode AE_2R, a green pixel electrode AE_2G, and a blue pixel electrode AE_2B. The red pixel electrode AE_2R, the green pixel electrode AE_2G, and the blue pixel electrode AE_2B can include the same material. The display panel 100 can emit red light in a region overlapping the red pixel electrode AE_2R, emit green light in a region overlapping the green pixel electrode AE_2G, and emit blue light in a region overlapping the blue pixel electrode AE_2B.

[0182] The red pixel electrode AE_2R, the green pixel electrode AE_2G, and the blue pixel electrode AE_2B can be arranged according to a certain rule (e.g., a set or predetermined rule). The red pixel electrode AE_2R, the green pixel electrode AE_2G, and the blue pixel electrode AE_2B can be arranged in the first display area 100A1 and the second display area 100A2 according to similar rules. For example, the red pixel electrode AE_2R, the green pixel electrode AE_2G, and the blue pixel electrode AE_2B can be arranged in the first display area 100A1 and the second display area 100A2 according to the same rule while only having different arrangement intervals. However, this is only an example, and embodiments of the inventive concept are not particularly limited thereto.

[0183] FIG. 10B is a plan view showing some enlarged components of a display layer according to some embodiments of the inventive concept.

[0184] FIG. 4 and FIG. 10B The second pixel electrode AE_2a, the barrier pattern BPa, and the common electrode CEa located in the second display area 100A2 are shown. In the barrier pattern BPa, a plurality of transmission portions BPoa (hereinafter, transmission portions) can be defined. The transmission portions BPoa can be spaced apart from the second pixel electrode AE_2a when viewed in the third direction DR3. That is, the transmission portions BPoa can not overlap the second pixel electrode AE_2a. In a portion of the common electrode CEa overlapping the transmission portions BPoa, a plurality of openings CEoa can be defined.

[0185] According to some embodiments of the inventive concept, the common electrode CEa can be patterned by using the barrier pattern BPa. Since a portion of the common electrode CEa is removed, the transmittance in the second display area 100A2 can be increased, and the aperture ratio in the second display area 100A2 can also be improved.

[0186] The second pixel electrode AE_2a can include a red pixel electrode AE_2Ra, a green pixel electrode AE_2Ga, and a blue pixel electrode AE_2Ba. The red pixel electrode AE_2Ra, the green pixel electrode AE_2Ga, and the blue pixel electrode AE_2Ba can be arranged in the second display area 100A2 according to a certain rule (e.g., a set or predetermined rule).

[0187] The size of the blue pixel electrode AE_2Ba can be greater than the size of each of the red pixel electrode AE_2Ra and the green pixel electrode AE_2Ga. One blue pixel electrode AE_2Ba can be adjacent to one red pixel electrode AE_2Ra and one green pixel electrode AE_2Ga in the second direction DR2. One red pixel electrode AE_2Ra and one green pixel electrode AE_2Ga can be adjacent to each other in the first direction DR1.

[0188] Each of the transmission portions BPoa and each of the openings CEoa can have a cross shape. However, the shape of each of the transmission portions BPoa and each of the openings CEoa is not particularly limited thereto. For example, each of the transmission portions BPoa and each of the openings CEoa can be modified to various shapes while being spaced apart from only the red pixel electrode AE_2Ra, the green pixel electrode AE_2Ga, and the blue pixel electrode AE_2Ba.

[0189] FIG. 10C is a plan view showing some enlarged components of a display layer according to some embodiments of the inventive concepts.

[0190] FIG. 4 and FIG. 10C The second pixel electrode AE_2a, the barrier pattern BPb, and the common electrode CEb located in the second display area 100A2 are shown. In the barrier pattern BPb, a plurality of transmission portions BPob (hereinafter, transmission portions) can be defined. The transmission portions BPob can be spaced apart from the second pixel electrode AE_2a when viewed in the third direction DR3. That is, the transmission portions BPob can not be superposed on the second pixel electrode AE_2a. In portions of the common electrode CEb superposed on the transmission portions BPob, a plurality of openings CEob can be defined.

[0191] The shapes of the transmission portions BPob and the openings CEob of FIG. 10B differ when compared to FIG. 10C Each of the transmission portions BPob and each of the openings CEob can have a hexagonal shape. In this case, according to some embodiments, as shown in FIG. 10C FIG. 10B ​The transmittance can decrease when each of the transmission portions BPoa and each of the openings CEoa illustrated in FIG. 11 are compared, but diffraction of light passing through the display panel 100 can be reduced. As the diffraction of light is reduced, the image quality of an image captured by the electronic module 200 can be improved.

[0192] The shapes of each of the transmission portions BPob and each of the openings CEob are not limited to FIG. 10B and FIG. 10C the shapes illustrated in FIG. 12. For example, each of the transmission portions BPob and each of the openings CEob can have a polygonal shape or a circular shape.

[0193] FIG. 10D are plan views showing some enlarged components of a display layer according to some embodiments of the inventive concept.

[0194] FIG. 4 and FIG. 10D illustrates a second pixel electrode AE_2b, a barrier pattern BPc, and a common electrode CEc located in the second display area 100A2. In the barrier pattern BPc, a plurality of transmission portions BPoc (hereinafter, transmission portions) can be defined. The transmission portions BPoc can be spaced apart from the second pixel electrode AE_2b when viewed in the third direction DR3. That is, the transmission portions BPoc can not overlap the second pixel electrode AE_2b. In portions of the common electrode CEc overlapping the transmission portions BPoc, a plurality of openings CEoc can be defined.

[0195] The second pixel electrode AE_2b can include a red pixel electrode AE_2Rb, a green pixel electrode AE_2Gb, and a blue pixel electrode AE_2Bb. The red pixel electrode AE_2Rb, the green pixel electrode AE_2Gb, and the blue pixel electrode AE_2Bb can be arranged in the second display area 100A2 according to a certain rule (for example, a set or predetermined rule). For example, the red pixel electrode AE_2Rb and the blue pixel electrode AE_2Bb can be alternately and repeatedly arranged along the first direction DR1, and the green pixel electrode AE_2Gb and the blue pixel electrode AE_2Bb can be alternately and repeatedly arranged along the second direction DR2.

[0196] A width of the red pixel electrode AE_2Rb in the first direction DR1 can be greater than a width of the red pixel electrode AE_2Rb in the second direction DR2. A width of the green pixel electrode AE_2Gb in the first direction DR1 can be less than a width of the green pixel electrode AE_2Gb in the second direction DR2.

[0197] FIGS. 10A-10DExamples of the arrangement of the pixel electrode, the shape of the transmissive portion of the barrier pattern, and the shape of the opening of the common electrode located in the second display region 100A2 are shown, but embodiments of the invention concept are not limited thereto. If only the transmissive portion of the barrier pattern and the opening of the common electrode are superposed on each other, the arrangement of the pixel electrode, the shape of the transmissive portion of the barrier pattern, and the shape of the opening of the common electrode can be modified differently.

[0198] FIGS. 10A-10D The transmissive portions BPo, BPoa, BPob, and BPoc are shown as surrounding the openings CEo, CEoa, CEob, and CEoc. However, this is only to distinguish the transmissive portions BPo, BPoa, BPob, and BPoc from the openings CEo, CEoa, CEob, and CEoc. Embodiments of the invention concept are not limited thereto. The transmissive portions BPo, BPoa, BPob, and BPoc and the openings CEo, CEoa, CEob, and CEoc can be substantially superposed when viewed in the third direction DR3. This can mean that the sidewalls of the barrier patterns BP, BPa, BPb, and BPc defining the transmissive portions BPo, BPoa, BPob, and BPoc are respectively superposed on each other within a process error range with the sidewalls of the common electrodes CE, CEa, CEb, and CEc defining the openings CEo, CEoa, CEob, and CEoc.

[0199] FIG. 11A is a cross-sectional view of a display layer according to some embodiments of the invention concept. FIG. 11A may be a portion of FIG. 10A corresponding to line II-II' of FIG. 11A When describing FIG. 8 and FIG. 9 the same components as described with reference to

[0200] The embodiments shown with respect to FIG. 8 and FIG. 9 differ in the barrier pattern BPw when compared to FIG. 11A In each of FIG. 8 and FIG. 9 the barrier pattern BP can comprise a first barrier pattern BP1 and a second barrier pattern BP2. FIG. 11A The barrier pattern BPw shown in may consist only of the first barrier pattern BP1. For example, the barrier pattern BPw can be located between the first insulating layer 10 and the second insulating layer 20. For example, the barrier pattern BPw is located on the same layer as the gate electrode GT and can comprise the same material as the material of the gate electrode GT.

[0201] The blocking pattern BPw can be a pattern used as a mask in a process of removing a portion of the common electrode CE. A portion of the common electrode CE overlaid with a transmission portion BPwo of the blocking pattern BPw can be removed. In the portion of the common electrode CE overlaid with the transmission portion BPwo, a plurality of openings CEo can be defined.

[0202] FIG. 11B is a cross-sectional view of a display layer according to some embodiments of the inventive concept. FIG. 11B may be a portion of the display layer corresponding to the line II-II’ of FIG. 10A When describing FIG. 11B , components that are the same as components described with reference to FIG. 8 and FIG. 9 are denoted by the same reference numerals, and a description thereof is omitted.

[0203] When compared with FIG. 8 and FIG. 9 , FIG. 11B the embodiments shown in FIG. 8 and FIG. 9 differ in the blocking pattern BPx. In FIG. 11B , the blocking pattern BP can include a first blocking pattern BP1 and a second blocking pattern BP2. FIG. 6 The blocking pattern BPx shown in FIG. 6 may consist of only the second blocking pattern BP2. For example, the blocking pattern BPx can be located between the second insulating layer 20 and the third insulating layer 30. For example, the blocking pattern BPx is located on the same layer as the second electrode E2 (see FIG. 6 ) of the capacitor CP (see ), and can include the same material as the material of the second electrode E2 (see

[0204] ).

[0205] FIG. 11C is a cross-sectional view of a display layer according to some embodiments of the inventive concept. FIG. 11C may be a portion of the display layer corresponding to the line II-II’ of FIG. 10A When describing FIG. 11C , components that are the same as components described with reference to FIG. 8 and FIG. 9 are denoted by the same reference numerals, and a description thereof is omitted.

[0206] When compared with FIG. 8 and FIG. 9 ,FIG. 11C The embodiments shown in FIGS. 1A and 1B are different in terms of a barrier pattern BPy. The barrier pattern BPy can include a first barrier pattern BPy1, a second barrier pattern BPy2, and a third barrier pattern BPy3. FIG. 8 and FIG. 9 The first barrier pattern BP1 and the second barrier pattern BP2 shown in FIGS. 2A and 2B, respectively, can correspond to FIG. 11C The first barrier pattern BPy1 and the second barrier pattern BPy2 shown in FIGS. 3A and 3B, respectively, can correspond to

[0207] The third barrier pattern BPy3 can be located below the first barrier pattern BPy1. For example, the third barrier pattern BPy3 can be located between the barrier layer 112br and the buffer layer 112bf.

[0208] The first barrier pattern BPy1, the second barrier pattern BPy2, and the third barrier pattern BPy3 can be stacked with each other. In the first barrier pattern BPy1, a first transmission portion BPy1o is defined, and in the second barrier pattern BPy2, a second transmission portion BPy2o can be disposed. In the third barrier pattern BPy3, a third transmission portion BPy3o can be disposed.

[0209] During a process of manufacturing the display panel 100 (see FIG. 2 ), portions of the common electrode CE that overlap the first transmission portion BPy1o, the second transmission portion BPy2o, and the third transmission portion BPy3o are removed, so that an opening CEo of the common electrode CE can be formed. Accordingly, the first transmission portion BPy1o, the second transmission portion BPy2o, the third transmission portion BPy3o, and the opening CEo of the common electrode CE can all be stacked in the third direction DR3.

[0210] FIG. 11D is a cross-sectional view of a display layer according to some embodiments of the inventive concept. FIG. 11D may be a cross-sectional view of a portion corresponding to FIG. 10A line II-II' of FIG. 1A. In describing FIG. 11D , components that are the same as those described above are denoted by the same reference numerals, and a description thereof is omitted.

[0211] Referring to FIG. 11D , the barrier layer 112br can include a first sub-barrier layer 112br1 and a second sub-barrier layer 112br2. The first sub-barrier layer 112br1 can be located on the base layer 111, and the second sub-barrier layer 112br2 can be located on the first sub-barrier layer 112br1.

[0212] The barrier pattern BPz can include a first barrier pattern BPz1, a second barrier pattern BPz2, and a third barrier pattern BPz3. FIG. 8 and FIG. 9The first and second barrier patterns BP1 and BP2 shown in FIG. 1A can correspond to the first and second barrier patterns BP1 and BP2 shown in FIG. 1B, respectively. FIG. 11D The first and second barrier patterns BPz1 and BPz2 shown in FIG. 1C can correspond to the first and second barrier patterns BP1 and BP2 shown in FIG. 1B, respectively.

[0213] The third barrier pattern BPz3 can be located below the first barrier pattern BPz1. For example, the third barrier pattern BPz3 can be located between the first sub-barrier layer 112br1 and the second sub-barrier layer 112br2.

[0214] FIG. 12 is a plan view of a display panel according to some embodiments of the inventive concept.

[0215] Referring to FIG. 12 , in the display panel 100-1, a display region 100Aa and a peripheral region 100N can be defined. The display region 100Aa can correspond to the display region 1000A shown in FIG. 1A. FIG. 1

[0216] The display region 100Aa can include a first display region 100A1a, a second display region 100A2a, and a third display region 100A3a. The third display region 100A3a can be located between the first display region 100A1a and the second display region 100A2a. The second display region 100A2a can be a region in which the electronic module 200 (see FIG. 2 ) is overlaid, and the third display region 100A3a can be a region adjacent to the second display region 100A2a.

[0217] FIG. 13 is a plan view showing an enlarged view of the region BB' of FIG. 12 .

[0218] Referring to FIG. 13 , a plurality of first pixel electrodes AE_1a (hereinafter, first pixel electrodes), a plurality of second pixel electrodes AE_2a (hereinafter, second pixel electrodes), a plurality of third pixel electrodes AE_3a (hereinafter, third pixel electrodes), a plurality of first pixel circuits CC_1a (hereinafter, first pixel circuits), a plurality of second pixel circuits CC_2a (hereinafter, second pixel circuits), and a plurality of third pixel circuits CC_3a (hereinafter, third pixel circuits) are shown.

[0219] ​The first pixel electrode AE_1a can be located in the first display region 100A1a, the second pixel electrode AE_2a can be located in the second display region 100A2a, and the third pixel electrode AE_3a can be located in the third display region 100A3a. The number of the first pixel electrodes AE_1a among the first pixel electrodes AE_1a located in one region (or the first number of the first pixel electrodes AE_1a) is larger than each of the number of the second pixel electrodes AE_2a among the second pixel electrodes AE_2a located in another region having the same size as that of the one region (or the second number of the second pixel electrodes AE_2a) and the number of the third pixel electrodes AE_3a among the third pixel electrodes AE_3a located in still another region having the same size as that of the one region (or the third number of the third pixel electrodes AE_3a). The resolution of the first display region 100A1a can be higher than the resolution of each of the second display region 100A2a and the third display region 100A3a. The density of the first pixel electrode AE_1a can be higher than the density of each of the second pixel electrode AE_2a and the third pixel electrode AE_3a.

[0220] Each of the first pixel circuit CC_1a, the second pixel circuit CC_2a, and the third pixel circuit CC_3a can have an equivalent circuit identical to that of the pixel circuit CC (see FIG. 5 ) described above. The first pixel circuit CC_1a can be electrically connected to the first pixel electrode AE_1a respectively, the second pixel circuit CC_2a can be electrically connected to the second pixel electrode AE_2a respectively, and the third pixel circuit CC_3a can be electrically connected to the third pixel electrode AE_3a respectively. FIG. 5

[0221] The first pixel circuit CC_1a can be located in the first display region 100A1a. The third pixel circuit CC_3a can be located in the third display region 100A3a. The second pixel circuit CC_2a can be spaced apart from the second pixel electrode AE_2a. For example, the second pixel circuit CC_2a can be located in the third display region 100A3a. The first pixel circuit CC_1a can be superposed with the first pixel electrode AE_1a respectively, the second pixel circuit CC_2a can not be superposed with the second pixel electrode AE_2a when viewed in the third direction DR3. The third pixel circuit CC_3a can be superposed with the third pixel electrode AE_3a respectively.

[0222] ​The display panel 100-1 can further include connection lines CL_1 for electrically connecting the second pixel electrodes AE_2a to the second pixel circuits CC_2a, respectively. Each of the connection lines CL_1 can include a transparent conductive material. Accordingly, degradation of the transmittance of the second display area 100A2a caused by the connection lines CL_1 can be reduced or minimized.

[0223] FIG. 14 is a cross-sectional view taken along FIG. 13 line III-III' shown in FIG. 1.

[0224] Referring to FIG. 13 and FIG. 14 Since the sixth transistor T6_2a is included in the second pixel circuit CC_2a, the sixth transistor T6_2a can be located in the third display area 100A3a. The second pixel electrode AE_2a can be electrically connected to the sixth transistor T6_2a through the connection line CL_1.

[0225] The connection line CL_1 can include a first connection part CLx and a second connection part CLy. Each of the first connection part CLx and the second connection part CLy can include a transparent conductive material.

[0226] The first connection part CLx can be located on the fifth insulating layer 50. The first connection part CLx can contact the second connection electrode CNE2 through the fifth insulating layer 50.

[0227] A sixth insulating layer 61 is located on the fifth insulating layer 50 and can cover the first connection part CLx. The sixth insulating layer 61 can also be located in the second display area 100A2a. The sixth insulating layer 61 can be an organic layer and can have a single-layer structure or a multi-layer structure. However, embodiments of the inventive concept are not limited thereto.

[0228] The second connection part CLy can be located on the sixth insulating layer 61. The second connection part CLy can contact the first connection part CLx through the sixth insulating layer 61.

[0229] A seventh insulating layer 71 is located on the sixth insulating layer 61 and can cover the second connection part CLy. The seventh insulating layer 71 can also be located in the second display area 100A2a. The seventh insulating layer 71 can be an organic layer and can have a single-layer structure or a multi-layer structure. However, embodiments of the inventive concept are not limited thereto.

[0230] The second pixel electrode AE_2a can be located on the seventh insulating layer 71. The second pixel electrode AE_2a can contact the second connection part CLy through the seventh insulating layer 71.

[0231] The pixel defining film 81 is positioned on the seventh insulating layer 71, and can cover a part of the second pixel electrode AE_2a. In the pixel defining film 81, an opening is defined. The opening of the pixel defining film 81 exposes at least a part of the second pixel electrode AE_2a.

[0232] The light emitting layer EL can be positioned on the second pixel electrode AE_2a. The common electrode CE can be positioned on the light emitting layer EL. The common electrode CE has an integral shape, and can be commonly positioned in a plurality of pixels. In the common electrode CE, an opening CEo can be defined. The opening CEo of the common electrode CE can be superimposed with the transmissive portion BPo of the barrier pattern BP.

[0233] FIG. 15A 、 FIG. 15B and FIG. 15C are diagrams for describing a method for manufacturing an electronic device according to some embodiments of the inventive concept.

[0234] Referring to FIG. 15A , the base layer 111 is formed on the substrate SUB. Thereafter, the circuit layer 112 is formed on the base layer 111. The step of forming the circuit layer 112 can include a step of forming the transistors T1, T2, T3, T4, T5, T6, and T7 (see FIG. 5 ), a step of forming the capacitor CP (see FIG. 5 ), and a step of forming the barrier pattern BP having the transmissive portion BPo. The barrier pattern BP can be positioned on the base layer 111.

[0235] The step of forming the barrier pattern BP can include a step of forming the first barrier pattern BP1 and a step of forming the second barrier pattern BP2. The first barrier pattern BP1 can be formed in the same process as the gate GT (see FIG. 6 ), and the second barrier pattern BP2 can be formed in the same process as the second electrode E2 (see FIG. 6 ).

[0236] Thereafter, the light emitting element layer 113_m is formed on the circuit layer 112. The light emitting element layer 113_m can include the pixel electrode AE, the light emitting layer EL positioned on the pixel electrode AE, respectively, and the common electrode CE_m continuously positioned on the light emitting layer EL.

[0237] The common electrode CE_m can be formed over the entire display area 100A (see FIG. 2 ), and the common electrode CE_m can be formed in a region superimposed with the transmissive portion BPo of the barrier pattern BP.

[0238] Referring to FIG. 15B , an example of the back surface of the display panel 100m during the manufacturing process is illustrated. The barrier pattern BP can be provided to be superimposed with the second display area 100A2 (see FIG. 4) superimposed.

[0239] According to some embodiments of the present inventive concept, the laser irradiation area LSA can be superimposed with the second display area 100A2 (see FIG. 4 ). That is, the second display area 100A2 (see FIG. 4 ) can be entirely scanned by the laser beam. The blocking pattern BP blocks the laser beam so that it can be possible to prevent the portion of the common electrode CE_m superimposed with the blocking pattern BP from being heated by the laser beam. The transmission portion BPo of the blocking pattern BP can transmit the laser beam. Thus, some areas of the common electrode CE_m superimposed with the transmission portion BPo can be heated by the laser beam.

[0240] When patterning a portion of the common electrode CE_m by selectively irradiating the laser beam on a specific area in the second display area 100A2 (see FIG. 4 ), the laser beam can be irradiated on an area smaller than the specific area in consideration of a laser processing tolerance. Thus, the area of the opening formed in the common electrode CE_m can be reduced. However, according to some embodiments of the present inventive concept, because the blocking pattern BP blocks the laser beam, the laser beam can be irradiated on the entire laser irradiation area LSA regardless of the laser processing tolerance. Thus, the area of the opening CEo formed in the common electrode CE_m can become larger than the area of the opening CEo formed in the common electrode CE_m of the comparative example. As a result, when patterning is performed by irradiating the laser beam on the entire second display area 100A2 (see FIG. 4 ), the transmittance of the second display area 100A2 can be further improved.

[0241] Referring to FIG. 15C , a step of removing the portion of the common electrode CE_m superimposed with the transmission portion BPo is shown. The laser beam LR is irradiated in a direction from the base layer 111 toward the common electrode CE_m. The portion of the common electrode CE_m superimposed with the transmission portion BPo can be heated by the laser beam LR. That is, a portion of the common electrode CE_m can be heated and melted. Thereafter, the portion of the common electrode CE_m can be cooled. When the portion of the common electrode CE_m that has been heated is cooled, the portion CE_sp of the common electrode CE_m can be removed.

[0242] According to the above description, the common electrode can have a plurality of openings defined therein. Accordingly, the transmittance of some areas of the display panel which are overlapped with the electronic module can be improved. In addition, a laser beam used in a process of forming a plurality of openings in the common electrode can be partially blocked by a blocking pattern in which a plurality of transmission portions are defined, and can be partially transmitted. When a plurality of openings are formed in the common electrode, the laser beam can be irradiated over the entire laser irradiation area without considering a laser processing tolerance. Accordingly, the area of the openings formed in the common electrode according to some embodiments of the inventive concept can be greater than the area of the openings formed considering the shape of the openings and the laser processing tolerance. As a result, the transmittance of some areas of the display panel can be further improved.

[0243] While aspects of the inventive concept have been described with reference to certain example embodiments, it will be understood by those skilled in the art that various changes in form and details can be made therein without departing from the spirit and scope of the inventive concept as set forth in the claims. Accordingly, the technical scope of embodiments of the inventive concept is not intended to be limited to what is set forth in the detailed description of the specification but is intended to be defined by the appended claims and their equivalents.

Claims

1. An electronic device, the electronic device comprising: A display panel includes a display area, the display area including a first display area and a second display area, the second display area having a higher transmittance than the first display area; as well as An electronic module is located below the second display area of ​​the display panel, wherein the display panel includes: Matrix layer; Multiple first pixel electrodes are located on the substrate layer and in the first display area; Multiple second pixel electrodes are located on the substrate layer and in the second display area; A common electrode, located on the plurality of first pixel electrodes and the plurality of second pixel electrodes, and defining a plurality of openings in the common electrode; and A blocking pattern is spaced apart from the common electrode, and the plurality of second pixel electrodes are placed between the blocking pattern and the common electrode. The blocking pattern also defines a plurality of transmissive portions that overlap with the plurality of openings. The plurality of second pixel electrodes and the plurality of openings are all stacked with the electronic module.

2. The electronic device according to claim 1, wherein, The display panel also includes: Multiple first pixel circuits are electrically connected to the multiple first pixel electrodes, respectively; and A plurality of second pixel circuits are electrically connected to the plurality of second pixel electrodes, wherein each of the plurality of first pixel circuits and the plurality of second pixel circuits includes: a transistor, including a gate, an active region, a source, and a drain; and a capacitor, including a first electrode electrically connected to the transistor and a second electrode facing the first electrode.

3. The electronic device according to claim 2, wherein, The blocking pattern includes a first blocking pattern and a second blocking pattern located on the first blocking pattern, wherein: The first barrier pattern is located on the same layer as the gate and includes the same material as the gate. The second blocking pattern is located on the same layer as the second electrode and includes the same material as the second electrode.

4. The electronic device according to claim 3, wherein, The blocking pattern also includes a third blocking pattern located below the first blocking pattern.

5. The electronic device according to claim 4, wherein, The display panel further includes a barrier layer located on the substrate layer and a buffer layer located on the barrier layer, wherein: The barrier layer includes a first sub-barrier layer located on the substrate layer and a second sub-barrier layer located on the first sub-barrier layer, and The third blocking pattern is located between the blocking layer and the buffer layer, or between the first sub-blocking layer and the second sub-blocking layer.

6. The electronic device according to claim 4, wherein, In the first blocking pattern, the second blocking pattern, and the third blocking pattern, a plurality of first transmitting portions, a plurality of second transmitting portions, and a plurality of third transmitting portions are respectively defined and superimposed on the plurality of openings of the common electrode.

7. The electronic device according to claim 2, wherein, The blocking pattern is located on the same layer as the gate or the second electrode, and includes the same material as the gate or the second electrode.

8. The electronic device according to claim 2, wherein, The display panel also includes a peripheral area adjacent to the display area, and The plurality of first pixel circuits are located in the first display area, and the plurality of second pixel circuits are located in the peripheral area.

9. The electronic device according to claim 2, wherein, The display panel further includes multiple connecting lines that electrically connect the plurality of second pixel electrodes and the plurality of second pixel circuits respectively, and each of the multiple connecting lines includes a transparent conductive material.

10. The electronic device according to claim 2, wherein, The display area further includes a third display area located between the first display area and the second display area, and the plurality of second pixel circuits are located in the third display area.

11. The electronic device according to claim 10, wherein, The display panel further includes: a plurality of third pixel electrodes located on the substrate layer and in the third display region; and a plurality of third pixel circuits located in the third display region and electrically connected to the plurality of third pixel electrodes, wherein a first number of the plurality of first pixel electrodes located in the first region is greater than each of a second number of the plurality of second pixel electrodes located in a second region having the same size as the first region and a third number of the plurality of third pixel electrodes located in a third region having the same size as the first region.

12. The electronic device according to claim 1, wherein, The plurality of openings and the plurality of transmissive portions are located in the second display area.

13. The electronic device according to claim 1, wherein, In the plan view, the plurality of transmissive portions and the plurality of openings are spaced apart from the plurality of second pixel electrodes.

14. An electronic device, the electronic device comprising: A display panel, wherein a display area is defined; as well as The electronic module is located below the display area of ​​the display panel, wherein The display panel includes: A light-emitting element has a pixel electrode located in the display area, a light-emitting layer located on the pixel electrode, and a common electrode located on the light-emitting layer; A blocking pattern is located below the light-emitting element, and the blocking pattern has a transmissive portion in a region spaced apart from the pixel electrode in a plan view; A pixel circuit, spaced apart from the pixel electrode and electrically connected to the light-emitting element; and A connecting line electrically connects the pixel circuit and the pixel electrode and includes a transparent conductive material, wherein, in the planar view, the portion of the common electrode overlapping the transmissive portion is removed. The light-emitting element is stacked with the electronic module.

15. The electronic device according to claim 14, wherein, The display panel also includes a peripheral area adjacent to the display area, and The pixel circuit is located in the peripheral region.

16. The electronic device according to claim 14, wherein, The pixel circuit includes: a transistor, including a gate, an active region, a source, and a drain; and a capacitor, including a first electrode electrically connected to the transistor and a second electrode facing the first electrode, and the blocking pattern includes a first blocking pattern and a second blocking pattern located on the first blocking pattern, wherein the first blocking pattern is located on the same layer as the gate and includes the same material as the gate, and the second blocking pattern is located on the same layer as the second electrode and includes the same material as the second electrode.

17. A method for manufacturing an electronic device, the method comprising the following steps: Set a base layer; A circuit layer is disposed on the substrate layer, the circuit layer including a blocking pattern having a transmissive portion; A light-emitting element is provided, the light-emitting element including a pixel electrode located on the circuit layer, a light-emitting layer located on the pixel electrode, and a common electrode located on the light-emitting layer; as well as The portion of the common electrode overlapping with the transmissive portion is removed by irradiating the common electrode with a laser in a direction from the substrate layer toward the common electrode. In this process, the blocking pattern acts as a mask to partially block the laser.

18. The method according to claim 17, wherein, The steps for setting the circuit layer also include: The transistor comprises a gate, an active region, a source, and a drain; and A capacitor is provided, the capacitor including a first electrode electrically connected to the transistor and a second electrode facing the first electrode, wherein the pixel electrode is spaced apart from the transistor.

19. The method according to claim 18, wherein, The step of setting the circuit layer including the blocking pattern includes setting a first blocking pattern and setting a second blocking pattern on the first blocking pattern, wherein the first blocking pattern is set in the same process as the gate, and the second blocking pattern is set in the same process as the second electrode.

20. The method according to claim 18, wherein, The step of setting the circuit layer further includes setting a connection line that electrically connects the transistor and the pixel electrode, wherein the connection line comprises a transparent conductive material.

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