Semiconductor package structure

Abstract

The present invention relates to a semiconductor package structure. The semiconductor package structure includes a substrate, a circuit layer on the substrate, a first underfill between the circuit layer and the substrate and around sidewalls of the circuit layer, and the first underfill has an upper surface coplanar with an upper surface of the circuit layer.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and more specifically, to a semiconductor packaging structure. Background Technology

[0002] refer to Figure 1A As shown, in the current packaging process, the main steps involve attaching the redistribution layer 10 to the carrier 30, bonding the RDL layer 10 and the carrier 30 to the substrate 20, and then forming the underfill 15. However, in this process, the underfill 15 may creep onto the sidewalls of the carrier 30 before the carrier 30 is removed. Because the underfill 15 contacts the sidewalls of the carrier 30, it can easily cause cracking 18 in the underfill 15 or cracking 19 in the RDL layer 10 during debonding of the carrier 30. Figure 1B As shown.

[0003] In addition, if the RDL layer is mounted on the substrate using a wafer-to-wafer bonding method, although it can avoid the bottom filler from creeping onto the carrier sidewalls, the position of the RDL layer must be based on the size of the substrate. Therefore, the RDL layer will have extra space that cannot be formed into circuits, resulting in a waste of dielectric layer space. Summary of the Invention

[0004] To address the aforementioned problems in related technologies, this invention proposes a semiconductor packaging structure and a method for forming the same.

[0005] According to one aspect of the present invention, a semiconductor package structure is provided, comprising: a substrate; a circuit layer located on the substrate; a first bottom filler located between the circuit layer and the substrate and surrounding the sidewall of the circuit layer, wherein the first bottom filler has an upper surface coplanar with the upper surface of the circuit layer.

[0006] In some embodiments, the sides of the first bottom filler are curved surfaces that protrude away from the circuit layer.

[0007] In some embodiments, the width of the line layer gradually decreases from top to bottom.

[0008] In some embodiments, the side of the first bottom filler has a cross-section at the location where the first bottom filler contacts the substrate, and the cross-section forms an angle with the upper surface of the substrate, the angle being in the range of 30° to 85°.

[0009] In some embodiments, the semiconductor package structure further includes a chip located on a circuit layer, wherein the active side of the chip faces down and is bonded to the circuit layer.

[0010] In some embodiments, the sidewalls of the first bottom filler are perpendicularly aligned with the sidewalls of the substrate.

[0011] In some embodiments, the semiconductor package structure further includes a second underfill material that fills the space between the chip and the circuit layer and surrounds the bottom of the chip.

[0012] In some embodiments, the circuit layer includes a metal ring structure exposed on the upper surface of the circuit layer, the metal ring structure being embedded in the circuit layer at a location adjacent to the first bottom filler.

[0013] In some embodiments, the circuit layer has vias, with the wider end of the via facing the substrate.

[0014] In some embodiments, a first pad is provided on the lower surface of the circuit layer, and a second pad is provided on the upper surface of the substrate. The first pad and the second pad are bonded to each other by solder.

[0015] In some embodiments, a first pad is provided on the lower surface of the circuit layer, and a second pad is provided on the upper surface of the substrate, with the first pad and the second pad being directly bonded.

[0016] According to another aspect of the present invention, a method for forming a semiconductor package structure is provided, comprising: step S1, providing a carrier; step S2, forming a dielectric layer on a portion of the surface of the carrier, and forming a circuit layer on the dielectric layer to form a line layer; step S3, bonding the line layer to a substrate, and forming a first underfill between the line layer and the substrate; and step S4, removing the carrier.

[0017] In some embodiments, step S2 includes: masking the carrier with a mask; forming a dielectric layer on the surface of the carrier not masked by a printing process.

[0018] In some embodiments, step S3 includes: forming a first bottom filler on a substrate; and mounting a circuit layer on the substrate.

[0019] In some embodiments, a first underfill is locally formed on a substrate using a printing process, and a circuit layer is placed on the first underfill on the substrate.

[0020] In some embodiments, before the circuit layer is placed, the upper surface of the first bottom filler on the substrate includes a protruding curved surface, and after the circuit layer is mounted on the substrate, the upper surface of the first bottom filler is coplanar with the upper surface of the circuit layer.

[0021] In some embodiments, after the circuit layer is mounted on the substrate, the side of the first bottom filler is a curved surface that protrudes away from the circuit layer.

[0022] In some embodiments, step S3 includes bonding the circuit layer to the substrate using a reflow process.

[0023] In some embodiments, prior to step S4, the upper surface of the first bottom filler is in direct contact with the carrier.

[0024] In some embodiments, the method further includes: bonding a chip to a circuit layer; and filling a second underfill material between the chip and the circuit layer. Attached Figure Description

[0025] The various aspects of the invention will be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, according to standard industrial practice, the components are not drawn to scale. In fact, the dimensions of the components may be arbitrarily increased or decreased for clarity of discussion.

[0026] Figure 1A and Figure 1B A schematic diagram of an existing semiconductor packaging structure is shown.

[0027] Figure 2A This is a schematic diagram of a semiconductor packaging structure according to an embodiment of the present invention.

[0028] Figure 2B yes Figure 2A A magnified view of a portion of region A1 in the middle.

[0029] Figures 3A to 3C as well as Figures 4A to 4C A partially enlarged view of the connection between the circuit layer and the substrate according to various embodiments of the present invention is shown.

[0030] Figure 5A and Figure 5B A partially enlarged view of the connection between the circuit layer and the substrate according to another embodiment of the present invention is shown.

[0031] Figures 6 to 9B A schematic diagram of a semiconductor package structure according to another embodiment of the present invention is shown.

[0032] Figures 10A to 10O A schematic diagram of the multiple stages of forming the circuit layers of a semiconductor package structure is shown.

[0033] Figures 11A to 11G A schematic diagram of several other stages in forming a semiconductor package structure is shown. Specific Implementation

[0034] The following disclosure provides numerous different embodiments or instances for implementing various features of the provided subject matter. Specific examples of elements and arrangements will be described below to simplify the invention. These are merely examples and are not intended to limit the invention. For example, in the following description, forming a first component above or on a second component can include embodiments where the first and second components are in direct contact, or embodiments where an additional component is formed between the first and second components such that the first and second components are not in direct contact. Furthermore, reference numerals and / or letters may be repeated throughout the various instances. Such repetition is for brevity and clarity only and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0035] Figure 2A This is a schematic diagram of a semiconductor packaging structure according to an embodiment of the present invention. (Reference) Figure 2A As shown, a circuit layer 120 is disposed on the substrate 110. In some embodiments, the circuit layer 120 may be a redistribution layer (RDL) or, for example, an interposer. A first underfill 130 is formed between the circuit layer 120 and the substrate 110. The first underfill 130 also surrounds the sidewalls of the circuit layer 120, and the upper surface of the first underfill 130 is coplanar with the upper surface of the circuit layer 120. Since the upper surface of the first underfill 130 is flush with the upper surface of the circuit layer 120, the first underfill 130 will not come into contact with the sidewalls of the carrier with the circuit layer 120 during the manufacturing process, thus avoiding problems such as underfill breakage or circuit layer breakage during or after carrier removal.

[0036] Continue to refer to Figure 2A As shown, the upper surface of the first bottom filler 130 is coplanar with the upper surface of the circuit layer 120, and the lower surface of the first bottom filler 130 is coplanar with the upper surface of the substrate 110. The side surface of the first bottom filler 130 connects the upper and lower surfaces. The side surface of the first bottom filler 130 is a curved structure protruding away from the circuit layer 120. The first bottom filler 130 with curved side surface can help protect the circuit layer 120 inside it, and the first bottom filler 130 filled between the circuit layer 120 and the substrate 110 can also protect the connecting components connecting the circuit layer 120 and the substrate 110.

[0037] At the location where the first bottom filler 130 contacts the upper surface of the substrate 110, an angle θ is formed between the cut surface P, which is tangent to the curved side surface of the first bottom filler 130, and the upper surface of the substrate 110. In some embodiments, the angle θ is in the range of 30° to 85°.

[0038] In the illustrated embodiment, the sidewalls of the circuit layer 120 have an inverted conical profile, and the width of the circuit layer 120 gradually decreases from top to bottom. The circuit layer 120 may include multiple stacked dielectric layers 122, 124, 126 and circuits located within the dielectric layers 122, 124, 126, including multilayer traces 128 and vias 129 interconnecting adjacent layer traces 128. In some embodiments, the materials of the respective dielectric layers 122, 124, 126 may be organic materials such as PI (polyimide), epoxy resin, acrylic acid, ABF (alloy film), PP (polypropylene), and / or molding compounds. In some embodiments, the thickness IDT of the respective dielectric layers 122, 124, 126 may be in the range of 5 μm to 20 μm. Furthermore, the lowermost dielectric layer 126 of the circuit layer 120, closest to the substrate 110, may extend upward to form the sidewalls of the circuit layer 120. In some embodiments, an angle α is formed between the sidewall of the circuit layer 120 formed by the lowermost dielectric layer 126 and the upper surface of the circuit layer 120, and the angle α is in the range of 30° to 85°.

[0039] Line layer 120 can be a redistribution layer with fine lines. In such an embodiment, the linewidth of the fine lines can be in the range of 0.5 μm to 10 μm, the spacing between the fine lines can be in the range of 0.5 μm to 10 μm, and the pitch between the fine lines can be in the range of 1 μm to 20 μm. Figure 2A As shown, the widths of the two ends of the via 129 in the circuit layer 120 are different. The wider end of the via 129 faces the substrate 110, giving the sidewall of the via 129 a tapered profile. That is, the width of the via 129 gradually increases from top to bottom.

[0040] Furthermore, chip 150 is bonded to the upper surface of circuit layer 120. Figure 2A In one embodiment, the active side of chip 150 is bonded to the circuit layer 120 with the active side facing down. A second bottom filler 160 is filled between chip 150 and circuit layer 120 and surrounds the lower part of chip 150.

[0041] In some embodiments, the width US of the upper surface of the first underfill 130 is in the range of 5 mm to 100 mm. The width ODS of the lower surface of the circuit layer 120 can be in the range of 2 mm to 100 mm. The width US of the upper surface of the first underfill 130 can be 1 to 2 times larger than the width ODS of the lower surface of the circuit layer 120. The thickness of the first underfill 130 can be in the range of 10 μm to 100 μm. At the upper surface of the first underfill 130, the distance DAD between the edge of the first underfill 130 and the edge of the circuit layer 120 can be in the range of 5 μm to 30 μm. The above dimensional configurations are merely examples, and other appropriate configurations can be made for the dimensions of the various components.

[0042] Figure 2B yes Figure 2A A magnified view of a portion of region A1 in the middle. (See diagram below.) Figure 2B As shown, a metal ring structure 170 is embedded in the circuit layer 120 near the first bottom filler 130. The metal ring structure 170 is exposed on the upper surface of the circuit layer 120. In some embodiments, the metal ring structure 170 includes two metal material layers 172 and 176 and a seed layer 174 sandwiched between the two metal material layers 172 and 176, wherein the width of the exposed metal material layer 172 may be greater than the width of the other underlying metal material layer 176.

[0043] The upper surface of the circuit layer 120 has a recess at the metal ring structure 170. The dielectric layer 124 in the circuit layer 120 forms one sidewall of the recess, and the first bottom filler 130 forms the other sidewall of the recess. The second bottom filler 160 fills the recess in the metal ring structure 170. By providing the metal ring structure 170 at the edge of the upper surface of the circuit layer 120 and having a recess in the metal ring structure 170, the second bottom filler 160 can be prevented from overflowing to the first bottom filler 130 outside the circuit layer 120; in addition, the adhesion between the second bottom filler 160 at the corner R1, the dielectric layer 126 in the circuit layer 120, and the first bottom filler 130 can be increased.

[0044] In some embodiments, the material of the first underfill 130 or the second underfill 160 may be a liquid material or a dry film material. In some embodiments, the material of the first underfill 130 or the second underfill 160 may be an organic material such as PI, epoxy resin, acrylic, ABF, PP and / or molding compound.

[0045] Figures 3A to 3C as well as Figures 4A to 4C A partially enlarged view is shown of the connection between the circuit layer and the substrate according to various embodiments of the present invention. Figures 3A to 3CIn the illustrated embodiment, a first pad 1201 is provided on the lower surface of the circuit layer 120 (not shown), and a second pad 1101 is provided on the upper surface of the substrate 110. The first pad 1201 on the lower surface of the circuit layer 120 and the second pad 1101 on the upper surface of the substrate 110 are connected by solder 1205. Figure 3A In the illustrated embodiment, solder 1205 has sidewalls with a curved structure and solder 1205 also extends onto a portion of the upper surface of substrate 110. Figure 3B In the illustrated embodiment, the width of the top end of the solder 1205 is greater than the width of the bottom end, and the sidewalls of the solder 1205 have a concave curved surface structure. Figure 3C In the embodiment shown, the width of the top end of the solder 1205 is greater than the width of the bottom end, and the sidewalls of the solder 1205 are inclined straight lines, thus having an inverted conical structure.

[0046] exist Figures 3A to 3C In the illustrated embodiment, the material of the first bottom filler 130 is a non-conductive adhesive (NCP), such as ABF or other adhesive materials. In such an embodiment, as... Figure 3A As shown, the upper surface of the substrate 110 has a recess 1103 exposing the second pad 1101. Solder 1205 completely fills the recess 1103 on the second pad 1101, and the entire surface of the second pad 1101 is in contact with the solder 1205 within the recess 1103. Figure 3B and Figure 3C In the example shown, solder 1205 extends into a recess 1103 of substrate 110 to engage with a second pad 1101, with a gap between solder 1205 and the sidewall of recess 1103. A first underfill 130 completely fills the gap between solder 1205 and the sidewall of recess 1103.

[0047] Figures 4A to 4C The solders in the illustrated embodiments have respectively with Figures 3A to 3C A similar structure. In Figures 4A to 4C In the illustrated embodiment, the material of the first bottom filler 130 is a non-conductive film (NCF). In such an embodiment, as... Figure 4A As shown, the solder 1205 does not completely fill the recess 1103 on the second pad 1101, resulting in a gap 1109 between the sidewall of the recess 1103, the upper surface of the second pad 1101, and the solder 1205. Figure 4B and Figure 4C In the example shown, the first bottom filler 130 does not completely fill the gap between the solder 1205 and the sidewall of the recess 1103. A gap 1109 is formed at the corner where the sidewall of the recess 1103 intersects with the upper surface of the second pad 1101, and the gap 1109 can extend between the upper surface of the second pad 1101 and the solder 1205.

[0048] Figure 5A and Figure 5B A partially enlarged view of the connection between the circuit layer and the substrate according to other embodiments of the present invention is shown. Figure 5A and Figure 5B As shown, a first pad 1201 is located on the lower surface of the circuit layer 120 (not shown), and a second pad 1101 is located on the upper surface of the substrate 110. The first pad 1201 and the second pad 1101 are directly bonded, for example, by a copper-copper (Cu-Cu) bond. Figure 5A In the illustrated embodiment, since the first pad 1201 and the second pad 1101 are copper-copper bonded, the opposing surfaces of the first pad 1201 and the second pad 1101 will be recessed, forming a gap 1110 between the first pad 1201 and the second pad 1101. In embodiments where the first underfill 130 uses NCP, such as Figure 5A The first bottom filler 130 will fill the gap between the first pad 1201 and the second pad 1101. Figure 5B In the embodiment shown, the first bottom filler 130 is made of organic material, and a gap 1112 is formed at the corner where the first pad 1201 and the second pad 1101 intersect.

[0049] Figure 6 A schematic diagram of a semiconductor package structure according to another embodiment of the present invention is shown. Figure 6 In the illustrated embodiment, the first bottom filler 130 may not have curved sidewalls, but rather vertically extending sidewalls. Furthermore, the sidewalls of the first bottom filler 130 are vertically aligned with the sidewalls of the substrate 110.

[0050] Figures 7A to 7C A schematic diagram of a semiconductor package structure according to another embodiment of the present invention is shown. Figure 7A and Figure 7C In the illustrated embodiment, a protective layer 180 is also disposed above the substrate 110. The material of the protective layer 180 can be, for example, molding compound or any other suitable material. The protective layer 180 surrounds the first underfill 130, the second underfill 160, and the chip 150. Figure 7A In the example, the sidewalls of the protective layer 180 are perpendicularly aligned with the sidewalls of the substrate 110 to cover the entire surface of the substrate 110, and the protective layer 180 may cover the upper surface of the chip 150. Figure 7B In the example, the sidewalls of the protective layer 180 are perpendicularly aligned with the sidewalls of the substrate 110, the protective layer 180 exposes the upper surface of the chip 150, and the upper surface of the protective layer 180 is coplanar with the upper surface of the chip 150. Figure 7CIn this example, the protective layer 180 does not cover the entire surface of the substrate 110. The sidewalls of the protective layer 180 are located between the sidewalls of the substrate 110 and the sidewalls of the first bottom filler 130. The protective layer 180 covers the upper surface of the chip 150. In other embodiments, the protective layer 180 may not cover the upper surface of the chip 150.

[0051] Figure 8 A schematic diagram of a semiconductor package structure according to other embodiments of the present invention is shown. For example... Figure 8 As shown, chip 150 can be disposed on circuit layer 120 with its active side facing upwards, and the active side of chip 150 is electrically connected to circuit layer 120 and substrate 110 via lead 802. In this embodiment, a second bottom filler may not be formed around chip 150, but a protective layer 180 may be formed to protect lead 802.

[0052] Figures 9A to 9B A schematic diagram of a semiconductor package structure according to other embodiments of the present invention is shown. For example... Figure 9A As shown, chip 150 can be bonded onto two circuit layers 120, each circuit layer 120 can be surrounded by a separate first underfill 130. Furthermore, a second underfill 160 can fill the gap between the two first underfills 130. Figure 9B As shown, two chips 150 can be bonded on a single circuit layer 120, each chip 150 being surrounded by a separate second underfill 160.

[0053] Figures 6 to 9B Other aspects of the illustrated embodiments may be consistent with the references. Figure 2A The content discussed is similar or the same, so it will not be described again.

[0054] According to embodiments of the present invention, a method for forming a semiconductor package structure is also provided. Figures 10A to 10O A schematic diagram of the multiple stages of forming the circuit layers of a semiconductor package structure is shown.

[0055] First refer to Figure 10A As shown, a patterned first seed layer 211 and a metal layer 231 located on the first seed layer 211 are formed on the carrier 201. Figure 10A The diagram shows two sets of patterned first seed layers 211 and metal layers 231 spaced apart from each other. It should be understood that more sets of first seed layers 211 and metal layers 231 spaced apart can be formed on the carrier 201.

[0056] like Figure 10BAs shown, a portion of the carrier 201 is masked by a mask 310, exposing another portion of the carrier 201. The mask 310 exposes the first seed layer 211 and the metal layer 231 on the carrier 201. A first dielectric layer 122 is formed on the surface of the carrier 201 that is not masked using a printing process. The first dielectric layer 122 covers the patterned first seed layer 211 and the metal layer 231. Then, a photolithography process is performed on the first dielectric layer 122.

[0057] like Figure 10C As shown, the photolithography process forms a plurality of openings 241 in the first dielectric layer 122, which expose the metal layer 231. A second seed layer 212 is formed on the carrier 201 and the first dielectric layer 122 and within the openings 241 of the first dielectric layer 122.

[0058] Then as Figure 10D As shown, a portion of the carrier 201 is covered by a mask 310, exposing another portion of the carrier 201. The mask 310 exposes the portion corresponding to the first dielectric layer 122. A first mask layer 251 is formed on a second seed layer 212 on the first dielectric layer 122 that is not covered by the mask 310 using a printing process.

[0059] like Figure 10E As shown, a photolithography process is performed on the first mask layer 251. The photolithography process forms multiple openings 242 in the first mask layer 251, with the openings 22 in the first mask layer 251 located above the openings 241 in the first dielectric layer 122. Then, metal material 270 is filled into the openings 242 in the first mask layer 251 and onto the second seed layer 212 not covered by the first mask layer 251. Afterwards, as... Figure 10F As shown, the first mask layer 251 and the second seed layer 212 located below the first mask layer 251 are removed. The second seed layer 212 and the metal material 270 within the opening 241 of the first dielectric layer 122 form a via, and the second seed layer 212 and the metal material 270 on the first dielectric layer 122 form a trace. Here, in the region outside the first dielectric layer 122, the second seed layer 212 and the metal material 270 that form the traces and vias on the carrier 201 are retained.

[0060] Then, you can refer to Figures 10B to 10F The second dielectric layer 124 continues to be formed in this manner. For example... Figure 10GAs shown, the second dielectric layer 124 covers the upper surface and sidewalls of the first dielectric layer 122. The edge of the second dielectric layer 124 also covers a portion of the second seed layer 212 and the metal material 270 thereon. Traces are formed on the second dielectric layer 124, and vias through the second dielectric layer 124 electrically connect adjacent traces. In the region outside the second dielectric layer 124, the third seed layer 213, which forms traces and vias, and the metal material 270 thereon are also retained. The third seed layer 213 and the metal material 270 thereon are located above the second seed layer 212 and the metal material 270 thereon, and the dimensions of the third seed layer 213 and the metal material 270 thereon are smaller than those of the second seed layer 212 and the metal material 270 thereon.

[0061] like Figure 10H As shown, a portion of the carrier 201 is masked by a mask 310, exposing another portion of the carrier 201. The mask 310 exposes the second dielectric layer 124. A third dielectric layer 126 is formed on the second dielectric layer 124, which is not masked by the mask 310, using a printing process, as shown. Figure 10I As shown, the formed third dielectric layer 126 covers the upper surface and sidewalls of the second dielectric layer 124. The third dielectric layer 126 also covers a portion of the third seed layer 213 and the metal material 270 thereon. Then, a photolithography process is performed on the third dielectric layer 126.

[0062] like Figure 10J As shown, the photolithography process forms multiple openings 243 in the third dielectric layer 126, each exposing the underlying traces. A fourth seed layer 214 is formed over the carrier 201 and the third dielectric layer 126, as well as within the openings 243 of the third dielectric layer 126.

[0063] like Figure 10K As shown, a second mask layer 252 is covered on the fourth seed layer 214. Photolithography is then performed on the second mask layer 252. (As shown...) Figure 10L As shown, the photolithography process forms multiple openings 244 in the second mask layer 252, and the openings 244 in the second mask layer 252 are located above the openings 243 in the third dielectric layer 126. Then, metal material 270 is filled into the fourth seed layer 214 through the openings 244 in the second mask layer 252, and solder 275 is formed on top of the metal material 270.

[0064] Then as Figure 10M As shown, the fourth seed layer 214 exposed on the second mask layer 252 and the third dielectric layer 126 is removed.

[0065] like Figure 10NAs shown, excess seed layers 212 and 213 and metal material 270 are further removed from the region outside the third dielectric layer 126. At the edge of the third dielectric layer 126, the third seed layer 213 covered by the third dielectric layer 126 and the metal material 270 thereon are retained, while the second seed layer 212 covered by the second dielectric layer 124 and the third dielectric layer 126 and the metal material 270 thereon are retained.

[0066] Then a reflow process is performed, which forms solder 275 into solder balls 276, thereby forming circuit layer 120, such as... Figure 10O As shown. The formed circuit layer 120 includes: a first dielectric layer 122, a second dielectric layer 124, and a third dielectric layer 126 covering the first seed layer 211 and the metal layer 231; traces and vias located in the first dielectric layer 122, the second dielectric layer 124, and the third dielectric layer 126; and solder balls 276 located on the third dielectric layer 126. Furthermore, at the bottom edge of the circuit layer 120, there is a stacked structure of the second seed layer 212, the metal material 270, the third seed layer 213, and the metal material 270.

[0067] Figures 11A to 11G Schematic diagrams are shown illustrating several additional stages in the formation of a semiconductor package structure. For example... Figure 11A As shown, a first underfill 130 is formed on a substrate 110. The first underfill 130 can be formed partially and intermittently on the substrate 110 using a printing process. After the first underfill 130 is formed, the first underfill 130 on the substrate 110 has a profile whose upper surface includes a protruding curved surface.

[0068] like Figure 11B As shown, the circuit layer 120 pre-formed on the carrier 201 is mounted opposite to the first bottom filler 130 on the substrate 110.

[0069] like Figure 11C As shown, the circuit layer 120 extends through the first underfill 130 to connect to the substrate 110, forming the first underfill 130 between the circuit layer 120 and the substrate 110. The circuit layer 120 and the substrate 110 can be bonded using solder balls 276 via a reflow process. After bonding, the upper surface of the first underfill 130 is in direct contact with the carrier 201. Therefore, after the circuit layer 120 is mounted on the substrate 110, the upper surface of the first underfill 130 is flush with the upper surface of the circuit layer 120. Furthermore, after the circuit layer 120 is mounted on the substrate 110, the sides of the first underfill 130 are curved surfaces protruding away from the circuit layer 120. The carrier 201 is then removed, as... Figure 11DAs shown. After removing the carrier 201, the first seed layer 211 in the circuit layer 120 and the second seed layer 212 at the edge of the circuit layer 120 are exposed. Then, the first seed layer 211 and the second seed layer 212 in the exposed circuit layer 120 are etched to remove the first seed layer 211 and the second seed layer 212.

[0070] like Figure 11E As shown, after removing the first seed layer 211 and the second seed layer 212, a metal layer 231 is exposed. The metal layer 231 can then be used as a pad to bond to the chip 150, thereby bonding the chip 150 onto the circuit layer 120. Additionally, after removing the first seed layer 211, metal material 270 at the edge of the circuit layer 120 is also exposed, thus forming a metal ring structure 170 with the metal material 270, the underlying third seed layer 213, and the metal material 270 below the third seed layer 213. Since the second seed layer 212 on the metal material 270 is removed, a recess 288 is formed in the metal ring structure 170. One sidewall of the recess 288 exposes a first bottom filler 130.

[0071] like Figure 11F As shown, a second underfill 160 is formed. The second underfill 160 fills the space between the chip 150 and the circuit layer 120. The second underfill 160 also fills the recess 288 on the metal ring structure 170. By providing the metal ring structure 170 at the edge of the circuit layer 120 and providing the recess 288 on the metal ring structure 170, the formed second underfill 160 can be prevented from overflowing to the first underfill 130 outside the circuit layer 120; in addition, the adhesion between the second underfill 160 at the corner, the dielectric layer in the circuit layer 120, and the first underfill 130 can be increased.

[0072] like Figure 11G As shown, the substrate 110 is cut along the dashed line L to form the final packaging structure.

[0073] In the above method, firstly, dielectric layers and mask layers are coated at certain regular locations (e.g., an array) on the surface of the carrier 201 using printing technology. In each dielectric layer, traces and vias are formed as a circuit layer 120 by photolithography. Next, a first underfill 130 is coated again on the surface of the substrate 110 using printing technology, bonding the carrier 201 with the circuit layer 120 to the substrate 110. The carrier 201 is then removed, leaving a flat upper surface of the first underfill 130. Finally, the chip 150 is bonded to the circuit layer 120. This invention utilizes printing technology to locally fabricate a circuit layer 120 on a carrier 201. The printing technology allows the circuit layer 120 to be formed into mutually spaced units. Then, a first underfill material 130 is applied to the substrate 110 at the location where the circuit layer 120 is to be connected. The circuit layer 120 is then flip-chip bonded to the substrate 110 through a reflow process. After the carrier 201 is removed, the first underfill material 130 will be coplanar with the upper surface of the circuit layer 120 and will not contact the sidewall of the carrier 201. Therefore, the first underfill material 130 or the circuit layer 120 can be prevented from cracking when the carrier 201 is removed.

[0074] The foregoing summary outlines features of several embodiments that enable those skilled in the art to better understand various aspects of this disclosure. Those skilled in the art should understand that other processes and structures can be readily designed or modified based on this invention to achieve the same objectives and / or benefits as the embodiments described herein. Those skilled in the art should also recognize that these equivalent structures do not depart from the spirit and scope of the invention, and that various changes, substitutions, and modifications can be made without departing from the spirit and scope of the invention.

Claims

1. A semiconductor packaging structure, characterized in that, include: substrate; A circuit layer is located on the substrate, the circuit layer including a dielectric layer and a metal ring structure exposed by the upper surface edge of the circuit layer; The chip is located on the circuit layer; A first bottom filler is located between the circuit layer and the substrate and surrounds the sidewall of the circuit layer, and the first bottom filler has an upper surface that is coplanar with the upper surface of the circuit layer; A second bottom filler is filled between the chip and the circuit layer and surrounds the bottom of the chip; The circuit layer has a recess, the dielectric layer forms one sidewall of the recess, the first bottom filler forms the other sidewall of the recess, the metal ring structure forms the bottom wall of the recess, and the second bottom filler fills the recess.

2. The semiconductor packaging structure according to claim 1, characterized in that, The side of the first bottom filler is a curved surface that protrudes away from the circuit layer.

3. The semiconductor packaging structure according to claim 1, characterized in that, The width of the line layer gradually decreases from top to bottom.

4. The semiconductor packaging structure according to claim 1, characterized in that, At the location where the first bottom filler contacts the substrate, the side of the first bottom filler has a cut surface, and the cut surface forms an angle with the upper surface of the substrate, the angle being in the range of 30° to 85°.

5. The semiconductor packaging structure according to claim 1, characterized in that, The active side of the chip faces down and is bonded to the circuit layer.

6. The semiconductor packaging structure according to claim 1, characterized in that, The sidewall of the first bottom filler is perpendicularly aligned with the sidewall of the substrate.

7. The semiconductor packaging structure according to claim 1, characterized in that, The metal ring structure is embedded in the circuit layer at a location adjacent to the first bottom filler.

8. The semiconductor packaging structure according to claim 1, characterized in that, The circuit layer has through-holes, with the wider end of the through-hole facing the substrate.

9. The semiconductor packaging structure according to claim 1, characterized in that, The lower surface of the circuit layer has a first pad, and the upper surface of the substrate has a second pad. The first pad and the second pad are bonded together by solder.

10. The semiconductor packaging structure according to claim 1, characterized in that, The lower surface of the circuit layer has a first pad, and the upper surface of the substrate has a second pad, which are directly bonded together.

Images