Semiconductor device and method for manufacturing the same

Abstract

The present application provides a semiconductor device and a method for manufacturing the same. In the semiconductor device, each active pattern is divided into multiple sub-patterns by a second isolation structure. Within each active pattern, the contact portion between the sub-pattern and the adjacent second isolation structure, in a plane parallel to the upper surface of the substrate, is arc-shaped and recessed toward the interior of the sub-pattern. Alternatively, each second isolation pattern includes a first isolation portion and a second isolation portion stacked sequentially on the substrate. Within a plane parallel to the upper surface of the substrate, the cross-sectional dimensions of the second isolation portion are larger than those of the first isolation portion. This increases the contact area between the active pattern and other components when contacting the bit line above it, enhancing the contact effect and improving the electrical performance of the device.

Description

Technical Field

[0001] The present application relates to the technical field of semiconductor devices, and in particular to a semiconductor device and a method for preparing the same. Background Art

[0002] As electronic products continue to miniaturize, the design of dynamic random access memory (DRAM) must also meet the requirements of high integration and high density. DRAM with a recessed gate structure has gradually replaced DRAM with only a planar gate structure because it can achieve a longer carrier channel length within the same semiconductor substrate.

[0003] Generally speaking, a DRAM with a recessed gate structure consists of a large number of memory cells (memory cells) clustered together to form an array area for data storage. Each memory cell may consist of a transistor element and a charge storage device connected in series to receive voltage signals from a word line (WL) and a bit line (BL). The bit line structure is electrically connected to the gate structure and active pattern on the substrate via a bit line plug. The bit line plug is set in a contact hole on the substrate surface. The bit line plug includes a seed layer and a semiconductor layer. The bit line plug is formed by filling the contact hole with the seed layer and semiconductor layer and then patterning it.

[0004] As the semiconductor industry enters a new era of high-performance and multifunctional integrated circuits, the density of fine active patterns on substrates will increase, resulting in a corresponding decrease in the size of active patterns and the spacing between them. This reduction in the size of each active pattern also affects the contact between other components and the active pattern, significantly impacting the device's electrical performance. Summary of the Invention

[0005] In response to the above problems, the present application provides a semiconductor device that solves the technical problem in the prior art that the small size of fine active patterns affects their contact effect with other components.

[0006] In a first aspect, the present application provides a semiconductor device, comprising:

[0007] semiconductor substrates;

[0008] A plurality of active patterns are spaced apart on the surface of the substrate; wherein the plurality of active patterns extend along a first direction and are arranged parallel to each other;

[0009] a first isolation structure disposed between any two adjacent active patterns;

[0010] Each of the active patterns is divided into a plurality of sub-patterns by the second isolation structure; in each of the active patterns, in a plane parallel to the upper surface of the substrate, the contact portion between the sub-pattern and the adjacent second isolation structure is in an arc shape that is concave toward the interior of the sub-pattern.

[0011] According to an embodiment of the present application, optionally, in the above-mentioned semiconductor device, the bottom of the second isolation structure and the bottom of the first isolation structure are located at different heights.

[0012] According to an embodiment of the present application, optionally, in the above-mentioned semiconductor device, materials of the first isolation structure and the second isolation structure respectively include different insulating materials.

[0013] According to an embodiment of the present application, optionally, the above-mentioned semiconductor device further includes:

[0014] a plurality of word line structures spaced apart within the surface of the substrate; wherein the plurality of word line structures extend along the second direction and are arranged parallel to each other, and each of the word line structures intersects with at least one of the sub-patterns;

[0015] a first interlayer insulating layer located above the substrate and covering the active pattern and the word line structure;

[0016] A plurality of bit line structures are spaced apart and arranged above the first interlayer insulating layer; wherein the plurality of bit line structures extend along a third direction and are arranged parallel to each other, the bit line structures intersect the word line structures perpendicularly, and each of the bit line structures is connected to at least one of the sub-patterns through a corresponding bit line contact plug.

[0017] According to an embodiment of the present application, optionally, in the above-mentioned semiconductor device,

[0018] The word line structure includes a trench, a gate insulating layer arranged on the sidewall and bottom of the trench, and a gate and a second interlayer insulating layer respectively filling the lower part and the upper part of the trench.

[0019] In a second aspect, the present application provides a semiconductor device, comprising:

[0020] semiconductor substrates;

[0021] A plurality of active patterns are spaced apart on the surface of the substrate; wherein the plurality of active patterns extend along a first direction and are arranged parallel to each other;

[0022] A first isolation structure is provided between any two adjacent active patterns;

[0023] In which, each of the active patterns is cut into multiple sub-patterns by a second isolation structure; each of the second isolation patterns includes a first isolation part and a second isolation part stacked in sequence on the substrate; in a plane parallel to the upper surface of the substrate, the cross-sectional size of the second isolation part is larger than the cross-sectional size of the first isolation part.

[0024] According to an embodiment of the present application, optionally, the above-mentioned semiconductor device further includes:

[0025] a storage node contact plug extending into the substrate surface and contacting an end portion of the sub-pattern;

[0026] The storage node contact plug extends into the substrate surface to a depth greater than or equal to a depth of the second isolation portion.

[0027] According to an embodiment of the present application, optionally, in the above-mentioned semiconductor device, in each of the active patterns, in a plane parallel to the upper surface of the substrate, a contact portion between the sub-pattern and the adjacent second isolation structure is in the shape of an arc recessed into the interior of the sub-pattern.

[0028] According to an embodiment of the present application, optionally, in the above-mentioned semiconductor device, the lower surface of the second isolation part completely covers the upper surface of the first isolation part.

[0029] According to an embodiment of the present application, optionally, in the above-mentioned semiconductor device, the bottom of the first isolation portion and the bottom of the first isolation structure are located at different heights.

[0030] According to an embodiment of the present application, optionally, in the above-mentioned semiconductor device, materials of the first isolation structure and the second isolation structure include different insulating materials respectively.

[0031] According to an embodiment of the present application, optionally, the above-mentioned semiconductor device further includes:

[0032] a plurality of word line structures spaced apart within the surface of the substrate; wherein the plurality of word line structures extend along the second direction and are arranged parallel to each other, and each of the word line structures intersects with at least one of the sub-patterns;

[0033] a first interlayer insulating layer located above the substrate and covering the active pattern and the word line structure;

[0034] A plurality of bit line structures are spaced apart and arranged above the first interlayer insulating layer; wherein the plurality of bit line structures extend along a third direction and are arranged parallel to each other, the bit line structures intersect the word line structures perpendicularly, each of the bit line structures is connected to at least one of the sub-patterns through a corresponding bit line contact plug, and the bit line structure is isolated from the adjacent storage node contact plug by a spacer.

[0035] According to an embodiment of the present application, optionally, in the above-mentioned semiconductor device,

[0036] The word line structure includes a trench, a gate insulating layer arranged on the sidewall and bottom of the trench, and a gate and a second interlayer insulating layer respectively filling the lower part and the upper part of the trench.

[0037] In a third aspect, the present application provides a method for preparing a semiconductor device, comprising:

[0038] providing a semiconductor substrate;

[0039] forming a plurality of active patterns spaced apart on the surface of the substrate; wherein the plurality of active patterns extend along a first direction and are arranged parallel to each other;

[0040] forming a first isolation structure filled between any two adjacent active patterns;

[0041] The substrate is patterned to form etching holes, so as to cut each active pattern into a plurality of sub-patterns; wherein, in each active pattern, in a plane parallel to the upper surface of the substrate, a contact portion between the sub-pattern and an adjacent etching hole is in an arc shape that is concave toward the middle of the sub-pattern;

[0042] A second isolation structure is formed to fill the etched hole.

[0043] According to an embodiment of the present application, optionally, in the above-mentioned method for manufacturing a semiconductor device, a diameter of the etched hole is larger than a line width of the active pattern and smaller than twice a distance between two adjacent active patterns.

[0044] According to an embodiment of the present application, optionally, in the above-mentioned method for preparing a semiconductor device, the bottom of the etched hole and the bottom of the first isolation structure are located at different heights.

[0045] In a fourth aspect, the present application provides a method for preparing a semiconductor device, comprising:

[0046] providing a semiconductor substrate;

[0047] forming a plurality of active patterns spaced apart on the surface of the substrate; wherein the plurality of active patterns extend along a first direction and are arranged parallel to each other;

[0048] forming a first isolation structure filled between any two adjacent active patterns;

[0049] Performing patterning on the substrate to form etched holes to cut each active pattern into a plurality of sub-patterns; wherein the etched holes include a first hole portion and a second hole portion stacked sequentially on the substrate, and the size of the second hole portion is larger than that of the first hole portion;

[0050] forming a second isolation structure filled in the etched hole;

[0051] The second isolation structure includes a first isolation portion and a second isolation portion respectively filled in the first hole portion and the second hole portion.

[0052] According to an embodiment of the present application, optionally, in the above-mentioned method for preparing a semiconductor device, in each of the active patterns, in a plane parallel to the upper surface of the substrate, the contact portion between the sub-pattern and the adjacent etched hole is in the shape of an arc that is recessed into the interior of the sub-pattern.

[0053] According to an embodiment of the present application, optionally, in the above-mentioned method for preparing a semiconductor device, the diameter of the first hole portion is larger than the line width of the active pattern, and the diameter of the second hole portion is smaller than twice the distance between two adjacent active patterns.

[0054] According to an embodiment of the present application, optionally, in the above-mentioned method for manufacturing a semiconductor device, the bottom of the first hole portion and the bottom of the first isolation structure are located at different heights.

[0055] Compared with the prior art, one or more embodiments of the above solutions may have the following advantages or beneficial effects:

[0056] The present application provides a semiconductor device and a method for manufacturing the same. In the semiconductor device, each active pattern is divided into multiple sub-patterns by a second isolation structure. Within each active pattern, the contact portion between the sub-pattern and the adjacent second isolation structure, in a plane parallel to the upper surface of the substrate, is arc-shaped and recessed toward the interior of the sub-pattern. Alternatively, each second isolation pattern includes a first isolation portion and a second isolation portion stacked sequentially on the substrate. Within a plane parallel to the upper surface of the substrate, the cross-sectional dimensions of the second isolation portion are larger than those of the first isolation portion. This increases the contact area between the active pattern and other components when contacting the bit line above it, enhancing the contact effect and improving the electrical performance of the device. BRIEF DESCRIPTION OF THE DRAWINGS

[0057] The accompanying drawings are used to provide a further understanding of the present application and constitute a part of the specification. Together with the following detailed description, they are used to explain the present application but do not constitute a limitation of the present application. In the accompanying drawings:

[0058] Figure 1 1 is a schematic diagram of a front plan view of a semiconductor device according to an exemplary embodiment of the present application;

[0059] Figure 2 yes Figure 1 Schematic diagram of the cross-sectional structure along the tangent line A-A';

[0060] Figure 3 yes Figure 1 Schematic diagram of the cross-sectional structure along the tangent line C-C';

[0061] Figure 4 yes Figure 1 Another schematic diagram of the front top view of the semiconductor device;

[0062] Figure 5 yes Figure 4 Schematic diagram of the cross-sectional structure along the tangent line B-B';

[0063] Figure 6 1 is a schematic diagram of a front plan view of another semiconductor device according to an exemplary embodiment of the present application;

[0064] Figure 7 yes Figure 6 Schematic diagram of the cross-sectional structure along the tangent line D-D';

[0065] Figure 8 1 is a schematic diagram of a front plan view of another semiconductor device according to an exemplary embodiment of the present application;

[0066] Figure 9 yes Figure 8 Schematic diagram of the cross-sectional structure along the tangent line B-B';

[0067] Figure 10 1 is a schematic diagram of a front plan view of another semiconductor device according to an exemplary embodiment of the present application;

[0068] Figure 11 yes Figure 10 Schematic diagram of the cross-sectional structure along the tangent line D-D';

[0069] Figure 12 This is a schematic flow chart of a method for manufacturing a semiconductor device according to an exemplary embodiment of the present application;

[0070] Figure 13 1 is a front plan view of a first intermediate structure formed in relevant steps of a method for manufacturing a semiconductor device according to an exemplary embodiment of the present application;

[0071] Figure 14 yes Figure 13 Schematic diagram of the cross-sectional structure along the tangent line A-A';

[0072] Figure 15 is a front top view schematic diagram of a second intermediate structure formed in relevant steps of a method for manufacturing a semiconductor device according to an exemplary embodiment of the present application;

[0073] Figure 16 yes Figure 15 Schematic diagram of the cross-sectional structure along the tangent line B-B';

[0074] Figure 17 is a front plan view of a third intermediate structure formed in relevant steps of a method for manufacturing a semiconductor device according to an exemplary embodiment of the present application;

[0075] Figure 18 and Figure 19 yes Figure 17 Schematic diagram of the cross-sectional structure along the tangent line A-A' and the tangent line C-C' respectively;

[0076] Figure 20 is a front plan view of a fourth intermediate structure formed in relevant steps of a method for manufacturing a semiconductor device according to an exemplary embodiment of the present application;

[0077] Figure 21 and Figure 22 yes Figure 20 Schematic diagram of the cross-sectional structure along the tangent line A-A' and the tangent line C-C' respectively;

[0078] Figure 23 is a front plan view of a fourth intermediate structure formed in relevant steps of a method for manufacturing a semiconductor device according to an exemplary embodiment of the present application;

[0079] Figure 24 and Figure 25 yes Figure 23 Schematic diagram of the cross-sectional structure along the tangent line A-A' and the tangent line C-C' respectively;

[0080] Figure 26 This is a schematic flow chart of another method for manufacturing a semiconductor device according to an exemplary embodiment of the present application;

[0081] Figure 27 is a front plan view schematically showing a first intermediate structure formed by relevant steps of another method for manufacturing a semiconductor device according to an exemplary embodiment of the present application;

[0082] Figure 28 yes Figure 27 Schematic diagram of the cross-sectional structure along the tangent line B-B';

[0083] In the drawings, like components are denoted by like reference numerals, and the drawings are not drawn to scale;

[0084] The accompanying drawings are numerals as follows:

[0085] 101 - substrate; 102 - active pattern; 1021 - sub-pattern; 103 - first isolation structure; 104 - second isolation structure; 105 - word line; 1051 - gate insulation layer; 1052 - gate; 1053 - second interlayer insulation layer; 106 - first interlayer insulation layer; 107 - first conductive layer; 108 - metal barrier layer; 109 - second conductive layer; 110 - storage node contact plug; CNT - contact hole;

[0086] 201-substrate; 202-active pattern; 2021-sub-pattern; 203-first isolation structure; 204-second isolation structure; 2041-first isolation portion; 2042-second isolation portion; 205-word line; 206-first interlayer insulating layer; 207-first conductive layer; 208-metal barrier layer; 209-second conductive layer; 210-storage node contact plug; CNT-contact hole. DETAILED DESCRIPTION

[0087] The following will describe in detail the implementation methods of the present application in conjunction with the accompanying drawings and examples, so that the implementation process of how the present application applies technical means to solve technical problems and achieve corresponding technical effects can be fully understood and implemented accordingly. The embodiments of the present application and the various features therein can be combined with each other without conflict, and the technical solutions formed are all within the scope of protection of this application. In the drawings, the sizes and relative sizes of layers and regions may be exaggerated for clarity. The same reference numerals throughout represent the same elements.

[0088] It should be understood that although the terms "first," "second," "third," etc. may be used to describe various elements, components, regions, layers, and / or portions, these elements, components, regions, layers, and / or portions should not be limited by these terms. These terms are merely used to distinguish one element, component, region, layer, or portion from another element, component, region, layer, or portion. Thus, a first element, component, region, layer, or portion discussed below may be referred to as a second element, component, region, layer, or portion without departing from the teachings of this application.

[0089] It will be understood that spatially relative terms, such as "above," "above," "below," "beneath," etc., may be used herein for convenience to describe the relationship of one element or feature to other elements or features illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use and operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, then elements or features described as "below other elements" would then be oriented "above" the other elements or features. Thus, the exemplary terms "below" and "beneath" can encompass both an orientation of above and below. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatial descriptors used herein interpreted accordingly.

[0090] The purpose of the terms used herein is only to describe specific embodiments and is not intended to limit the present application. When used herein, the singular forms "a", "an", and "the" are intended to include the plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "comprising" and / or "including", when used in this specification, determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0091] Embodiments of the present application are described herein with reference to cross-sectional views which are schematic illustrations of ideal embodiments (and intermediate structures) of the present application. As such, variations from the shapes shown due to, for example, manufacturing techniques and / or tolerances can be expected. Therefore, embodiments of the present application should not be limited to the specific shapes of the regions shown herein, but rather include deviations in shape due to, for example, manufacturing. For example, an implanted region shown as a rectangle typically has rounded or curved features and / or an implant concentration gradient at its edges, rather than a binary change from an implanted region to a non-implanted region. Similarly, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which the implantation is performed. Therefore, the regions shown in the figures are schematic in nature, and their shapes are not intended to illustrate the actual shape of the region of the device and are not intended to limit the scope of the present application.

[0092] In order to fully understand the present application, detailed structures and steps will be provided in the following description to illustrate the technical solutions proposed by the present application. The preferred embodiments of the present application are described in detail below. However, in addition to these detailed descriptions, the present application may also have other implementation methods.

[0093] Example 1

[0094] like Figure 1 、 Figure 2 and Figure 3 As shown, an embodiment of the present application provides a semiconductor device, including a semiconductor substrate 101, an active pattern 102, a first isolation structure 103, a second isolation structure 104, a word line structure 105, a first interlayer insulating layer 106 and a bit line structure (not marked in the figure).

[0095] The semiconductor substrate 101 may include, for example, at least one of a single crystal silicon substrate 101 and a silicon epitaxial layer.

[0096] like Figure 4 and Figure 5 As shown, multiple active patterns 102 are arranged at intervals on the substrate 101. The multiple active patterns 102 extend along a first direction and are arranged parallel to each other. The active patterns 102 are formed by ion implantation to form doped regions (not shown in the figure). The upper surface of the active pattern 102 is flush with the upper surface of the substrate 101.

[0097] The first isolation structure 103 is disposed between any two adjacent active patterns 102 , that is, any two adjacent active patterns 102 are isolated by the first isolation structure 103 .

[0098] Each active pattern 102 is divided into multiple sub-patterns 1021 by the second isolation structure 104; in each active pattern 102, in a plane parallel to the upper surface of the substrate 101, the contact portion between the sub-pattern 1021 and the adjacent second isolation structure 104 is in the shape of an arc that is concave toward the inside of the sub-pattern 1021.

[0099] The first isolation structure 103 and the second isolation structure 104 are used to define the shape of the sub-pattern 1021 .

[0100] Compared with the existing round-head shaped active pattern 102, the active sub-pattern 1021 of this shape increases the contact area with other components when contacting the bit line above it, reduces the contact resistance, strengthens the contact effect, and improves the electrical performance of the device.

[0101] The sub-patterns 1021 in two adjacent active patterns 102 are arranged in an alternating manner.

[0102] In some cases, the bottom of the second isolation structure 104 is located at the same height as the bottom of the first isolation structure 103. It can be understood that the bottom of the second isolation structure 104 is flush with the bottom of the first isolation structure 103.

[0103] In some cases, the bottom of the second isolation structure 104 and the bottom of the first isolation structure 103 are located at different heights. Figure 5As shown, the bottom of the second isolation structure 104 may be lower than the bottom of the first isolation structure 103 . In addition, the bottom of the second isolation structure 104 may also be higher than the bottom of the first isolation structure 103 .

[0104] That is to say, the bottom of the second isolation structure 104 and the bottom of the first isolation structure 103 are located at the same height or at different heights, and both can achieve the same insulation effect.

[0105] The first isolation structure 103 and the second isolation structure 104 are made of different insulating materials.

[0106] In some cases, the dielectric constant of the insulating material in the second isolation structure 104 is lower than the dielectric constant of the insulating material in the first isolation structure 103. That is, the second isolation structure 104 forms a low-dielectric region relative to the first isolation structure 103. When a word line passes through the second isolation structure 104, the coupling performance between the word line and the adjacent active pattern 102 is reduced, thereby avoiding crosstalk between the word lines and improving the electrical conductivity of the word lines.

[0107] In some cases, such as Figure 6 and 7 As shown, the semiconductor device may further include a storage node contact plug 110 extending into the surface of the substrate 101 and contacting an end portion of the sub-pattern 1021 .

[0108] It should be noted that in order to Figure 6 The position of the storage node contact plug 110 is clearly shown in FIG. Figure 6 The first interlayer insulating layer 106 is not shown in FIG. Figure 7 The position and shape of the first interlayer insulating layer 106 can be understood.

[0109] The storage node contact plugs 110 are located on both sides of the bit line structure and contact the ends of the adjacent sub-patterns 1021 on both sides of the bit line structure. The storage node contact plugs 110 are isolated from the adjacent bit line structures by spacers (not shown).

[0110] In this embodiment, the inwardly concave shape of the end of the sub-pattern 1021 can increase the contact area between the sub-pattern 1021 and the storage node contact plug 110, reduce the contact resistance, strengthen the contact effect between the two, and improve the electrical performance of the device.

[0111] A plurality of word line structures 105 are spaced apart and disposed on the surface of the substrate 101, and the plurality of word line structures 105 are spaced apart and disposed along the second direction (eg Figure 1 The word line structures 105 extend in the horizontal direction (as shown in FIG) and are arranged parallel to each other. Each word line structure 105 intersects with at least one sub-pattern 1021 .

[0112] The word line structure 105 includes a trench (not labeled in the figure), a gate 1052 and an insulating layer 1051 disposed on the sidewalls and bottom of the trench, and the gate 1052 and a second interlayer insulating layer 1053 filling the lower and upper portions of the trench respectively.

[0113] The thickness of the gate 1052 is smaller than the depth of the trench, but the bottom of the gate 1052 is higher than the bottom of the active pattern 102. The second interlayer insulating layer 1053 is formed of, for example, a silicon nitride layer and / or a silicon oxynitride layer.

[0114] The first interlayer insulating layer 106 is located over the substrate 101 and covers the active patterns 102 and the word line structures 105 .

[0115] A plurality of bit line structures are spaced apart and disposed above the first interlayer insulating layer 106, and the ... along the third direction (eg Figure 1 The bit line structures 105 extend in a vertical direction (as shown in FIG) and are arranged in parallel with each other. The bit line structures 105 intersect vertically with the word line structures 105. Each bit line structure is connected to at least one sub-pattern 1021 through a corresponding bit line contact plug.

[0116] The material of the first interlayer insulating layer 106 includes at least one of a silicon oxide layer, a silicon nitride layer, or a silicon oxynitride layer.

[0117] A bitline contact plug (not labeled in the figure) is disposed within a contact hole CNT extending through the first interlayer insulating layer 106. The contact hole CNT extends through the first interlayer insulating layer 106 and into the active pattern 102, the first isolation structure 103, and the wordline structure 105. The contact hole CNT can be disposed at any position within the sub-pattern 1021. Even at the end of the sub-pattern 1021, since the end of the sub-pattern 1021 is recessed toward the center in this application, the protruding portions on both sides can increase the contact area between the bitline contact plug and the sub-pattern 1021, ensuring effective contact without affecting the electrical performance of the device.

[0118] The bit line structure includes a first conductive layer 107, a metal barrier layer 108, and a second conductive layer 109. The first conductive layer 107 and the second conductive layer 109 may be made of at least one of metal silicide, polysilicon, metal nitride, and metal.

[0119] The first conductive layer 107 is located above the first interlayer insulating layer 106 and in the contact hole CNT. The metal barrier layer 108 is located above the first conductive layer 107 . The second conductive layer 109 is located above the metal barrier layer 108 .

[0120] An embodiment of the present application provides a semiconductor device comprising a plurality of active patterns 102 spaced apart within a surface of a substrate 101; wherein the plurality of active patterns 102 extend along a first direction and are arranged parallel to one another; a first isolation structure 103 disposed between any two adjacent active patterns 102; wherein each active pattern 102 is divided into a plurality of sub-patterns 1021 by a second isolation structure 104; and within each active pattern 102, in a plane parallel to the upper surface of the substrate 101, the contact portion between the sub-pattern 1021 and the adjacent second isolation structure 104 is in the shape of an arc recessed into the interior of the sub-pattern 1021. When the active pattern 102 contacts the bit line above it, the contact area with other components is increased, thereby enhancing the contact effect and improving the electrical performance of the device.

[0121] Example 2

[0122] An embodiment of the present application provides a semiconductor device, including a semiconductor substrate 201 , an active pattern 202 , a first isolation structure 203 , a second isolation structure 204 , a word line structure 205 , a first interlayer insulating layer 206 and a bit line structure (not labeled in the figure).

[0123] The semiconductor substrate 201 may include, for example, at least one of a single crystal silicon substrate 201 and a silicon epitaxial layer.

[0124] like Figure 8 and Figure 9 As shown, multiple active patterns 202 are arranged at intervals on the substrate 201. The multiple active patterns 202 extend along a first direction and are arranged parallel to each other. The active patterns 202 are formed by ion implantation to form doped regions (not shown in the figure). The upper surface of the active pattern 202 is flush with the upper surface of the substrate 201.

[0125] The first isolation structure 203 is disposed between any two adjacent active patterns 202 , that is, any two adjacent active patterns 202 are isolated by the first isolation structure 203 .

[0126] In which, each active pattern 202 is cut into multiple sub-patterns 2021 by a second isolation structure 204; each second isolation pattern includes a first isolation part 2041 and a second isolation part 2042 stacked in sequence on the substrate 201; in a plane parallel to the upper surface of the substrate 201, the cross-sectional size of the second isolation part 2042 is larger than the cross-sectional size of the first isolation part 2041.

[0127] The second isolation portion 2042 with a larger size ensures the insulation effect between the two adjacent sub-patterns 2021, avoiding crosstalk between the sub-patterns 2021. The first isolation portion 2041 with a smaller size allows the end of the sub-pattern 2021 to be extended. When contacting other components extending into the substrate 201, the contact area between the two can be increased, the contact resistance can be reduced, the contact effect between the two can be enhanced, and the electrical performance of the device can be improved.

[0128] like Figure 10 and 11 As shown, in some cases, the semiconductor device further includes a storage node contact plug 210 extending into the surface of the substrate 201 and contacting an end portion of the sub-pattern 2021 .

[0129] It should be noted that in order to Figure 10 The position of the storage node contact plug 210 is clearly shown in FIG. Figure 10 The first interlayer insulating layer 206 is not shown in FIG. Figure 11 The position and shape of the first interlayer insulating layer 206 can be understood.

[0130] The storage node contact plugs 210 are located on both sides of the bit line structure and contact the ends of the adjacent sub-patterns 2021 on both sides of the bit line structure. The storage node contact plugs 210 are isolated from the adjacent bit line structures by spacers (not shown).

[0131] The extension depth of the storage node contact plug 210 in the surface of the substrate 201 is greater than or equal to the depth of the second isolation portion 2042 .

[0132] Therefore, the storage node contact plug 210 contacts the end of the sub-pattern 2021, which is actually in contact with the end of the sub-pattern 2021 adjacent to the first isolation part 2041. The area of ​​the end of this part is larger than the area of ​​the end of the sub-pattern 2021 adjacent to the second isolation part 2042. Therefore, while ensuring the insulation performance between the sub-patterns 2021, the contact area between the sub-pattern 2021 and the storage node contact plug 210 is also increased, the contact resistance is reduced, the contact effect between the two is enhanced, and the electrical performance of the device is improved.

[0133] The lower surface of the second isolation portion 2042 completely covers the upper surface of the first isolation portion 2041 .

[0134] In some cases, in each active pattern 202 , in a plane parallel to the upper surface of the substrate 201 , a contact portion between the sub-pattern 2021 and the adjacent second isolation structure 204 is in an arc shape that is recessed toward the inside of the sub-pattern 2021 .

[0135] That is, in each active pattern 202 , in a plane parallel to the upper surface of the substrate 201 , the contact portion between the sub-pattern 2021 and the first isolation portion 2041 or the second isolation portion 2042 of the adjacent second isolation structure 204 is in an arc shape recessed toward the inside of the sub-pattern 2021 .

[0136] The first isolation structure 203 and the second isolation structure 204 are used to define the shape of the sub-pattern 2021 .

[0137] Compared with the existing round-head shaped active pattern 202, the active sub-pattern 2021 of this shape increases the contact area with other components when contacting the bit line above it, strengthens the contact effect, and improves the electrical performance of the device.

[0138] The sub-patterns 2021 in two adjacent active patterns 202 are arranged in an alternating manner.

[0139] In some cases, the bottom of the first isolation portion 2041 is located at the same height as the bottom of the first isolation structure 203. It can be understood that the bottom of the second isolation structure 204 is flush with the bottom of the first isolation structure 203.

[0140] In some cases, the bottom of the first isolation portion 2041 and the bottom of the first isolation structure 203 are located at different heights. Figure 9 As shown, the bottom of the first isolation portion 2041 may be lower than the bottom of the first isolation structure 203 . In addition, the bottom of the second isolation structure 204 may also be higher than the bottom of the first isolation structure 203 .

[0141] That is to say, the bottom of the second isolation structure 204 and the bottom of the first isolation structure 203 are located at the same height or at different heights, and both can achieve the same insulation effect.

[0142] The first isolation structure 203 and the second isolation structure 204 are made of different insulating materials.

[0143] In some cases, the dielectric constant of the insulating material in the second isolation structure 204 is lower than the dielectric constant of the insulating material in the first isolation structure 203. That is, the second isolation structure 204 forms a low-dielectric region relative to the first isolation structure 203. When a word line passes through the second isolation structure 204, the coupling performance between the word line and the adjacent active pattern 202 is reduced, thereby avoiding crosstalk between the word lines and improving the electrical conductivity of the word lines.

[0144] A plurality of word line structures 205 are disposed at intervals on the surface of the substrate 201 . The plurality of word line structures 205 extend along the second direction and are arranged parallel to each other. Each word line structure 205 intersects with at least one sub-pattern 2021 .

[0145] The word line structure 205 includes a trench, a gate 2052 and an insulating layer 2051 disposed on the sidewalls and bottom of the trench, and the gate 2052 and a second interlayer insulating layer 2053 respectively filling the lower and upper portions of the trench.

[0146] The thickness of the gate 2052 is smaller than the depth of the trench, but the bottom of the gate 2052 is higher than the bottom of the active pattern 202. The second interlayer insulating layer 2053 is formed of, for example, a silicon nitride layer and / or a silicon oxynitride layer.

[0147] The first interlayer insulating layer 206 is located over the substrate 201 and covers the active patterns 202 and the word line structures 205 .

[0148] Multiple bit line structures are spaced apart and arranged above the first interlayer insulating layer 206, and the multiple bit line structures extend along the third direction and are arranged parallel to each other. The bit line structures intersect the word line structures 205 vertically, and each bit line structure is connected to at least one sub-pattern 2021 through a corresponding bit line contact plug.

[0149] The material of the first interlayer insulating layer 206 includes at least one of a silicon oxide layer, a silicon nitride layer, or a silicon oxynitride layer.

[0150] The bitline contact plug is disposed within a contact hole CNT extending through the first interlayer insulating layer 206. The contact hole CNT extends through the first interlayer insulating layer 206 and into the active pattern 202, the first isolation structure 203, and the wordline structure 205. The contact hole CNT can be disposed at any position within the sub-pattern 2021. Even if the contact hole CNT is disposed at the end of the sub-pattern 2021, since the end of the sub-pattern 2021 is recessed toward the center in the present application, the protruding portions on both sides can increase the contact area between the bitline contact plug and the sub-pattern 2021, ensuring effective contact without affecting the electrical performance of the device.

[0151] The bit line structure includes a first conductive layer 207, a metal barrier layer 208, and a second conductive layer 209. The first conductive layer 207 and the second conductive layer 209 may be made of at least one of metal silicide, polysilicon, metal nitride, and metal.

[0152] The first conductive layer 207 is located above the first interlayer insulating layer 206 and in the contact hole CNT. The metal barrier layer 208 is located above the first conductive layer 207 . The second conductive layer 209 is located above the metal barrier layer 208 .

[0153] The present embodiment provides a semiconductor device comprising a plurality of active patterns 202 spaced apart within a surface of a substrate 201. The plurality of active patterns 202 extend along a first direction and are arranged parallel to one another. A first isolation structure 203 is provided between any two adjacent active patterns 202 to provide isolation. Each active pattern 202 is divided into a plurality of sub-patterns 2021 by a second isolation structure 204. Each second isolation pattern comprises a first isolation portion 2041 and a second isolation portion 2042 stacked sequentially on the substrate 201. In a plane parallel to the upper surface of the substrate 201, the cross-sectional dimensions of the second isolation portion 2042 are greater than those of the first isolation portion 2041. This increases the contact area between the active pattern 202 and other components when contacting the bit line above it, enhancing the contact effect and improving the electrical performance of the device.

[0154] Example 3

[0155] Based on the first embodiment, this embodiment provides a method for manufacturing a semiconductor device. Figure 12 It is a schematic flow chart of a method for preparing a semiconductor device shown in an embodiment of the present disclosure. Figure 13-Figure 25 This is a schematic diagram of the front view and cross-sectional structure of the relevant steps of the method for preparing a semiconductor device shown in the embodiment of the present disclosure. Figure 12 and Figure 13-Figure 25 The detailed steps of an exemplary method for preparing a semiconductor device proposed in an embodiment of the present disclosure are described.

[0156] like Figure 12 As shown, the method for preparing the semiconductor device of this embodiment includes the following steps:

[0157] Step S110 : providing a semiconductor substrate 101 .

[0158] The semiconductor substrate 101 may include, for example, at least one of a single crystal silicon substrate 101 and a silicon epitaxial layer.

[0159] Step S120 : forming a plurality of active patterns 102 spaced apart on the surface of the substrate 101 ; wherein the plurality of active patterns 102 extend along a first direction and are arranged parallel to each other.

[0160] The active pattern 102 is formed by forming a doped region (not shown in the figure) through ion implantation. The upper surface of the active pattern 102 is flush with the upper surface of the substrate 101 .

[0161] Step S130: Figure 13 and 14 As shown, a first isolation structure 103 is formed to fill between any two adjacent active patterns 102 for isolation.

[0162] The first isolation structure 103 is disposed between any two adjacent active patterns 102 , that is, any two adjacent active patterns 102 are isolated by the first isolation structure 103 .

[0163] Step S140: The substrate 101 is patterned to form etching holes (not marked in the figure) to cut each active pattern 102 into multiple sub-patterns 1021; wherein, in each active pattern 102, in a plane parallel to the upper surface of the substrate 101, the contact portion between the sub-pattern 1021 and the adjacent etching hole is in the shape of an arc that is concave toward the middle of the sub-pattern 1021.

[0164] In the present application, the gap between two adjacent active patterns 102 is first filled by the first isolation structure 103, and then the active pattern 102 is cut into multiple sub-patterns 1021 by etching. In this way, when the etching hole is formed, the edges of the active pattern 102 are protected by the first isolation structure 103. During etching, the exposed position of the mask pattern (the shape of the exposed area of ​​the mask pattern is consistent with the shape of the etching hole) is mainly etched. The etching rate of the edge of the active pattern 102 is very small, and the active pattern 102 is mainly etched, so this sub-pattern with an inwardly recessed end can be formed.

[0165] In some cases, the bottom of the etched hole is located at the same height as the bottom of the first isolation structure 103. It can be understood that the bottom of the etched hole is flush with the bottom of the first isolation structure 103.

[0166] In some cases, the bottom of the etched hole is located at a different height than the bottom of the first isolation structure 103. As shown in the figure, the bottom of the etched hole can be lower than the bottom of the first isolation structure 103. In addition, the bottom of the etched hole can also be higher than the bottom of the first isolation structure 103.

[0167] The diameter of the etched hole is larger than the line width of the active pattern 102 and smaller than twice the distance between two adjacent active patterns 102 .

[0168] Step S150: Figure 15 and Figure 16 As shown, a second isolation structure 104 is formed to fill the etched hole.

[0169] In each active pattern 102 , in a plane parallel to the upper surface of the substrate 101 , a contact portion between the sub-pattern 1021 and the adjacent second isolation structure 104 is in an arc shape that is recessed toward the inside of the sub-pattern 1021 .

[0170] The first isolation structure 103 and the second isolation structure 104 are used to define the shape of the sub-pattern 1021 .

[0171] Compared with the existing round-head shaped active pattern 102, the active sub-pattern 1021 of this shape increases the contact area with other components when contacting the bit line above it, strengthens the contact effect, and improves the electrical performance of the device.

[0172] The sub-patterns 1021 in two adjacent active patterns 102 are arranged in an alternating manner.

[0173] In some cases, the bottom of the second isolation structure 104 is located at the same height as the bottom of the first isolation structure 103. It can be understood that the bottom of the second isolation structure 104 is flush with the bottom of the first isolation structure 103.

[0174] In some cases, the bottom of the second isolation structure 104 and the bottom of the first isolation structure 103 are located at different heights. Figure 16 As shown, the bottom of the second isolation structure 104 may be lower than the bottom of the first isolation structure 103 . In addition, the bottom of the second isolation structure 104 may also be higher than the bottom of the first isolation structure 103 .

[0175] That is to say, the bottom of the second isolation structure 104 and the bottom of the first isolation structure 103 are located at the same height or at different heights, and both can achieve the same insulation effect.

[0176] The first isolation structure 103 and the second isolation structure 104 are made of different insulating materials.

[0177] In some cases, the dielectric constant of the insulating material in the second isolation structure 104 is lower than the dielectric constant of the insulating material in the first isolation structure 103. That is, the second isolation structure 104 forms a low-dielectric region relative to the first isolation structure 103. When a word line passes through the second isolation structure 104, the coupling performance between the word line and the adjacent active pattern 102 is reduced, thereby avoiding crosstalk between the word lines and improving the electrical conductivity of the word lines.

[0178] After step S150, the method further includes the following steps:

[0179] S160: Figure 17 、 Figure 18 and Figure 19 As shown, a plurality of word line structures 105 are formed and spaced apart on the surface of the substrate 101 ; wherein the plurality of word line structures 105 extend along the second direction and are arranged parallel to each other, and each word line structure 105 intersects with at least one sub-pattern 1021 ;

[0180] S170: Figure 20 、 Figure 21 and Figure 22As shown, a first interlayer insulating layer 106 is formed over the substrate 101 and covers the active pattern 102 and the word line structure 105;

[0181] S180: Figure 23 、 Figure 24 and Figure 25 As shown, a plurality of bit line structures are formed and spaced apart above the first interlayer insulating layer 106; wherein the plurality of bit line structures extend along a third direction and are arranged parallel to each other, the bit line structures intersect the word line structures 105 vertically, and each bit line structure is connected to at least one sub-pattern 1021 through a corresponding bit line contact plug.

[0182] The word line structure 105 includes a trench, a gate 1052 and an insulating layer 1051 disposed on the sidewalls and bottom of the trench, and the gate 1052 and a second interlayer insulating layer 1053 filling the lower and upper portions of the trench, respectively.

[0183] The thickness of the gate 1052 is smaller than the depth of the trench, but the bottom of the gate 1052 is higher than the bottom of the active pattern 102. The second interlayer insulating layer 1053 is formed of, for example, a silicon nitride layer and / or a silicon oxynitride layer.

[0184] The material of the first interlayer insulating layer 106 includes at least one of a silicon oxide layer, a silicon nitride layer, or a silicon oxynitride layer.

[0185] The bitline contact plug is disposed within a contact hole CNT extending through the first interlayer insulating layer 106. The contact hole CNT extends through the first interlayer insulating layer 106 and into the active pattern 102, the first isolation structure 103, and the wordline structure 105. The contact hole CNT can be disposed at any position within the sub-pattern 1021. Even if the contact hole CNT is disposed at an end of the sub-pattern 1021, since the end of the sub-pattern 1021 is recessed toward the center in the present application, the protruding portions on both sides can increase the contact area between the bitline contact plug and the sub-pattern 1021, thereby ensuring effective contact without affecting the electrical performance of the device.

[0186] The bit line structure includes a first conductive layer 107, a metal barrier layer 108, and a second conductive layer 109. The first conductive layer 107 and the second conductive layer 109 may be made of at least one of metal silicide, polysilicon, metal nitride, and metal.

[0187] The first conductive layer 107 is located above the first interlayer insulating layer 106 and in the contact hole CNT. The metal barrier layer 108 is located above the first conductive layer 107 . The second conductive layer 109 is located above the metal barrier layer 108 .

[0188] The final structure is Figures 1 to 3 shown.

[0189] In some cases, the above method further comprises:

[0190] S190: Figure 6 and 7 As shown, a storage node contact plug 110 is formed to extend into the surface of the substrate 101 and contact the end of the sub-pattern 1021 .

[0191] The storage node contact plug 110 is located on both sides of the bit line structure and contacts the ends of the adjacent sub-patterns 1021 on both sides of the bit line structure. The storage node contact plug 110 is isolated from the adjacent bit line structure by spacers.

[0192] In this embodiment, the inwardly concave shape of the end of the sub-pattern 1021 can increase the contact area between the sub-pattern 1021 and the storage node contact plug 110, reduce the contact resistance, strengthen the contact effect between the two, and improve the electrical performance of the device.

[0193] An embodiment of the present application provides a method for fabricating a semiconductor device, comprising forming a plurality of spaced active patterns 102 on the surface of a substrate 101; wherein the plurality of active patterns 102 extend along a first direction and are arranged parallel to each other; forming a first isolation structure 103 between any two adjacent active patterns 102; patterning the substrate 101 to form etched holes to divide each active pattern 102 into a plurality of sub-patterns 1021; wherein, in each active pattern 102, in a plane parallel to the upper surface of the substrate 101, the contact portion between the sub-pattern 1021 and the adjacent etched hole is in the shape of an arc that is concave toward the center of the sub-pattern 1021; and forming a second isolation structure 104 within the etched hole. When the active pattern 102 contacts the bit line above it, it increases the contact area with other components, strengthens the contact effect, and improves the electrical performance of the device.

[0194] Example 4

[0195] Based on the second embodiment, this embodiment of the present application provides a method for preparing a semiconductor device. Figure 26 It is a schematic flow chart of a method for preparing a semiconductor device shown in an embodiment of the present disclosure. Figure 27-28 This is a schematic diagram of the front view and cross-sectional structure of the relevant steps of the method for preparing a semiconductor device shown in the embodiment of the present disclosure. Figure 26 and Figure 27-28 The detailed steps of an exemplary method for preparing a semiconductor device proposed in an embodiment of the present disclosure are described.

[0196] like Figure 26 As shown, the method for preparing the semiconductor device of this embodiment includes the following steps:

[0197] Step S220: providing a semiconductor substrate 201 .

[0198] The semiconductor substrate 201 may include, for example, at least one of a single crystal silicon substrate 201 and a silicon epitaxial layer.

[0199] Step S220 : forming a plurality of active patterns 202 spaced apart from each other on the surface of the substrate 201 ; wherein the plurality of active patterns 202 extend along a first direction and are arranged parallel to each other.

[0200] The active pattern 202 is formed by forming a doped region (not shown in the figure) through ion implantation, and the upper surface of the active pattern 202 is flush with the upper surface of the substrate 201 .

[0201] Step S230 : forming a first isolation structure 203 filled between any two adjacent active patterns 202 for isolation.

[0202] The first isolation structure 203 is disposed between any two adjacent active patterns 202 , that is, any two adjacent active patterns 202 are isolated by the first isolation structure 203 .

[0203] Step S240: Patterning the substrate 201 to form etching holes (not marked in the figure) to cut each active pattern 202 into multiple sub-patterns 2021; wherein the etching holes include a first hole portion and a second hole portion stacked in sequence on the substrate 201, and the diameter of the second hole portion is larger than the diameter of the first hole portion.

[0204] In some cases, the bottom of the first hole portion is located at the same height as the bottom of the first isolation structure 203. It can be understood that the bottom of the first hole portion is flush with the bottom of the first isolation structure 203.

[0205] In some cases, the bottom of the first hole portion is located at a different height than the bottom of the first isolation structure 203. The bottom of the first hole portion can be lower than the bottom of the first isolation structure 203. Alternatively, the bottom of the first hole portion can be higher than the bottom of the first isolation structure 203.

[0206] The diameter of the first hole portion is larger than the line width of the active pattern 202 , and the diameter of the second hole portion is smaller than twice the distance between two adjacent active patterns 202 .

[0207] In some cases, in each active pattern 202 , in a plane parallel to the upper surface of the substrate 201 , a contact portion between the sub-pattern 2021 and an adjacent etched hole is in an arc shape that is recessed toward the inside of the sub-pattern 2021 .

[0208] Step S250: Figure 27 and Figure 28As shown, a second isolation structure 204 is formed to fill the etched hole; wherein the second isolation structure 204 includes a first isolation portion 2041 and a second isolation portion 2042 respectively filled in the first hole portion and the second hole portion.

[0209] The second isolation portion 2042 with a larger size ensures the insulation effect between the two adjacent sub-patterns 2021, avoiding crosstalk between the sub-patterns 2021. The first isolation portion 2041 with a smaller size allows the end of the sub-pattern 2021 to be extended. When contacting other components extending into the substrate 201, the contact area between the two can be increased, the contact resistance can be reduced, the contact effect between the two can be enhanced, and the electrical performance of the device can be improved.

[0210] The lower surface of the second isolation portion 2042 completely covers the upper surface of the first isolation portion 2041 .

[0211] In some cases, in each active pattern 202 , in a plane parallel to the upper surface of the substrate 201 , a contact portion between the sub-pattern 2021 and the adjacent second isolation structure 204 is in an arc shape that is recessed toward the inside of the sub-pattern 2021 .

[0212] In the present application, the gap between two adjacent active patterns 202 is first filled by the first isolation structure 203, and then the active pattern 202 is cut into multiple sub-patterns 2021 by etching. In this way, when the etching hole is formed, the edges of the active pattern 202 are protected by the first isolation structure 203. During etching, the exposed position of the mask pattern (the shape of the exposed area of ​​the mask pattern is consistent with the shape of the etching hole) is mainly etched. The etching rate of the edge of the active pattern 202 is very small, and the active pattern 202 is mainly etched, so this sub-pattern with an inwardly recessed end can be formed.

[0213] The first isolation structure 203 and the second isolation structure 204 are used to define the shape of the sub-pattern 2021 .

[0214] Compared with the existing round-head shaped active pattern 202, the active sub-pattern 2021 of this shape increases the contact area with other components when contacting the bit line above it, strengthens the contact effect, and improves the electrical performance of the device.

[0215] The sub-patterns 2021 in two adjacent active patterns 202 are arranged in an alternating manner.

[0216] In some cases, the bottom of the first isolation portion 2041 is located at the same height as the bottom of the first isolation structure 203. It can be understood that the bottom of the second isolation structure 204 is flush with the bottom of the first isolation structure 203.

[0217] In some cases, the bottom of the first isolation portion 2041 and the bottom of the first isolation structure 203 are located at different heights. Figure 28 As shown, the bottom of the first isolation portion 2041 may be lower than the bottom of the first isolation structure 203 . In addition, the bottom of the second isolation structure 204 may also be higher than the bottom of the first isolation structure 203 .

[0218] That is to say, the bottom of the second isolation structure 204 and the bottom of the first isolation structure 203 are located at the same height or at different heights, and both can achieve the same insulation effect.

[0219] The first isolation structure 203 and the second isolation structure 204 are made of different insulating materials.

[0220] In some cases, the dielectric constant of the insulating material in the second isolation structure 204 is lower than the dielectric constant of the insulating material in the first isolation structure 203. That is, the second isolation structure 204 forms a low-dielectric region relative to the first isolation structure 203. When a word line passes through the second isolation structure 204, the coupling performance between the word line and the adjacent active pattern 202 is reduced, thereby avoiding crosstalk between the word lines and improving the electrical conductivity of the word lines.

[0221] After step S250, the method further includes the following steps:

[0222] S260: forming a plurality of word line structures 205 spaced apart on the surface of the substrate 201; wherein the plurality of word line structures 205 extend along the second direction and are arranged parallel to each other, and each word line structure 205 intersects with at least one sub-pattern 2021;

[0223] S270: forming a first interlayer insulating layer 206 located above the substrate 201 and covering the active pattern 202 and the word line structure 205;

[0224] S280: forming a plurality of bit line structures spaced apart and arranged above the first interlayer insulating layer 206; wherein the plurality of bit line structures extend along a third direction and are arranged parallel to each other, the bit line structures intersect the word line structures 205 vertically, and each bit line structure is connected to at least one sub-pattern 2021 through a corresponding bit line contact plug.

[0225] The word line structure 205 includes a trench, a gate 2052 and an insulating layer 2051 disposed on the sidewalls and bottom of the trench, and the gate 2052 and a second interlayer insulating layer 2053 respectively filling the lower and upper portions of the trench.

[0226] The thickness of the gate 2052 is smaller than the depth of the trench, but the bottom of the gate 2052 is higher than the bottom of the active pattern 202. The second interlayer insulating layer 2053 is formed of, for example, a silicon nitride layer and / or a silicon oxynitride layer.

[0227] The material of the first interlayer insulating layer 206 includes at least one of a silicon oxide layer, a silicon nitride layer, or a silicon oxynitride layer.

[0228] The bitline contact plug is disposed within a contact hole CNT extending through the first interlayer insulating layer 206. The contact hole CNT extends through the first interlayer insulating layer 206 and into the active pattern 202, the first isolation structure 203, and the wordline structure 205. The contact hole CNT can be disposed at any position within the sub-pattern 2021. Even if the contact hole CNT is disposed at the end of the sub-pattern 2021, since the end of the sub-pattern 2021 is recessed toward the center in the present application, the protruding portions on both sides can increase the contact area between the bitline contact plug and the sub-pattern 2021, ensuring effective contact without affecting the electrical performance of the device.

[0229] The bit line structure includes a first conductive layer 207, a metal barrier layer 208, and a second conductive layer 209. The first conductive layer 207 and the second conductive layer 209 may be made of at least one of metal silicide, polysilicon, metal nitride, and metal.

[0230] The first conductive layer 207 is located above the first interlayer insulating layer 206 and in the contact hole CNT. The metal barrier layer 208 is located above the first conductive layer 207 . The second conductive layer 209 is located above the metal barrier layer 208 .

[0231] In some cases, the above method further comprises:

[0232] S290: Figure 10 and 11 As shown, a storage node contact plug 210 is formed extending into the surface of the substrate 201 and contacting the end of the sub-pattern 2021 ; wherein the extension depth of the storage node contact plug 210 in the surface of the substrate 201 is greater than or equal to the depth of the second isolation portion 2042 .

[0233] The storage node contact plug 210 is located on both sides of the bit line structure and contacts the ends of the adjacent sub-patterns 2021 on both sides of the bit line structure. The storage node contact plug 210 is isolated from the adjacent bit line structure by spacers.

[0234] The storage node contact plug 210 contacts the end of the sub-pattern 2021, which is actually in contact with the end of the sub-pattern 2021 adjacent to the first isolation part 2041. The area of ​​the end of this part is larger than the area of ​​the end of the sub-pattern 2021 adjacent to the second isolation part 2042. Therefore, while ensuring the insulation performance between the sub-patterns 2021, the contact area between the sub-pattern 2021 and the storage node contact plug 210 is also increased, the contact resistance is reduced, the contact effect between the two is enhanced, and the electrical performance of the device is improved.

[0235] The present invention provides a method for fabricating a semiconductor device, comprising forming a plurality of spaced active patterns 202 on a surface of a substrate 201; wherein the plurality of active patterns 202 extend along a first direction and are arranged parallel to each other; forming a first isolation structure 203 between any two adjacent active patterns 202; patterning the substrate 201 to form etched holes to divide each active pattern 202 into a plurality of sub-patterns 2021; wherein the etched holes include a first hole portion and a second hole portion stacked sequentially on the substrate 201, the second hole portion having a larger diameter than the first hole portion; and forming a second isolation structure 204 filled in the etched holes; wherein the second isolation structure 204 includes a first isolation portion 2041 and a second isolation portion 2042 respectively filled in the first hole portion and the second hole portion. This increases the contact area between the active pattern 202 and other components when contacting the bit line above it, thereby enhancing the contact effect and improving the electrical performance of the device.

[0236] Although the embodiments disclosed in this application are as described above, the contents described are merely embodiments adopted to facilitate understanding of this application and are not intended to limit this application. Any person skilled in the art of the art to which this application belongs may make any modifications and changes in the form and details of the implementation without departing from the spirit and scope disclosed in this application. However, the scope of protection of this application shall still be based on the scope defined by the attached claims.

Claims

1. A semiconductor device, characterized in that: include: semiconductor substrates; A plurality of active patterns are spaced apart on the surface of the substrate; wherein the plurality of active patterns extend along a first direction and are arranged parallel to each other; a first isolation structure disposed between any two adjacent active patterns; In which, each of the active patterns is cut into multiple sub-patterns by the second isolation structure; in each of the active patterns, in a plane parallel to the upper surface of the substrate, the contact portion between the sub-pattern and the adjacent second isolation structure is in the shape of an arc that is concave toward the interior of the sub-pattern; the diameter of the second isolation structure is greater than the line width of the active pattern.

2. The semiconductor device according to claim 1, wherein The bottom of the second isolation structure and the bottom of the first isolation structure are located at different heights.

3. The semiconductor device according to claim 1, wherein The first isolation structure and the second isolation structure are made of different insulating materials.

4. The semiconductor device according to claim 1, wherein Also includes: a plurality of word line structures spaced apart within the surface of the substrate; wherein the plurality of word line structures extend along the second direction and are arranged parallel to each other, and each of the word line structures intersects with at least one of the sub-patterns; a first interlayer insulating layer located above the substrate and covering the active pattern and the word line structure; A plurality of bit line structures are spaced apart and arranged above the first interlayer insulating layer; wherein the plurality of bit line structures extend along a third direction and are arranged parallel to each other, the bit line structures intersect the word line structures perpendicularly, and each of the bit line structures is connected to at least one of the sub-patterns through a corresponding bit line contact plug.

5. The semiconductor device according to claim 4, wherein The word line structure includes a trench, a gate insulating layer arranged on the sidewall and bottom of the trench, and a gate and a second interlayer insulating layer respectively filling the lower part and the upper part of the trench.

6. A semiconductor device, characterized in that: include: semiconductor substrates; A plurality of active patterns are spaced apart on the surface of the substrate; wherein the plurality of active patterns extend along a first direction and are arranged parallel to each other; A first isolation structure is provided between any two adjacent active patterns; In which, each of the active patterns is cut into multiple sub-patterns by a second isolation structure; each of the second isolation structures includes a first isolation part and a second isolation part stacked in sequence on the substrate; in a plane parallel to the upper surface of the substrate, the cross-sectional size of the second isolation part is larger than the cross-sectional size of the first isolation part; the lower surface of the second isolation part completely covers the upper surface of the first isolation part.

7. The semiconductor device according to claim 6, wherein: Also includes: a storage node contact plug extending into the substrate surface and contacting an end portion of the sub-pattern; The storage node contact plug extends into the substrate surface to a depth greater than or equal to a depth of the second isolation portion.

8. The semiconductor device according to claim 6, wherein: In each of the active patterns, in a plane parallel to the upper surface of the substrate, a contact portion between the sub-pattern and the adjacent second isolation structure is in an arc shape recessed toward the interior of the sub-pattern.

9. The semiconductor device according to claim 6, wherein: The bottom of the first isolation portion and the bottom of the first isolation structure are located at different heights.

10. The semiconductor device according to claim 6, wherein The first isolation structure and the second isolation structure are made of different insulating materials.

11. The semiconductor device according to claim 7, wherein Also includes: a plurality of word line structures spaced apart within the surface of the substrate; wherein the plurality of word line structures extend along the second direction and are arranged parallel to each other, and each of the word line structures intersects with at least one of the sub-patterns; a first interlayer insulating layer located above the substrate and covering the active pattern and the word line structure; A plurality of bit line structures are spaced apart and arranged above the first interlayer insulating layer; wherein the plurality of bit line structures extend along a third direction and are arranged parallel to each other, the bit line structures intersect the word line structures perpendicularly, each of the bit line structures is connected to at least one of the sub-patterns through a corresponding bit line contact plug, and the bit line structure is isolated from the adjacent storage node contact plug by a spacer.

12. The semiconductor device according to claim 11, wherein The word line structure includes a trench, a gate insulating layer arranged on the sidewall and bottom of the trench, and a gate and a second interlayer insulating layer respectively filling the lower part and the upper part of the trench.

13. A method for preparing a semiconductor device, characterized in that: include: providing a semiconductor substrate; forming a plurality of active patterns spaced apart on the surface of the substrate; wherein the plurality of active patterns extend along a first direction and are arranged parallel to each other; forming a first isolation structure filled between any two adjacent active patterns; The substrate is patterned to form etched holes, so as to cut each active pattern into a plurality of sub-patterns; wherein, in each active pattern, in a plane parallel to the upper surface of the substrate, a contact portion between the sub-pattern and an adjacent etched hole is in an arc shape that is concave toward the middle of the sub-pattern; and the diameter of the etched hole is larger than the line width of the active pattern; A second isolation structure is formed to fill the etched hole.

14. The method according to claim 13, characterized in that The diameter of the etched hole is less than twice the distance between two adjacent active patterns.

15. The method according to claim 13, characterized in that The bottom of the etched hole and the bottom of the first isolation structure are located at different heights.

16. A method for preparing a semiconductor device, characterized in that: include: providing a semiconductor substrate; forming a plurality of active patterns spaced apart on the surface of the substrate; wherein the plurality of active patterns extend along a first direction and are arranged parallel to each other; forming a first isolation structure filled between any two adjacent active patterns; Performing patterning on the substrate to form etched holes to cut each active pattern into a plurality of sub-patterns; wherein the etched holes include a first hole portion and a second hole portion stacked sequentially on the substrate, and the size of the second hole portion is larger than that of the first hole portion; forming a second isolation structure filled in the etched hole; The second isolation structure includes a first isolation portion and a second isolation portion respectively filled in the first hole portion and the second hole portion; the lower surface of the second isolation portion completely covers the upper surface of the first isolation portion.

17. The method according to claim 16, characterized in that In each of the active patterns, in a plane parallel to the upper surface of the substrate, a contact portion between the sub-pattern and the adjacent etched hole is in an arc shape that is recessed toward the inside of the sub-pattern.

18. The method according to claim 16, characterized in that A diameter of the first hole portion is larger than a line width of the active pattern, and a diameter of the second hole portion is smaller than twice a distance between two adjacent active patterns.

19. The method according to claim 16, wherein The bottom of the first hole portion and the bottom of the first isolation structure are located at different heights.

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