A process method of P-type doped control gate floating gate type split gate flash memory
By employing a P-type doped gate control method in the gate-splitting flash memory process, the problems of threshold voltage reduction and leakage current increase caused by device miniaturization were solved, achieving an increase in threshold voltage and a decrease in leakage current while maintaining the device's junction breakdown voltage and process compatibility.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- HUA HONG SEMICON WUXI LTD
- Filing Date
- 2021-11-15
- Publication Date
- 2026-06-02
AI Technical Summary
In the miniaturization process of existing 2-bit/cell gate-based floating gate flash memory devices, the control gate's ability to control the channel is weakened, resulting in a decrease in the threshold voltage after programming and an increase in leakage current. Furthermore, adding a P-type injection layer to prevent the floating gate storage transistor from punching through and to increase the threshold voltage will reduce the junction breakdown voltage of the device.
The floating gate type split-gate flash memory process using P-type doped control gates involves low-energy, high-dose, and large-tilt-angle P-type impurity implantation after the second etching of CG-Poly to dope the CG-Poly. Combined with the work function difference of the heavily P-type doped polysilicon gate, the threshold voltage is increased and the leakage current is reduced.
The threshold voltage was increased by approximately 1.1V, leakage current was significantly reduced, and the junction breakdown voltage remained unchanged, improving process compatibility and device performance.
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Figure CN114038852B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of flash memory technology, specifically a floating gate type split-gate flash memory process method with a P-type doped control gate. Background Technology
[0002] Flash memory is a non-volatile memory, meaning data is not lost when power is off. Because flash memory doesn't rewrite data byte-by-byte like RAM (Random Access Memory), it cannot replace RAM. A flash memory card is a storage device that uses flash memory technology to store electronic information. It's commonly used in small digital products such as digital cameras, PDAs, and MP3 players as a storage medium, hence its small size, resembling a card, hence the name "flash memory card." Depending on the manufacturer and application, flash memory cards include SmartMedia (SM card), Compact Flash (CF card), MultiMediaCard (MMC card), Secure Digital (SD card), Memory Stick, XD-PictureCard (XD card), and Microdrive. Although these flash memory cards differ in appearance and specifications, their underlying technology is the same. The difference between NOR and NAND flash memory is significant. To illustrate, NOR flash memory is more like RAM, with independent address and data lines, but it's more expensive and has a smaller capacity. NAND flash memory, on the other hand, is more like a hard drive, sharing I / O lines for both address and data. Similar to a hard drive, all information is transmitted through a single I / O line. Furthermore, NAND flash memory is cheaper than NOR flash memory while offering much larger capacity. Therefore, NOR flash memory is better suited for frequent random read / write operations, typically used to store program code and run it directly within the flash memory. Mobile phones are major users of NOR flash memory, hence their typically small "memory" capacity. NAND flash memory is primarily used for data storage; commonly used flash memory products such as flash drives and memory cards use NAND flash memory. It's also important to understand that flash memory speed is actually quite limited. Its operating speed and frequency are much lower than RAM, and the hard drive-like operation of NAND flash memory is significantly slower than direct access to RAM. Therefore, don't assume that the performance bottleneck of flash drives is the interface, or that adopting a USB 2.0 interface will result in a significant performance boost. As mentioned earlier, NAND flash memory operates inefficiently due to its architecture and interface design; it does operate quite similarly to a hard drive (although NAND flash memory was indeed designed with hard drive compatibility in mind). Its performance characteristics are also similar to hard drives: small data blocks are processed very slowly, while large data blocks are processed very quickly—a difference far greater than with other storage media. This performance characteristic is very noteworthy. Flash memory offers fast access, is noiseless, and generates little heat. Users with small storage needs can disregard this and simply buy flash memory for the same storage capacity. However, if a large capacity (e.g., 500GB) is required, a hard drive is preferable, as it is cheaper and can still meet the user's needs.Flash memory has become the mainstream non-volatile semiconductor storage technology. Flash memory is divided into two types: multi-gate flash memory and split-gate flash memory. Split-gate flash memory technology is widely used in various embedded electronic products such as financial IC cards and automotive electronics.
[0003] The existing 2-bit / cell (two bits per storage unit) grid-flying flash memory structure is as follows: Figure 1 As shown, the manufacturing process is as follows: Figure 2 As shown, with the continuous miniaturization of the device control gate, the control gate's control over the channel becomes weaker, resulting in a decrease of approximately 1.5V in the threshold voltage (Vtp) after Flash cell programming. This leads to a sharp increase in device leakage current (IrO1). Therefore, to reduce IrO1, the dose of the P-type injection layer for anti-push-through and threshold voltage of the floating-gate memory transistor must be increased. However, increasing the dose of the P-type injection layer for anti-push-through and threshold voltage of the floating-gate memory transistor will reduce the junction breakdown voltage of the device. Summary of the Invention
[0004] The purpose of this invention is to provide a floating gate type split-gate flash memory process with a P-type doped control gate, so as to solve the problems mentioned in the background art.
[0005] To achieve the above objectives, the present invention provides the following technical solution:
[0006] A floating-gate type multi-gate flash memory process includes a medium-to-high voltage P-type well formed on a P-type substrate, a floating gate dielectric layer, an N-type doped floating gate polysilicon, an ONO (Oxide-Nitride-Oxide) dielectric stack between polysilicon layers, a P-type doped control gate (CG) polysilicon, a first sidewall dielectric layer, P-type implantation for punch-through protection and threshold voltage setting of the floating gate storage transistor, a second sidewall dielectric layer, a select gate dielectric layer, an N-type doped select gate polysilicon layer, a dielectric layer protecting the select gate polysilicon, a lightly doped drain (LDD) ion implantation layer, a third sidewall dielectric layer, a heavily doped source / drain ion implantation layer, and an implantation layer for adjusting the threshold voltage of the select transistor device. The process steps are as follows:
[0007] S1: Defines the active area for the floating gate flash memory and the peripheral logic area;
[0008] S2: Injection forms a P-type injection layer that prevents punch-through and sets the threshold voltage for floating-gate memory transistors;
[0009] S3: Perform the first CG-Poly etching and ion implantation to form the threshold voltage implantation layer for the selector device;
[0010] S4: A self-aligned selection gate is formed using CMP method;
[0011] S5: Perform low-energy, high-dose, and large-tilt-angle P-type impurity implantation to dope CG-Poly;
[0012] S6: Perform LDD injection, third sidewall deposition and etching, and source / drain injection in sequence.
[0013] As a further aspect of the present invention: In S1, a floating gate oxide layer is first grown by thermal oxidation on a P-type substrate; an N-type in-situ doped polysilicon layer and a silicon nitride layer are grown; then, the STI (shallow-trench-isolation) process is used; simultaneously, the active regions of the flash memory and the peripheral logic region are defined, and implantation is performed to form a medium-to-high voltage P-type well.
[0014] As a further embodiment of the present invention: in S2, an ONO layer between polysilicon layers, an undoped polysilicon layer, and a thick silicon nitride layer are deposited sequentially; the flash memory cell region is defined by photolithography, and the silicon nitride layer in the opening region is etched away; using the thick silicon nitride layer as a mask, a P-type injection layer for anti-punch-through and threshold voltage of the floating gate storage transistor is formed.
[0015] As a further embodiment of the present invention: In S3, firstly, an insulating dielectric layer is deposited, and anisotropic etching is performed to form a first sidewall, followed by CG-Poly first etching; then, an insulating dielectric layer is deposited again, and anisotropic etching is performed to form a second sidewall. The second sidewall and the first sidewall are used together as a hard mask, and self-aligned etching is performed to form a floating gate. Ion implantation is then performed to adjust the threshold voltage of the selector, forming an adjustment selector device threshold voltage implantation layer.
[0016] As a further embodiment of the present invention: in S4, a select gate dielectric layer and a select gate polysilicon layer are deposited sequentially, and a self-aligned select gate is formed by CMP.
[0017] As a further embodiment of the present invention: In S5, thermal oxidation forms a dielectric layer protecting the selected gate polysilicon above the N-type doped selected gate polysilicon layer, and together with the first sidewall and the selected gate dielectric layer, it serves as a hard mask. Wet etching removes the remaining silicon nitride layers on both sides, and then low-energy, high-dose, large-tilt-angle P-type impurity implantation is performed to dope the CG-Poly before the second etching of the CG-Poly; or the second self-aligned etching removes the CG-Poly at the opening, and low-energy, high-dose, large-tilt-angle P-type impurity implantation is performed to dope the CG-Poly after the second etching of the CG-Poly.
[0018] As a further embodiment of the present invention: in S6, the control gate, the ONO layer, and the floating gate are etched sequentially, LDD implantation is performed sequentially, a lightly doped drain ion implantation layer and a third sidewall dielectric layer are deposited and etched, and a source / drain implantation layer is performed to form a heavily doped source / drain ion implantation layer.
[0019] Compared with the prior art, the beneficial effects of the present invention are:
[0020] 1. This invention employs low-energy, high-dose, and large-tilt-angle P-type impurity implantation to dope CG-Poly before or after the second CG-Poly etching. By placing the doping implantation of CG-Poly after the second CG-Poly etching, the implanted P-type impurity ions undergo less thermal propagation, reducing the diffusion of P-type impurity ions from CG-Poly to other materials and improving process compatibility.
[0021] 2. This invention also utilizes the work function difference of a P-type heavily doped polysilicon gate. Work function of N-type heavily doped polysilicon gate The voltage is increased by about 1.2V, which increases Vtp by about 1.1V and significantly reduces leakage current.
[0022] 3. This invention uses P-type CG-Poly, which can increase Vtp while keeping the junction doping unchanged, thus minimizing the impact on the junction breakdown voltage. Attached Figure Description
[0023] Figure 1 This is a structural diagram of an existing 2-bit / cell segmented floating gate flash memory.
[0024] Figure 2 This is a process flow diagram for existing 2-bit / cell segmented floating-gate flash memory.
[0025] Figure 3 A flowchart illustrating the manufacturing process steps of a floating gate split-gate flash memory with a P-type doped control gate.
[0026] Figure 4 This is a partial structural diagram of a floating gate split-gate flash memory process with a P-type doped control gate.
[0027] Figure 5 This is a partial structural diagram of a floating gate split-gate flash memory process with a P-type doped control gate.
[0028] Figure 6 This is a partial structural diagram of a floating gate split-gate flash memory process with a P-type doped control gate.
[0029] Figure 7This is a partial structural diagram of a floating gate split-gate flash memory process with a P-type doped control gate.
[0030] Figure 8 This is a partial structural diagram of a floating gate split-gate flash memory process with a P-type doped control gate.
[0031] Figure 9 This is a partial structural diagram of a floating gate split-gate flash memory process with a P-type doped control gate.
[0032] Figure 10 This is a partial structural diagram of a floating gate split-gate flash memory process with a P-type doped control gate.
[0033] Figure 11 This is a process simulation diagram illustrating the floating gate split-gate flash memory fabrication process using a P-type doped control gate.
[0034] Figure 12 This is a device simulation table diagram for the floating gate split-gate flash memory process with a P-type doped control gate.
[0035] Figure 13 This is a schematic diagram of the structure in the floating gate split-gate flash memory process with a P-type doped control gate.
[0036] The figure shows: 101 A medium-to-high voltage P-type well formed on a P-type substrate; 102 A floating gate dielectric layer; 103 N-type doped floating gate polysilicon; 104 An ONO dielectric stack between polysilicon layers; 105 P-type doped control gate polysilicon; 106 A first sidewall dielectric layer; 107 A P-type implantation layer for preventing punch-through and setting threshold voltage of the floating gate storage transistor; 108 A second sidewall dielectric layer; 109 A select gate dielectric layer; 110 N-type doped select gate polysilicon layer; 111 A dielectric layer protecting the select gate polysilicon; 112 A lightly doped drain ion implantation layer; 113 A third sidewall dielectric layer; 114 A heavily doped source / drain ion implantation layer; 115 An implantation layer adjusting the threshold voltage of the select transistor device; 501 A thick silicon nitride layer; 502 A silicon nitride layer; and 503 A trench. Detailed Implementation
[0037] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.
[0038] Please see Figures 1-13In this embodiment of the invention, a floating gate split-gate flash memory process with a P-type doped control gate includes: 101 a medium-to-high voltage P-type well formed on a P-type substrate; 102 a floating gate dielectric layer; 103 N-type doped floating gate polysilicon; 104 an ONO dielectric stack between polysilicon layers; 105 P-type doped control gate polysilicon; 106 a first sidewall dielectric layer; 107 a P-type implantation layer for preventing punch-through and setting threshold voltage of the floating gate storage transistor; 108 a second sidewall dielectric layer; 109 a select gate dielectric layer; 110 an N-type doped select gate polysilicon layer; 111 a dielectric layer protecting the select gate polysilicon; 112 a lightly doped drain ion implantation layer; 113 a third sidewall dielectric layer; 114 a heavily doped source / drain ion implantation layer; 115 an implantation layer for adjusting the threshold voltage of the select transistor device; 501 a thick silicon nitride layer; 502 a silicon nitride layer; and 503 a trench. The process steps are as follows:
[0039] S1: Defines the active area for the floating gate flash memory and the peripheral logic area;
[0040] S2: Injection forms a P-type injection layer that prevents punch-through and sets the threshold voltage for floating-gate memory transistors;
[0041] S3: Perform the first CG-Poly etching and ion implantation to form the threshold voltage implantation layer for the selected transistor device;
[0042] S4: A self-aligned selection gate is formed using CMP method;
[0043] S5: Perform low-energy, high-dose, and large-tilt-angle P-type impurity implantation to dope CG-Poly;
[0044] S6: Perform LDD injection, third sidewall deposition and etching, and source / drain injection in sequence.
[0045] In step S1, a floating gate oxide layer 102 is first grown on a P-type substrate by thermal oxidation; an N-type in-situ doped polysilicon layer 103 and a silicon nitride layer 502 are grown; an STI process is then performed; simultaneously, the active regions of the flash memory and peripheral logic areas are defined, and implantation is performed to form a medium-to-high voltage P-type well 101, such as... Figure 4 As shown.
[0046] In step S2, an ONO layer between polysilicon layers, an undoped polysilicon layer 105, and a thick silicon nitride layer 501 are deposited sequentially. The flash memory cell region is defined by photolithography, and the silicon nitride layer in the opening region is etched away. Using 501 as a mask, P-type implantation for anti-punch-through and threshold voltage thresholding of the floating gate storage transistor is performed to form 107. Figure 5 As shown.
[0047] In step S3, an insulating dielectric layer is deposited, and anisotropic etching is used to form a first sidewall 106, followed by a first CG-Poly etching. Then, an insulating dielectric layer is deposited again, and anisotropic etching is used to form a second sidewall 108. Using the second and first sidewalls together as a hard mask, self-aligned etching is performed to form a floating gate, and ion implantation is performed to adjust the selector threshold voltage, forming step 115. Figure 6 As shown.
[0048] In step S4, a select gate dielectric layer 109 and a select gate polysilicon layer 110 are deposited sequentially. A self-aligned select gate is then formed using CMP (Continuous Metallurgy Processing). Figure 7 As shown.
[0049] In step S5, thermal oxidation forms 111 above 110, and together with the first sidewall and the selected gate dielectric layer 109, it serves as a hard mask. Wet etching removes the remaining silicon nitride layers 501 on both sides, and then before the second etching of CG-Poly (as shown in the image). Figure 8 (As shown) perform low-energy, high-dose, large-tilt-angle P-type impurity implantation to dope CG-Poly; or remove the CG-Poly at the opening using a second self-aligned etching, after the second CG-Poly etching (as shown) Figure 9 (As shown) Low-energy, high-dose, and large-tilt-angle P-type impurity implantation was performed to dope CG-Poly.
[0050] In step S6, the control gate 105, ONO layer 104, and floating gate 103 are etched sequentially, followed by LDD implantation 112, deposition and etching of the third sidewall 113, and source / drain implantation 114. Figure 10 As shown.
[0051] Simulation results show that the doping of CG-Poly can reach approximately 7.0e19cm. -3 ,like Figure 11 As shown; device simulation revealed that, while maintaining a constant junction BV, the leakage current was reduced by approximately three orders of magnitude, such as... Figure 12 As shown.
[0052] Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art can still modify the technical solutions described in the foregoing embodiments or make equivalent substitutions for some of the technical features. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.
Claims
1. A floating-gate type split-gate flash memory process with a P-type doped control gate, characterized in that, Includes the following steps: S1: First, a floating gate oxide layer is thermally oxidized and grown on a P-type substrate (102); an N-type undoped polysilicon layer is grown (103); then, the active regions of the flash memory and peripheral logic area are defined by STI process, and the active regions of the flash memory are implanted to form a medium-to-high voltage P-type well (101); S2: Sequentially deposit an ONO layer between polysilicon layers, an undoped polysilicon layer, and a thick silicon nitride layer; define the flash memory cell region by photolithography, and etch away the silicon nitride layer in the opening region; use the thick silicon nitride layer as a mask to perform P-type injection for the floating gate transistor to prevent punch-through and threshold voltage to form the P-type injection layer for the floating gate transistor (107); S3: First, an insulating dielectric layer is deposited, and anisotropic etching is used to form the first sidewall (106). Then, CG-Poly first etching is performed in the opening region of the flash memory. The insulating dielectric layer is deposited again, and anisotropic etching is used to form the second sidewall (108). The second sidewall (108) and the first sidewall (106) are used together as a hard mask. Self-aligned etching is used to form a floating gate, and ion implantation is performed to adjust the threshold voltage of the selector. An adjustment selector device threshold voltage implantation layer (115) is formed on the upper part of the P-type implantation layer (107) in the opening region of the flash memory. S4: Sequentially deposit the select gate dielectric layer (109) and the select gate polysilicon layer (110), and form a self-aligned select gate by CMP. S5: Thermal oxidation forms a protective dielectric layer over the N-type doped selected gate polysilicon layer, and together with the first sidewall and the selected gate dielectric layer, it serves as a hard mask. Wet etching removes the remaining silicon nitride layers on both sides. Then, before the second etching of CG-Poly, low-energy, high-dose, and large-tilt-angle P-type impurity implantation is performed to dope CG-Poly; or, the second self-aligned etching removes the CG-Poly at the opening, and after the second etching of CG-Poly, low-energy, high-dose, and large-tilt-angle P-type impurity implantation is performed to dope CG-Poly. S6: Perform LDD injection, third sidewall deposition and etching, and source / drain injection in sequence.
2. The floating-gate type split-gate flash memory process method according to claim 1, characterized in that: In step S6, the control gate, ONO layer, and floating gate are etched sequentially, LDD implantation is performed sequentially, and a lightly doped drain ion implantation layer and a third sidewall dielectric layer are deposited and etched to form a source-drain implantation layer. Source-drain implantation and a heavily doped source-drain ion implantation layer are then performed.