Array substrate, manufacturing method thereof, and display device

Abstract

The present disclosure relates to the field of display technology, and discloses an array substrate, a method for manufacturing the same, and a display device. The array substrate includes a base substrate, a first conductive layer, a protective layer, an interlayer dielectric layer, and a second conductive layer. The first conductive layer is disposed on one side of the base substrate and includes a connecting portion. The protective layer is disposed on a side of the first conductive layer away from the base substrate and is provided with a first via hole connected to the connecting portion. The interlayer dielectric layer is disposed on a side of the protective layer away from the base substrate and is provided with a second via hole connected to the first via hole. The orthographic projection of the second via hole on the base substrate overlaps the orthographic projection of the protective layer on the base substrate. The second conductive layer is disposed on a side of the interlayer dielectric layer away from the base substrate and is connected to the connecting portion via the first and second via holes. The array substrate is less susceptible to poor contact and has excellent display effects.

Description

Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular, to an array substrate, a method for preparing the array substrate, and a display device including the array substrate. Background Art

[0002] In large-scale OLED (Organic Electroluminescence Display) display devices, thicker metal layers and insulating film layers are used to achieve uniform signal transmission; however, poor contact is easily caused at via holes formed in the thicker insulating film layers.

[0003] It should be noted that the information disclosed in the above background technology section is only used to enhance the understanding of the background of the present disclosure, and therefore may include information that does not constitute prior art known to ordinary technicians in the field. Summary of the Invention

[0004] The purpose of the present disclosure is to overcome the above-mentioned shortcomings of the prior art that are prone to poor contact, and to provide an array substrate that is not prone to poor contact, a method for preparing the array substrate, and a display device including the array substrate.

[0005] According to one aspect of the present disclosure, there is provided an array substrate, comprising:

[0006] substrate;

[0007] A first conductive layer is provided on one side of the base substrate, wherein the first conductive layer includes a connecting portion;

[0008] a protective layer, disposed on a side of the first conductive layer away from the base substrate, the protective layer being provided with a first via hole, the first via hole being connected to the connecting portion;

[0009] an interlayer dielectric layer disposed on a side of the protective layer away from the base substrate, wherein a second via hole is disposed on the interlayer dielectric layer, the second via hole being connected to the first via hole, and an orthographic projection of the second via hole on the base substrate overlapping with an orthographic projection of the protective layer on the base substrate;

[0010] The second conductive layer is provided on a side of the interlayer dielectric layer away from the base substrate, and the second conductive layer is connected to the connecting portion through the first via hole and the second via hole.

[0011] In an exemplary embodiment of the present disclosure, the material of the protective layer is one or both of photosensitive organic silicon and silicon oxide formed by exposing the photosensitive organic silicon to light.

[0012] In an exemplary embodiment of the present disclosure, the array substrate further includes:

[0013] An isolation layer is provided between the protection layer and the interlayer dielectric layer. A third via hole is provided on the isolation layer. The third via hole is connected to the second via hole and the first via hole.

[0014] In an exemplary embodiment of the present disclosure, the first conductive layer includes:

[0015] an active layer comprising a channel portion and a conductor portion, wherein the conductor portion is the connecting portion;

[0016] A first data line, wherein a portion of the first data line is the connecting portion.

[0017] In an exemplary embodiment of the present disclosure, the array substrate further includes:

[0018] a light shielding layer, provided between the base substrate and the active layer;

[0019] a buffer layer, disposed between the light shielding layer and the active layer;

[0020] a gate insulating layer, disposed on a side of the active layer away from the base substrate;

[0021] The gate is arranged on a side of the gate insulating layer away from the base substrate.

[0022] According to another aspect of the present disclosure, a method for preparing an array substrate is provided, comprising:

[0023] providing a substrate;

[0024] forming a first conductive layer on one side of the base substrate, wherein the first conductive layer includes a connecting portion;

[0025] forming a protective material layer on a side of the first conductive layer away from the base substrate, and processing the protective material layer to form a protective layer;

[0026] forming an interlayer dielectric material layer on a side of the protective layer away from the base substrate, and patterning the interlayer dielectric material layer to form a second via hole, wherein an orthographic projection of the second via hole on the base substrate overlaps with an orthographic projection of the protective layer on the base substrate;

[0027] performing patterning on the protective layer to form a first via hole, wherein the first via hole is connected to the connecting portion, and the second via hole is connected to the first via hole;

[0028] A second conductive layer is formed on a side of the interlayer dielectric layer away from the base substrate, and the second conductive layer is connected to the connecting portion through the first via hole and the second via hole.

[0029] In an exemplary embodiment of the present disclosure, the processing of the protective material layer to form the protective layer includes:

[0030] The protective material layer opposite to the connecting portion is half-exposed, and the remaining protective material layer is fully exposed, so that the exposed protective material layer forms an isolation layer and the unexposed protective material layer forms the protective layer.

[0031] In an exemplary embodiment of the present disclosure, while patterning the interlayer dielectric material layer to form the second via hole, the preparation method further includes:

[0032] The isolation layer is patterned to form a third via hole, wherein the third via hole is connected to the second via hole and the first via hole.

[0033] In an exemplary embodiment of the present disclosure, before patterning the protective layer to form the first via hole, the preparation method further includes:

[0034] The protective layer is exposed to light.

[0035] In an exemplary embodiment of the present disclosure, patterning the protective layer to form the first via hole includes:

[0036] The protective layer is dry-etched by a mixture of CF4 plasma and O2 plasma to form a first via hole.

[0037] In an exemplary embodiment of the present disclosure, the protective material layer is made of photosensitive silicone, which forms silicon oxide after exposure.

[0038] In an exemplary embodiment of the present disclosure, the processing of the protective material layer to form the protective layer further includes:

[0039] The isolation layer is developed to remove the isolation layer.

[0040] In an exemplary embodiment of the present disclosure, patterning the protective layer to form the first via hole includes:

[0041] The protective layer is dry-etched using a mixture of SF6 plasma and O2 plasma to form a first via hole.

[0042] In an exemplary embodiment of the present disclosure, it is characterized in that the material of the protective material layer is photosensitive silicone, and the photosensitive silicone includes silicone resin and photosensitizer.

[0043] According to yet another aspect of the present disclosure, a display device is provided, comprising: an array substrate as described above.

[0044] In the array substrate disclosed herein, a protective layer is provided on a side of the first conductive layer away from the base substrate. On the one hand, when the interlayer dielectric layer is etched to form the second via hole, the protective layer can protect the first conductive layer to prevent the connection portion of the first conductive layer from being etched and resulting in poor etching, which will not affect the connection between the connection portion and the second conductive layer, and thus poor contact is less likely to occur. On the other hand, when the protective layer is etched to form the first via hole, due to the thin thickness of the protective layer and the small etching amount, excessive etching will not occur, and the connection portion of the first conductive layer will not be etched and resulting in poor etching, which will not affect the connection between the connection portion and the second conductive layer, and thus poor contact is less likely to occur. On the other hand, the protective layer has a flattening effect, which can reduce the step difference of the film layer and provide a relatively flat base surface for the second conductive layer, which is beneficial to the formation of the second conductive layer and the conductive effect. The array substrate can improve the display effect of the display panel.

[0045] It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0046] The accompanying drawings are incorporated into and constitute a part of the specification, illustrate embodiments consistent with the present disclosure, and together with the specification, are used to explain the principles of the present disclosure. Obviously, the drawings described below are only some embodiments of the present disclosure, and those skilled in the art can derive other drawings based on these drawings without inventive effort.

[0047] Figure 1 FIG. 4 is a schematic diagram of the display effect of a display device when the thickness of the interlayer dielectric layer is 8000 angstroms. FIG.

[0048] Figure 2 FIG. 4 is a schematic diagram showing the display effect of a display device when the thickness of the interlayer dielectric layer is 9000 angstroms. FIG.

[0049] Figure 3 FIG. 4 is a schematic diagram of the display effect of a display device when the thickness of the interlayer dielectric layer is 12000 angstroms. FIG.

[0050] Figure 4 Schematic diagram of the structure of an exemplary embodiment of the array substrate disclosed herein.

[0051] Figure 5FIG. 4 is a structural diagram of another exemplary embodiment of the array substrate disclosed herein.

[0052] Figure 6 The present invention is a schematic flow chart of an exemplary embodiment of a method for preparing an array substrate.

[0053] Figure 7-13 Schematic diagram of the structure of each step of an exemplary embodiment of a method for preparing an array substrate disclosed herein.

[0054] Figure 14-17 Schematic diagram of the structure of each step of another exemplary embodiment of the method for preparing an array substrate disclosed herein.

[0055] Description of reference numerals:

[0056] 1. Base substrate; 2. Light shielding layer; 3. Buffer layer;

[0057] 4. First conductive layer; 4a. Active layer; 41. Conductor portion; 42. Channel portion; 43. First data line; 44. Connecting portion;

[0058] 5. Gate insulating layer; 6. Gate electrode;

[0059] 7. Protective material layer; 71. Isolation layer; 72. Protective layer; 73. First via hole; 74. Third via hole;

[0060] 8. Interlayer dielectric material layer; 81. Interlayer dielectric layer; 82. Second via hole;

[0061] 9. Second conductive layer; 91. Source electrode; 92. Drain electrode; 93. Second data line;

[0062] 10. Mask plate; 101. Semi-transparent area; 102. Fully transparent area. DETAILED DESCRIPTION

[0063] Example embodiments will now be described more fully with reference to the accompanying drawings. However, the example embodiments can be implemented in many forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete and will fully convey the concepts of the example embodiments to those skilled in the art. Like reference numerals in the figures represent identical or similar structures, and thus their detailed descriptions will be omitted. Furthermore, the figures are merely schematic illustrations of the present disclosure and are not necessarily drawn to scale.

[0064] Although relative terms such as "upper" and "lower" are used in this specification to describe the relationship of one illustrated component to another, these terms are used herein for convenience only, such as in accordance with the orientation of the illustrations in the accompanying drawings. It will be understood that if the illustrated device were flipped upside down, the component described as "upper" would become the component "lower." When a structure is referred to as "on" another structure, this may mean that the structure is integrally formed with the other structure, that the structure is "directly" disposed on the other structure, or that the structure is "indirectly" disposed on the other structure via the other structure.

[0065] The terms "a", "an", "the", "said" and "at least one" are used to indicate the presence of one or more elements / components / etc.; the terms "including" and "having" are used to express open-ended inclusion and mean that additional elements / components / etc. may be present in addition to the listed elements / components / etc.; the terms "first", "second" and "third" etc. are used only as labels and are not intended to limit the quantity of their objects.

[0066] The inventors have found that when etching a thicker insulating film layer to form a via hole, due to the difference in etching depth, it is necessary to maintain a larger etching amount to achieve the etching amount of the via hole with the deepest etching depth. However, this is prone to excessive etching. The thicker the insulating film layer, the greater the excessive etching, and the more serious the uneven etching. As a result, the conductive layer at the via hole is easily etched, resulting in poor etching, affecting the connection with the second conductive layer 9 and causing poor contact, which ultimately affects the display of the display device; refer to Figure 1-Figure 3 The diagram shows the display effects of a display device when the interlayer dielectric layer has different thicknesses. Therefore, the thicker the insulating film layer, the less ideal the display effect.

[0067] The exemplary embodiment of the present disclosure provides an array substrate, such as Figure 3 and Figure 4 As shown, the array substrate may include a base substrate 1, a first conductive layer 4, a protective layer 72, an interlayer dielectric layer 81 and a second conductive layer 9; the first conductive layer 4 is provided on one side of the base substrate 1, and the first conductive layer includes a connecting portion 44; the protective layer 72 is provided on a side of the first conductive layer 4 away from the base substrate 1, and a first via 73 is provided on the protective layer 72, and the first via 73 is connected to the connecting portion 44; the interlayer dielectric layer 81 is provided on a side of the protective layer 72 away from the base substrate 1, and a second via 82 is provided on the interlayer dielectric layer 81, and the second via 82 is connected to the first via 73, and the orthographic projection of the second via 82 on the base substrate 1 overlaps with the orthographic projection of the protective layer 72 on the base substrate 1; the second conductive layer 9 is provided on a side of the interlayer dielectric layer 81 away from the base substrate 1, and the second conductive layer 9 is connected to the connecting portion 44 through the first via 73 and the second via 82.

[0068] In the array substrate disclosed herein, when the interlayer dielectric layer 81 is etched to form the second via hole 82, the protective layer 72 can protect the first conductive layer 4, thereby preventing the connection portion 44 of the first conductive layer 4 from being etched and causing poor etching, which will not affect the connection between the connection portion 44 and the second conductive layer 9, and thus poor contact is not likely to occur; when the protective layer 72 is etched to form the first via hole 73, due to the thin thickness of the protective layer 72 and the small etching amount, excessive etching will not occur, thereby preventing the connection portion 44 of the first conductive layer 4 from being etched and causing poor etching, which will not affect the connection between the connection portion 44 and the second conductive layer 9, and thus poor contact is not likely to occur; the protective layer 72 has a flattening effect, which can reduce the film layer step difference and provide a relatively flat base surface for the second conductive layer 9, which is beneficial to the formation of the second conductive layer 9 and the conductive effect; the array substrate can improve the display effect of the display panel.

[0069] In this exemplary embodiment, the base substrate 1 may be a rigid substrate, for example, a glass substrate; the base substrate 1 may be a flexible substrate, for example, a PI (polyimide) substrate.

[0070] A light-shielding layer 2, which can be made of metal, is provided on one side of the base substrate 1. The orthographic projection of the thin-film transistor on the base substrate 1 lies within the orthographic projection of the light-shielding layer 2 on the base substrate 1. Light incident from the base substrate 1 generates photogenerated carriers, which in turn significantly affect the properties of the thin-film transistor and ultimately the image quality of the display device. The light-shielding layer 2 blocks light incident from the base substrate 1, thereby preventing any impact on the properties of the thin-film transistor and the display quality of the display device.

[0071] A buffer layer 3 is provided on a side of the light shielding layer 2 away from the base substrate 1 . The buffer layer 3 is made of an insulating material and can insulate the light shielding layer 2 from the first conductive layer 4 .

[0072] A first conductive layer 4 is provided on a side of the buffer layer 3 away from the base substrate 1. The first conductive layer 4 may include an active layer 4a and a first data line 43. The active layer 4a may include a channel portion 42 and a conductor portion 41. The conductor portion 41 is a connecting portion 44. Two conductor portions 41 may be provided, and the two conductor portions 41 may be disposed on opposite sides of the channel portion 42. The material of the active layer 4a may be IGZO (Indium Gallium Zinc Oxide).

[0073] A portion of the first data line 43 is also the connecting portion 44 . The first data line 43 , the gate electrode 6 , and the gate line can be formed through a single patterning process.

[0074] A gate insulating layer 5 is provided on the side of the first conductive layer 4 away from the base substrate 1. Specifically, a gate insulating layer 5 is provided on the side of the channel portion 42 away from the base substrate 1. The orthographic projection of the channel portion 42 on the base substrate 1 is located within the orthographic projection of the gate insulating layer 5 on the base substrate 1, or the orthographic projection of the channel portion 42 on the base substrate 1 coincides with the orthographic projection of the gate insulating layer 5 on the base substrate 1; that is, the gate insulating layer 5 at least covers the channel portion 42. Of course, the gate insulating layer 5 can also cover the entire array substrate.

[0075] A gate 6 is provided on a side of the gate insulating layer 5 away from the base substrate 1. The orthographic projection of the gate 6 on the base substrate 1 is located within the orthographic projection of the gate insulating layer 5 on the base substrate 1, or the orthographic projection of the gate 6 on the base substrate 1 coincides with the orthographic projection of the gate insulating layer 5 on the base substrate 1. The gate insulating layer 5 insulates and isolates the channel portion 42 from the gate 6.

[0076] Reference Figure 4 As shown, a protective layer 72 is provided on the side of the first data line 43 away from the base substrate 1 and on the side of the conductor portion 41 away from the base substrate 1. The protective layer 72 covers a portion of the first data line 43 and the conductor portion 41. A first via 73 is provided on the protective layer 72. The first via 73 connects to the connecting portion 44, that is, the first via 73 connects to the first data line 43 and the conductor portion 41. The material of the protective layer 72 can be photosensitive silicone, and its thickness is greater than or equal to 1000 angstroms and less than or equal to 6000 angstroms. Of course, in other exemplary embodiments of the present disclosure, the protective layer 72 can cover the entire array substrate.

[0077] Reference Figure 5 As shown, in another exemplary embodiment of the present disclosure, an isolation layer 71 is provided on a side of the protective layer 72 away from the base substrate 1. A third via 74 is provided on the isolation layer 71. The third via 74 is connected to the second via 82 and the first via 73. That is, the third via 74 is connected to the first data line 43 and the conductor portion 41 through the first via 73. In this exemplary embodiment, the material of the protective layer 72 and the isolation layer 71 can be silicon oxide formed by exposing photosensitive organic silicon. However, the protective layer 72 and the isolation layer 71 are not formed by the same exposure process, which will be described in detail in the subsequent preparation method. The thickness of the protective layer 72 is greater than or equal to 1000 angstroms and less than or equal to 6000 angstroms, for example, can be 3000 angstroms; the thickness of the isolation layer 71 is greater than or equal to 3000 angstroms and less than or equal to 11000 angstroms.

[0078] Of course, in other exemplary embodiments of the present disclosure, when some of the photosensitive silicone remains unexposed or the silicon oxide is not completely removed, the material of the protective layer 72 can be a mixture of the photosensitive silicone and the silicon oxide formed after the photosensitive silicone is exposed.

[0079] Reference Figure 4 As shown, an interlayer dielectric layer 81 is provided on the side of the protective layer 72 away from the base substrate 1, and a second via 82 is provided on the interlayer dielectric layer 81. The second via 82 is connected to the first via 73, that is, the second via 82 is connected to the connecting portion 44 through the first via 73. The orthographic projection of the second via 82 on the base substrate 1 overlaps with the orthographic projection of the protective layer 72 on the base substrate 1, that is, the orthographic projection of the second via 82 on the base substrate 1 can be located within the orthographic projection of the protective layer 72 on the base substrate 1; or, the orthographic projection of the second via 82 on the base substrate 1 can coincide with or partially coincide with the orthographic projection of the protective layer 72 on the base substrate 1. The material of the interlayer dielectric layer 81 can be silicon oxide. Figure 5 As shown, the interlayer dielectric layer 81 is arranged on the side of the isolation layer 71 away from the substrate 1. The structure of the interlayer dielectric layer 81 is similar to Figure 4 The same as shown, will not be repeated here.

[0080] Reference Figure 4 and Figure 5 As shown, a second conductive layer 9 is provided on the side of the interlayer dielectric layer 81 away from the base substrate 1. The second conductive layer 9 may include a source electrode 91, a drain electrode 92 and a second data line 93. The source electrode 91 and the drain electrode 92 are connected to the two conductor portions 41 respectively through the second via hole 82 and the first via hole 73; the second data line 93 is connected to the source electrode 91, and the second data line 93 is connected to the first data line 43 through the second via hole 82 and the first via hole 73 to form a data line, so that the data line forms a double-layer structure, which can reduce the resistance of the data line and improve the display effect; moreover, in the case of a short circuit between the first data line 43 or the second data line 93, it will not affect the display of the display panel.

[0081] It should be noted that the array substrate described above is a top-gate array substrate; in other exemplary embodiments of the present disclosure, the array substrate may also be a bottom-gate array substrate or a dual-gate array substrate. The first conductive layer 4 described above may include an active layer 4a; in other exemplary embodiments of the present disclosure, the first conductive layer 4 may also include a gate 6, a source electrode 91, a drain electrode 92, and the like.

[0082] Based on the same inventive concept, the exemplary embodiment of the present disclosure provides a method for preparing an array substrate, referring to Figure 6 As shown, the preparation method may include the following steps:

[0083] Step S10: providing a base substrate 1.

[0084] In step S20 , a first conductive layer 4 is formed on one side of the base substrate 1 . The first conductive layer 4 includes a connecting portion 44 .

[0085] In step S30 , a protective material layer 7 is formed on a side of the first conductive layer 4 away from the base substrate 1 , and the protective material layer 7 is processed to form a protective layer 72 .

[0086] In step S40 , an interlayer dielectric material layer 8 is formed on the side of the protective layer 72 away from the base substrate 1 , and the interlayer dielectric material layer 8 is patterned to form a second via 82 . The orthographic projection of the second via 82 on the base substrate 1 overlaps with the orthographic projection of the protective layer 72 on the base substrate 1 .

[0087] In step S50 , the protective layer 72 is patterned to form a first via hole 73 . The first via hole 73 is connected to the connecting portion 44 , and the second via hole 82 is connected to the first via hole 73 .

[0088] In step S60 , a second conductive layer 9 is formed on a side of the interlayer dielectric layer 81 away from the base substrate 1 . The second conductive layer 9 is connected to the connecting portion 44 through the first via hole 73 and the second via hole 82 .

[0089] In the preparation method of the array substrate disclosed herein, when etching the interlayer dielectric layer 81 to form the second via hole 82, the protective layer 72 can protect the first conductive layer 4 to prevent the connection portion 44 of the first conductive layer 4 from being etched and resulting in poor etching, which will not affect the connection between the connection portion 44 and the second conductive layer 9, and thus poor contact is not likely to occur; when etching the protective layer 72 to form the first via hole 73, due to the thin thickness of the protective layer 72 and the small etching amount, excessive etching will not occur, and the connection portion 44 of the first conductive layer 4 will not be etched and resulting in poor etching, which will not affect the connection between the connection portion 44 and the second conductive layer 9; the protective layer 72 has a flattening effect, which can reduce the film layer step difference and provide a relatively flat base surface for the second conductive layer 9, which is conducive to the formation of the second conductive layer 9 and the conductive effect; the array substrate can improve the display effect of the display panel.

[0090] The following describes in detail the various steps of the method for preparing the array substrate.

[0091] Step S10: providing a base substrate 1.

[0092] In this example embodiment, referring to Figure 7 As shown, a base substrate 1 is provided. The base substrate 1 may be a rigid substrate, for example, a glass substrate; the base substrate 1 may be a flexible substrate, for example, a PI (polyimide) substrate.

[0093] A light-shielding material layer is formed on one side of the base substrate 1 by sputtering, evaporation, deposition and other processes, and the light-shielding material layer is patterned to form a light-shielding layer 2. The light-shielding material layer can be made of metal, and the thickness of the light-shielding layer 2 is about 1500 angstroms.

[0094] A buffer layer 3 is formed on the side of the light shielding layer 2 away from the base substrate 1 and on the exposed base substrate 1 by a coating process or a spin coating process. The buffer layer 3 has a thickness of about 4000 angstroms.

[0095] In step S20 , a first conductive layer 4 is formed on one side of the base substrate 1 , wherein the first conductive layer 4 includes a connecting portion 44 .

[0096] In this example embodiment, referring to Figure 7 As shown, an active material layer is formed on the side of the buffer layer 3 away from the base substrate 1 through processes such as sputtering, evaporation, and deposition. The active material layer is then patterned to form an active layer 4a. Part of the active layer 4a is conductively connected to form a conductor portion 41. The unconducted area serves as a channel portion 42. A thin film transistor has a channel portion 42, with two conductor portions 41 disposed on opposite sides of the channel portion 42. The thickness of the active layer 4a is approximately 340 angstroms, and both conductor portions 41 serve as connectors 44.

[0097] A gate insulating material layer is formed on the side of the active layer 4a away from the base substrate 1 by a coating process or a spin coating process, and the gate insulating material layer is patterned to form a gate insulating layer 5. The orthographic projection of the channel portion 42 on the base substrate 1 is located within the orthographic projection of the gate insulating layer 5 on the base substrate 1, or the orthographic projection of the channel portion 42 on the base substrate 1 coincides with the orthographic projection of the gate insulating layer 5 on the base substrate 1. The thickness of the gate insulating layer 5 is approximately 1500 angstroms. Of course, in another exemplary embodiment of the present disclosure, the gate insulating layer 5 can completely cover the entire array substrate.

[0098] A gate material layer is formed on the side of the gate insulating layer 5 away from the base substrate 1 and on the side of the buffer layer 3 away from the base substrate 1 through processes such as sputtering, evaporation, and deposition. The gate material layer is then patterned to form a first data line 43, a gate 6, and a gate line. That is, the first data line 43 is formed at the same time as the gate 6, the gate 6 is connected to the gate line, and the first data line 43 is not connected to the gate 6 or the gate line. A portion of the first data line 43 is also a connecting portion 44. The orthographic projection of the gate 6 on the base substrate 1 is within the orthographic projection of the gate insulating layer 5 on the base substrate 1, or the orthographic projection of the gate insulating layer 5 on the base substrate 1 coincides with the orthographic projection of the gate 6 on the base substrate 1. The thickness of the gate 6 is approximately 8000 angstroms.

[0099] In step S30 , a protective material layer 7 is formed on a side of the first conductive layer 4 away from the base substrate 1 , and the protective material layer 7 is processed to form a protective layer 72 .

[0100] In this example embodiment, referring to Figure 7As shown, a protective material layer 7 is formed on the side of the gate 6 away from the base substrate 1 and on the side of the conductor portion 41 away from the base substrate 1 through a coating process or a spin coating process. The material of the protective material layer 7 can be a photosensitive organic silicone, for example, polymethylsiloxane or polydimethylsiloxane. The thickness of the protective material layer 7 is greater than or equal to 4000 angstroms and less than or equal to 12000 angstroms. The preparation process of the protective material layer 7 made of this material is highly efficient and simple. To increase the adhesion between the protective material layer 7 and the conductor portion 41, the protective material layer 7 can be subjected to oxygen plasma treatment or surface hydroxylation treatment.

[0101] The protective material layer 7 may be pre-cured at a curing temperature of 60 to 100° C. and a curing time of 20 to 120 seconds. Of course, the curing temperature and curing time may be set according to device requirements.

[0102] Reference Figure 8 As shown, with arrows representing light, a mask plate 10 is placed on the side of the protective material layer 7 away from the base substrate 1. The mask plate 10 may include multiple fully transparent areas 102 and multiple semi-transparent areas 101. The orthographic projections of the semi-transparent areas 101 on the base substrate 1 coincide with the orthographic projections of the connecting portion 44 on the base substrate 1, and the orthographic projections of the fully transparent areas 102 on the base substrate 1 coincide with the orthographic projections of the remaining portions on the base substrate 1. Alternatively, the orthographic projection of the connecting portion 44 on the base substrate 1 may lie within the orthographic projections of the semi-transparent areas 101 on the base substrate 1. Then, the protective material layer 7 is irradiated with ultraviolet light, i.e., the protective material layer 7 is exposed. The protective material layer 7 opposite to the fully transparent area 102 is completely changed to form an isolation layer 71, and the material of the isolation layer 71 is silicon oxide (SiOx); the part of the protective material layer 7 opposite to the semi-transparent area 101, which is far away from the base substrate 1, is changed to form an isolation layer 71, and the material of the isolation layer 71 is silicon oxide (SiOx). The part close to the base substrate 1 does not change the material to form a protective layer 72, and the material of the protective layer 72 can be photosensitive silicone. So that the orthographic projection of the connecting portion 44 on the base substrate 1 is located within the orthographic projection of the protective layer 72 on the base substrate 1, or the orthographic projection of the connecting portion 44 on the base substrate 1 coincides with the orthographic projection of the protective layer 72 on the base substrate 1. Finally, the mask 10 is removed to form Figure 9 The structure shown.

[0103] Of course, in other exemplary embodiments of the present disclosure, the orthographic projection of the second via hole 82 on the base substrate 1 overlaps with the orthographic projection of the protection layer 72 on the base substrate 1 , so that the purpose of the protection layer 72 protecting the connection portion can be achieved.

[0104] In another exemplary embodiment of the present disclosure, referring to Figure 14As shown, the isolation layer 71 can be developed to remove the isolation layer 71, leaving only the protective layer 72 on the side of the isolation layer 71 close to the base substrate 1. The material of the protective material layer 7 in this exemplary embodiment can be a mixture of silicone resin and photosensitive agent, that is, the photosensitive silicone includes silicone resin and photosensitive agent, and the silicone resin and photosensitive agent can be removed together by development after exposure.

[0105] In step S40, an interlayer dielectric material layer 8 is formed on the side of the protective layer 72 away from the base substrate 1, and the interlayer dielectric material layer 8 is patterned to form a second via 82, wherein the orthographic projection of the second via 82 on the base substrate 1 overlaps with the orthographic projection of the protective layer 72 on the base substrate 1.

[0106] In this example embodiment, referring to Figure 10 As shown, an interlayer dielectric material layer 8 is formed on the side of the isolation layer 71 away from the substrate 1 by coating or spin coating. The material of the interlayer dielectric material layer 8 can be silicon oxide (SiOx). The thickness of the interlayer dielectric material layer 8 is about 9000 angstroms.

[0107] A photoresist is formed on the side of the interlayer dielectric material layer 8 away from the substrate 1 by a coating process, and the photoresist is exposed and developed to remove the photoresist at the second via hole 82. Figure 11 As shown, the interlayer dielectric material layer 8 is dry-etched to form a second via hole 82 and an interlayer dielectric layer 81. The dry etching may be performed using a mixture of CF4 plasma and O2 plasma. The orthographic projection of the second via hole 82 on the base substrate 1 overlaps with the orthographic projection of the protective layer 72 on the base substrate 1, so that the protective layer 72 can protect the connecting portion 44 when the second via hole 82 is formed.

[0108] While the interlayer dielectric material layer 8 is dry-etched, the isolation layer 71 is also etched, so that a third via hole 74 is formed on the isolation layer 71 . The third via hole 74 is connected to the second via hole 82 .

[0109] Since the etching selectivity of the interlayer dielectric material layer 8 and the protective layer 72 is relatively large, for example, greater than 10; therefore, this etching cannot etch the protective layer 72, and thus cannot etch the connecting portion 44 of the first conductive layer 4, and effectively protects the connecting portion 44 of the first conductive layer 4 to avoid over-etching of the connecting portion 44.

[0110] In another exemplary embodiment of the present disclosure, referring to Figure 15 As shown, since the isolation layer 71 has been removed by development, an interlayer dielectric material layer 8 is formed on the side of the protective layer 72 away from the base substrate 1 by a coating process or a spin coating process. Figure 16As shown, since the etching selectivity for the interlayer dielectric material layer 8 and the protective layer 72 is relatively large (e.g., greater than 10), only the interlayer dielectric material layer 8 is dry-etched during the etching process to form the second via 82 and the interlayer dielectric layer 81. The dry etching process can employ a mixture of CF4 plasma and O2 plasma. During the dry etching of the interlayer dielectric material layer 8, the protective layer 72 cannot be etched, and thus the connection portion 44 of the first conductive layer 4 cannot be etched. This effectively protects the connection portion 44 of the first conductive layer 4, preventing over-etching of the connection portion 44.

[0111] In step S50 , the protection layer 72 is patterned to form a first via hole 73 .

[0112] In this example embodiment, referring to Figure 12 As shown, the arrows in the figure represent light, which exposes the protective layer 72. This exposure does not require a mask 10, and the entire layer can be exposed. The material of the protective layer 72 is changed from photosensitive silicone to silicon oxide, that is, the material of the protective layer 72 is changed to the same material as the isolation layer 71.

[0113] Reference Figure 13 As shown, the protective layer 72 is dry-etched to form a first via hole 73, and the first via hole 73 is connected to the connection portion 44. The dry etching can be performed using a mixture of CF4 plasma and O2 plasma.

[0114] In another exemplary embodiment of the present disclosure, referring to Figure 17 As shown, the protective layer 72 may not be exposed, and the protective layer 72 may be directly dry-etched using a mixture of SF6 plasma and O2 plasma.

[0115] Since the protective layer 72 is thin and the etching amount is small, there will be no excessive etching, so the connection portion 44 of the first conductive layer 4 will not be etched poorly, and the connection between the connection portion 44 and the second conductive layer 9 will not be affected, so poor contact is not likely to occur.

[0116] In step S60 , a second conductive layer 9 is formed on a side of the interlayer dielectric layer 81 away from the base substrate 1 , and the second conductive layer 9 is connected to the connecting portion 44 through the first via hole 73 and the second via hole 82 .

[0117] Reference Figure 4 and Figure 5As shown, a second conductive material layer is formed on the side of the interlayer dielectric layer 81 away from the base substrate 1 by sputtering, evaporation, deposition and other processes, and the second conductive material layer is etched to form a second conductive layer 9. The second conductive layer 9 may include a source 91, a drain 92 and a second data line 93, etc. The second data line 93 is connected to the source 91; the source 91 and the drain 92 are connected to the two connecting parts 44 through the first via 73 and the first via 73 respectively, and the second data line 93 is connected to the first data line 43 through the first via 73 and the first via 73 to form a data line.

[0118] It is understood that the functions of "source" and "drain" may be interchanged when using thin-film transistors with opposite polarities or when the direction of current changes during circuit operation. Therefore, in this specification, "source" and "drain" may be interchanged.

[0119] It should be noted that the above-described method for preparing an array substrate is a method for preparing a top-gate array substrate; in other exemplary embodiments of the present disclosure, the array substrate may also be a bottom-gate array substrate or a dual-gate array substrate, and its preparation method is not described in detail here. The above-described first conductive layer 4 may include an active layer 4a; in other exemplary embodiments of the present disclosure, the first conductive layer 4 may also include a gate electrode 6, a source electrode 91 or a drain electrode 92, etc., and a protective layer 72 may be formed on the gate electrode 6, the source electrode 91 or the drain electrode 92, etc. to protect the gate electrode 6, the source electrode 91 or the drain electrode 92, etc. The thickness of each of the above-mentioned film layers is for illustrative purposes only and can be adjusted as needed.

[0120] It should be noted that although the steps of the array substrate manufacturing method of the present disclosure are described in a specific order in the accompanying drawings, this does not require or imply that the steps must be performed in this specific order, or that all steps must be performed to achieve the desired results. Additionally or alternatively, certain steps may be omitted, multiple steps may be combined into one step, and / or a single step may be broken down into multiple steps.

[0121] Based on the same inventive concept, an exemplary embodiment of the present disclosure provides a display device, which may include any of the above array substrates. The specific structure of the array substrate has been described in detail above, so it will not be repeated here.

[0122] The specific type of the display device is not particularly limited, and any type of display device commonly used in the field can be used, such as a liquid crystal display panel, an OLED display panel; specifically, it can also be a mobile device such as a mobile phone, a wearable device such as a watch, a VR device, etc. Those skilled in the art can make corresponding choices based on the specific purpose of the display device, which will not be elaborated here.

[0123] It should be noted that, in addition to the array substrate, the display device also includes other necessary components and components. Taking the liquid crystal display panel as an example, it can also include a liquid crystal layer, a color film substrate, a backlight module, etc.; taking the OLED display panel as an example, it can also include an anode, a light-emitting layer, a cathode, and a cover plate, etc.; taking the display as an example, specific components such as the outer casing, circuit board, power cord, etc., technical personnel in this field can make corresponding supplements based on the specific usage requirements of the display device, which will not be repeated here.

[0124] Compared with the prior art, the beneficial effects of the display device provided by the exemplary embodiment of the present invention are the same as the beneficial effects of the array substrate provided by the above exemplary embodiment, and are not described in detail here.

[0125] Those skilled in the art will readily appreciate other embodiments of the present disclosure after considering the specification and practicing the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of the present disclosure that follow the general principles of the present disclosure and include common knowledge or customary techniques in the art not disclosed herein. The description and examples are to be considered as exemplary only, with the true scope and spirit of the present disclosure being indicated by the appended claims.

Claims

1. A method for preparing an array substrate, characterized in that: include: providing a substrate; forming a first conductive layer on one side of the base substrate, wherein the first conductive layer includes a connecting portion; forming a protective material layer on a side of the first conductive layer away from the base substrate, and processing the protective material layer to form a protective layer, wherein the material of the protective material layer is photosensitive organic silicon, and the photosensitive organic silicon forms silicon oxide after exposure; forming an interlayer dielectric material layer on a side of the protective layer away from the base substrate, and dry-etching the interlayer dielectric material layer using a mixture of CF4 plasma and O2 plasma to form a second via hole and an interlayer dielectric layer, wherein an orthographic projection of the second via hole on the base substrate overlaps with an orthographic projection of the protective layer on the base substrate; performing patterning on the protective layer to form a first via hole, wherein the first via hole is connected to the connecting portion, and the second via hole is connected to the first via hole; forming a second conductive layer on a side of the interlayer dielectric layer away from the base substrate, wherein the second conductive layer is connected to the connecting portion through the first via hole and the second via hole; The step of processing the protective material layer to form a protective layer includes: performing a half-exposure process on the protective material layer opposite to the connecting portion and a full-exposure process on the remaining protective material layer, so that the exposed protective material layer forms an isolation layer and the unexposed protective material layer forms the protective layer; While patterning the interlayer dielectric material layer to form the second via hole, the preparation method further includes: performing patterning on the isolation layer to form a third via hole, wherein the third via hole is connected to the second via hole and the first via hole; Before patterning the protective layer to form the first via hole, the preparation method further includes: The protective layer is exposed to light.

2. The method for preparing an array substrate according to claim 1, wherein: The patterning of the protective layer to form the first via hole comprises: The protective layer is dry-etched by a mixture of CF4 plasma and O2 plasma to form a first via hole.

3. The method for preparing an array substrate according to claim 1, wherein: The photosensitive silicone comprises silicone resin and a photosensitizer.

4. An array substrate prepared by the preparation method according to any one of claims 1 to 3, characterized in that: The array substrate includes: substrate; A first conductive layer is provided on one side of the base substrate, wherein the first conductive layer includes a connecting portion; a protective layer, disposed on a side of the first conductive layer away from the base substrate, the protective layer being provided with a first via hole connected to the connecting portion, and the material of the protective layer being photosensitive silicone; an interlayer dielectric layer disposed on a side of the protective layer away from the base substrate, wherein a second via hole is disposed on the interlayer dielectric layer, the second via hole being connected to the first via hole, and an orthographic projection of the second via hole on the base substrate overlapping with an orthographic projection of the protective layer on the base substrate; a second conductive layer, provided on a side of the interlayer dielectric layer away from the base substrate, the second conductive layer being connected to the connecting portion through the first via hole and the second via hole; An isolation layer is provided between the protection layer and the interlayer dielectric layer. A third via hole is provided on the isolation layer. The third via hole is connected to the second via hole and the first via hole.

5. The array substrate according to claim 4, wherein: The first conductive layer includes: an active layer comprising a channel portion and a conductor portion, wherein the conductor portion is the connecting portion; A first data line, wherein a portion of the first data line is the connecting portion.

6. The array substrate according to claim 5, wherein: The array substrate further includes: a light shielding layer, provided between the base substrate and the active layer; a buffer layer, disposed between the light shielding layer and the active layer; a gate insulating layer, disposed on a side of the active layer away from the base substrate; The gate is arranged on a side of the gate insulating layer away from the base substrate.

7. A display device, characterized in that: include: The array substrate according to any one of claims 4 to 6.

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