A precision large-banded digital phase-locked amplifier with hybrid sampling structure

Abstract

The application provides a precision large-bandwidth digital phase-locked amplifier with a hybrid sampling structure, comprising a signal-to-be-tested link, a reference signal link, a digital logic and a computing system; the signal-to-be-tested link inputs a signal to be tested, and outputs a first analog-to-digital conversion signal and a second analog-to-digital conversion signal to the digital logic and the computing system; the reference signal link inputs a reference signal, and outputs a third analog-to-digital conversion signal and a hysteresis comparison signal to the digital logic and the computing system; the digital logic and the computing system output a plurality of control signals to the signal-to-be-tested link and the reference signal link; the digital phase-locked amplifier with the hybrid sampling structure has a low-frequency sampling mode, a frequency down-conversion sampling mode and a high-frequency sampling mode, and the signal-to-be-tested link can improve the signal-to-noise ratio in the measurement of low-frequency signals and high-frequency signals.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of weak signal detection instrument, more particularly, to a precision large bandwidth digital phase locked amplifier with hybrid sampling structure. BACKGROUND

[0002] There are several weak signals in nature and human social life, how to detect these weak signals has gradually become an important issue in the fields of biomedical, basic disciplines, electronic information, material engineering and the like.

[0003] The phase locked amplifier is a kind of weak signal detection instrument, which can extract the signal of specific frequency from strong noise background. According to the system architecture, the phase locked amplifier can be divided into analog phase locked amplifier and digital phase locked amplifier. The phase sensitive detector, which is the core of the analog phase locked amplifier, is realized by analog multiplier. However, due to the nonlinearity of analog devices and the external interference, it is difficult to further improve the dynamic reserve range. Therefore, the digital phase locked amplifier replaces the analog operation with digital operation, which overcomes the above-mentioned shortcomings.

[0004] As shown in Fig. 1, the conventional digital phase locked amplifier generally comprises a reference signal link, a to-be-detected signal link and a digital logic and calculation system. The to-be-detected signal link generally comprises amplification, filtering and single analog-to-digital conversion, and the reference signal link generally comprises filtering and single analog-to-digital conversion. The digital signals output by the to-be-detected signal link and the reference signal link are multiplied in the phase sensitive detection module in the digital logic and calculation system, and then low-pass filtered and mathematically operated to calculate the amplitude of the to-be-detected signal and the phase difference with the reference signal. Figure 1 The conventional digital phase locked amplifier has the following deficiencies. For a to-be-detected signal with higher frequency, the sampling rate of the analog-to-digital converter in the to-be-detected signal link needs to be higher. The analog-to-digital converter with several MSPS sampling rate can achieve 24 bits, but the ultra-high-speed analog-to-digital converter with a sampling rate higher than 250 MSPS generally has less than 14 bits, which means that a choice between high speed and high precision must be made. However, the measurement precision of the instrument is the prerequisite for detecting weak signals. For a low-frequency signal, the noise performance is far from that of the low-frequency digital phase locked amplifier due to the use of the ultra-high-speed analog-to-digital converter with lower bits. For a high-frequency signal, the conventional digital phase locked amplifier inevitably introduces lower signal-to-noise ratio. It is not only difficult in technology but also extremely high in cost to seek an ultra-high-speed analog-to-digital converter with higher bits.

[0005] SUMMARY The present application provides a precision large bandwidth digital phase locked amplifier with hybrid sampling structure, which can improve the signal-to-noise ratio of the to-be-detected signal link in the measurement of low-frequency signals and high-frequency signals.

[0006] The present application provides a precision large bandwidth digital phase locked amplifier with hybrid sampling structure, which can improve the signal-to-noise ratio of the to-be-detected signal link in the measurement of low-frequency signals and high-frequency signals.

[0007] In order to achieve the above technical effects, the technical scheme of the present application is as follows:

[0008] The precision large-bandwidth digital phase-locked amplifier with a hybrid sampling structure comprises a to-be-measured signal link, a reference signal link, a digital logic and a computing system; the to-be-measured signal link inputs a to-be-measured input signal and outputs a first analog-to-digital conversion signal and a second analog-to-digital conversion signal to the digital logic and the computing system; the reference signal link inputs a reference input signal and outputs a third analog-to-digital conversion signal and a hysteresis comparison signal to the digital logic and the computing system; and the digital logic and the computing system output a plurality of control signals to the to-be-measured signal link and the reference signal link.

[0009] Further, the to-be-measured signal link comprises a low-noise pre-stage amplification circuit, a first low-pass filter, a first analog-to-digital converter, a mixer, a digitally-controlled oscillator, a gating circuit, a second low-pass filter and a second analog-to-digital converter.

[0010] The to-be-measured input signal is amplified by the low-noise pre-stage amplification circuit and then filtered by the first low-pass filter to obtain a first low-pass filtered signal.

[0011] The digitally-controlled oscillator is controlled to generate a sinusoidal signal with an adjustable frequency and input the sinusoidal signal into the mixer, so that the down-converted component output by the mixer is fixed in a low-frequency range; if the frequency of the reference input signal is , the frequency of the digitally-controlled oscillator is set as , the frequency components output by the mixer are and , the second low-pass filter filters out the component and only leaves the component to be transmitted to the second analog-to-digital converter.

[0012] The first low-pass filtered signal is divided into three paths and connected to the gating circuit, the mixer and the first analog-to-digital converter respectively, which determines three sampling modes of the to-be-measured signal link, i.e., a low-frequency sampling mode, a down-conversion sampling mode and a high-frequency sampling mode.

[0013] The down-converted mixer signal obtained after the first low-pass filtered signal passes through the mixer is connected to the gating circuit, and the first analog-to-digital conversion signal obtained after the first low-pass filtered signal passes through the first analog-to-digital converter.

[0014] The gating circuit selects the first low-pass filter signal or the mixer signal to obtain a gating circuit signal connected to the second low-pass filter.

[0015] The gating circuit signal passes through the second low-pass filter and the second analog-to-digital converter in sequence to obtain the second analog-to-digital conversion signal.

[0016] Further, the reference signal link comprises a low noise amplifier, a third low pass filter, a third analog-to-digital converter, and a hysteresis comparator; the reference input signal is amplified by the low noise amplifier, and then filtered by the third low pass filter to obtain a third low pass filtered signal; the third low pass filtered signal is divided into two paths, and then respectively passes through the third analog-to-digital converter and the hysteresis comparator to obtain a third analog-to-digital converted signal and a hysteresis comparison signal.

[0017] Further, the digital logic and computing system comprises a data gate, a digital phase-locked loop, a frequency measurement module, a digital sine wave generator, a phase-sensitive detection module, and a microprocessor, which are implemented on an Soc chip comprising an FPGA and a microprocessor.

[0018] The data gate selects the first analog-to-digital converter or the second analog-to-digital converter to be connected to the phase-sensitive detection module.

[0019] The third analog-to-digital converted signal is connected to the digital sine wave generator to control the phase after passing through the digital phase-locked loop.

[0020] The hysteresis comparison signal is connected to the microprocessor and transmits frequency information after passing through the frequency measurement module, and is connected to the digital sine wave generator to control the frequency.

[0021] The phase-sensitive detection module multiplies and filters the signals from the data gate and the digital sine wave generator, and is connected to the microprocessor.

[0022] The microprocessor calculates the amplitude of the input signal to be measured and the phase difference between the input signal to be measured and the reference input signal according to the signals output by the phase-sensitive detection module.

[0023] Further, in the low-frequency sampling mode, the gating circuit selects the first low pass filtered signal, and then sequentially passes through the second low pass filter and the second analog-to-digital converter to obtain a second analog-to-digital converted signal, which is connected to the digital logic and computing system and then connected to the phase-sensitive detection module through the data gate.

[0024] In the down-conversion sampling mode, the gating circuit selects the mixer signal, and then sequentially passes through the second low pass filter and the second analog-to-digital converter to obtain a second analog-to-digital converted signal, which is connected to the digital logic and computing system and then connected to the phase-sensitive detection module through the data gate.

[0025] In the high-frequency sampling mode, the first low pass filtered signal passes through the first analog-to-digital converter to obtain a first analog-to-digital converted signal, which is connected to the digital logic and computing system and then connected to the phase-sensitive detection module through the data gate.

[0026] Further, the microprocessor controls the low noise preamplifier circuit, the digital controlled oscillator, and the gating circuit through the level conversion circuit interface, and controls the data gate and the phase-sensitive detection module through the digital bus interface.

[0027] Preferably, the gating circuit is a high-speed analog switch; the digital logic and computing system is a combination of Soc chips containing FPGAs and microprocessors, CPLD and DSP chips, or ASIC chips.

[0028] Compared with the prior art, the beneficial effects of the technical scheme of the present application are:

[0029] The present application adds a mixer, a digitally controlled oscillator and another set of low-pass filters and a low-speed high-precision analog-to-digital converter to the to-be-measured signal link, and selects the signal to the low-speed high-precision analog-to-digital converter through a gating circuit. According to the selection between the gating circuit and the two analog-to-digital converters, the to-be-measured signal link can have three sampling modes, namely a low-frequency sampling mode, a down-conversion sampling mode and a high-frequency sampling mode. The low-frequency sampling mode can achieve the optimal signal-to-noise ratio in the measurement of low-frequency signals, and the low-frequency signals are finally given to the low-speed high-precision analog-to-digital converter through the gating circuit. The down-conversion sampling mode can improve the signal-to-noise ratio in the measurement of high-frequency signals, because the bit number of the ultrahigh-frequency analog-to-digital converter is low, but the high-frequency signal cannot be directly given to the low-speed high-precision analog-to-digital converter, so it needs to be down-converted through the mixer to obtain a low-frequency signal, and then given to the low-speed high-precision analog-to-digital converter. The high-frequency sampling mode retains the most basic data path of the traditional structure of the digital phase-locked amplifier, and this branch cannot be replaced by other branches when performing harmonic measurement of the phase-locked amplifier. The hybrid sampling structure of the digital phase-locked amplifier of the present application has a low-frequency sampling mode, a down-conversion sampling mode and a high-frequency sampling mode, which can improve the signal-to-noise ratio of the to-be-measured signal link in the measurement of low-frequency signals and high-frequency signals. BRIEF DESCRIPTION OF DRAWINGS

[0030] Figure 1 is a traditional digital phase-locked amplifier structure diagram in the prior art;

[0031] Figure 2 is a system block diagram of the digital phase-locked amplifier described in Embodiment 1;

[0032] Figure 3 is a system block diagram of the low-frequency sampling mode of the digital phase-locked amplifier described in Embodiment 1;

[0033] Figure 4 is a system block diagram of the down-conversion sampling mode of the digital phase-locked amplifier described in Embodiment 1;

[0034] Figure 5 is a system block diagram of the high-frequency sampling mode of the digital phase-locked amplifier described in Embodiment 1;

[0035] Figure 6 is a control block diagram of the microprocessor described in Embodiment 1;

[0036] Figure 7 is a signal-to-noise ratio curve comparison diagram of the present application and a conventional structure digital phase-locked amplifier described in embodiment 1;

[0037] In the figure, 1 is a signal link to be measured; 2 is a reference signal link; 3 is a digital logic and computing system 3; 11 is a low-noise pre-stage amplification circuit; 12 is a first low-pass filter; 13 is a first analog-to-digital converter; 14 is a frequency mixer; 15 is a numerically controlled oscillator; 16 is a gating circuit; 17 is a second low-pass filter; 18 is a second analog-to-digital converter; 21 is a low-noise amplifier; 22 is a third low-pass filter; 23 is a third analog-to-digital converter; 24 is a hysteresis comparator; 31 is a data gate; 32 is a digital phase-locked loop; 33 is a frequency measurement module; 34 is a digital sine wave generator; 35 is a phase-sensitive detection module; 36 is a microprocessor; 41 is a level conversion circuit interface; and 42 is a digital bus interface. DETAILED DESCRIPTION

[0038] The accompanying drawings are only used for illustrative purposes and should not be construed as limiting the patent;

[0039] In order to better illustrate the present embodiment, some components in the accompanying drawings may be omitted, enlarged or reduced, and do not represent the actual product size;

[0040] It is understandable for those skilled in the art that some well-known structures and their descriptions in the accompanying drawings may be omitted.

[0041] The technical solutions of the present application will be further described below in combination with the accompanying drawings and embodiments.

[0042] As shown in Figure 2 The present application provides a precision large-bandwidth digital phase-locked amplifier with a mixed sampling structure, which comprises a signal link to be measured 1, a reference signal link 2, and a digital logic and computing system 3. The signal link to be measured 1 inputs a measured input signal, and outputs a first analog-to-digital conversion signal and a second analog-to-digital conversion signal to the digital logic and computing system 3. The reference signal link 2 inputs a reference input signal, and outputs a third analog-to-digital conversion signal and a hysteresis comparison signal to the digital logic and computing system 3. The digital logic and computing system 3 outputs a plurality of control signals to the signal link to be measured 1 and the reference signal link 2.

[0043] The signal link to be measured 1 comprises a low-noise pre-stage amplification circuit 11, a first low-pass filter 12, a first analog-to-digital converter 13, a frequency mixer 14, a numerically controlled oscillator 15, a gating circuit 16, a second low-pass filter 17, and a second analog-to-digital converter 18.

[0044] The measured input signal is amplified by the low-noise pre-stage amplification circuit 11, and then filtered by the first low-pass filter 12 to obtain a first low-pass filtered signal.

[0045] The digitally controlled oscillator generates a sinusoidal signal with adjustable frequency to input the mixer, so that the down-converted component of the mixer output is fixed in a low frequency range. If the frequency of the reference input signal is , the frequency of the digitally controlled oscillator is set as , the frequency components of the mixer output are and , the second low-pass filter filters out the component and only the component is transmitted to the second analog-to-digital converter;

[0046] The first low-pass filtered signal is divided into three paths and connected to the gating circuit 16, the mixer 14 and the first analog-to-digital converter 13, which determines three sampling modes of the signal link to be measured, i.e. low frequency sampling mode, down-conversion sampling mode and high frequency sampling mode;

[0047] The first low-pass filtered signal is connected to the gating circuit 16 after being down-converted by the mixer 14, and the first low-pass filtered signal is connected to the first analog-to-digital converter 13 to obtain the first analog-to-digital conversion signal;

[0048] The gating circuit 16 selects the first low-pass filtered signal or the mixer signal to obtain the gating circuit signal connected to the second low-pass filter 17;

[0049] The gating circuit signal is connected to the second low-pass filter 17 and the second analog-to-digital converter 18 in turn to obtain the second analog-to-digital conversion signal.

[0050] The reference signal link 2 comprises a low noise amplifier 21, a third low-pass filter 22, a third analog-to-digital converter 23 and a hysteresis comparator 24.

[0051] The reference input signal is amplified by the low noise amplifier 21 and filtered by the third low-pass filter 22 to obtain the third low-pass filtered signal;

[0052] The third low-pass filtered signal is divided into two paths and connected to the third analog-to-digital converter 23 and the hysteresis comparator 24 to obtain the third analog-to-digital conversion signal and the hysteresis comparison signal.

[0053] The digital logic and computing system 3 comprises a data gate 31, a digital phase-locked loop 32, a frequency measurement module 33, a digital sinusoidal generator 34, a phase-sensitive detection module 35 and a microprocessor 36, which are realized on an Soc chip containing FPGA and microprocessor.

[0054] The data gate 31 selects the first analog-to-digital converter 13 or the second analog-to-digital converter 18 to be connected to the phase-sensitive detection module 35;

[0055] The third analog-to-digital conversion signal is connected to the digital sinusoidal generator 34 to control the phase after passing through the digital phase-locked loop 32.

[0056] After passing through the frequency measurement module 33, the hysteresis comparison signal is connected to the digital sine generator 34 to control the frequency, and to the microprocessor 36 to transmit the signal frequency information.

[0057] The phase-sensitive detection module 35 multiplies and filters the signals from the data selector 31 and the digital sine generator 34, and then connects them to the microprocessor 36.

[0058] The microprocessor 36 calculates the amplitude of the input signal to be tested and the phase difference between it and the reference input signal based on the signal output by the phase-sensitive detection module 35.

[0059] like Figure 3 As shown, in the low-frequency sampling mode, after the gating circuit 16 selects and connects to the first low-pass filter signal, it passes through the second low-pass filter 17 and the second analog-to-digital converter 18 in sequence to obtain the second analog-to-digital conversion signal, which is then connected to the digital logic and computing system 3 and connected to the phase-sensitive detection module 35 through the data gating device 31.

[0060] like Figure 4 As shown, in the downconversion sampling mode, after the selection circuit 16 selects the signal to be connected to the mixer, it passes through the second low-pass filter 17 and the second analog-to-digital converter 18 in sequence to obtain the second analog-to-digital conversion signal, which is then connected to the digital logic and computing system 3 and connected to the phase-sensitive detection module 35 through the data selector 31.

[0061] like Figure 5 As shown, in the high-frequency sampling mode, the first low-pass filtered signal passes through the first analog-to-digital converter 13 to obtain the first analog-to-digital converted signal, which is then connected to the digital logic and computing system 3 and connected to the phase-sensitive detection module 35 through the data selector 31.

[0062] like Figure 6 As shown, the microprocessor 36 controls the low-noise preamplifier circuit 11, the numerically controlled oscillator 15, and the gating circuit 16 through the level conversion circuit interface 41, and controls the data gating device 31 and the phase-sensitive detection module 35 through the digital bus interface 42.

[0063] like Figure 7 As shown, comparing the signal-to-noise ratio curves of the precision high-bandwidth digital lock-in amplifier with the hybrid sampling structure of this invention and the traditional structure of the digital lock-in amplifier, it can be seen that in the traditional structure, only a single ultra-high frequency analog-to-digital converter is used.

[0064] The signal-to-noise ratio is low under low-frequency signals, and gradually decreases with the increase of the frequency of the to-be-measured signal.In the mixed structure of the application, for low-frequency signals, the digital phase-locked amplifier works in a low-frequency sampling mode, and a low-speed high-precision second analog-to-digital converter 18 is used for sampling, so that the signal-to-noise ratio is higher; for high-frequency signals, the digital phase-locked amplifier works in a down-conversion frequency sampling mode or a high-frequency sampling mode, and the signal-to-noise ratio in the high-frequency sampling mode is the same as that of the traditional structure, which is to meet the demand of harmonic measurement, and the signal-to-noise ratio in the down-conversion frequency sampling mode is improved compared with the traditional structure.

[0065] Compared with the traditional structure of the digital phase-locked amplifier, the innovative technical key point of the application lies in the structural design of the to-be-measured signal link. In the previous structure, the to-be-measured input signal is connected to an analog-to-digital converter after passing through an amplification circuit and a filter circuit in turn, but for high-frequency signals, the bit number of the super-high-speed analog-to-digital converter is low, resulting in low signal-to-noise ratio of the to-be-measured signal link.

[0066] The application adds a mixer, a digital controlled oscillator, and another set of low-pass filters and a low-speed high-precision analog-to-digital converter to the to-be-measured signal link, and selects the signal to the low-speed high-precision analog-to-digital converter through a gating circuit. According to the selection between the gating circuit and the two analog-to-digital converters, the to-be-measured signal link can have three sampling modes, namely a low-frequency sampling mode, a down-conversion frequency sampling mode, and a high-frequency sampling mode.

[0067] The low-frequency sampling mode can achieve the optimal signal-to-noise ratio in the measurement of low-frequency signals, and the low-frequency signals are finally given to the low-speed high-precision analog-to-digital converter through the gating circuit.

[0068] The down-conversion frequency sampling mode can improve the signal-to-noise ratio in the measurement of high-frequency signals. Because the bit number of the super-high-speed analog-to-digital converter is low, the high-frequency signal cannot be directly given to the low-speed high-precision analog-to-digital converter, so it needs to be down-converted through the mixer to obtain a low-frequency signal, and then given to the low-speed high-precision analog-to-digital converter.

[0069] The high-frequency sampling mode retains the most basic data path of the traditional structure of the digital phase-locked amplifier, and this branch cannot be replaced by other branches when performing harmonic measurement of the phase-locked amplifier.

[0070] In summary, the traditional structure of the digital phase-locked amplifier only has a high-frequency sampling mode, while the mixed sampling structure of the digital phase-locked amplifier of the application has a low-frequency sampling mode, a down-conversion frequency sampling mode, and a high-frequency sampling mode, which can improve the signal-to-noise ratio of the to-be-measured signal link in the measurement of low-frequency signals and high-frequency signals.

[0071] The same or similar reference signs correspond to the same or similar parts;

[0072] The position relationship described in the drawings is for illustration only and should not be construed as limiting the patent;

[0073] Obviously, the above-mentioned embodiments of the present application are only examples for clearly explaining the present application, and are not intended to limit the embodiments of the present application. Based on the above description, other different forms of changes or variations can be made by those skilled in the art. Here, it is not necessary and impossible to exhaust all the embodiments. Any modification, equivalent replacement and improvement, etc. made within the spirit and principle of the present application should be included in the protection scope of the claims of the present application.

Claims

1. A precision large-banded digital phase-locked amplifier of hybrid sampling architecture, characterized in that, It includes signal link (1) to be measured, reference signal link (2), digital logic and computing system (3);The signal link (1) to be measured inputs the input signal to be measured, and output first analog-digital conversion signal and second analog-digital conversion signal to digital logic and computing system (3);The reference signal link (2) inputs reference input signal, and output third analog-digital conversion signal and hysteresis comparison signal to digital logic and computing system (3);The digital logic and computing system (3) output several control signals to the signal link (1) to be measured and reference signal link (2); The signal link (1) to be measured includes low-noise pre-stage amplification circuit (11), first low-pass filter (12), first analog-digital converter (13), frequency mixer (14), digital controlled oscillator (15), gating circuit (16), second low-pass filter (17) and second analog-digital converter (18); The input signal to be measured is amplified through low-noise pre-stage amplification circuit (11), and then filtered through first low-pass filter (12), to obtain first low-pass filter signal; The numerically controlled oscillator (15) is controlled to generate a sinusoidal signal of adjustable frequency into the mixer (14) so that the down-converted component of the mixer (14) output is fixed in a low frequency range, if the frequency of the reference input signal is , the frequency of the numerically controlled oscillator is set to , the frequency component of the mixer output is and , the second low pass filter (17) filters out the component and only leaves the component to the second analog-digital converter (18); The first low-pass filter signal is divided into three paths, which are connected to gating circuit (16), frequency mixer (14) and first analog-digital converter (13) respectively, which determines three sampling modes of the signal link to be measured, which are low-frequency sampling mode, down-conversion sampling mode and high-frequency sampling mode; The first low-pass filter signal is connected to gating circuit (16) after being down-converted through frequency mixer (14), and the first low-pass filter signal is connected to second analog-digital converter (18) after being converted through first analog-digital converter (13), to obtain first analog-digital conversion signal; The gating circuit (16) selects first low-pass filter signal or frequency mixer signal, to obtain gating circuit signal connected to second low-pass filter (17); The gating circuit signal is sequentially connected to second low-pass filter (17) and second analog-digital converter (18), to obtain second analog-digital conversion signal; The reference signal link (2) includes low-noise amplifier (21), third low-pass filter (22), third analog-digital converter (23) and hysteresis comparator (24);The reference input signal is amplified through low-noise amplifier (21), and then filtered through third low-pass filter (22), to obtain third low-pass filter signal;The third low-pass filter signal is divided into two paths, which are connected to third analog-digital converter (23) and hysteresis comparator (24) respectively, to obtain third analog-digital conversion signal and hysteresis comparison signal; The digital logic and computing system (3) includes data gate (31), digital phase-locked loop (32), frequency measurement module (33), digital sine wave generator (34), phase-sensitive detection module (35) and microprocessor (36), which are realized on Soc chip containing FPGA and microprocessor; The data gate (31) selects first analog-digital converter (13) or second analog-digital converter (18) connected to phase-sensitive detection module (35); The third analog-digital conversion signal is connected to digital sine wave generator (34) to control phase after being connected to digital phase-locked loop (32). The hysteresis comparison signal is connected to the digital sine generator (34) to control the frequency after the frequency measurement module (33), and is connected to the microprocessor (36) to transmit the signal frequency information. The phase-sensitive detection module (35) is connected to the microprocessor (36) after multiplying and filtering the signals from the data gate (31) and the digital sine generator (34); The microprocessor (36) calculates the amplitude of the input signal to be measured and the phase difference between the reference input signal according to the signal output by the phase-sensitive detection module (35); In the low-frequency sampling mode, the gating circuit (16) is connected to the first low-pass filter signal, and then sequentially passes through the second low-pass filter (17) and the second analog-to-digital converter (18) to obtain the second analog-to-digital conversion signal, and is connected to the digital logic and calculation system (3) through the data gate (31) to the phase-sensitive detection module (35); In the sampling mode, the gating circuit (16) is connected to the mixer signal, and then sequentially passes through the second low-pass filter (17) and the second analog-to-digital converter (18) to obtain the second analog-to-digital conversion signal, and is connected to the digital logic and calculation system (3) through the data gate (31) to the phase-sensitive detection module (35); In the high-frequency sampling mode, the first low-pass filter signal passes through the first analog-to-digital converter (13) to obtain the first analog-to-digital conversion signal, and is connected to the digital logic and calculation system (3) through the data gate (31) to the phase-sensitive detection module (35).

2. The precision large-bang digital phase locked amplifier of mixed sampling architecture according to claim 1, characterized in that, The microprocessor (36) controls the low-noise preamplifier circuit (11), the digital controlled oscillator (15) and the gating circuit (16) through the level conversion circuit interface (41), and controls the data gate (31) and the phase-sensitive detection module (35) through the digital bus interface (42).

3. The precision large-bang digital phase locked amplifier of mixed sampling architecture according to claim 2, characterized in that, The gating circuit (16) is a high-speed analog switch.

4. The precision large-bang digital phase locked amplifier of claim 3, wherein, The digital logic and calculation system (3) is a combination of Soc chips containing FPGAs and microprocessors, CPLD and DSP chips, or ASIC chips.

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