An integrated chip and data processing method

Abstract

An integrated chip and a data processing method are used to enhance the security of a system and improve the service processing efficiency of the system. The integrated chip comprises: an application processor configured to write first data in an off-chip memory through a storage controller in a normal security mode, wherein the address of the first data in the off-chip memory is a first address; a security processor configured to send a first read instruction to the storage controller in an enhanced security mode, the first read instruction being used to request reading the first data at the first address; and the storage controller is configured to read the first data from the off-chip memory and send the first data to the security processor.

Description

Technical Field

[0001] This application relates to the field of chip technology, and in particular to an integrated chip and a data processing method. Background Technology

[0002] With the development of smart terminals and the popularization of internet applications, smart terminals are becoming increasingly functional. In many application scenarios, the security requirements for smart terminals are also rising, such as mobile payment scenarios and mobile phone screen unlocking scenarios.

[0003] To enhance system security, existing systems-on-chips (SoCs) typically employ a TrustZone architecture. In this architecture, the application processor (AP) operates in a time-sharing manner between non-secure and secure modes. The AP handles general applications in non-secure mode and processes programs requiring security measures in secure mode. However, numerous attack models and instances exist that allow the AP to bypass security restrictions when switching from non-secure to secure mode, making it difficult to guarantee the security of the TrustZone architecture.

[0004] One approach to enhance system security is to add a dedicated security processor to the TrustZone architecture. That is, the SoC integrates an application processing unit (AP) and a separate security processor, which can internally include the processor and other security components. The security processor operates within an independent security domain of the SoC, and it and the AP cannot directly access each other; instead, they exchange information via interrupts. Figure 1 As shown, when the AP transmits data to the security processor, it first transmits the data to the Inbox. When the Inbox receives the data, it triggers an interrupt in the security processor, which then reads the data from the Inbox. When the security processor transmits data to the AP, it first transmits the data to the Outbox. When the Outbox receives the data, it sends an interrupt message to the interrupt controller. Upon receiving the interrupt message, the interrupt controller triggers an interrupt in the AP, and the AP reads the data from the Outbox.

[0005] use Figure 1In the information exchange scheme shown, the mailbox includes an Inbox and an Outbox. The Inbox and Outbox are typically on-chip buffers of the SoC, fabricated on the same die as the SoC. Due to the limited storage space of the buffers, the efficiency of information exchange between the AP and the security processor is low, especially when processing large data streams. Using the above scheme will significantly increase processing time and impact processing efficiency. Summary of the Invention

[0006] This application provides an integrated chip and a data processing method to enhance system security and improve system business processing efficiency.

[0007] In a first aspect, embodiments of this application provide an integrated chip, comprising: an application processor configured to write first data to an off-chip memory via a storage controller in a normal security mode, wherein the address of the first data in the off-chip memory is a first address; a security processor configured to send a first read instruction to the storage controller in an enhanced security mode, the first read instruction being used to request the reading of the first data at the first address; and a storage controller configured to read the first data from the off-chip memory and send the first data to the security processor.

[0008] Using the integrated chip provided in the first aspect, the application processor writes first data to the off-chip memory via the storage controller in normal security mode, and the security processor can read the first data via the storage controller in enhanced security mode. This scheme enables the application processor to transfer first data to the security processor. In the integrated chip provided in the first aspect, the application processor and the security processor can interact via the off-chip memory under the control of the storage controller. Compared to existing schemes where the application processor and security processor interact via mailboxes (Inbox and Outbox), the off-chip memory offers greater storage space and transmission bandwidth. Therefore, the interaction scheme provided in the first aspect can improve the efficiency of information exchange, especially when processing large data streams. Data interaction via off-chip memory can significantly reduce processing time, thereby improving processing efficiency.

[0009] In one possible design, the security processor is also used to: process the first data read in enhanced security mode and write the processed data to off-chip memory via the memory controller; the application processor is also used to: read the processed data from off-chip memory via the memory controller in normal security mode.

[0010] Using the above scheme, after the security processor processes the first data, it can also transfer the processed data to the application processor through off-chip memory.

[0011] Furthermore, when the application processor reads the processed data from the off-chip memory through the memory controller, it can do so in the following manner: in normal security mode, it sends a second read instruction to the memory controller, the second read instruction being used to request the reading of the processed data; the memory controller is also used to: read the processed data from the off-chip memory and send the processed data to the application processor.

[0012] In other words, when the application processor reads the data obtained after the above processing, it can control the storage controller to read it.

[0013] In addition, the security processor is also used to: after the processed data is written to the off-chip memory through the memory controller, notify the application processor to read the processed data via an interrupt.

[0014] Using the above scheme, the security processor can notify the application processor to read the processed data via an interrupt.

[0015] In one possible design, the application processor is also used to: after writing the first data to the off-chip memory via the memory controller, notify the security processor to read the first data via an interrupt.

[0016] In one possible design, when the storage controller reads first data from off-chip memory and sends the first data to the security processor, it can be implemented in the following way: the storage controller determines that the first read instruction has been authenticated; the storage controller reads the first data and sends the first data to the security processor.

[0017] By adopting the above scheme, the storage controller will only respond to the first read request if the first read instruction is authenticated, thus ensuring the security of the first data.

[0018] Specifically, when the memory controller determines that the first read instruction has passed authentication, it performs the following actions: the memory controller determines that the first address belongs to a first storage area of ​​off-chip memory, the first storage area is configured to allow the processor in normal security mode to perform read and write operations, and to allow the processor in enhanced security mode to perform read operations; the memory controller determines that the security processor is in enhanced security mode and the first read instruction is a read instruction.

[0019] Using the above scheme, the off-chip memory is configured with storage areas of different security attributes to allow data interaction between the processor and the off-chip memory in different security modes. The first storage area can be regarded as the storage area used for interaction between the application processor and the security processor. In the first storage area, the application processor in normal security mode can read and write data, while the security processor in enhanced security mode can read data. Therefore, the application processor can transfer data to the security processor through the first storage area.

[0020] In addition, the security processor is also used to: configure the first storage area to allow the processor to perform read and write operations in normal security mode, and to allow the processor to perform read operations in enhanced security mode.

[0021] Specifically, the security processor can send first configuration information to the storage controller. This first configuration information instructs the first storage area to allow read and write operations by the processor in normal security mode, and to allow read operations by the processor in enhanced security mode. The storage controller then saves this first configuration information.

[0022] By adopting the above scheme, only the security processor can configure the storage area related to the processor's operating permissions in enhanced security mode, thereby enhancing the system's security.

[0023] In one possible design, when the security processor writes the processed data to off-chip memory through the memory controller, it specifically performs the following: in enhanced security mode, the security processor sends a first write instruction to the memory controller, the first write instruction being used to request the processing data to be written at a second address; the memory controller is also used to: determine that the first write instruction has passed authentication; and write the processed data to the second address.

[0024] Using the above scheme, the storage controller will only respond to the first write instruction if the first write instruction is authenticated, thus ensuring the security of the data in the second address.

[0025] Specifically, when the storage controller determines that the first write instruction has passed authentication, it is used to: determine that the second address belongs to the second storage area of ​​the off-chip memory, the second storage area is configured to allow the processor in enhanced security mode to perform read and write operations, and to allow the processor in normal security mode to perform read operations; and determine that the security processor is in enhanced security mode.

[0026] Using the above scheme, the off-chip memory is configured with storage areas of different security attributes to allow data interaction between processors operating in different security modes and the off-chip memory. The second storage area can be considered as a storage area for interaction between the application processor and the security processor. In the second storage area, the security processor in enhanced security mode can read and write data, while the application processor in normal security mode can read data; therefore, the security processor can transfer data to the application processor through the second storage area.

[0027] In one possible design, the security processor is also used to: configure the second storage area to allow the processor to perform read and write operations in enhanced security mode, and to allow the processor to perform read operations in normal security mode.

[0028] Specifically, the security processor can send second configuration information to the storage controller. This second configuration information instructs the second storage area to allow processors in enhanced security mode to perform read and write operations, and to allow processors in normal security mode to perform read operations. The storage controller then saves this second configuration information.

[0029] By adopting the above scheme, only the security processor can configure the storage area related to the processor's operating permissions in enhanced security mode, thereby enhancing the system's security.

[0030] In one possible design, the security processor is further configured to: write second data into off-chip memory via the memory controller in enhanced security mode before processing the first data read, wherein the address of the second data in the off-chip memory is a third address; when the security processor processes the first data read in enhanced security mode, it is specifically configured to: send a third read instruction to the memory controller in enhanced security mode, the third read instruction being used to request the reading of the second data at the third address; read the second data from the off-chip memory via the memory controller; compare the first data with the second data, and use the comparison result as the processed data.

[0031] Using the above scheme, when the security processor processes the first data, it can compare the first data with the second data previously stored in off-chip memory, and use the comparison result as the processed data. The second data can be stored in an enhanced security read / write area in off-chip memory. Data in this storage area can only be accessed by the processor in enhanced security mode, thus ensuring the security of the second data.

[0032] In one possible design, the storage controller is also configured to: determine that the security processor is in enhanced security mode if the enhanced security indication information in the first read instruction is a first specified value.

[0033] Using the above scheme, since only the security processor can set the enhanced security indication information to the first specified value, the storage controller can determine that the processor sending the first read instruction is in enhanced security mode when the enhanced security indication information in the first read instruction is the first specified value.

[0034] In addition, the aforementioned enhanced security indication information is transmitted via signal lines on the internal bus of the integrated chip.

[0035] In other words, enhanced security indication information can be transmitted through a separate signal line on the internal bus, thus isolating enhanced security data from ordinary security data at the hardware level, thereby ensuring system security.

[0036] In one possible design, the application processor is also used for: time-sharing operation in non-secure mode and normal secure mode.

[0037] Using the above scheme, the processor in the integrated chip has a three-level security architecture. This means that in addition to the original two-level security architecture of non-secure / secure, a higher-level security architecture (i.e., enhanced security) is added. The processor in the integrated chip can have three security attributes, with enhanced security having the highest level, followed by ordinary security, and non-secure security having the lowest. The secure processor with enhanced security has an independent hardware architecture and a storage area (enhanced security read / write area) that is not shared with processors of other security attributes. Therefore, the secure processor can form a secure space that is difficult for malicious code to access, thus protecting the user's critical data at the hardware level. Storing the user's critical data in the enhanced security read / write area ensures the security of the user's critical data.

[0038] Secondly, embodiments of this application provide an integrated chip, comprising: a bus including a first signal line and a second signal line, the first signal line being used to transmit enhanced security indication information, and the second signal line being used to transmit ordinary security indication information; a security processor being used to send a first read instruction to a storage controller via the bus in an enhanced security mode, wherein the enhanced security indication information contained in the first read instruction is transmitted via the first signal line; and an application processor being used to send a second read instruction to the storage controller via the bus in an ordinary security mode, wherein the ordinary security indication information contained in the second read instruction is transmitted via the second signal line.

[0039] Using the above scheme, in the integrated chip, the security processor, application processor, and memory controller are connected via a bus. Access commands (including a first read command and a second read command) issued by the security processor and application processor via the bus contain enhanced security indication information and ordinary security indication information. The enhanced security indication information is transmitted through a first signal line on the bus, and the ordinary security indication information is transmitted through a second signal line on the bus. The memory controller can determine the security attributes of the processor sending the access command based on the received enhanced and ordinary security indication information.

[0040] In one possible design, the integrated chip provided by the second aspect may further include a memory controller for determining that the security processor is in enhanced security mode if the enhanced security indication information included in the first read instruction is a first specified value.

[0041] The above scheme provides a specific implementation method for determining the security mode of processing based on the enhanced security indication information transmitted in the first signal line.

[0042] In one possible design, the storage controller is also configured to: determine that the application processor is in normal security mode if the normal security indication information in the second read instruction is a second specified value; and determine that the application processor is in non-security mode if the normal security indication information in the second read instruction is a third specified value.

[0043] The above scheme provides a specific implementation method for determining the security mode of processing based on the ordinary security indication information transmitted in the second signal line.

[0044] Thirdly, embodiments of this application provide a data processing method, which includes the following steps: a storage controller receives a first read instruction sent by a security processor, the first read instruction being used to request the reading of first data at a first address in an off-chip memory; the storage controller determines that the first read instruction has passed authentication; the storage controller reads the first data from the off-chip memory and sends the first data to the security processor.

[0045] In one possible design, the memory controller determines that the first read instruction has passed authentication by: the memory controller determining, by querying a local register, that the first address belongs to a first storage region of off-chip memory, the first storage region being configured to allow the processor in normal security mode to perform read and write operations, and to allow the processor in enhanced security mode to perform read operations; the memory controller determining that the security processor is in enhanced security mode and that the first read instruction is a read instruction.

[0046] In one possible design, the storage controller determines that the security processor is in an enhanced security mode, including: the storage controller determines that the security processor is in an enhanced security mode when the enhanced security indication information in the first read instruction is a first specified value.

[0047] In one possible design, the method further includes: the storage controller receiving first configuration information sent by the security processor, the first configuration information being used to instruct the first storage area to allow the processor in normal security mode to perform read and write operations, and to allow the processor in enhanced security mode to perform read operations; the storage controller storing the first configuration information in a local register.

[0048] In one possible design, the method further includes: after the storage controller sends the first data to the security processor, it receives a first write instruction sent by the security processor, the first write instruction being used to request the writing of processed data at a second address, the processed data being obtained by the security processor after processing the first data; the storage controller determines that the first write instruction has passed authentication; and the storage controller writes the processed data to the second address.

[0049] In one possible design, the memory controller determines that the first write instruction has passed authentication by: the memory controller determining, by querying a local register, that the second address belongs to a second storage region of off-chip memory, the second storage region being configured to allow the processor in enhanced security mode to perform read and write operations, and to allow the processor in normal security mode to perform read operations; the memory controller then determines that the security processor is in enhanced security mode.

[0050] In one possible design, the method further includes: the storage controller receiving second configuration information sent by the security processor, the second configuration information being used to instruct the second storage area to allow the processor in enhanced security mode to perform read and write operations, and to allow the processor in normal security mode to perform read operations; the storage controller storing the second configuration information in a local register.

[0051] In one possible design, the method further includes: after the storage controller writes the processed data to the second address, receiving a second read instruction sent by the application processor, the second read instruction being used to request reading the processed data; the storage controller determining that the second read instruction has passed authentication; the storage controller reading the processed data and sending the processed data to the application processor.

[0052] In one possible design, the method further includes: the storage controller determining that the second read instruction has passed authentication, which can be achieved by the storage controller determining that the second address belongs to the second storage region; the storage controller determining that the application processor is in normal security mode and the second read instruction is a read instruction.

[0053] The storage controller determines that the application processor is in normal security mode in the following way: when the normal security indication information in the second read instruction is a second specified value, the storage controller determines that the application processor is in normal security mode.

[0054] Furthermore, the technical effects of any of the possible design methods in the second to third aspects can be found in the technical effects of different design methods in the first aspect, and will not be repeated here. Attached Figure Description

[0055] Figure 1 A schematic diagram illustrating the interaction process between an application processor and a security processor, provided for existing technologies;

[0056] Figure 2 This is a schematic diagram of the structure of the first type of integrated chip provided in the embodiments of this application;

[0057] Figure 3 This is a schematic diagram of the structure of the second type of integrated chip provided in the embodiments of this application;

[0058] Figure 4 This is a schematic diagram of the storage area division of an off-chip memory provided in an embodiment of this application;

[0059] Figure 5 A schematic diagram of a bus signal line configuration provided in an embodiment of this application;

[0060] Figure 6 This is a schematic diagram of the structure of a security processor provided in an embodiment of this application;

[0061] Figure 7 This is a schematic diagram of the structure of the third type of integrated chip provided in the embodiments of this application;

[0062] Figure 8 A schematic diagram illustrating the interaction flow of various devices in an integrated chip, provided as an embodiment of this application;

[0063] Figure 9 A schematic diagram of an authentication process for a storage controller provided in an embodiment of this application;

[0064] Figure 10 A flowchart illustrating the operations performed by a SoC as provided in an embodiment of this application;

[0065] Figure 11 This is a schematic diagram of the structure of the fourth integrated chip provided in the embodiments of this application;

[0066] Figure 12 This is a flowchart illustrating a data processing method provided in an embodiment of this application. Detailed Implementation

[0067] This application provides an integrated chip and a data processing method to enhance system security and improve system business processing efficiency.

[0068] The application scenarios of the embodiments of this application will be introduced below.

[0069] The embodiments of this application can be applied to integrated chips, specifically, such as... Figure 2 As shown, the integrated chip includes an application processor, a security processor, and a memory controller connected via a bus. The application processor is responsible for running the operating system and processing related applications; the security processor processes security data within the integrated chip; and the memory controller is connected to off-chip memory and controls data interaction between the processor (e.g., the security processor or application processor) within the integrated chip and the off-chip memory. The memory controller enables data interaction between the application processor and the off-chip memory, as well as between the security processor and the off-chip memory. Data interaction between the application processor and the security processor within the integrated chip is also possible.

[0070] Off-chip memory can be understood as memory located outside the die containing the application processor and security processor. That is, off-chip memory is... Figure 2 The integrated chips shown belong to different dies. During chip packaging, the die containing the off-chip memory and the die containing the integrated chips can be packaged in different chips or in the same chip. Figure 2 This example only illustrates the two components packaged in different chips. Figure 2 In the integrated chip shown, the memory controller is responsible for data access and control of the off-chip memory. For example, if the off-chip memory is dynamic random access memory (DRAM), the memory controller can be a DRAM controller (DMC), which is responsible for data access and control of the DRAM; if the off-chip memory is flash memory, the memory controller can be a flash controller (FC), which is responsible for data access and control of the flash memory.

[0071] DRAM can be used to store dynamic data during the operation of the integrated chip; since Flash can retain data even after the system is powered off, it can be used to store image programs and data that are intended to be retained even after the program is powered off. Of course, off-chip memory can also be other types of memory, such as synchronous dynamic random access memory (SDRAM), but this application does not specifically limit this.

[0072] Furthermore, this application does not specifically limit the number of memory controllers in the integrated chip or the number of off-chip memories connected to the integrated chip. For example, if the integrated chip includes the aforementioned DMC and FC, Figure 2 The structure of the integrated chip shown can be as follows: Figure 3 As shown. In Figure 3 In the integrated chip shown, the DMC is connected to the DRAM, and the FC is connected to the Flash. The application processor and the security processor in the integrated chip can interact with each other through the DRAM under the control of the DMC, or the application processor and the security processor in the integrated chip can interact with each other through the Flash under the control of the FC.

[0073] Similar to the application processor in the TrustZone architecture, the application processor in this embodiment can operate in a time-sharing manner between a non-secure mode and a secure mode. Furthermore, the integrated chip provided in this embodiment also includes a security processor, which operates in a higher-level security mode. To distinguish between the two security modes, the security mode of the application processor is referred to as "normal security mode" in this embodiment, and the security mode of the security processor is referred to as "enhanced security mode."

[0074] In the description of the embodiments of this application, the application processor is in a non-secure mode, which can also be referred to as the application processor having non-secure attributes. At this time, the application processor can issue operations with non-secure attributes. The application processor is in a normal secure mode, which can also be referred to as the application processor having normal security attributes. At this time, the application processor can issue operations with normal security attributes. The security processor is in an enhanced security mode, which can also be referred to as the security processor having enhanced security attributes. At this time, the security processor can issue operations with enhanced security attributes.

[0075] It is easy to see that in this embodiment, the processor has a three-level security architecture, that is, the processor has three levels of security attributes: non-security attributes, ordinary security attributes, and enhanced security attributes. Among them, the enhanced security attribute has a higher security level than the ordinary security attribute, which allows the secure processor with enhanced security attributes to form an isolated, closed, and secure space that is difficult for malicious code to access, thereby ensuring the security of user critical data in this space.

[0076] Accordingly, in this embodiment, storage areas with different security attributes can be configured in the off-chip memory according to different security levels, so that processors in different security modes can interact with the off-chip memory. For example, an enhanced security attribute storage area can be configured in the off-chip memory. Data stored in the enhanced security attribute storage area can only be accessed by the processor in enhanced security mode. Other processors in the integrated chip (e.g., application processors) cannot access the enhanced security attribute storage area. In the description of this embodiment, the enhanced security attribute storage area can be called the enhanced secure read / write area (enhanced_secure W / R area). As another example, a normal security attribute storage area can be configured in the off-chip memory. Data stored in the normal security attribute storage area can only be accessed by the processor in normal security mode. Other processors in the integrated chip (e.g., security processors) cannot access the normal security attribute storage area. In the description of this embodiment, the normal security attribute storage area can be called the normal secure read / write area (secure W / R area).

[0077] By configuring storage regions with different security attributes in off-chip memory, insecure, secure, and enhanced-security data within the integrated chip can be physically isolated. This creates a secure, enclosed space that is difficult for third-party applications running on the application processor or malicious code that may be present in the operating system to access. Code executed and data stored in such a space have a higher level of security and are more difficult for attackers to breach, thus ensuring the security of critical user data.

[0078] Furthermore, to enable data interaction between the security processor and the application processor, the off-chip memory can also be configured with storage areas for processor read / write in normal security mode and processor read data in enhanced security mode. Simultaneously, it can also be configured with storage areas for processor read data in both normal and enhanced security modes. In the description of the embodiments of this application, the storage areas for processor read / write in normal security mode and processor read data in enhanced security mode can be referred to as the normal secure read / write / enhanced secure read area (secure W / R enhanced_secure R area), and the storage areas for processor read data in both normal and enhanced security modes can be referred to as the enhanced secure read / write / normal secure read area (enhanced_secure W / R secure R area).

[0079] In a specific example, let's refer to the normal secure read / write / enhanced secure read area as storage area A, and the enhanced secure read / write / normal secure read area as storage area B. When the application processor transmits data to the security processor, it can write the data to storage area A and then notify the security processor to read the data from storage area A. Similarly, when the security processor transmits data to the application processor, it can write the data to storage area B and then notify the application processor to read the data from storage area B. Therefore, data interaction between the security processor and the application processor can be achieved through storage areas A and B.

[0080] For example, the memory region partitioning in off-chip memory can be as follows: Figure 4 As shown. In Figure 4 In the example, the off-chip memory can be divided into five memory regions. From 0x0000 to 0x3FFF is the non-secure read / write space, where processors in normal secure mode can read data; this region can be called the non-secure read / write / normal secure read region. From 0x4000 to 0x5FFF is the normal secure read / write space, where only processors in normal secure mode can read and write data. From 0x6000 to 0x7FFF is the memory region used for data exchange between processors in enhanced secure mode and processors in normal secure mode; specifically, from 0x6000 to 0x6FFF is the normal secure read / write / enhanced secure read region; from 0x7000 to 0x7FFF is the enhanced secure read / write / normal secure read region; and finally, from 0x8000 to 0xBFFF is the enhanced secure read / write space, where only processors in enhanced secure mode can read and write data.

[0081] It should be noted that the above-mentioned off-chip memory storage area division is only a specific example. In actual applications, the space size and read / write permissions of the storage area can be flexibly configured according to requirements. This application embodiment does not make specific limitations on this.

[0082] exist Figure 2 In the integrated chip shown, the bus (interconnect) is responsible for connecting the various subsystems (such as security processors, application processors, and memory controllers) to ensure the proper execution of the bus protocol. This bus can be a daisy chain bus, a ring bus, a crossbar bus, or any other type of bus. Furthermore, the bus can also be divided into a configuration bus and a data bus.

[0083] In the prior art, since application processors can operate in a time-sharing manner in non-secure mode and normal secure mode, the secure mode of the application processor can be indicated by 1 bit of data transmitted in a custom signal line in the configuration bus. In this application, this 1 bit of data is referred to as normal security indication information. For example, when the normal security indication information is "1", it indicates that the application processor is in normal secure mode; when the normal security indication information is "0", it indicates that the application processor is in non-secure mode.

[0084] Furthermore, since the integrated chip provided in this application embodiment also includes a security processor in enhanced security mode, it is also possible to indicate whether the processor is working in enhanced security mode through 1 bit data transmitted in another custom signal line. In this application, this 1 bit data is referred to as enhanced security indication information. For example, when the enhanced security indication information is "1", it indicates that the processor is in enhanced security mode; when the enhanced security indication information is "0", it indicates that the processor is not in enhanced security mode. In the integrated chip provided in this application embodiment, only the security processor can set the enhanced security indication information to "1", that is, only the security processor can issue enhanced security attribute operations to the configuration bus, and other processors cannot issue enhanced security attribute operations to the configuration bus.

[0085] For example, in the embodiments of this application, the signal line configuration of the bus (Interconnect) can be as follows: Figure 5 As shown. From Figure 5As can be seen, in addition to the data, address, and control signals required by the bus standard, there are also reserved signals transmitted on the bus, used to transmit user-defined signals. In this embodiment, ordinary security indication information can be transmitted through the secure signal line on the reserved signal line, and enhanced security indication information can be transmitted through the enhanced secure signal line.

[0086] Through the aforementioned hardware connection method of the bus, the processor's non-secure attributes, secure attributes, and enhanced security attributes are transmitted on the bus. The memory controller can authenticate the processor's data access based on these attributes, thereby protecting secure data and enhanced security data at the hardware level.

[0087] For example, access instructions (e.g., read or write instructions) issued by the application processor are transmitted via the bus, and the general security indication information in the access instructions is transmitted via... Figure 5 The access command is transmitted via a security signal line. Upon receiving the access command, the storage controller determines that the normal security indication information transmitted on the security signal line is "1", thus determining that the processor sending the access command is in normal security mode; or, upon receiving the access command, the storage controller determines that the normal security indication information is "0", thus determining that the processor sending the access command is in non-security mode.

[0088] For example, the access command issued by the security processor is transmitted via the bus, and the enhanced security indication information in the access command is transmitted via... Figure 5 The enhanced security signal line is transmitted in the memory. After receiving the access command, the memory controller determines that the enhanced security indication information transmitted on the enhanced security signal line is "1", and thus determines that the processor that sent the access command is in enhanced security mode.

[0089] In practical applications, the above authentication operations can be performed by the firewall of the storage controller. Specifically, the firewall in the storage controller has two functions: first, to store the storage area configuration information of the off-chip memory in the storage controller's local registers; second, to authenticate the access commands issued by the processor (such as a security processor or application processor) when it accesses the off-chip memory through the storage controller.

[0090] For example, an application processor sends a data write command to the storage controller, requesting to write data to a storage area with enhanced security attributes. Upon receiving this data write command, the firewall in the storage controller determines that the normal security indication information transmitted on the security signal line is "1," thus confirming that the processor sending the data write command is in normal security mode. Furthermore, after receiving the data write command, the firewall in the storage controller, by querying the storage area configuration information stored in its local registers, determines that the address requested by the data write command belongs to an enhanced security read / write area. Since the processor sending the data write command does not have enhanced security attributes, the data write command fails the firewall's authentication, and the firewall returns an instruction error indication to the application processor.

[0091] For example, the security processor sends a data read command to the storage controller, requesting to read data in the normal security read / write / enhanced security read zone. Upon receiving this data read command, the firewall in the storage controller determines that the enhanced security indication information transmitted on the enhanced security signal line is "1", thus confirming that the processor sending the data read command is in enhanced security mode. Furthermore, after receiving the data read command, the firewall in the storage controller, by querying the storage zone configuration information stored in its local registers, determines that the address requested by the data read command belongs to the normal security read / write / enhanced security read zone. Since the processor sending the data read command has enhanced security attributes and the command is a read command, the data read command passes the firewall's authentication, and the storage controller sends the data read command to off-chip memory to complete the data read.

[0092] In this embodiment, the security processor can also be called an enhanced security processor (EPS). EPS can be considered a security subsystem within an integrated chip, and is an independent processor separate from the application processor. Figure 6 As shown, the EPS can include an independent central processing unit (CPU) and a cryptographic engine module resistant to physical attacks. Both the CPU and the cryptographic engine module in the EPS have enhanced security attributes. Furthermore, in this embodiment, the CPU in the EPS can also configure the cryptographic engine module in a normal security mode, allowing external processors (such as application processors) to also use the cryptographic engine module to perform related cryptographic operations.

[0093] exist Figure 6In the EPS shown, the CPU can also be called a secure core or a secure CPU. Specifically, a secure core may also include read-only memory (ROM), random access memory (RAM), L1 cache, and L2 cache, which can only be accessed by a processor with enhanced security attributes.

[0094] exist Figure 6 The EPS shown may include various encryption and decryption engines in its encryption and decryption engine module. The encryption and decryption algorithms used by these engines include, but are not limited to, Rivest Shamir Adleman (RSA) encryption algorithm, elliptic curve cryptography (ECC) algorithm, advanced encryption standard (AES) algorithm, data encryption standard (DES) algorithm, and secure hash algorithm (SHA).

[0095] In an EPS (Enhanced Security Module), the CPU and encryption / decryption engine modules are connected via the EPS's internal bus. This internal bus can use the same signal line configuration as the integrated chip bus; that is, it includes both enhanced security signal lines for transmitting enhanced security indication information and security signal lines for transmitting ordinary security indication information. The EPS internal bus connects to the integrated chip bus for data and configuration parameter transfer.

[0096] In this embodiment, the EPS can be used to implement operations with high security requirements in integrated chips, such as storing the root key, key derivation, accelerating the operation of encryption and decryption algorithms, and supporting application scenarios such as protection against physical attacks, protection against side-channel attacks, underlying driver software, secure operating system (OS), security applications, and security protocols. Security applications include, but are not limited to, fingerprint recognition and facial recognition.

[0097] It should be noted that the embodiments of this application do not specifically limit the type of integrated chip. The integrated chip can be a SoC, an electronic control unit (ECU), an Internet of Things (IoT) chip, or other chips in the terminal.

[0098] The embodiments of this application will now be described in further detail with reference to the accompanying drawings.

[0099] It should be noted that in the embodiments of this application, "multiple" refers to two or more. Furthermore, it should be understood that in the description of this application, terms such as "first" and "second" are used only for descriptive purposes and should not be construed as indicating or implying relative importance, nor as indicating or implying order.

[0100] See Figure 7 This is a schematic diagram of an integrated chip structure provided in an embodiment of this application. Figure 7 The integrated chip 700 shown includes an application processor 701, a security processor 702, and a memory controller 703.

[0101] In the ordinary security mode, the application processor 701 is used to write first data to the off-chip memory through the storage controller 703, wherein the address of the first data in the off-chip memory is a first address; the security processor 702 is used to send a first read instruction to the storage controller 703 in the enhanced security mode, wherein the first read instruction is used to request to read the first data at the first address; the storage controller 703 reads the first data from the off-chip memory and sends the first data to the security processor 702.

[0102] Application processor 701 interacts with security processor 702 in the above manner, enabling application processor 701 to transmit first data to security processor 702. Specifically, when application processor 701 transmits first data to security processor 702, unlike existing technologies that use mailboxes (Inbox and Outbox) for data transmission, it writes the first data to be transmitted into off-chip memory, and then security processor 702 reads the first data from off-chip memory. Compared with the mailbox method, this data transmission method improves the information interaction efficiency between application processor 701 and security processor 702 because off-chip memory has a larger storage space and transmission bandwidth. Especially when processing large data streams, data interaction via off-chip memory can significantly reduce processing time, thereby improving processing efficiency.

[0103] It should be noted that the processor in this embodiment has a three-level security architecture, with the enhanced security attribute having the highest security level. To ensure that the security processor with enhanced security attributes forms a secure space that is difficult for malicious code to access, in this embodiment, the application processor typically interacts with the security processor in normal security mode. When the application processor is in non-secure mode, it typically does not interact with the security processor, thereby preventing the theft of critical user data in non-secure mode. Of course, in this embodiment, the security mode of the application processor 701 is not limited; that is, the application processor 701 can work in non-secure mode and normal security mode in a time-sharing manner while performing other operations, and only needs to be in normal security mode when interacting with the security processor 702.

[0104] After writing the first data through the storage controller 703, the application processor 701 can further notify the security processor 702 to read the first data via an interrupt. Upon receiving the notification from the application processor 701, the security processor 702 can send a first read command.

[0105] In other words, in this embodiment, when the application processor 701 sends the first data to the security processor 702, it can first store the first data in off-chip memory, and then notify the security processor 702 to read the first data via an interrupt, triggering the security processor 702 to send a first read instruction. After receiving the first read instruction, the storage controller 703 reads the first data from the off-chip memory and sends the first data to the security processor 702. Using this approach, although the application processor 701 and the security processor 702 also need to interact via interrupts, the data transmitted via interrupts is only used to notify the security processor 702 to read the first data, and the amount of data transmitted is small, so it will not have a significant impact on business processing efficiency.

[0106] In addition, after reading the first data, the security processor 702 can process the first data and write the processed data to the off-chip memory through the storage controller 703; then, the application processor 701 can read the processed data from the off-chip memory through the storage controller 703 in normal security mode.

[0107] Similarly, after the security processor 702 writes the processed data to the off-chip memory through the storage controller 703, it can also notify the application processor 701 to read the processed data via an interrupt.

[0108] In other words, after the security processor 702 processes the first data, it can also write the processed data into the off-chip memory in a similar way to how the application processor 701 transmits the first data, and then notify the application processor 701 through an interrupt to trigger the application processor 701 to read the processed data.

[0109] Specifically, the application processor 701 can send a second read instruction to the storage controller 703 in normal safe mode to request to read the processed data; then, the storage controller 703 can read the processed data from the off-chip memory and send the processed data to the application controller 701.

[0110] Furthermore, before processing the first data read, the security processor 702 can also write second data into the off-chip memory via the memory controller 703 in enhanced security mode, wherein the address of the second data in the off-chip memory is a third address. Then, when the security processor 702 processes the first data read in enhanced security mode, it can do so in the following way: in enhanced security mode, it sends a third read instruction to the memory controller 703, which requests to read the second data at the third address; then, the security processor 702 reads the second data from the off-chip memory via the memory controller 703; finally, it compares the first data with the second data, and uses the comparison result as the processed data.

[0111] In other words, when the security processor 702 processes the first data, it can compare the first data with the second data previously stored in off-chip memory, and use the comparison result as the processed data. The second data can be stored in an enhanced security read / write area in the off-chip memory. Data in this storage area can only be accessed by the processor in enhanced security mode, thus ensuring the security of the second data. For example, the second data can be user fingerprint templates, facial recognition templates, payment passwords, and other data with high security requirements.

[0112] Of course, the above processing procedure of the security processor 702 is only an example. In actual applications, the security processor 702 can process the first data in various ways.

[0113] Based on the above description, one possible interaction method between the application processor 701, the security processor 702, and the storage controller 703 can be as follows: Figure 8 As shown.

[0114] S801: In enhanced security mode, security processor 702 sends second data to memory controller 703 to request that second data be written to off-chip memory.

[0115] The address of the second data in the off-chip memory is the third address.

[0116] S802: The memory controller 703 writes second data to the off-chip memory.

[0117] Specifically, the security processor 702 can write second data into the enhanced security read / write area in the off-chip memory. The data in this storage area can only be read and written by processors in enhanced security mode. Processors without enhanced security attributes do not have permission to access the data in this storage area, thereby ensuring the security of the data in this storage area.

[0118] S803: Application processor 701 sends first data to memory controller 703 in normal security mode to request that first data be written to off-chip memory.

[0119] The address of the first data in the off-chip memory is the first address.

[0120] S804: The memory controller 703 writes the first data to the off-chip memory.

[0121] Specifically, the application processor 701 can write the first data in the normal secure read / write / enhanced secure read area of ​​the off-chip memory.

[0122] S805: After receiving an interrupt message from the application processor 701, the security processor 702 sends a first read instruction to the storage controller 703 in enhanced security mode.

[0123] The first read instruction is used to request the reading of the first data at the first address.

[0124] S806: The storage controller 703 reads the first data from the off-chip memory and sends the first data to the security processor 702.

[0125] S807: The security processor 702 sends a third read instruction to the storage controller 703 in enhanced security mode.

[0126] The third read instruction is used to request the reading of the second data at the third address.

[0127] S808: The storage controller 703 reads the second data from the off-chip memory and sends the second data to the security processor 702.

[0128] S809: In enhanced security mode, the security processor 702 compares the first data with the second data and uses the comparison result as the processed data.

[0129] S810: In enhanced security mode, the security processor 702 sends the processed data to the memory controller 703 to request that the processed data be written to the off-chip memory.

[0130] S811: The storage controller 703 writes the data obtained after the above processing into the off-chip memory.

[0131] Specifically, the security processor 702 can write the first data in the enhanced secure read / write / normal secure read area of ​​the off-chip memory.

[0132] S812: After receiving the interrupt message sent by the security processor 702, the application processor 701 sends a second read instruction to the memory controller 703 in normal security mode.

[0133] The second read instruction is used to request the reading of the data obtained after the processing.

[0134] S813: The storage controller 703 reads the processed data from the off-chip memory and sends the processed data to the application processor 701.

[0135] In a specific example, the first data may be fingerprint data collected by the terminal device where the integrated chip 700 is located, and the second data may be a fingerprint template pre-stored in the enhanced security read / write area by the security processor 702. By executing S801-S802, the security processor 702 stores the fingerprint template in the off-chip memory through the storage controller 703; by executing S803-S804, the application processor 701 stores the collected fingerprint data in the off-chip memory through the storage controller 703; by executing S805-S808, the security processor 702 reads the fingerprint template and the collected fingerprint data from different storage areas of the off-chip memory respectively, and by executing S809, compares the fingerprint template and the collected fingerprint data, and uses the comparison result as the processed data; by executing S810-S811, the security processor 702 writes the processed data into the off-chip memory; by executing S812-S813, the application processor 701 can read the processed data. If the comparison result indicates that the fingerprint data currently collected by the terminal device matches the fingerprint template, the application processor 701 can perform fingerprint unlocking or payment processing after receiving the data obtained after the processing; if the comparison result indicates that the fingerprint data currently collected by the terminal device does not match the fingerprint template, the application processor 701 can perform fingerprint unlocking rejection or payment rejection.

[0136] As can be seen from the foregoing description, in this embodiment, when a processor (such as application processor 701 or security processor 702) requests access to off-chip memory, it needs to do so under the control of storage controller 703. Specifically, storage controller 703 can authenticate the read or write commands sent by the processor. If the authentication is successful, storage controller 703 will respond to the command; if the authentication fails, storage controller 703 will reject the processor's access request.

[0137] The authentication process of read and write commands by the storage controller 703 is described below.

[0138] I. Authentication of Read Commands

[0139] Specifically, when the storage controller 703 reads the first data from the off-chip memory and sends the first data to the security processor 702, it can be achieved in the following way: the storage controller 703 determines that the first read instruction has been authenticated; the storage controller 703 reads the first data and sends the first data to the security processor 702.

[0140] It is clear that the storage controller 703 will only respond to the request of the first read instruction if the first read instruction authentication is successful. If the first read instruction authentication fails, the storage controller 703 will reject the request of the first read instruction and return a bus error indication to the security processor 702.

[0141] In a specific implementation, when the storage controller 703 determines that the first read instruction has passed authentication, it can do so in the following ways: the storage controller 703 determines that the first address belongs to the first storage area of ​​the off-chip memory, the first storage area is configured to allow the processor in normal security mode to perform read and write operations, and to allow the processor in enhanced security mode to perform read operations; the storage controller 703 determines that the security processor 702 is in enhanced security mode and the first read instruction is a read instruction.

[0142] As mentioned earlier, the off-chip memory is configured with storage areas of different security attributes to allow data interaction between the processor and the off-chip memory in different security modes. Here, the first storage area can be considered as the storage area used for interaction between the application processor 701 and the security processor 702. In the first storage area, the application processor 701 in normal security mode can read and write data, while the security processor 702 in enhanced security mode can read data. Therefore, the application processor 701 can transfer data to the security processor 702 through the first storage area. The first storage area can be considered as the aforementioned normal security read / write / enhanced security read area.

[0143] Generally, when authenticating a read instruction sent by the processor, the memory controller 703 first determines which off-chip memory region the requested address belongs to by querying the local register. Then, the memory controller 703 first determines the security attribute of the processor sending the read instruction, and then determines whether the processor with that security attribute has permission to perform a read operation in that memory region. In the example above, the memory controller 703 determines by querying the local register that the first address requested by the first read instruction belongs to a first memory region that allows read / write operations by the processor in normal security mode and read operations by the processor in enhanced security mode. Then, the memory controller 703 determines that the secure processor 702 sending the first read instruction is in enhanced security mode, the first memory region allows read operations by the processor in enhanced security mode, and the first read instruction is indeed a read instruction; therefore, the first read instruction passes the authentication of the memory controller 703.

[0144] The authentication method for the first read instruction described above by the memory controller 703 is only one specific example. In practical applications, the memory controller 703 needs to authenticate any read instruction received to read data from off-chip memory. For example, in... Figure 8 In the illustrated interaction flow, when the storage controller 703 executes S808 to read the second data from the external memory and sends the second data to the security processor 702, it also needs to authenticate the third read instruction sent by the security processor 702. Similarly, when the storage controller 703 executes S813 to read the processed data from the external memory and sends the processed data to the application processor 701, it also needs to authenticate the second read instruction sent by the application processor 701. The authentication methods for the third and second read instructions are similar to those for the first read instruction, and will not be repeated here.

[0145] Of course, the above examples illustrate the scenario where read command authentication succeeds. In practical applications, the storage controller 703 may also fail to authenticate read commands. For instance, if the storage controller 703 receives a read command from the application processor 701 requesting to read data stored in the enhanced security read / write zone, the storage controller 703 determines by querying its local register that the address requested by the read command belongs to the enhanced security read / write zone. Simultaneously, the storage controller 703 determines that the application processor 701 sending the read command is in normal security mode, and processors in normal security mode are not allowed to read data stored in the enhanced security read / write zone. Therefore, the storage controller 703 determines that the read command authentication fails.

[0146] II. Authentication of Write Commands

[0147] Specifically, when the security processor 702 writes the processed data to the off-chip memory through the memory controller 703, it can do so in the following way: the security processor 702 sends a first write instruction to the memory controller 703 in enhanced security mode. The first write instruction is used to request that the processed data be written at the second address. The memory controller 703 is also used to: determine that the first write instruction has passed authentication; and write the processed data to the second address.

[0148] It is clear that the storage controller 703 will only respond to the request of the first write command if the first write command authentication is successful. If the first write command authentication fails, the storage controller 703 will reject the request of the first write command and return a bus error indication to the security processor 702.

[0149] In specific implementation, when the storage controller 703 determines that the first write instruction authentication is successful, it can do so in the following ways: the storage controller 703 determines that the second address belongs to the second storage area of ​​the off-chip memory, the second storage area is configured to allow the processor in enhanced security mode to perform read and write operations, and to allow the processor in normal security mode to perform read operations; the storage controller 703 determines that the security processor 702 is in enhanced security mode.

[0150] As mentioned earlier, the off-chip memory is configured with storage areas of different security attributes to allow data interaction between the processor and the off-chip memory in different security modes. Here, the second storage area can be considered as the storage area used for interaction between the application processor 701 and the security processor 702. In the second storage area, the security processor 702 in enhanced security mode can read and write data, while the application processor 701 in normal security mode can read data. Therefore, the security processor 702 can transfer data to the application processor 701 through the second storage area. The second storage area can be considered as the aforementioned enhanced security read / write / normal security read area.

[0151] Generally, when authenticating a write instruction sent by the processor, the memory controller 703 first determines which off-chip memory region the address requested by the write instruction belongs to by querying the local register. Then, the memory controller 703 first determines the security attribute of the processor sending the write instruction, and then determines whether the processor with that security attribute has permission to perform a write operation in that memory region. In the example above, the memory controller 703 determines by querying the local register that the second address requested by the first write instruction belongs to a second memory region that allows processors in enhanced security mode to perform read and write operations, and allows processors in normal security mode to perform read operations. Then, the memory controller 703 determines that the secure processor 702 that sent the first write instruction is in enhanced security mode, and that the second memory region allows processors in enhanced security mode to perform both write and read operations; therefore, the first write instruction can pass the authentication of the memory controller 703.

[0152] The authentication method for the first write command described above by the memory controller 703 is only one specific example. In practical applications, the memory controller 703 needs to authenticate any write command that writes data to off-chip memory. For example, in... Figure 8 In the interactive flow shown, when the storage controller 703 executes S802 to write second data to the external memory, it also needs to authenticate the write instruction sent by the security processor 702 to write the second data; when the storage controller 703 executes S804 to write first data to the external memory, it also needs to authenticate the write instruction sent by the application processor 701 to write the first data; when the storage controller 703 executes S811 to write the data obtained after processing to the external memory, it also needs to authenticate the write instruction sent by the security processor 702 to write the data obtained after processing. The authentication methods for the write instructions listed above are similar to the authentication methods for the first write instruction, and will not be described again here.

[0153] Of course, the above examples illustrate the scenario where write command authentication succeeds. In practical applications, the storage controller 703 may also fail to authenticate write commands. For instance, if the storage controller 703 receives a write command from the application processor 701 requesting data to be written to the second storage area, the storage controller 703 determines by querying its local register that the address requested by the write command belongs to the second storage area, which allows processors in enhanced security mode to perform read and write operations and processors in normal security mode to perform read operations. Simultaneously, the storage controller 703 determines that the application processor 701 sending the write command is in normal security mode, and processors in normal security mode are not allowed to write data to the second storage area. Therefore, the storage controller 703 determines that the write command authentication fails.

[0154] As mentioned earlier, the firewall in the storage controller 703 can be used to perform the authentication operation on the access commands described above. During authentication, the firewall needs to determine which storage region the address requested by the access command belongs to. Since off-chip memory is configured with multiple storage regions, the firewall in the storage controller 703 needs to verify each storage region requested by the access command when it receives an access command from the processor. Assume the off-chip memory uses... Figure 4 Given the storage area configuration shown, the specific process by which the firewall in storage controller 703 authenticates received access commands can be as follows: Figure 9 As shown.

[0155] Specifically, after receiving an access instruction to access off-chip memory, the storage controller 703 first determines whether the access address corresponding to the access instruction belongs to the enhanced security read / write region. If it belongs to the enhanced security read / write region, it determines whether the enhanced security indication information in the access instruction is "1". If it is "1", it means that the processor sending the access instruction is in enhanced security mode, the access instruction passes the firewall authentication, and the storage controller 703 sends the access instruction to the off-chip memory to complete the data read / write. If it is "0", it means that the processor sending the access instruction is not in enhanced security mode, the access instruction fails the firewall authentication, and the storage controller 703 returns a bus error indication.

[0156] If the access address corresponding to the access instruction does not belong to the enhanced security read / write zone, then it is determined whether the access address belongs to the enhanced security read / write / normal security read zone. If it belongs to the enhanced security read / write / normal security read zone, then it is determined whether the enhanced security indication information in the access instruction is "1", or whether the normal security indication information is "1" and the access instruction requests a read operation. Here, a normal security indication information of "1" indicates that the processor is in normal security mode. If either of the above two conditions is met, the access instruction passes firewall authentication, and the memory controller 703 sends the access instruction to the off-chip memory to complete the data read / write. If neither of the above two conditions is met, the access instruction fails firewall authentication, and the memory controller 703 returns a bus error indication.

[0157] If the access address corresponding to the access command does not belong to the enhanced security read / write / normal security read zone, then it is determined whether the access address belongs to the normal security read / write / enhanced security read zone. If it belongs to the normal security read / write / enhanced security read zone, then it is determined whether the normal security indication information in the access command is "1", or whether the enhanced security indication information is "1" and the access command requests a read operation. If either of the above two conditions is met, the access command passes the firewall authentication; if neither of the above two conditions is met, the access command fails the firewall authentication.

[0158] If the access address corresponding to the access command does not belong to the normal security read / write / enhanced security read zone, then it is determined whether the access address belongs to the normal security read / write zone. If it belongs to the normal security read / write zone, then it is determined whether the normal security indication information in the access command is "1". If it is "1", it means that the processor sending the access command is in normal security mode, and the access command is authenticated by the firewall; if the normal security indication information is "0", it means that the processor sending the access command is not in normal security mode, and the access command is not authenticated by the firewall.

[0159] If the access address corresponding to the access command does not belong to the normal secure read / write zone, it means that the access address belongs to the insecure read / write / normal secure read zone. In this case, it can be determined whether both the enhanced security indication information and the normal security indication information are "0", or whether the normal security indication information is "1" and the access command requests a read operation. If either of the above two conditions is met, the access command passes the firewall authentication; if neither of the above two conditions is met, the access command fails the firewall authentication.

[0160] As can be seen from the above introduction to the firewall authentication process, the firewall needs to verify whether the address requested by the access command belongs to a certain storage area one by one during the authentication process. After determining that the access address belongs to a certain storage area, it then judges whether the security attributes of the processor that sent the access command and the read / write attributes of the access command meet the requirements of the storage area. If they meet the requirements, the access command is authenticated; otherwise, the access command is not authenticated.

[0161] Of course, the above authentication process is only an illustration, and this process uses the storage area configuration of off-chip memory. Figure 4 The example shown illustrates this. If the off-chip memory's storage area configuration uses other methods, the authentication process will also be adjusted accordingly based on the memory's storage area configuration. Furthermore, in... Figure 9 The authentication process shown requires verifying the storage region to which the access address belongs one by one. In practice, the order in which the storage regions are verified is not limited to [specific steps]. Figure 9 As shown in the diagram.

[0162] In this embodiment, when authenticating an access instruction, the storage controller 703 needs to confirm the storage region corresponding to the access address based on the storage region configuration information of the off-chip memory. As mentioned above, the storage region configuration information of the off-chip memory can be stored in the local register of the storage controller 703. Specifically, the storage region configuration can be performed by the security processor 702 and the application processor 701.

[0163] For example, the security processor 702 is further configured to: configure a first storage area to allow the processor to perform read and write operations in normal security mode, and a storage area to allow the processor to perform read operations in enhanced security mode.

[0164] Specifically, the security processor 702 can send first configuration information to the storage controller 703. The first configuration information is used to instruct the first storage area to allow the processor in normal security mode to perform read and write operations, and to allow the processor in enhanced security mode to perform read operations. Then, the storage controller 703 saves the first configuration information.

[0165] For example, the security processor 702 is further configured to: configure the second storage area to allow the processor to perform read and write operations in enhanced security mode, and to allow the processor to perform read operations in normal security mode.

[0166] Specifically, the security processor 702 can send second configuration information to the storage controller 703. This second configuration information instructs the second storage area to allow read / write operations by the processor in enhanced security mode, and to allow read operations by the processor in normal security mode. The storage controller 703 then saves this second configuration information.

[0167] The security processor 702 can send the first configuration information and the second configuration information to the storage controller 703 in a single configuration message, or it can send the first configuration information and the second configuration information separately.

[0168] The above only describes the configuration of the first and second storage areas of the off-chip memory. In practical applications, the security processor 702 and the application processor 701 can configure other storage areas in the off-chip memory, such as enhanced security read / write areas, normal security read / write areas, and non-security read / write / normal security read areas. The configuration process is similar to the configuration process of the first and second storage areas described above, and will not be repeated here.

[0169] It should be noted that, in this embodiment of the application, to enhance system security, all storage areas related to enhanced security attributes are configured by the security processor 702. For example, for Figure 4The storage area configurations of the off-chip memory shown, including the enhanced secure read / write area, the enhanced secure read / write / normal secure read area, and the normal secure read / write / enhanced secure read area, are all configured by the security processor 702.

[0170] Furthermore, as can be seen from the above description of the firewall authentication process, in addition to determining the storage region to which the access address belongs, the firewall also needs to determine the security attributes of the processor sending the access command during authentication. As mentioned earlier, the security attribute information (i.e., ordinary security indication information) of the application processor 701 can be transmitted via the security signal lines in the configuration bus, while the security attribute information (i.e., enhanced security indication information) of the security processor 702 can be transmitted via the enhanced security indication information and ordinary security indication information transmitted through these two custom signal lines. After receiving the access command, the storage controller 703 can determine the security attributes of the processor sending the access command by using the enhanced security indication information and ordinary security indication information transmitted through these two custom signal lines.

[0171] Therefore, the storage controller 703 can also be used to determine that the security processor 702 is in enhanced security mode when the enhanced security indication information in the first read instruction is a first specified value. The enhanced security indication information is transmitted via signal lines on the integrated chip's internal bus.

[0172] In practical applications, the first specified value can be "1".

[0173] In this embodiment, only the security processor 702 can set the enhanced security indication information to the first specified value. Therefore, when the enhanced security indication information in the first read instruction is the first specified value, the storage controller 703 can determine that the processor sending the first read instruction is in the enhanced security mode.

[0174] In addition to the above-mentioned methods for determining enhanced security mode, the storage controller 703 can also determine the processor's normal security mode and non-security mode based on enhanced security indication information and normal security indication information.

[0175] For example, if the enhanced security indication information is "1", it means that the processor sending the access command is in enhanced security mode; if the enhanced security indication information is "0" and the normal security indication information is "1", it means that the processor sending the access command is in normal security mode; if the enhanced security indication information is "0" and the normal security indication information is "0", it means that the processor sending the access command is in non-security mode.

[0176] Below, we take an integrated chip as a SoC, and this SoC adopts... Figure 3Taking the structure shown as an example, the processing procedure of the enhanced security application in this application embodiment will be described. Specifically, the operation flow of the SoC can be as follows: Figure 10 As shown.

[0177] 1. Begin enhancing security applications.

[0178] 2. After the SoC starts up, the CPU configuration DMC in EPS contains enhanced security-related areas.

[0179] The enhanced security-related areas include enhanced security read / write areas, enhanced security read / write / normal security read areas, and normal security read / write / enhanced security read areas. In other words, any storage area related to the read / write permissions of a processor with enhanced security attributes can be considered an enhanced security-related area; these areas are configured by the CPU in the EPS.

[0180] 3. The encryption / decryption engine module in EPS decrypts and verifies the enhanced security applications and data stored in Flash, and stores them in the enhanced security read / write area in DRAM.

[0181] Decrypted and verified data is stored in an enhanced security read / write area. This data can only be accessed by processors with enhanced security attributes, such as the CPU or encryption / decryption engine module in the EPS.

[0182] 4. When the AP encounters an application that requires EPS processing, it writes the raw data that needs EPS processing to the normal secure read / write / enhanced secure read area in DRAM and sends an interrupt to the CPU in the EPS.

[0183] After the AP issues an interrupt, the EPS can read the data written by the AP in the normal secure read / write / enhanced secure read area.

[0184] 5. After the CPU in the EPS receives an interrupt, the EPS reads and processes the data output from the AP to the DRAM. All intermediate data is written to the enhanced security read / write area of ​​the DRAM.

[0185] Intermediate data refers to the intermediate data generated during EPS operations. This intermediate data is stored in an enhanced security read / write area and can only be accessed by processors with enhanced security attributes (such as the CPU or encryption / decryption engine module in EPS).

[0186] 6. After the EPS operation is completed, the final result is written to the enhanced security read / write / normal security read area of ​​the DRAM, and an interrupt is sent to the AP.

[0187] After the EPS issues an interrupt, the AP can read the final result written by the EPS in the enhanced security read / write / normal security read area.

[0188] 7. After receiving an interrupt, the AP reads the final result of the EPS operation from the enhanced security read / write / normal security read area of ​​DRAM.

[0189] 8. End enhanced security applications.

[0190] It should be noted that, Figure 10 The processing procedure shown is merely a specific example of the interaction flow between the application processor and the security processor in this application embodiment. Figure 10 For implementation details not described in the illustrated processing flow, please refer to [link to relevant documentation]. Figure 7 The relevant description is shown in the integrated chip 700.

[0191] In summary, using the integrated chip 700 provided in this application embodiment, after the application processor 701 writes first data to the off-chip memory via the storage controller 703 in normal security mode, the security processor 702 can read the first data via the storage controller 703 in enhanced security mode. Using the above scheme, the application processor 701 can transmit the first data to the security processor 702. In the integrated chip 700, the application processor 701 and the security processor 702 can interact via off-chip memory under the control of the storage controller 703. Compared with the prior art scheme where the application processor and security processor interact via mailboxes (Inbox and Outbox), the off-chip memory has a larger storage space and transmission bandwidth. Therefore, the interaction scheme provided in this application embodiment can improve the efficiency of information interaction, especially when processing large data streams. Data interaction via off-chip memory can significantly reduce processing time, thereby improving processing efficiency.

[0192] Furthermore, the processor in this embodiment has a three-level security architecture, namely, adding a higher-level security architecture (i.e., enhanced security) on top of the original two-level security architecture of non-secure / secure integrated chip. The processor in the integrated chip can have three security attributes, with enhanced security having the highest security level, followed by ordinary security, and non-secure security having the lowest security level. In specific implementation, the security processor 702 with enhanced security has an independent hardware architecture and a storage area (enhanced security read / write area) that is not shared with processors of other security attributes. Therefore, the security processor 702 can form a secure space that is difficult for malicious code to access, thereby protecting the user's critical data at the hardware level. Storing the user's critical data in the enhanced security read / write area can ensure the security of the user's critical data.

[0193] Based on the same inventive concept, embodiments of this application also provide an integrated chip. See also Figure 11The integrated chip 1100 includes a bus 1101 containing a first signal line and a second signal line. The first signal line is used to transmit enhanced security indication information, and the second signal line is used to transmit normal security indication information. A security processor 1102 is used to send a first read instruction to the storage controller via the bus 1101 in enhanced security mode. The enhanced security indication information contained in the first read instruction is transmitted via the first signal line. An application processor 1103 is used to send a second read instruction to the storage controller via the bus in normal security mode. The normal security indication information contained in the second read instruction is transmitted via the second signal line.

[0194] The first signal line can be Figure 5 The enhanced secure signal line in the bus signal line configuration shown can be the second signal line. Figure 5 The secure signal line in the bus signal line configuration shown.

[0195] In the integrated chip 1100, the security processor 1102, application processor 1103, and memory controller are connected via bus 1101. Access instructions (including a first read instruction and a second read instruction) issued by the security processor 1102 and application processor 1103 via bus 1101 contain enhanced security indication information and ordinary security indication information. The enhanced security indication information is transmitted via a first signal line in bus 1101, and the ordinary security indication information is transmitted via a second signal line in bus 1101. The memory controller can determine the security attributes of the processor sending the access instruction based on the received enhanced and ordinary security indication information.

[0196] Specifically, the integrated chip 1100 may further include a storage controller, which is configured to determine that the security processor 1102 is in enhanced security mode when the enhanced security indication information included in the first read instruction is a first specified value.

[0197] For example, the first specified value can be "1". In this embodiment, only the security processor 1102 can set the enhanced security indication information to the first specified value. Therefore, when the enhanced security indication information in the first read instruction is the first specified value, the storage controller can determine that the processor sending the first read instruction is in enhanced security mode.

[0198] In addition, the storage controller is also configured to: determine that the application processor 1103 is in normal security mode when the normal security indication information in the second read instruction is a second specified value; and determine that the application processor 1103 is in non-security mode when the normal security indication information in the second read instruction is a third specified value.

[0199] For example, the second specified value can be "1" and the third specified value can be "0".

[0200] In the integrated chip 1100, after receiving the second read instruction, the storage controller determines that the enhanced security indication information in the second read instruction is not the first specified value. Therefore, the storage controller can determine that the application processor 1103 that sent the second read instruction does not have enhanced security attributes. At this point, the storage controller further determines the normal security indication information in the second read instruction. If the normal security indication information is the second specified value, the application processor 1103 is determined to be in normal security mode; if the normal security indication information is the third specified value, the application processor 1103 is determined to be in non-security mode.

[0201] It should be understood that in the integrated chip 1100, after receiving a read instruction, the storage controller will determine the security attribute of the processor that sent the read instruction based on the enhanced security indication information and the normal security indication information in the read instruction; similarly, after receiving a write instruction, the storage controller will also determine the security attribute of the processor that sent the write instruction based on the enhanced security indication information and the normal security indication information in the write instruction. The determination method is the same as the aforementioned method for determining the read instruction, and will not be repeated here.

[0202] It should be noted that both integrated chip 1100 and integrated chip 700 are integrated chips provided in the embodiments of this application, and their implementation methods can be referred to each other, which will not be repeated here.

[0203] Based on the same inventive concept, embodiments of this application also provide a data processing method. See [link to relevant documentation]. Figure 12 The data processing method includes the following steps.

[0204] S1201: The storage controller receives the first read command sent by the security processor.

[0205] The first read instruction is used to request the reading of the first data at the first address in the off-chip memory.

[0206] S1202: The storage controller determines that the first read instruction has passed authentication.

[0207] S1203: The storage controller reads the first data from the off-chip memory and sends the first data to the security processor.

[0208] Optionally, the memory controller determines that the first read instruction has passed authentication, which can be achieved in the following way: the memory controller determines that the first address belongs to the first storage area of ​​the off-chip memory by querying the local register. The first storage area is configured to allow the processor in normal security mode to perform read and write operations, and to allow the processor in enhanced security mode to perform read operations. The memory controller determines that the security processor is in enhanced security mode and that the first read instruction is a read instruction.

[0209] Furthermore, the storage controller determines that the security processor is in enhanced security mode, which can be achieved in the following way: if the enhanced security indication information in the first read instruction is a first specified value, the storage controller determines that the security processor is in enhanced security mode.

[0210] also, Figure 12 The data processing method shown further includes: the storage controller receiving first configuration information sent by the security processor, the first configuration information being used to instruct the first storage area to allow the processor in normal security mode to perform read and write operations, and to allow the processor in enhanced security mode to perform read operations; the storage controller storing the first configuration information in a local register.

[0211] Optionally, Figure 12 The data processing method shown further includes: after the storage controller sends the first data to the security processor, it receives a first write instruction sent by the security processor. The first write instruction is used to request the writing of the processed data at the second address. The processed data is obtained by the security processor after processing the first data. The storage controller determines that the first write instruction has passed authentication. The storage controller writes the processed data to the second address.

[0212] Optionally, the memory controller can determine that the first write instruction has passed authentication by querying the local register to determine that the second address belongs to the second storage area of ​​the off-chip memory. The second storage area is configured to allow the processor in enhanced security mode to perform read and write operations, and to allow the processor in normal security mode to perform read operations. The memory controller then determines that the security processor is in enhanced security mode.

[0213] Furthermore, the storage controller can also receive second configuration information sent by the security processor. The second configuration information is used to instruct the second storage area to allow the processor in enhanced security mode to perform read and write operations, and to allow the processor in normal security mode to perform read operations. The storage controller saves the second configuration information in a local register.

[0214] The security processor can send the first configuration information and the second configuration information in the same message or send them separately.

[0215] Optionally, Figure 12 The data processing method shown further includes: after the storage controller writes the processed data to the second address, it can also receive a second read instruction sent by the application processor. The second read instruction is used to request to read the processed data; the storage controller determines that the second read instruction has passed authentication; then, the storage controller reads the processed data and sends the processed data to the application processor.

[0216] Specifically, the storage controller determines that the second read instruction has passed authentication. This can be achieved by: the storage controller determining that the second address belongs to the second storage area; or the storage controller determining that the application processor is in normal security mode and that the second read instruction is a read instruction.

[0217] Specifically, the storage controller determines that the application processor is in normal security mode. This can be achieved by the storage controller determining that the application processor is in normal security mode when the normal security indication information in the second read instruction is a second specified value.

[0218] It should be noted that, Figure 12 The data processing method shown is Figure 7 A specific example of the authentication process of the memory controller 703 in the integrated chip 700 is shown. Figure 12 For details regarding the implementation methods and their technical effects not described in the data processing methods shown, please refer to [link to relevant documentation]. Figure 7 The relevant description is shown in the integrated chip 700.

[0219] Obviously, those skilled in the art can make various modifications and variations to the embodiments of this application without departing from the scope of the embodiments of this application. Therefore, if these modifications and variations to the embodiments of this application fall within the scope of the claims of this application and their equivalents, this application also intends to include these modifications and variations.

Claims

1. An integrated chip, characterized in that, include: An application processor is configured to write first data to off-chip memory via a storage controller in a normal security mode, wherein the address of the first data in the off-chip memory is a first address; A security processor is configured to send a first read instruction to the storage controller in an enhanced security mode, the first read instruction being used to request the reading of the first data at the first address; The security processor is further configured to: process the first data read in the enhanced security mode, and write the processed data into the off-chip memory through the storage controller; The application processor is also configured to read the processed data from the off-chip memory via the storage controller in the normal security mode; The storage controller is configured to determine that the first address belongs to a first storage area of ​​the off-chip memory, the first storage area being configured to allow the processor to perform read and write operations in the normal security mode and to allow the processor to perform read operations in the enhanced security mode. The storage controller determines that the security processor is in the enhanced security mode and that the first read instruction is a read instruction; The storage controller reads the first data and sends the first data to the security processor.

2. The integrated chip as described in claim 1, characterized in that, When the application processor reads the processed data from the off-chip memory through the storage controller, it is specifically used for: In the normal security mode, a second read command is sent to the storage controller, the second read command being used to request the reading of the processed data; The storage controller is further configured to: read the processed data from the off-chip memory and send the processed data to the application processor.

3. The integrated chip as described in claim 1, characterized in that, The security processor is also used for: After the processed data is written to the off-chip memory through the storage controller, the application processor is notified to read the processed data via an interrupt.

4. The integrated chip as described in claim 1 or 2, characterized in that, The application processor is also used for: After the first data is written to the off-chip memory by the storage controller, the security processor is notified to read the first data via an interrupt.

5. The integrated chip as described in claim 1 or 2, characterized in that, The security processor is also used for: The first storage area is configured to allow the processor to perform read and write operations in the normal security mode and to allow the processor to perform read operations in the enhanced security mode.

6. The integrated chip as described in claim 2, characterized in that, When the security processor writes the processed data to the off-chip memory via the storage controller, it is specifically used for: The security processor sends a first write instruction to the storage controller in the enhanced security mode, the first write instruction being used to request the data obtained after processing to be written at a second address; The storage controller is also used for: The first write instruction has been authenticated. The processed data is written to the second address.

7. The integrated chip as described in claim 6, characterized in that, When the storage controller determines that the first write instruction has passed authentication, it specifically performs the following functions: The storage controller determines that the second address belongs to a second storage region of the off-chip memory, and the second storage region is configured to allow the processor in the enhanced security mode to perform read and write operations, and to allow the processor in the normal security mode to perform read operations. The storage controller determines that the security processor is in the enhanced security mode.

8. The integrated chip as described in claim 7, characterized in that, The security processor is also used for: The second storage area is configured to allow the processor to perform read and write operations in the enhanced security mode, and to allow the processor to perform read operations in the normal security mode.

9. The integrated chip as described in claim 2, characterized in that, The security processor is also used for: Before processing the first data read, in the enhanced security mode, the storage controller writes the second data into the off-chip memory, wherein the address of the second data in the off-chip memory is a third address; When the security processor processes the first data read in the enhanced security mode, it is specifically used for: In the enhanced security mode, a third read instruction is sent to the storage controller, the third read instruction being used to request the reading of the second data under the third address; The second data is read from the off-chip memory via the storage controller; The first data is compared with the second data, and the comparison result is used as the data obtained after the processing.

10. The integrated chip as described in claim 1, characterized in that, The storage controller is also used for: If the enhanced security indication information in the first read instruction is a first specified value, it is determined that the security processor is in the enhanced security mode.

11. The integrated chip as described in claim 10, characterized in that, The enhanced security indication information is transmitted via signal lines on the internal bus of the integrated chip.

12. The integrated chip as described in claim 1, characterized in that, The application processor is also used for: Time-sharing operation in both non-secure mode and the normal secure mode.

13. An integrated chip, characterized in that, include: A bus including a first signal line and a second signal line, wherein the first signal line is used to transmit enhanced security indication information and the second signal line is used to transmit ordinary security indication information; An application processor is configured to write first data to off-chip memory via a storage controller in a normal security mode, wherein the address of the first data in the off-chip memory is a first address; A security processor is configured to send a first read instruction to the storage controller via the bus in an enhanced security mode, wherein the enhanced security indication information contained in the first read instruction is transmitted via the first signal line; The security processor is further configured to: process the first data read in the enhanced security mode, and write the processed data into the off-chip memory through the storage controller; An application processor is configured to send a second read instruction to the storage controller via the bus in a normal security mode, wherein the normal security indication information contained in the second read instruction is transmitted via the second signal line; The application processor is also configured to read the processed data from the off-chip memory via the storage controller in the normal security mode; The storage controller is configured to determine that the security processor is in the enhanced security mode when the enhanced security indication information included in the first read instruction is a first specified value; The storage controller is further configured to determine that the first address belongs to a first storage area of ​​the off-chip memory, the first storage area being configured to allow the processor in the normal security mode to perform read and write operations, and to allow the processor in the enhanced security mode to perform read operations. The storage controller determines that the security processor is in the enhanced security mode and that the first read instruction is a read instruction; The storage controller reads the first data and sends the first data to the security processor.

14. The integrated chip as described in claim 13, characterized in that, The storage controller is also used for: If the normal security indication information in the second read instruction is a second specified value, the application processor is determined to be in the normal security mode; if the normal security indication information in the second read instruction is a third specified value, the application processor is determined to be in the non-security mode.

15. A data processing method, applied to an integrated chip as described in claims 1-12 or 13-14, characterized in that, include: The storage controller determines that the first address belongs to a first storage area of ​​the off-chip memory by querying the local register. The first storage area is configured to allow the processor to perform read and write operations in normal security mode and to allow the processor to perform read operations in enhanced security mode. The storage controller determines that the security processor is in the enhanced security mode and that the first read instruction is a read instruction; The storage controller reads the first data from the off-chip memory and sends the first data to the security processor.

16. The method as described in claim 15, characterized in that, The storage controller determines that the security processor is in the enhanced security mode, including: When the enhanced security indication information in the first read instruction is a first specified value, the storage controller determines that the security processor is in the enhanced security mode.

17. The method as described in claim 16, characterized in that, Also includes: The storage controller receives first configuration information sent by the security processor. The first configuration information is used to instruct the first storage area to allow the processor in the normal security mode to perform read and write operations, and to allow the processor in the enhanced security mode to perform read operations. The storage controller stores the first configuration information in the local register.

18. The method as described in claim 16, characterized in that, Also includes: After sending the first data to the security processor, the storage controller receives a first write instruction from the security processor. The first write instruction is used to request the writing of the processed data at the second address. The processed data is obtained by the security processor after processing the first data. The storage controller determines that the first write instruction has passed authentication; The storage controller writes the processed data to the second address.

19. The method as described in claim 18, characterized in that, The storage controller determines that the first write instruction has passed authentication, including: The storage controller determines that the second address belongs to the second storage area of ​​the off-chip memory by querying the local register. The second storage area is configured to allow the processor in the enhanced security mode to perform read and write operations, and to allow the processor in the normal security mode to perform read operations. The storage controller determines that the security processor is in the enhanced security mode.

20. The method as described in claim 19, characterized in that, Also includes: The storage controller receives second configuration information sent by the security processor. The second configuration information is used to instruct the second storage area to allow the processor in the enhanced security mode to perform read and write operations, and to allow the processor in the normal security mode to perform read operations. The storage controller stores the second configuration information in the local register.

21. The method as described in claim 19, characterized in that, Also includes: After writing the processed data to the second address, the storage controller receives a second read instruction sent by the application processor. The second read instruction is used to request to read the processed data. The storage controller determines that the second read instruction has been authenticated; The storage controller reads the processed data and sends the processed data to the application processor.

22. The method as described in claim 21, characterized in that, The storage controller determines that the second read instruction has passed authentication, including: The storage controller determines that the second address belongs to the second storage area; The storage controller determines that the application processor is in the normal security mode and that the second read instruction is a read instruction.

23. The method as described in claim 22, characterized in that, The storage controller determines that the application processor is in the normal security mode, including: When the normal security indication information in the second read instruction is a second specified value, the storage controller determines that the application processor is in the normal security mode.

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