Parallel cross entropy benchmarking

Abstract

Methods, systems, and apparatus for benchmarking quantum computing hardware. In one aspect, a method includes defining an initial circuit configured to operate on an array of qubits, wherein the initial circuit includes multiple instances of a two-qubit gate, wherein each instance of the two-qubit gate performs the same operation on a corresponding adjacent pair of qubits in the array; partitioning the initial circuit into multiple layers, wherein the instances of the two-qubit gate in the corresponding layer can be implemented in parallel; for each layer in the multiple layers: constructing a benchmarking circuit for the layer, wherein each benchmarking circuit of the layer includes one or more cycles of quantum gates, each cycle including: a layer of instances of the two-qubit gate and multiple single-qubit gates; implementing the constructed benchmarking circuit to obtain experimental benchmarking data; and adjusting control parameters of a control model using the experimental benchmarking data.

Description

Technical Field

[0001] This specification relates to quantum computing. Background Art

[0002] Quantum computing uses quantum mechanical phenomena such as superposition and entanglement to perform calculations. A quantum circuit is an example model of quantum computing, where the computation is a series of quantum logic gates that are reversible transformations of the quantum mechanical analog of an n-bit register. Summary of the Invention

[0003] This specification describes techniques for benchmarking multi-qubit quantum gates.

[0004] In general, one innovative aspect of the subject matter described in this specification can be implemented in a method comprising: defining a control model for implementing a two-qubit quantum gate; adjusting the control model for implementing the two-qubit quantum gate, the adjusting comprising: defining an initial quantum circuit configured to operate on a qubit array, wherein the initial quantum circuit comprises a plurality of instances of the two-qubit gate, wherein each instance of the two-qubit gate performs the same operation on respective adjacent pairs of qubits in the qubit array; partitioning the initial quantum circuit into multiple layers of instances of the two-qubit gate, wherein the instances of the two-qubit gate in each layer can be implemented in parallel; for each layer in the multiple layers of two-qubit gate instances: constructing one or more benchmarking circuits for the layer, wherein each benchmarking circuit for the layer comprises one or more cycles of quantum gates, each cycle comprising: a layer of instances of the two-qubit gate and a plurality of single-qubit gates, wherein each single-qubit gate in the plurality of single-qubit gates corresponds to a respective qubit in the qubit array; executing the constructed benchmarking circuits to obtain experimental benchmarking data; and using the generated experimental benchmarking data to adjust control parameters of the control model for implementing the two-qubit quantum gate.

[0005] Other implementations of this aspect include corresponding classical and quantum computer systems, apparatuses, and computer programs recorded on one or more computer storage devices, each of which is configured to perform the actions of the method. One or more classical and / or computer systems can be configured to perform specific operations or actions by installing software, firmware, hardware, or a combination thereof on the system, which software, firmware, hardware, or a combination thereof causes the system to perform these actions during operation. One or more computer programs can be configured to perform specific operations or actions by including instructions that, when executed by a data processing device, cause the device to perform the actions.

[0006] The foregoing and other implementations can each optionally include one or more of the following features, alone or in combination. In some implementations, constructing a benchmarking circuit for a layer of instances of two-qubit gates includes assigning one or more clock cycles of the quantum gates to a qubit array, and for each clock cycle, includes: randomly sampling a plurality of single-qubit quantum gates from a predetermined set of single-qubit quantum gates, wherein each randomly sampled single-qubit quantum gate corresponds to a corresponding qubit in the qubit array; assigning the randomly sampled plurality of single-qubit quantum gates to corresponding qubits in the qubit array, and assigning instances of the two-qubit gates in the layer to corresponding nearest-neighbor qubit pairs in the qubit array.

[0007] In some implementations, the predetermined set of single-qubit quantum gates includes and T quantum gates, where represents a π / 2 rotation around the X axis, represents a π / 2 rotation about the y-axis, and T represents a non-Clifford diagonal matrix {0, e iπ / 4}.

[0008] In some implementations, assigning the randomly sampled plurality of single-qubit quantum gates to corresponding qubits in the qubit array includes assigning a second single-qubit gate to qubit q in a current clock cycle, wherein the second single-qubit gate is different from a first single-qubit gate assigned to qubit q in a previous clock cycle.

[0009] In some implementations, constructing one or more benchmarking circuits for the layer includes constructing multiple benchmarking circuits having different corresponding circuit depths.

[0010] In some implementations, implementing the constructed benchmarking circuit to obtain experimental benchmarking data includes, for each constructed benchmarking circuit: initializing each qubit in the qubit array in an initial state; applying the constructed benchmarking circuit to the initialized qubits in the qubit array, wherein instances of the two-qubit gate in each layer of instances of the two-qubit gate are implemented in parallel; measuring each qubit in the qubit array to obtain measurement data for each qubit; and extracting the experimental benchmarking data from the measurement data.

[0011] In some implementations, the method further includes applying a Hadamard gate to each qubit in the initial state before applying the constructed benchmarking circuit to the initialized qubit in the qubit array.

[0012] In some implementations, using the generated experimental benchmarking data to adjust control parameters of a control model for implementing a two-qubit quantum gate includes: classically simulating each constructed benchmarking circuit to obtain classical benchmarking data representing an output distribution of an ideal implementation of the constructed benchmarking circuit; comparing the classical benchmarking data with the experimental benchmarking data, including determining a cross-entropy difference between the classical benchmarking data and the experimental benchmarking data, wherein the cross-entropy difference represents the fidelity of the implementation of the constructed benchmarking circuit; and adjusting the control parameters of the control model for implementing the two-qubit quantum gate to improve the fidelity of the parallel implementation of the constructed benchmarking circuit.

[0013] In some implementations, the method further includes estimating the fidelity of an implementation of the constructed benchmark analysis circuit as a function of circuit depth; and determining an error-per-cycle metric by fitting the fidelity of the implementation of the constructed benchmark analysis circuit as a function of circuit depth to an exponential.

[0014] In some implementations, the control parameters of the control model include control angles of one or more quantum gates.

[0015] In some implementations, the qubit array comprises a 2D array, and wherein the multiple layers of instances of the two-qubit gate comprise four layers of instances of the two-qubit gate.

[0016] The subject matter described in this specification can be implemented in a specific manner to achieve one or more of the following advantages.

[0017] Systems implementing the techniques described herein enable multi-qubit entangled gates to be benchmarked efficiently and effectively. Compared to other techniques, such as those in which individual copies of a multi-qubit gate are benchmarked separately, the presently described techniques reduce the runtime of the benchmarking to constant time, making it easily scalable. Furthermore, compared to other techniques, such as those in which non-idealities in quantum hardware operation, such as crosstalk and unwanted qubit interactions, are ignored, the presently described techniques allow such non-idealities to be captured while maintaining the tractability of the benchmarking process.

[0018] The presently described techniques can be applied to improve quantum computing hardware. Benchmarking results, such as those for quantum gate fidelity, can be used to identify adjustments that can improve the accuracy of existing quantum computing hardware, for example, by increasing the precision with which quantum computing hardware performs quantum operations. For example, benchmarking results can be used to adjust the control model used to implement quantum gates. Errors in the adjusted control model can be less sensitive to drift because the errors are quadratic and determined adjustments result in increasingly accurate control models. Benchmarking results can also be used to calibrate or validate quantum computing hardware.

[0019] The details of one or more implementations of the subject matter of this specification are set forth in the accompanying drawings and the description below. Other features, aspects, and advantages of the subject matter will become apparent from the description, drawings, and claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1 Depicts an example system for benchmarking the performance of quantum computing hardware.

[0021] Figure 2A An example of dividing an initial quantum circuit into multiple layers that can be implemented in parallel is illustrated.

[0022] Figure 2B Illustration of an example benchmarking quantum circuit.

[0023] Figure 3 is a flow chart of an example process for tuning a control model that implements a two-qubit quantum gate.

[0024] Figure 4A Example diagrams showing the differences in gate behavior between individual and parallel operations due to such control crosstalk and stray qubit-qubit interactions.

[0025] Figure 4B Example plot showing the differences in unitary model parameters between unitaries obtained in isolated and parallel experiments. DETAILED DESCRIPTION

[0026] Overview

[0027] Quantum circuits are models of quantum computing in which quantum logic gates are applied to qubit registers in a specific order to encode quantum information. In theory, by applying a correctly chosen sequence of quantum logic gates, any quantum algorithm can be implemented with high precision. However, in practice, quantum logic gates are prone to errors—experiments attempting to implement unitary quantum operations that represent ideal quantum logic gates actually result in noisy quantum operations.

[0028] Benchmarking techniques can be applied to determine how closely noisy quantum operations performed by quantum hardware resemble ideal unitary quantum operations, thereby characterizing the performance of quantum hardware. For example, benchmarking techniques can be applied to characterize the performance of an implementation of a two-qubit quantum gate. This can involve using quantum hardware to execute a random quantum circuit containing multiple instances of the two-qubit gate and simulating the same random quantum circuit using a classical computer. The results of the quantum and classical computations can be compared to determine how noisy the quantum operations are, as well as their fidelity and purity.

[0029] For quantum hardware consisting of a square array of N qubits with nearest-neighbor connectivity, there are ~2N nearest-neighbor qubit pairs, each characterized by a two-qubit gate. Since benchmarking a single entangled gate operating on the corresponding qubit pair can take several minutes, benchmarking the ~2N qubit pairs sequentially is very expensive and scales linearly with the size of the system. Furthermore, operating a single two-qubit gate in isolation is different from operating it in the context of a complex algorithm on a large device, as non-idealities such as crosstalk and unwanted interactions can affect the implementation of the two-qubit gate. However, because the Hilbert space is large, it becomes computationally very difficult to directly measure large qubit systems using known benchmarking techniques such as cross-entropy benchmarking.

[0030] This specification describes a technique for benchmarking multi-qubit quantum gates in parallel to efficiently and effectively evaluate quantum computing hardware performance. The set of multi-qubit quantum gates to be characterized is partitioned into multiple layers that can be executed simultaneously. A separate benchmarking experiment is then performed for each layer, where all multi-qubit gates in the layer are executed in parallel. This allows system-level non-idealities to be captured while maintaining the low complexity of classical simulations, because each qubit nominally interacts with only one neighbor, so each pair of qubits can be simulated classically separately.

[0031] Example Hardware

[0032] Figure 1 An example system for benchmarking the performance of quantum computing hardware is depicted. Example system 100 is an example of a system implemented as classical and quantum computer programs on one or more classical and quantum computers at one or more locations, in which the systems, components, and techniques described below can be implemented.

[0033] System 100 includes a classical processor 102 in data communication with quantum computing hardware 104. For convenience, classical processor 102 and quantum computing hardware 104 are illustrated as separate entities, however, in some implementations, classical processor 102 can be included in quantum computing hardware 104, e.g., quantum computing hardware 104 can include one or more components for performing classical computing operations.

[0034] Quantum computing hardware 104 includes components for performing quantum computations using quantum circuits. For example, quantum computing hardware 104 includes a quantum system 120 and a control device 122. Quantum system 120 includes one or more multi-level quantum subsystems, such as qubits, for performing algorithmic operations or quantum computations. The specific implementation of the multi-level quantum subsystems included in quantum computing hardware 104 and how they interact with each other depend on various factors, including the type of quantum computation being performed by the quantum computing hardware. For example, the multi-level quantum subsystems may include qubits implemented via atoms, molecules, or solid-state quantum systems. In other examples, qubits may include, but are not limited to, superconducting qubits or semiconductor qubits.

[0035] Multi-level quantum subsystems can be frequency-tunable. For example, each qubit can have an associated operating frequency that can be adjusted, for example, using one or more control devices 122, by applying voltage pulses via one or more drive lines coupled to the qubit. Example operating frequencies include a qubit idle frequency, a qubit interaction frequency, and a qubit readout frequency. Different frequencies correspond to different operations that a qubit can perform. For example, setting the operating frequency to a corresponding idle frequency can cause a qubit to enter a state in which it does not strongly interact with other qubits and can be used to execute a single-qubit gate. As another example, where qubits interact via a coupler with a fixed coupling, the qubits can be configured to interact with each other by setting their respective operating frequencies to a gate-dependent frequency that is detuned from their common interaction frequency. In other cases, such as when qubits interact via a tunable coupler, the qubits can be configured to enable interaction between the qubits by setting the parameters of their respective couplers, and then interact with each other by setting their respective operating frequencies to a gate-dependent frequency that is detuned from their common interaction frequency. Such interactions can be performed to perform multi-qubit gates, such as the two-qubit gates described in this specification.

[0036] The control device 122 can further include a measurement device, such as a readout resonator. The measurement results (measurement data) obtained via the measurement device can be provided to a classical processor included in the quantum computing hardware 104 or to the classical processor 102 for processing and analysis.

[0037] A classical processor 102 receives input data 106 representing a control model U(θ, φ) for implementing an entangled two-qubit quantum gate (referred to herein as a two-qubit gate). For example, U(θ, φ) can represent a fermionic analog gate, such as a gate modeled as iSWAP(θ) followed by Cphase(φ) (and optionally one or more single-qubit Z-gates), where θ, φ represent specific control angles for the fermionic analog gate. The control model represents a mapping between the parameters of the quantum gate (e.g., qubit rotation angle, phase, etc.) and the control parameters of the physical system used to implement the quantum gate (e.g., control line voltage, pulse shape, operating frequency, etc.).

[0038] The classical processor 102 processes the received input data 106 to generate output data 108 representing an adjusted control model U(θ′, φ′). For example, the output data 108 may include a control model whose model parameters θ, φ have been adjusted so that the control model U(θ′, φ′) provides a representation of a two-qubit gate that, when implemented by the quantum computing hardware 104, achieves improved gate fidelity.

[0039] The classical processor 102 includes a plurality of components for processing received input data. For example, the classical processor 102 may include a random quantum circuit generator 110 , a circuit simulator 112 , and a data processing module 114 .

[0040] The random quantum circuit generator 110 can be configured to define a quantum circuit based on the quantum computing hardware 104 (e.g., the number of qubits included in the quantum computing hardware, how they are arranged, and how they interact with each other) and the received input data 106. For example, the random quantum circuit generator 110 can be configured to define an initial quantum circuit that includes multiple instances of a two-qubit gate specified in the input data 106, where each instance of the two-qubit gate performs the same operation on a corresponding pair of interacting qubits in the quantum system 120. In some implementations, the instances of the two-qubit gate operate on all possible pairs of interacting qubits in the 2D array of qubits. Figure 2A Example initial quantum circuits are illustrated and described.

[0041] The random quantum circuit generator 110 can also be configured to define a random benchmark analysis quantum circuit based on the defined initial quantum circuit. Each initial quantum circuit defined by the random quantum circuit generator 110 can be divided into multiple layers, where instances of two-qubit gates in corresponding layers can be implemented in parallel. Figure 2A An example of partitioning an initial quantum circuit into multiple layers is illustrated and described, where instances of two-qubit gates in each layer can be implemented in parallel.

[0042] The random quantum circuit generator 110 uses this property to define random benchmarking quantum circuits, where each defined random benchmarking quantum circuit corresponds to a respective partitioning level of an instance of a two-qubit gate.

[0043] To define a benchmark quantum circuit corresponding to a corresponding partitioning layer of instances of two-qubit gates, random quantum circuit generator 110 is configured to randomly sample single-qubit gates from a predefined set of single-qubit gates, such as a set of single-qubit gates that can be implemented by quantum hardware 104. Each randomly sampled single-qubit quantum gate corresponds to a corresponding qubit in quantum system 120. Furthermore, each qubit in the quantum system has an associated single-qubit gate in each cycle. In some implementations, random quantum circuit generator 110 is configured to implement one or more rules for sampling and distributing single-qubit gates, as described below with reference to Figure 3 Described in more detail.

[0044] To generate a benchmark quantum circuit corresponding to a corresponding partitioned layer of instances of the two-qubit gate, the random quantum circuit generator 110 is configured to define a cycle of quantum gates, where each cycle includes a corresponding instance of a randomly sampled single-qubit gate, followed by a layer of instances of the two-qubit gate. The number of cycles included in the benchmark quantum circuit defines the depth of the benchmark quantum circuit. In some implementations, the random quantum circuit generator 110 defines multiple benchmark quantum circuits of different depths, for example, to enable the system to estimate circuit fidelity as a function of circuit depth.

[0045] Quantum circuit 130 is an example of a random benchmarking quantum circuit generated by random quantum circuit generator 110. Example quantum circuit 130 illustrates a benchmarking quantum circuit configured to operate on two qubits, q1 and q2. Example quantum circuit 130 includes four cycles, where each cycle includes two randomly sampled single-qubit gates. For example, cycle 1 includes randomly sampled single-qubit gates R1 and R2 that operate on qubits q1 and q2, respectively; cycle 2 includes randomly sampled single-qubit gates R3 and R4 that operate on qubits q1 and q2, respectively; and so on. Each cycle also includes a corresponding layer, "layer x," of instances of two-qubit gates.

[0046] Classical processor 102 is configured to send data 116 representing the defined benchmark quantum circuit to quantum computing hardware 104. Quantum computing hardware 104 is configured to implement the defined benchmark quantum circuit using quantum system 120 and control device 122. Due to the specific construction of the benchmark quantum circuit defined by random quantum circuit generator 110, quantum computing hardware 104 implements two-qubit gates in parallel in each layer of instances of the two-qubit gates.

[0047] Quantum computing hardware 104 can provide output data representing the results of the circuit implementation, such as experimental benchmarking data 124, and send this data to classical processor 102. In some implementations, classical processor 102 can process the received experimental benchmarking data 124 (which includes data corresponding to the entire multi-qubit Hilbert space) to extract data for each qubit pair, for example, to extract data corresponding to a collection of two-qubit Hilbert spaces, where the two-qubit Hilbert spaces can be analyzed independently. For example, experimental benchmarking data 124 can include multiple n-bit bit strings representing the results of measuring all qubits simultaneously. To analyze this data, the data corresponding to each qubit pair can be considered separately (as if the paired qubits had been individually benchmarked). Classical processor 102 can convert the data (bit strings) corresponding to each qubit pair into probabilities for the four possible two-qubit output states: 00, 10, 01, and 11. These probabilities can be used in the processing steps described below.

[0048] The classical processor 102 is also configured to provide data 116 representing the defined benchmark quantum circuit to a circuit simulator module 112. The circuit simulator module 112 is configured to perform classical computations to simulate an implementation of the benchmark quantum circuit defined by the data 116, for example, computing the output distribution of an ideal implementation of the constructed benchmark circuit using the best known control model U(θ, φ). The circuit simulator 112 can provide output data representing circuit simulation results, such as classical benchmark data 126, to a processing module 114 included in the classical processor 102.

[0049] The data processing module 114 is configured to process experimental benchmarking data 124 received from the quantum computing hardware 104 and classical benchmarking data 126 received from the circuit simulator 112 .

[0050] Processing the experimental benchmarking data and the classical benchmarking data can include applying a cross-entropy benchmarking technique, where the cross-entropy is used as a measure of the correspondence between the experimental benchmarking data and the classical benchmarking data representing the output distribution of an ideal circuit. For example, the data processing module 114 can be configured to determine the cross-entropy (or average cross-entropy) of the experimental benchmarking data 124 and the classical benchmarking data 126. The (average) cross-entropy difference can be used as an estimate of the fidelity of the two-qubit gate—this property applies to both incoherent and coherent errors, except that in the case of coherent errors, the fluctuation around the average is greater than in the case of incoherent errors. Other fidelity metrics may be used in addition or alternatively. By estimating the fidelity of the two-qubit gate as a function of circuit depth, the data processing module 114 can further determine a measure of per-cycle error by fitting the fidelity as a function of circuit depth to an exponential.

[0051] The data processing module 114 is further configured to use the estimated fidelity of the two-qubit gate to determine adjusted control parameters θ′, φ′ of the control model U specified by the input data 106. For example, the control parameters θ, φ can be adjusted to minimize the error estimated by the applied benchmarking technique, i.e., the control model U(θ, φ) is “fitted” to the benchmarking data to maximize the correspondence between the control model and the data.

[0052] Classical processor 102 provides output data representing the adjusted control model U(θ′, φ′). In some implementations, an outer loop can be executed to seek optimal values ​​for the control parameters to further improve the performance of quantum computing hardware 104, i.e., the method can be iterated. System 100 can use the adjusted control model U(θ′, φ′) to execute two-qubit quantum gates in future applications, for example, as part of a quantum computation performed by quantum computing hardware 104.

[0053] Figure 2A An example of partitioning an initial quantum circuit 200 into multiple layers 200a-200d that can be implemented in parallel is illustrated. Example initial quantum circuit 200 operates on a square array of qubits, such as qubit 202 (although it will be appreciated that other array shapes may also be used). Example initial quantum circuit 200 includes multiple instances of two-qubit gates configured to operate on nearest-neighbor qubit pairs, such as two-qubit gate 204. Each adjacent qubit pair in the square array is operated on by a corresponding two-qubit gate. Benchmarking each of the two-qubit gates shown in circuit 200 individually and sequentially is computationally expensive and scales linearly with the system size.

[0054] Example initial quantum circuit 200 can be divided into multiple layers, four layers in this example, of instances of two-qubit gates, where the instances of two-qubit gates in corresponding layers can be implemented in parallel. For example, layers 200a-200d each include a corresponding subset of the multiple instances of two-qubit gates included in example initial quantum circuit 200. Because each qubit in each layer 200a-200d is operated by only one two-qubit gate, the two-qubit gates in each layer 200a-200d can be implemented in parallel. Therefore, benchmarking of each two-qubit gate shown in circuit 200 can be performed in groups and in constant time, independent of system size.

[0055] Figure 2B The diagram shows Figure 2A200d. Each benchmarking quantum circuit 206a-206d includes d periods of quantum gates, where each period includes a layer of randomly sampled single-qubit gates followed by a corresponding partitioned layer of two-qubit gates. For example, benchmarking circuit 206a includes d periods of quantum gates, where each period includes a layer of randomly sampled single-qubit gates, such as layer 208, followed by a corresponding partitioned layer of two-qubit gates, such as Figure 2A Benchmarking circuit 206c includes d cycles of quantum gates, where each cycle includes a layer of randomly sampled single-qubit gates, such as layer 210 (which differs from layer 208 in that each layer of single-qubit gates is constructed using a separate random sampling), followed by a corresponding partitioned layer of two-qubit gates, such as Figure 2A layer 200c, and so on.

[0056] Hardware Programming

[0057] Figure 3 is a flow chart of an example process 300 for adjusting a control model for implementing a two-qubit quantum gate. For convenience, process 300 will be described as being performed by a system of one or more classical computing devices and quantum computing devices located in one or more locations. For example, a system appropriately programmed according to the present specification Figure 1 The system 100 is capable of performing the process 300 .

[0058] The system defines a control model for implementing a two-qubit quantum gate (step 302). For example, the system can define an approximate control model for implementing a two-qubit quantum gate after running a basic calibration operation.

[0059] The system adjusts the control model to implement the two-qubit gate. Adjusting the control model can include the following steps:

[0060] The system defines an initial quantum circuit that is configured to operate on a 2D array of qubits (step 304). The initial quantum circuit includes multiple instances of a two-qubit gate, where each instance of the two-qubit gate performs the same operation on a corresponding adjacent pair of qubits in the 2D array of qubits. In some implementations, the multiple instances of the two-qubit gate operate on all adjacent pairs of qubits in the 2D array of qubits, as described above with reference to Figure 2A Shown and described.

[0061] The system divides the initial quantum circuit into multiple layers of instances of the two-qubit gate, wherein the instances of the two-qubit gate in the corresponding layers can be implemented in parallel (step 306). The number of layers into which the initial quantum circuit is divided depends on the qubit array. For example, in a square array of qubits, the initial quantum circuit can be divided into four layers of instances of the two-qubit gate, as described above with reference to Figure 2B shown.

[0062] The system performs a separate benchmark analysis for each layer of instances of two-qubit gates. For each layer of instances of two-qubit gates, the system constructs a benchmark analysis circuit for the layer (step 308). The benchmark analysis circuit for the layer includes one or more cycles of quantum gates. Each cycle includes a layer of instances of two-qubit gates and multiple single-qubit gates, where each single-qubit gate corresponds to a corresponding qubit in the 2D qubit array. To construct the benchmark analysis circuit for the layer of two-qubit gates, the system selects a circuit depth d for the benchmark analysis circuit and allocates d clock cycles of the quantum gate to the 2D array of qubits. In some implementations, the system selects multiple circuit depths and constructs multiple benchmark analysis circuits corresponding to the multiple circuit depths.

[0063] To distribute the clock cycles of the quantum gates to the 2D array of qubits, the system randomly samples multiple single-qubit quantum gates from a predetermined set of single-qubit quantum gates. For example, the system can randomly sample a number of single-qubit quantum gates from a set that includes The method comprises randomly sampling single-qubit quantum gates from a quantum gate set of T quantum gates. Each randomly sampled single-qubit quantum gate corresponds to a corresponding qubit in the 2D array of qubits, and the number of randomly sampled single-qubit quantum gates may be equal to the number of qubits in the 2D array, i.e., a corresponding randomly sampled single-qubit quantum gate is assigned to each qubit in the 2D array of qubits.

[0064] In some implementations, the system can implement one or more rules for assigning randomly sampled single-qubit quantum gates to a 2D array of qubits. For example, the system can implement a rule whereby any single-qubit quantum gate assigned to a qubit q in the 2D array in a current clock cycle should be different from a single-qubit quantum gate assigned to a qubit q in the 2D array in a previous cycle.

[0065] The system then assigns a randomly sampled plurality of single-qubit quantum gates to corresponding qubits in the 2D array of qubits and assigns two-qubit gates in the layer of two-qubit gates to corresponding nearest-neighbor qubit pairs in the 2D array of qubits. A square array of qubits and an example benchmark circuit with a circuit depth d are illustrated above with reference to FIG2 .

[0066] The system implements the constructed benchmark analysis circuit to obtain experimental benchmark analysis data (step 310). In order to implement each constructed benchmark analysis circuit, the system is in the initial state Initialize each qubit in the 2D array of qubits, apply the constructed benchmarking circuit to the initialized qubit in the 2D array of qubits, and measure each qubit in the 2D array of qubits to obtain measurement data for each qubit. In some implementations, the system may also apply a Hadamard gate to each qubit after initializing the qubits in the 2D array of qubits in the initial state and before applying the constructed benchmarking circuit. Because instances of the two-qubit gate in each of the one or more cycles included in the benchmarking circuit can be implemented in parallel, as described above with reference to step 304, applying the constructed benchmarking circuit to the initialized qubit in the 2D array of qubits includes applying instances of the two-qubit gate in each of the one or more cycles included in the benchmarking circuit in parallel. Because the qubits are divided into pairs, the simulation cost is linear in the depth of the circuit.

[0067] The system then extracts experimental benchmark analysis data from the measurement data for each qubit. For example, the system can process the received measurement data (including data corresponding to the entire multi-qubit Hilbert space) to extract data for qubit pairs, such as data corresponding to a collection of two-qubit Hilbert spaces, where the two-qubit Hilbert spaces can be analyzed independently.

[0068] The system uses the generated experimental benchmarking data to adjust control parameters of the control model to implement the two-qubit quantum gate (step 312). For example, the system can classically simulate each constructed benchmark circuit to obtain classical benchmarking data representing the output distribution of an ideal implementation of the constructed benchmark circuit. The system can then compare the classical benchmarking data with the experimental benchmarking data. For example, the system can apply a cross-entropy benchmarking technique to estimate the fidelity of the implementation of the constructed benchmark circuit. In an implementation in which the system constructs multiple benchmarking circuits corresponding to multiple circuit depths, the system can estimate the fidelity as a function of the circuit depth and determine a measure of per-cycle error by fitting the fidelity as a function of the circuit depth to an exponential.

[0069] The system can then use the estimated fidelity to adjust the control parameters of the control model used to implement the two-qubit quantum gate to improve the fidelity of the two-qubit quantum gate implementation. The system can use the adjusted control model to implement two-qubit quantum gates with higher fidelity in future quantum computing.

[0070] As already described in this specification, operating a single two-qubit gate in isolation is different from operating it in the context of a complex algorithm on a large device because non-idealities such as crosstalk and unwanted interactions affect the implementation of the two-qubit gate. Figure 4A An example graph 400 illustrates the difference in gate behavior between individual and parallel operations due to such control crosstalk and stray qubit-qubit interactions. Curve 400 shows the difference in gate behavior between individual and parallel operations due to such control crosstalk and stray qubit-qubit interactions. Figure 3 The optimization benchmark analyzes how the error approaches the purity limit using both isolated and parallel experiments performed by the example process 300. Parallel operation increases the error by approximately 0.003. This increase is primarily due to purity error, which can arise from unintended interactions with other qubits, while system-scale coherent errors appear as incoherent errors when focusing on individual pairs. Figure 3 The unitary obtained in the implementation of the example process 300 of is slightly different from the isolated case - this is achieved by applying the unitary from the isolated optimization to the unitary from Figure 3 The data from the parallel experiments are shown, which increases the error.

[0071] Figure 4B Shown according to Figure 3 An example graph 450 of the differences in unitary model parameters between isolated experiments and unitary units obtained in parallel experiments implemented using the example process 300 is shown. Curve 450 shows a major change in the single-qubit phase Δ. This demonstrates that most of the additive effects of parallel operation at the single-qubit level can be accounted for and indicates that in these particular experiments, there was no excessive spurious entanglement.

[0072] Both curves 400 and 450 illustrate that gate and qubit errors are different for isolated qubits compared to interacting qubits in a 2D array, and illustrate how a system implementing the techniques described in this specification can more accurately determine the optimal parameters for implementing a target multi-qubit quantum gate on multiple qubits in a large device.

[0073] The digital and / or quantum subject matter and implementation of digital functional operations and quantum operations described in this specification can be implemented in digital electronic circuits, suitable quantum circuits, or more generally, in quantum computing systems, in tangibly embodied digital and / or quantum computer software or firmware, in digital and / or quantum computer hardware, in systems including the structures disclosed in this specification and their structural equivalents, or in a combination of one or more thereof. The term "quantum computing system" may include, but is not limited to, a quantum computer, a quantum information processing system, a quantum cryptography system, or a quantum simulator.

[0074] Implementations of the digital and / or quantum subject matter described in this specification can be implemented as one or more digital and / or quantum computer programs, i.e., one or more modules of digital and / or quantum computer program instructions encoded on a tangible, non-transitory storage medium for execution by a data processing device or to control the operation of the data processing device. The digital and / or quantum computer storage medium can be a machine-readable storage device, a machine-readable storage substrate, a random or serial access storage device, one or more qubits, or a combination of one or more thereof. Alternatively or additionally, the program instructions can be encoded on an artificially generated propagated signal that can encode digital and / or quantum information, such as a machine-generated electrical, optical, or electromagnetic signal, the signal being generated to encode digital and / or quantum information for transmission to a suitable receiver device for execution by the data processing device.

[0075] The terms quantum information and quantum data refer to information or data carried, held, or stored by a quantum system, where the smallest non-trivial system is a qubit, a system that defines a unit of quantum information. It should be understood that the term "qubit" includes all quantum systems that can be appropriately approximated as a two-level system in the corresponding context. Such quantum systems can include multi-level systems, for example, having two or more energy levels. For example, such systems can include atoms, electrons, photons, ions, or superconducting qubits. In many implementations, the computational basis states are identified by the ground state and the first excited state, however, it should be understood that other arrangements in which computational states are identified by higher-level excited states are also possible.

[0076] The term "data processing apparatus" refers to digital and / or quantum data processing hardware and encompasses all types of equipment, devices, and machines for processing digital and / or quantum data, including, for example, programmable digital processors, programmable quantum processors, digital computers, quantum computers, multiple digital and quantum processors or computers, and combinations thereof. The apparatus can also be or further include specialized logic circuitry, such as an FPGA (field programmable gate array), an ASIC (application-specific integrated circuit), or a quantum simulator, i.e., a quantum data processing apparatus designed to simulate or generate information about a specific quantum system. Specifically, a quantum simulator is a special-purpose quantum computer that lacks the ability to perform general-purpose quantum computations. In addition to the hardware, the apparatus can optionally include code that creates an execution environment for digital and / or quantum computer programs, such as code constituting processor firmware, a protocol stack, a database management system, an operating system, or a combination of one or more of these.

[0077] A digital computer program, which may also be referred to or described as a program, software, software application, module, software module, script, or code, can be written in any form of programming language, including compiled or interpreted languages, or declarative or procedural languages, and it can be deployed in any form, including as a stand-alone program or as a module, component, subroutine, or other unit suitable for use in a digital computing environment. A quantum computer program, which may also be referred to or described as a program, software, software application, module, software module, script, or code, can be written in any form of programming language, including compiled or interpreted languages, or declarative or procedural languages, and translated into a suitable quantum programming language, or can be written in a quantum programming language, such as QCL or Quipper.

[0078] A digital and / or quantum computer program can, but need not, correspond to a file in a file system. The program can be stored in a portion of a file that stores other programs or data, such as one or more scripts stored in a markup language document, a single file dedicated to the program in question, or multiple collaborative files, such as a file storing one or more modules, subroutines, or code portions. The digital and / or quantum computer program can be deployed to be executed on a single quantum computer or on multiple digital and / or quantum computers located at one location or distributed across multiple locations and interconnected by a digital and / or quantum data communication network. A quantum data communication network is understood to be a network that can use quantum systems, such as qubits, to send quantum data. Typically, a digital data communication network cannot send quantum data, but a quantum data communication network can send both quantum data and digital data.

[0079] The processes and logic flows described in this specification can be performed by one or more programmable digital and / or quantum computers, operating, where appropriate, with one or more digital and / or quantum processors, executing one or more digital and / or quantum computer programs to perform functions by operating on input data and generating output. The processes and logic flows can also be performed by dedicated logic circuits, such as FPGAs and ASICs, or quantum simulators, and the apparatus can also be implemented as dedicated logic circuits, or by a combination of dedicated logic circuits or quantum simulators and one or more programmed digital and / or quantum computers.

[0080] For a system comprised of one or more digital and / or quantum computers, being "configured to" perform a particular operation or action means that the system has installed thereon software, firmware, hardware, or a combination thereof that, when operated, causes the system to perform those operations or actions. For one or more digital and / or quantum computer programs configured to perform a particular operation or action, it means that the one or more programs include instructions that, when executed by a digital and / or quantum data processing device, cause the device to perform those operations or actions. A quantum computer can receive instructions from a digital computer that, when executed by the quantum computing device, cause the device to perform the operations or actions.

[0081] A digital and / or quantum computer suitable for executing a digital and / or quantum computer program can be based on a general-purpose or a dedicated digital and / or quantum processor, or both, or any other type of central digital and / or quantum processing unit. Typically, the central digital and / or quantum processing unit will receive instructions and digital and / or quantum data from a read-only memory, a random access memory, or a quantum system suitable for sending quantum data, such as photons, or a combination thereof.

[0082] Elements of a digital and / or quantum computer include a central processing unit for executing or performing instructions and one or more memory devices for storing instructions and digital, numerical, and / or quantum data. The central processing unit and memory can be supplemented by or incorporated into dedicated logic circuits or quantum simulators. Typically, a digital and / or quantum computer will also include or be operatively coupled to one or more mass storage devices for storing digital and / or quantum data, such as magnetic disks, magneto-optical disks, optical disks, or quantum systems suitable for storing quantum information, to receive digital and / or quantum data from or transmit digital and / or quantum data to, or both. However, a digital and / or quantum computer need not have such devices.

[0083] Digital and / or quantum computer-readable media suitable for storing digital and / or quantum computer program instructions and digital and / or quantum data include all forms of non-volatile digital and / or quantum memory, media, and storage devices, including, for example, semiconductor memory devices such as EPROM, EEPROM, and flash memory devices; magnetic disks, such as internal hard disks or removable disks; magneto-optical disks; CD-ROMs and DVD-ROMs; and quantum systems, such as trapped atoms or electrons. It should be understood that quantum memory is a device capable of storing quantum data for a long time with high fidelity and high efficiency, such as a light-matter interface in which light is used for transmission, and matter for storing and preserving quantum features such as superposition or quantum coherence.

[0084] The control of the various systems or portions thereof described in this specification can be implemented in a digital and / or quantum computer program product that includes instructions stored on one or more non-transitory machine-readable storage media and executable on one or more digital and / or quantum processing devices. The systems or portions thereof described in this specification can each be implemented as an apparatus, method, or system that may include one or more digital and / or quantum processing devices and memory to store executable instructions to perform the operations described in this specification.

[0085] Although this specification contains many specific implementation details, these should not be interpreted as limitations on the scope of what is claimed, but rather as descriptions of features that are peculiar to a particular implementation. Certain features described in this specification in the context of separate implementations can also be implemented in combination in a single implementation. Conversely, various features described in the context of a single implementation can also be implemented individually or in any suitable sub-combination in multiple implementations. In addition, although features may be described above as working in certain combinations and even initially claimed, in some cases, one or more features in a claimed combination can be deleted from that combination, and a claimed combination can refer to a variant of a sub-combination or a sub-combination.

[0086] Similarly, although operations are described in a particular order in the accompanying drawings, this should not be understood as requiring that the operations be performed in the particular order shown or in sequential order, or that all illustrated operations be performed, in order to achieve the desired results. In some cases, multitasking and parallel processing may be advantageous. Furthermore, the separation of various system modules and components in the above-described implementations should not be understood as requiring such separation in all implementations, and it should be understood that the described program components and systems can generally be integrated into a single software product or packaged into multiple software products.

[0087] Particular implementations of the subject matter have been described. Other implementations are within the scope of the following claims. For example, the actions recited in the claims can be performed in a different order and still achieve the desired results. As an example, the processes depicted in the accompanying figures do not necessarily require the particular order shown or sequential order to achieve the desired results. In certain circumstances, multitasking and parallel processing can be advantageous.

Claims

1. A method implemented by one or more classical processors and one or more quantum computing systems, the method comprising: One or more classical processors define a control model for implementing a two-qubit quantum gate; A control model for implementing a two-qubit quantum gate is adapted by one or more classical processors and one or more quantum computing systems, the adapting comprising: defining, by one or more classical processors, an initial quantum circuit configured to operate on a qubit array, wherein the initial quantum circuit comprises a plurality of instances of a two-qubit gate, wherein each instance of the two-qubit gate performs the same operation on a corresponding adjacent pair of qubits in the qubit array; Partitioning the initial quantum circuit into multiple layers of instances of the two-qubit gate by one or more classical processors, wherein the instances of the two-qubit gate in respective layers can be implemented in parallel; For each layer in the multiple layers of instances of two-qubit gates: constructing, by one or more classical processors, one or more benchmarking circuits for the layer, wherein each benchmarking circuit of the layer comprises one or more cycles of quantum gates, each cycle comprising: a layer of instances of two-qubit gates and a plurality of single-qubit gates, wherein each single-qubit gate in the plurality of single-qubit gates corresponds to a respective qubit in the qubit array; Implementing the constructed benchmarking circuit using one or more quantum computing systems to obtain experimental benchmarking data; estimating the fidelity of a two-qubit quantum gate using experimental benchmarking data by one or more classical processors; and Control parameters of a control model for implementing the two-qubit quantum gate are adjusted by one or more classical processors based on the estimated fidelity to increase the fidelity of the implementation of the two-qubit quantum gate.

2. The method according to claim 1, wherein Constructing a benchmarking circuit for a layer of instances of a two-qubit gate involves assigning one or more clock cycles of the quantum gate to the qubit array and, for each clock cycle, including: randomly sampling a plurality of single-qubit quantum gates from a predetermined set of single-qubit quantum gates, wherein each randomly sampled single-qubit quantum gate corresponds to a respective qubit in the qubit array; assigning a randomly sampled plurality of single-qubit quantum gates to corresponding qubits in the qubit array; and Instances of two-qubit gates in the layer are assigned to corresponding nearest-neighbor qubit pairs in the qubit array.

3. The method according to claim 2, wherein: The predetermined set of single-qubit quantum gates includes and T quantum gates, where represents a π / 2 rotation around the X axis, represents a π / 2 rotation about the y-axis, and T represents a non-Clifford diagonal matrix {0,e iπ / 4 }.

4. The method according to claim 2, wherein: Assigning a plurality of randomly sampled single-qubit quantum gates to corresponding qubits in a qubit array comprises: A second single-qubit gate is assigned to qubit q in a current clock cycle, where the second single-qubit gate is different from a first single-qubit gate assigned to qubit q in a previous clock cycle.

5. The method according to claim 1, wherein Constructing one or more benchmarking circuits for the layer includes constructing a plurality of benchmarking circuits having different corresponding circuit depths.

6. The method according to claim 1, wherein Implementing the constructed benchmark circuits to obtain experimental benchmark data includes, for each constructed benchmark circuit: Initializing each qubit in the qubit array in an initial state by one or more quantum computing systems; applying the constructed benchmark analysis circuit to initialized qubits in a qubit array by one or more quantum computing systems, wherein instances of the two-qubit gate in each layer of instances of the two-qubit gate are implemented in parallel; measuring, by one or more quantum computing systems, each qubit in the qubit array to obtain measurement data for each qubit; and Experimental benchmarking data corresponding to a collection of two-qubit Hilbert spaces is extracted from the measurement data by one or more quantum computing systems.

7. The method according to claim 5, further comprising: Before applying the constructed benchmarking circuit to the initialized qubits in the qubit array, a Hadamard gate is applied by one or more quantum computing systems to each qubit in the initial state.

8. The method according to claim 1, wherein Adjusting the control parameters of the control model used to implement a two-qubit quantum gate involves: simulating each constructed benchmark circuit by one or more quantum computing systems to obtain classical benchmark data representing an output distribution of an ideal realization of the constructed benchmark circuit; and Comparing the classical benchmarking data with the experimental benchmarking data by one or more quantum computing systems includes determining a cross-entropy difference between the classical benchmarking data and the experimental benchmarking data, wherein the cross-entropy difference represents the fidelity of an implementation of the constructed benchmarking circuit.

9. The method according to claim 8, further comprising: estimating the fidelity of an implementation of the constructed benchmark circuit by one or more classical processors as a function of circuit depth; as well as A metric of per-cycle error is determined by one or more classical processors by fitting the fidelity of an implementation of a constructed benchmarked circuit as a function of circuit depth to an exponential.

10. The method according to claim 1, wherein The control parameters of the control model include control angles of one or more quantum gates.

11. The method according to claim 1, wherein The qubit array comprises a 2D array, and wherein the multi-layer instance of the two-qubit gate comprises a four-layer instance of the two-qubit gate.

12. A device for quantum computing, comprising: One or more classic processors; as well as Quantum computing hardware, communicating with one or more classical processors, in Quantum computing hardware includes: qubit arrays, and a control device configured to operate the qubit array; The device is configured to perform the method according to any one of claims 1 to 11.

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