Improvements in or relating to quantum computing

Abstract

1. An apparatus comprising a two-dimensional array of quantum gates, wherein a controller is configured to control the two-dimensional array of quantum gates, wherein the controller is configured to control the apparatus to operate as a single machine state to perform a gate operation sequence for all of the quantum gates, the gate operation sequence being selected from a plurality of gate operation sequences, each of the gate operation sequences having a different maximum duration.

Description

[Technical Field]

[0001] The present invention relates to scheduling optimization in quantum computers. [Background technology]

[0002] Generally, unlike so-called "classical computing," quantum computing relies on the quantum mechanical properties of particles or matter to produce or modify data. Data can be represented by quantum bits or "qubits," which are two-state quantum mechanical systems. Unlike classical computing, qubits can be in a superposition of quantum states. Another feature of quantum computing is entanglement between qubits, where the state of one particle or atom is influenced by another particle or atom.

[0003] Quantum mechanical qubits can simultaneously encode information as combinations of zeros and ones. This property enables many complex numerical applications that have traditionally been difficult with classical computers. Examples include artificial intelligence, image processing and recognition, cryptography, or secure communications.

[0004] Within the ionic hyperfine electron states (Zeeman split states) this can be revealed by the use of magnetic fields and different electronic levels used as different qubit states, and electrons moving between levels using microwave radiation or lasers.

[0005] In an ion trap quantum computer, an ion trap is used to control ions used in quantum computing, and surface electrodes are used to generate electric fields to manipulate and trap ions suspended in free space. The surface electrode potential of the ion trap is then controlled by a DAC. State-of-the-art quantum computers use many DACs of the same type, for example, 16-bit DACs with update rates exceeding 1 MHz.

[0006] Ion traps are used to implement gates, which perform quantum operations on trapped qubits. Examples of quantum gates are the Pauli gate, the rotation gate (e.g., with any angle), the swap gate, and the CNOT gate. Some, such as the phase (Z) gate, are single-qubit gates, while others, such as the CNOT and swap, are two-qubit gates.

[0007] When executing a quantum algorithm, it is preferable to minimize the delay between quantum operations. Ideally, gate operations are performed simultaneously on all qubits. However, different gate operations have different durations. In general, two-qubit gates take significantly longer than single-qubit gates. In turn, three-qubit gates take longer than two-qubit gates.

[0008] The different durations of the qubit gates can create long wait times while the longer duration gate operations are completed, which further significantly increases the runtime of the algorithm and thus reduces the overall performance of the device. Summary of the Invention [Problem to be solved by the invention]

[0009] The objective of the present invention is to minimize the runtime in quantum algorithms. [Means for solving the problem]

[0010] According to the present invention, there is provided an apparatus comprising a plurality of quantum processors and a controller configured to control the plurality of quantum processors, wherein the controller is configured to control the plurality of quantum processors to perform process operation sequences, the process operation sequences being selected from a plurality of process operation sequences, each process operation sequence comprising a plurality of phases, each phase having a phase duration, and the controller is configured to control the apparatus to operate as a single state machine such that all quantum processors controlled by the controller perform the same phase of the same process operation sequence at the same time. [Brief explanation of the drawings]

[0011] [Figure 1] FIG. 1 shows an array of electrodes in a quantum processor for use in connection with the present invention. [Figure 2] Figure 2 shows a two-dimensional array of quantum processors. [Figure 3] FIG. 3 shows a typical process operation sequence. [Figure 4] FIG. 4 shows a sequence of several process operations. DETAILED DESCRIPTION OF THE INVENTION

[0012] A controller may comprise multiple sub-controllers, each controlling multiple quantum processors. In this way, no fields or signals controlled by other / different controllers coherently affect the qubits in a quantum processor. Therefore, no fields or signals coherently affect the qubits in a quantum processor that are not controlled by one of the controllers or sub-controllers. All fields coherently affecting the qubits in a quantum processor are controlled by the controller or sub-controller. All control signals from each of the sub-controllers control all quantum processors to perform the same function simultaneously.

[0013] For example, all quantum processors on a single plate or within a single computer may simultaneously execute the same phase of the same process operation sequence.

[0014] There are multiple quantum processors, and may be at least 10, at least 100, or more than 1000.

[0015] During each phase, all quantum processors perform the same function. Different functions include mapping, cooling, shuttling, single-qubit gate operations, two-qubit gate operations, and measurement. Because multiple gate operations are treated as the same function, different quantum processors may perform different gate operations during the same phase. A single-qubit gate operation may be any single-qubit gate operation. A two-qubit gate operation may be any gate operation, including two-qubit or single-qubit gates.

[0016] Qubits scheduled for gate operations that can be completed according to the selected process operation sequence undergo the process operation sequence, while qubits scheduled for process operation sequences that cannot be completed within the selected process operation sequence are not executed. Thus, the quantum processor either executes the selected process operation sequence or does not perform a process operation. Not performing a process operation includes performing an identification operation.

[0017] By having multiple process operation sequences, the utility of the device can be optimized. For example, if only a few qubits in the system are scheduled for long gate operations, while the rest are scheduled for short gate operations, a shorter process operation sequence may be selected. In the next iteration, if more qubits can be scheduled for longer gate operations, a longer gate operation sequence may be selected. Thus, redundancy in the device is minimized.

[0018] The process operation sequences may include different phases, each having a phase duration.

[0019] All processors perform either the same sequence of process operations or discrimination operations during the same period. Discrimination operations are operations that do not change the state of the qubit. For example, this can include spin echo and collaborative cooling, and no discrimination operations.

[0020] Each process operation sequence may include a shuttling phase, an observation phase, a gating phase, and a measurement phase, and the controller is configured to control each process to simultaneously execute the same respective phase on each processor. Each phase of each process operation sequence may have a maximum duration.

[0021] A process operation sequence can include any qubit gating operation completed within the maximum gating period of the process operation sequence.

[0022] The first gate operation sequence includes only single-qubit gate operations, and the second gate operation sequence includes two-qubit operations. This groups longer gate operations together, since two-qubit gate operations are generally longer than single-qubit gate operations. The second gate operation sequence can include both two-qubit and single-qubit gate operations.

[0023] The first gate operation sequence can include any single-qubit gate operation completed within the maximum gate operation period.

[0024] Each quantum processor may include a plurality of electrodes and a DAC, each electrode independently controlled by a DAC. Each processor may include an ion trap, which may be a surface ion trap. The multiple quantum processors may include a two-dimensional array of quantum processors.

[0025] According to the present invention, there is provided a quantum computer comprising the above-described device.

[0026] According to the present invention, there is provided a method of operating a quantum computer having a plurality of quantum processors and a controller, the method including selecting a single process operation sequence from a plurality of process operation sequences, each process operation sequence including a plurality of phases, each phase having a phase duration, and simultaneously executing the same phase of the same process gate operation sequence on all processors such that the quantum computer operates as a single state machine.

[0027] Referring to Figure 1, there is an exemplary arrangement of electrodes in a quantum processor associated with the present invention. Figure 1 shows an x-junction device 12 in a trap ion quantum computer 10. The x-junction 12 comprises a plurality of electrodes 22 configured to trap ions in a region of the x-junction device 12. Each electrode 22 is driven by a DAC to perform a function of the region of the x-junction device 12. The x-junction device 12 is divided into regions. The regions of the x-junction device 12 can be divided into crystal operations 14, junction shuttling 16, logic regions / gate zones 18, and linear shuttling 20 depending on the function performed in each region.

[0028] The x-junction is divided into four sections: the north section (above center as shown in FIG. 1), the east section (right of center as shown in FIG. 1), the south section (below center as shown in FIG. 1), and the west section (left of center as shown in FIG. 1). If there are no ions in a section, no signal may be applied to any of the electrodes. Alternatively, there may be a signal, but no change in signal. Similarly, if ions are shuttling from left to center, no signal may be applied to the electrodes in the northeast or south sections.

[0029] A quantum computer typically has multiple quantum processors (hereafter referred to as "processors"). In the implementation shown in FIG. 2, there is a two-dimensional array of processors 25 and controller 26. Each processor has a zone in which a gating operation can be performed. Examples of gating operations are Pauli gates, rotate gates, swap gates, and CNOT gates. Qubits are shuttled between processors as described above. A gating operation then occurs before the qubits are shuttled between processors again. In accordance with the present invention, controller 26 controls all processors in the device to simultaneously perform the same function, such that all processors shuttling, performing a gating operation, or measuring simultaneously. The gating operation performed by each individual processor at a particular time can vary, so that some may perform a first gating operation and others a second gating operation.

[0030] While some or most of the processors are simultaneously performing the same functions, some processors perform discrimination operations, which are operations that maintain the state of the qubits, and may include no operation at all, or cooling or spin echoes for noise cancellation.

[0031] Typically, there are multiple process operation sequences in which qubits are first shuttled into place. To shuttling one or more qubits, the qubits are mapped. A typical process operation sequence includes multiple phases, such as a mapping phase 31, a shuttling phase 32, a gating phase 33, and then a measurement phase 34, as shown in process operation sequence 30 of FIG. 3. According to the present invention, each of these phases has a different duration for each of the process operation sequences.

[0032] All processors 25 in the quantum computer execute the same process operation sequence 30, or identification operation (including no function, cooling or spin echo cancellation, or an identification gate operation). For all processors 25 executing the process operation sequence 30 (but not the identification operation), all processors execute the shuttling function during an initial shuttling phase 31. Some qubits may be fully shut down before the end of the shuttling phase, but each processor does not begin observation. Once the mapping phase is complete, all processors 25 then begin the shuttling phase 32, during which qubits are shuttled. Some qubits do not need to be shut down, and therefore each processor executes an identification operation. Again, observation of some qubits may be completed before the end of the mapping phase, but the processor does not move on to a gate operation. If a processor completes a phase before the phase period is complete, it may execute the identification operation for the remaining duration of that phase period. Once the observation period is complete, all processors begin the gate operation phase 33. Different processors may perform different gating operations during the gating phase, but they are each performing a gating or identification operation. For example, some may perform rotations around the x-axis and some around the y-axis, but they all perform a gating function. Again, some gating operations complete sooner than others, but no processor begins measuring before the gating phase period is complete. Then, all processors begin the measurement phase.

[0033] In this way, each phase has a fixed maximum duration. An example sequence is: Shuttling phase, mapping phase, gate phase, Gate Phase, Mapping Phase, Shuttling Phase Shuttling phase, measurement phase, Shuttling phase, mapping phase, gate phase, mapping phase, measurement phase, Measurement phase, Shuttling phase, Mapping phase, Gate phase Mapping phase, cooling phase, gate phase, measurement phase, Measurement phase, shuttling phase, cooling phase, mapping phase, single qubit gate phase, two qubit gate phase, single qubit gate phase.

[0034] As will be appreciated, this is not an exclusive list of sequences and many further variations are possible.

[0035] As noted above, each phase has a maximum duration after which the next phase begins. For example, if a function (e.g., a shuttling or gate operation) is incomplete, subsequent functions in the process operation sequence are not performed for that process / qubit, and the process / gate begins again during the next iteration of the process operation sequence.

[0036] FIG. 4 shows multiple process operation sequences 30, 40, 50, and 60. As can be seen, they each have a different duration, and each phase within each has a different duration. In this example, each sequence has a shuttling phase 31, 41, 51, or 61, a mapping phase 32, 42, 52, or 62, a gate operation phase 33, 43, 53, or 63, and a measurement phase 34, 44, 54, or 64. Sequences 30 and 40 are both single-qubit gate operation sequences, but have different durations for the different phases. In particular, gate operation phase 43 is longer than gate operation phase 33, so gate operation sequence 40 can be used if a gate of longer duration is used. Gate operation sequence 50 is a two-qubit gate operation sequence with a longer duration for the gate operation phase because two-qubit gate operations are generally longer than single-bit gate operations. Gate operation sequence 60 is a three-qubit gate operation sequence that still has a longer gate operation phase.

[0037] Each of the different gate operation sequences has a different gate operation phase duration. The controller 26 selects a gate operation sequence, and all gates in the two-dimensional array of gates perform that gate operation sequence (or identification operation). In this way, the device operates as a single state machine because all gates are simultaneously performing the same function. A qubit scheduled to undergo a gate operation that takes longer than the gate operations in the selected sequence, or whose shuttling (or other) phase is too short, is held until the next process operation sequence, which may have a longer gate operation phase or a longer shuttling phase, after which it can complete the gate operation.

[0038] The duration of the phases in each process operation sequence is set, but is set to a period when the majority of gates have completed their required operations. For example, shuttling between processors may take a variable amount of time (based primarily on the distance traveled by the qubits). The shuttling phase of each process operation sequence has a fixed period during which the qubits are shuttled. Even if some qubits are incompletely shuttled at the end of the shuttling phase of a process operation sequence, the process operation sequence proceeds, and the processor with the incompletely shut qubit simply performs the identification operation. Shuttling is then completed during the next process operation sequence. While this is described with reference to shuttling, it may apply to any phase.

[0039] If the gate operations scheduled for most qubits are single gate operations, a gate operation sequence such as 30 can be selected. Some of the qubits may be scheduled for two-qubit gate operations, but those gate operations can wait until the next iteration. This avoids long wait times while several qubits undergo two-qubit gate operations. In the next iteration or gate operation sequence, a higher percentage of qubits may be scheduled to undergo two-qubit gate operations, and thus gate operation sequence 50 may be selected. During gate operation 50, it may be a completed two-qubit gate operation, although in an alternative arrangement, a single-qubit gate operation may also be completed. In fact, any gate operation that can be completed in a shorter period than the gate operation phase may be completed. During subsequent iterations, a shorter single-qubit gate operation sequence may be selected. However, the order in which the gate operations are performed should satisfy the gate transformation rules.

[0040] Therefore, the controller 26 selects the gate operation sequence to optimize overall system performance and reduce latency.

[0041] Although a sequence of shuttling, observing, gating, and measuring is illustrated here, other sequences can alternatively be used, one of which is shown in FIG. 5 with an additional counting phase 75.

[0042] During a selected gating sequence, all processors are either executing a gating sequence or an identification operation. A processor executing a gating sequence may not execute all phases of the sequence. For example, if a particular processor does not require shuttling, the processor may not execute that phase in the sequence, but will execute a subsequent phase when it is initiated.

[0043] Any two-qubit interaction can be decomposed into a series of one- and two-qubit gates. The figure below illustrates the series of single-qubit and two-qubit gates into which any two-qubit interaction can be decomposed, where Ry(φ) is the rotation of φ about the y-axis, Rx(φ) is the rotation of φ about the x-axis, and MS is a Molmer-Sorensen gate. JPEG2025535171000002.jpg28170

[0044] Thus, it is clear that in a sequence there are often many more single-qubit gate operations than two-qubit gate operations. Rather than allocating enough gate operation time within every gate operation cycle for scheduling purposes, it is often worthwhile to perform many more of the longer two-qubit gate operations.

[0045] As a further example, a CNOT gate can be decomposed into a series of Rx, Rx and Molmer-Sorensen gates as shown below: JPEG2025535171000003.jpg33170

[0046] The process operation sequences in Figure 4 are described as single-qubit, two-qubit, or three-qubit process operation sequences. However, they may alternatively be defined by the maximum duration of a gate operation phase rather than by the number of qubits in the gate operation. Thus, in the first process operation sequence 30, any gate operation that can be completed within gate operation phase 33 may be used. In the second process operation sequence 40, any gate operation that can be completed within gate operation phase 43 may be used. In the third gate operation sequence, any gate operation (whether single-qubit, two-qubit, or three-qubit) that can be completed in gate operation phase 53 may be completed.

[0047] According to the present invention, the plurality of process operation sequences each have a plurality of phases, each phase having a phase duration.

[0048] The controller controls all quantum processors controlled by the controller to simultaneously execute the same phase of the same sequence of process operations, hence operating as a single state machine.

[0049] All control signals from the controller control all quantum processors controlled by the controller to perform the same phase of the same process operation sequence, i.e., there are no control signals from the controller-controlled quantum processors to perform different phases or operations.

[0050] The control signals may control electromagnetic fields, e.g., magnetic fields or radio waves, all of which are involved in the same phase of the same process operation sequence. There may be individual fields for individual quantum processors and / or there may be a global field. However, all control signals from a controller controlling a quantum processor generate signals or fields to perform the same phase of the same process operation sequence on the quantum processor. As an example, all electromagnetic fields generated by control signals from a controller to a quantum processor involve the same phase of the same process operation sequence.

[0051] Thus, all fields (controlled by the controller) that affect the quantum processor control the quantum processor to perform the same phase of the same process operation sequence, i.e., no control signal coherently affects qubits to perform anything other than the same phase of the same process operation sequence.

[0052] As used herein, "and / or" should be taken as a specific disclosure of each of the two specified features or components with or without the other. For example, "A and / or B" should be taken as a specific disclosure of (i) A, (ii) B, and (iii) each of A and B, as if each were individually set forth herein.

[0053] Unless the context dictates otherwise, the above feature descriptions and definitions are not limited to any particular aspect or embodiment of the invention, but apply equally to all aspects and embodiments described.

[0054] Those skilled in the art will further appreciate that although the present invention has been described by way of example with reference to certain embodiments, it is not limited to the disclosed embodiments and alternative embodiments may be constructed without departing from the scope of the invention as defined in the appended claims.

Claims

1. 1. An apparatus comprising: a plurality of quantum processors; and a controller configured to control the plurality of quantum processors, the controller configured to control the plurality of quantum processors to perform a process operation sequence, the process operation sequence being selected from a plurality of process operation sequences, each process operation sequence including a plurality of phases, each phase having a phase duration, the controller configured to control the apparatus to operate as a single state machine such that all quantum processors controlled by the controller simultaneously perform the same phase of the same process operation sequence.

2. The apparatus of claim 1 , wherein each of the plurality of process operation sequences has a different process operation sequence duration.

3. 3. The apparatus of claim 1, wherein the different gate operations comprise a single function.

4. The apparatus of claim 1 , wherein the controller is configured to control all of the quantum processors to perform either the same sequence of process operations or identification operations during the same period of time.

5. The apparatus of claim 2 , wherein the discrimination operation comprises one of a spin echo, co-cooling, a discrimination gate operation, and no operation.

6. The apparatus of any one of claims 1 to 5, wherein the phase duration is the maximum period during which each quantum processor executes the phase function.

7. The apparatus of any one of claims 1 to 6, wherein each process operation sequence includes a mapping phase and a gating phase.

8. 8. The apparatus of claim 1, wherein each process operation sequence includes a mapping phase, a shuttling phase, a gating phase, and a measurement phase, and wherein the controller is configured to control each process to perform the same respective phase simultaneously on each quantum processor.

9. 9. The apparatus of claim 1, wherein a process operation sequence includes any qubit gating operation completed within a maximum gating operation duration of the process operation sequence.

10. 10. The apparatus of claim 1, wherein the first sequence of process operations includes only single-qubit gate operations, and the second sequence of gate operations includes two-qubit and single-qubit gate operations.

11. 10. The apparatus of claim 9, wherein the first process operation sequence can include any single-qubit gate operation completed within the maximum gate operation period.

12. 12. Apparatus according to any preceding claim, wherein each quantum processor comprises a plurality of electrodes and a DAC, each electrode being independently controlled by the DAC.

13. 13. Apparatus according to any preceding claim, wherein the plurality of quantum processors comprises a two-dimensional array of processors.

14. Apparatus according to any preceding claim, wherein each quantum processor comprises an ion trap.

15. A quantum computer comprising the device according to any one of claims 1 to 14.

16. 1. A method of operating a quantum computer comprising a plurality of quantum processors and a controller, the method comprising: selecting a single process operation sequence from a plurality of process operation sequences, each process operation sequence including a plurality of phases, each phase having a phase duration; generating control signals to simultaneously execute the same phase of the same process gating sequence on all of the processors controlled by the controller to operate as a single state machine.

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