Just-in-time compilation method and device

Abstract

The present invention provides a real-time compilation method and device. The method includes: obtaining multiple instruction information; generating and storing a first coded instruction of at least one first instruction information, wherein the coding length in the first instruction information is fixed; if there is at least one second instruction information, the second instruction information is added to a jump list, and the jump list is compiled and linked to determine the coding length of the second instruction information, wherein the coding length of the second instruction information is not fixed; in the process of sequentially executing multiple instruction information, when the instruction information to be executed is the first instruction information, the first coded instruction of the first instruction information is transmitted to the memory space for execution; when the instruction information to be executed is the second instruction information, the second coded instruction is generated according to the coding length of the second instruction information, and transmitted to the memory space for execution. The embodiment of the present invention can reduce the delay of executing instructions.

Description

Technical Field

[0001] The present invention relates to the field of computer technology, and in particular to a just-in-time compilation method and device. Background Art

[0002] coreCLR (core common language running) is an open source framework that provides components for the operation process of virtual machines. The virtual machine that runs through the components provided by coreCLR can be called a coreCLR virtual machine. coreCLR can run on virtual machines of various operating systems, such as Windows virtual machines, Linux virtual machines, Mac virtual machines, etc. When the coreCLR virtual machine receives instruction information, it uses the JIT (Just In Time) compiler to binary encode the instruction information to obtain the encoded instruction, and executes the encoded instruction immediately after encoding.

[0003] Therefore, how to reduce the delay of executing instructions becomes an urgent problem to be solved. Summary of the invention

[0004] The present invention provides a just-in-time compilation method and device for reducing the delay of executing instructions.

[0005] In a first aspect, the present invention provides a just-in-time compilation method, applied to a coreCLR virtual machine, the method comprising:

[0006] Get multiple instruction information before compiling and linking;

[0007] Generate and store a first encoding instruction of at least one first instruction information among the multiple instruction information, wherein the encoding length of the first instruction information is fixed;

[0008] If there is at least one second instruction information among the multiple instruction information, the second instruction information is added to the jump list, and the jump list is compiled and linked to determine the encoding length of the second instruction information, and the encoding length of the second instruction information is not fixed;

[0009] In the process of sequentially executing the multiple instruction information, when the instruction information to be executed is the first instruction information, the first encoded instruction of the first instruction information is transmitted to the corresponding memory space for execution; if the instruction information to be executed is the second instruction information, a second encoded instruction is generated according to the encoding length of the second instruction information, and the second encoded instruction is transmitted to the corresponding memory space for execution.

[0010] Optionally, the first instruction information does not include a branch jump instruction with an uncertain target address, and the second instruction information includes a branch jump instruction with an uncertain target address.

[0011] Optionally, the method further comprises:

[0012] Before performing the compiling and linking, applying for corresponding memory space according to the length of the first encoding instruction;

[0013] After the second encoding instruction is generated, corresponding memory space is applied for according to the length of the second encoding instruction.

[0014] Optionally, the first instruction information includes: third instruction information containing a function call, fourth instruction information containing an immediate value whose length is greater than or equal to a preset length threshold, and fifth instruction information in the first instruction information except the third instruction information and the fourth instruction information, and the method further includes:

[0015] Determine a structure corresponding to each piece of the instruction information from at least one preset structure, wherein the at least one preset structure includes at least one of the following: a first structure for storing the encoding instruction of the fifth instruction information, a second structure for storing the second instruction information, a third structure for storing the encoding instruction of the third instruction information, and a fourth structure for storing the encoding instruction of the fourth instruction information, wherein the second structure, the third structure, and the fourth structure inherit the first structure;

[0016] The plurality of instruction information are stored in a transmission list in the form of corresponding structures respectively;

[0017] The sequentially executing the plurality of instruction information includes:

[0018] The plurality of instruction information are executed in the order in the issue list.

[0019] Optionally, storing the plurality of instruction information in corresponding structures into a transmission list respectively includes:

[0020] storing at least two associated second instruction information in the same structure into the transmission list, wherein the memory size of the structure is fixed;

[0021] The encoding instructions of at least two associated first instruction information are stored in a transmission list in the same structure.

[0022] Optionally, storing the encoding instructions of at least two associated first instruction information in the same structure into the transmission list includes:

[0023] The encoding instructions of at least two first instruction information for constructing the same immediate value are stored in the issue list in the same structure.

[0024] Optionally, determining the encoding length of the second instruction information includes:

[0025] In the process of traversing the jump list, for each piece of the second instruction information in the jump list, determining the address difference between the second instruction information and the target instruction information to which the second instruction information jumps in the jump list;

[0026] If the address difference is less than or equal to a preset address difference threshold, determining a preset coding length corresponding to the preset address difference threshold as the coding length of the second instruction information;

[0027] If the address difference is greater than a preset address difference threshold, the preset encoding length corresponding to the preset address difference threshold is increased by a preset length as the encoding length of the second instruction information, and the jump list is traversed again after the traversal is completed.

[0028] In a second aspect, the present invention provides an electronic device, comprising:

[0029] Instruction information acquisition module, used to obtain multiple instruction information before compiling and linking;

[0030] A first coding instruction storage module, used for generating and storing a first coding instruction of at least one first instruction information among the plurality of instruction information, wherein the coding length of the first instruction information is fixed;

[0031] A coding length determining module, configured to add the second instruction information to a jump list if there is at least one second instruction information among the plurality of instruction information, and to compile and link the jump list to determine the coding length of the second instruction information, wherein the coding length of the second instruction information is not fixed;

[0032] A coding instruction execution module is used to, during the process of sequentially executing the multiple instruction information, when the instruction information to be executed is the first instruction information, transmit the first coding instruction of the first instruction information to the corresponding memory space for execution; if the instruction information to be executed is the second instruction information, generate a second coding instruction according to the coding length of the second instruction information, and transmit the second coding instruction to the corresponding memory space for execution.

[0033] Optionally, the first instruction information does not include a branch jump instruction with an uncertain target address, and the second instruction information includes a branch jump instruction with an uncertain target address.

[0034] Optionally, the device further comprises:

[0035] A first memory application module, used for applying for corresponding memory space according to the length of the first coding instruction before performing the compiling and linking;

[0036] The second memory application module is used to apply for corresponding memory space according to the length of the second encoding instruction after generating the second encoding instruction.

[0037] Optionally, the first instruction information includes: third instruction information indicating a function call, fourth instruction information indicating an immediate value having a length greater than or equal to a preset length threshold, and fifth instruction information other than the third instruction information and the fourth instruction information in the first instruction information, and the device further includes:

[0038] a structure determination module, used to determine a structure corresponding to each piece of the instruction information from at least one preset structure, wherein the at least one preset structure includes at least one of the following: a first structure for storing the encoding instruction of the fifth instruction information, a second structure for storing the second instruction information, a third structure for storing the encoding instruction of the third instruction information, and a fourth structure for storing the encoding instruction of the fourth instruction information, wherein the second structure, the third structure, and the fourth structure inherit the first structure;

[0039] A structure storage module, used for storing the plurality of instruction information in a transmission list in the form of corresponding structures respectively;

[0040] The coding instruction execution module is also used for:

[0041] The plurality of instruction information are executed in the order in the issue list.

[0042] Optionally, the structure storage module is also used for:

[0043] At least two associated second instruction information are stored in the emission list in the same structure, and the memory size of the structure is fixed; and the encoding instructions of at least two associated first instruction information are stored in the emission list in the same structure.

[0044] Optionally, the structure storage module is also used for:

[0045] The encoding instructions of at least two first instruction information for constructing the same immediate value are stored in the issue list in the same structure.

[0046] Optionally, the coding length determination module is further used for:

[0047] In the process of traversing the jump list, for each piece of the second instruction information in the jump list, determining the address difference between the second instruction information and the target instruction information to which the second instruction information jumps in the jump list;

[0048] If the address difference is less than or equal to a preset address difference threshold, determining a preset coding length corresponding to the preset address difference threshold as the coding length of the second instruction information;

[0049] If the address difference is greater than a preset address difference threshold, the preset encoding length corresponding to the preset address difference threshold is increased by a preset length as the encoding length of the second instruction information, and the jump list is traversed again after the traversal is completed.

[0050] In a third aspect, an embodiment of the present invention provides a coreCLR virtual machine, including: a language compiler and a just-in-time compiler;

[0051] The language compiler is used to convert the source code into instruction information of MSIL language;

[0052] The just-in-time compiler is used to execute the method of the first aspect.

[0053] In a fourth aspect, an embodiment of the present invention further provides an electronic device, comprising: at least one processor and a memory;

[0054] The memory stores computer-executable instructions;

[0055] The at least one processor executes the computer-executable instructions stored in the memory, so that the electronic device implements the method described in the first aspect above.

[0056] In a fifth aspect, an embodiment of the present invention further provides a non-temporary computer-readable storage medium, wherein the computer-readable storage medium stores computer execution instructions, and when the computer execution instructions are executed by a processor of an electronic device, the electronic device implements the method described in the first aspect.

[0057] In a sixth aspect, an embodiment of the present invention further provides a computer program for implementing the method described in the first aspect.

[0058] The instant compilation method and device provided by the present invention are applied to the coreCLR virtual machine. The present invention can obtain multiple instruction information before compiling and linking; generate and store the first encoding instruction of at least one first instruction information in the multiple instruction information, and the encoding length of the first instruction information is fixed; if there is at least one second instruction information in the multiple instruction information, the second instruction information is added to the jump list, and the jump list is compiled and linked to determine the encoding length of the second instruction information, and the encoding length of the second instruction information is not fixed; in the process of sequentially executing multiple instruction information, when the instruction information to be executed is the first instruction information, the first encoding instruction of the first instruction information is transmitted to the corresponding memory space for execution; if the instruction information to be executed is the second instruction information, the second encoding instruction is generated according to the encoding length of the second instruction information, and the second encoding instruction is transmitted to the corresponding memory space for execution. Since the encoding length of the first instruction information is fixed, the first instruction information can be encoded in advance to obtain the corresponding first encoding instruction, avoiding encoding when executing the instruction, and reducing the delay of executing the instruction. BRIEF DESCRIPTION OF THE DRAWINGS

[0059] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the invention and, together with the description, serve to explain the principles of the invention.

[0060] Figure 1 The flowchart of the steps of the just-in-time compilation method provided by the embodiment of the present invention is exemplified;

[0061] Figure 2 The structure block diagram of an electronic device provided by an embodiment of the present invention is exemplarily shown;

[0062] Figure 3 The schematic diagram of the structure of the coreCLR virtual machine provided by the embodiment of the present invention is exemplified;

[0063] Figure 4 The structural block diagram of another electronic device provided by an embodiment of the present invention is exemplarily shown.

[0064] The above drawings have shown clear embodiments of the present invention, which will be described in more detail below. These drawings and text descriptions are not intended to limit the scope of the present invention in any way, but to illustrate the concept of the present invention for those skilled in the art by referring to specific embodiments. DETAILED DESCRIPTION

[0065] Exemplary embodiments will be described in detail herein, examples of which are shown in the accompanying drawings. When the following description refers to the drawings, the same numbers in different drawings represent the same or similar elements unless otherwise indicated. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present invention. Instead, they are merely examples of devices and methods consistent with some aspects of the present invention as detailed in the appended claims.

[0066] The following specific embodiments may be combined with each other, and the same or similar concepts or processes may not be described in detail in some embodiments. The embodiments of the present invention will be described below in conjunction with the accompanying drawings.

[0067] The embodiment of the present invention can be applied to a coreCLR virtual machine, which can receive instruction information and execute the instruction after receiving the instruction information to implement various functions based on the instruction.

[0068] In the prior art, the instruction execution process of a virtual machine mainly includes: first, obtaining multiple instruction information, and storing the instruction information containing a memory address jump instruction in a jump list; then, determining the encoding length corresponding to the instruction information in the jump list according to the order of the instruction information in the jump list; finally, encoding each instruction information according to the encoding length of each instruction information in the jump list to obtain an encoded instruction and executing it, and encoding the instruction information that does not contain a memory address jump instruction according to the encoding to obtain an encoded instruction and executing it.

[0069] The memory address jump instructions include but are not limited to: function call instructions, data segment access instructions, and branch jump instructions.

[0070] However, the above solution encodes all instruction information only when the instruction is executed, so this encoding process will lead to a long waiting time for executing the instruction information, resulting in a large delay in executing the instruction.

[0071] In order to solve the above problem, the inventor studied the above process and found that the encoding length of part of the instruction information in the memory jump instruction is fixed. This part of the instruction information can be encoded in advance to obtain the corresponding encoding instruction, which reduces the delay of executing the instruction.

[0072] The following specific embodiments are used to describe in detail the technical solutions of the present invention and how the technical solutions of the present application solve the above-mentioned technical problems. The following specific embodiments can be combined with each other, and the same or similar concepts or processes may not be repeated in some embodiments. The embodiments of the present invention will be described below in conjunction with the accompanying drawings.

[0073] Figure 1The flowchart of a just-in-time compilation method provided by an embodiment of the present invention is exemplarily shown, which can be applied to the coreCLR virtual machine. Figure 1 , the above-mentioned instant compilation method may include S101 to S102:

[0074] S101: Obtain multiple instruction information before compiling and linking.

[0075] The plurality of instruction information may be instruction information included in a preset code block, and the instruction information in the code block is obtained before executing the preset code block. The instruction information is instructions in an instruction set corresponding to the coreCLR core common language runtime.

[0076] The execution of the above preset code block can be triggered by the visual interface and sent to the coreCLR virtual machine. It can be understood that the coreCLR virtual machine serves as a background server, and the visual interface serves as a front-end client, which can be an application running in a terminal device.

[0077] The above-mentioned compilation and linking can refer to the detailed description in S103, which will not be repeated here.

[0078] S102: Generate and store a first coding instruction of at least one first instruction information among the multiple instruction information, where the coding length of the first instruction information is fixed.

[0079] The instruction information may include memory address jump instructions, and the memory address jump instructions may include but are not limited to: data segment access instructions, branch jump instructions between different branch codes within a function, and function call instructions.

[0080] The above-mentioned data segment access instruction refers to a jump instruction introduced when accessing a segment of data in a target memory address in the instruction information. The target memory address and the current memory address are not continuous, so it is necessary to jump from the current memory address to the target memory address to fetch data.

[0081] For the above data segment access instruction, the embodiment of the present invention sets a minimum encoding length for the function. When the minimum encoding length is sufficient, the data segment access instruction will not cause the encoding length of the instruction information to change.

[0082] The branch jump instruction between the branch codes in the above function can be a jump instruction between different branch codes in the same function. For example, there are usually multiple branch codes with preset conditions in a function, and each branch code includes a condition judgment part and a main part. When a branch code A1 is executed, if the preset condition of the branch code is not met, the main part of A1 is not executed, but the condition judgment part of A1 jumps to the condition judgment part of the next branch code A2 to determine whether the preset condition of A2 is met. This jump instruction between branch codes is a branch jump instruction.

[0083] When the target address of a branch jump instruction is uncertain, the number of encoding instructions required to jump to the target address cannot be determined, so the encoding length of the instruction information including the branch jump instruction with an uncertain target address is not fixed. The instruction information is the second instruction information.

[0084] The above-mentioned function call instruction refers to a jump instruction between different functions, and the function here can also be called a method. For example, when function A calls function B, there is a memory address jump instruction between function A and function B, and the memory address difference between the two is the difference between the starting memory address of function A and the starting memory address of function B.

[0085] Function jump instructions usually jump from function A to a fixed position first, and then jump from the fixed position to the target function B. The jump between function A and the fixed position usually sets a maximum encoding length, which can support the longest jump of the virtual machine. The number of encoding instructions corresponding to the jump between the fixed position and the target function B is usually fixed, so that the function call will not cause the encoding length of the instruction information to change.

[0086] In summary, when the instruction information does not include a branch jump instruction with an uncertain target address, the encoding length of the instruction information is fixed, and the instruction information is the first instruction information. For example, the instruction information that only includes the above-mentioned function call and / or data segment access can be the first instruction information. Of course, the instruction information that does not include the above-mentioned memory address jump instruction is also the first instruction information.

[0087] When the instruction information includes a branch jump instruction with an uncertain target address, the encoding length of the instruction information is not fixed, and the instruction information is the second instruction information.

[0088] It should be noted that the coding instruction is a binary code of the instruction information, and each instruction information may correspond to one or more coding instructions of fixed length. For example, the first instruction information may correspond to one or more first coding instructions, and the second instruction information may correspond to one or more second coding instructions. The fixed coding length of the first instruction information means that the number of first coding instructions corresponding to one first instruction information is fixed, while the non-fixed coding length of the second instruction information means that the number of second coding instructions corresponding to one second instruction information is non-fixed.

[0089] When the encoding length of the first instruction information is fixed, it is not necessary to determine the encoding length of the first instruction information according to the relative offset address of the first instruction information in the jump list, and thus it is not necessary to add the first instruction information to the jump list. In this way, the number of instruction information included in the jump list is small, thereby shortening the time required to traverse the jump list, thereby reducing the delay in executing instructions.

[0090] S103: If there is at least one second instruction information in the plurality of instruction information, the second instruction information is added to the jump list, and the jump list is compiled and linked to determine the encoding length of the second instruction information. The encoding length of the second instruction information is not fixed.

[0091] The jump list stores the instruction information of variable encoding length in S103, and the jump list needs to be compiled and linked to determine the encoding length of each second instruction information in the jump list.

[0092] In the prior art, a lot of instruction information is added to the jump list, including various memory address jump instructions, which makes the compilation and linking process take longer, thereby also causing a longer delay in executing the instructions.

[0093] The embodiment of the present invention can only add the second instruction information including the branch jump with uncertain target address to the jump list, which can effectively reduce the size of the jump list, help reduce the compilation and linking time, and further reduce the delay of executing instructions.

[0094] The compilation link is specifically to determine the relative offset address corresponding to each second instruction information by traversing the jump list, and the relative offset address is related to the position of the second instruction information in the jump list. After determining the relative offset address of each second instruction information, its encoding length can be determined according to the relative offset address.

[0095] Optionally, the above-mentioned determination of the encoding length of the second instruction information includes: in the process of traversing the jump list, for each second instruction information in the jump list, determining the address difference in the jump list between the second instruction information and the target instruction information to which the second instruction information jumps; if the address difference is less than or equal to a preset address difference threshold, then determining the preset encoding length corresponding to the preset address difference threshold as the encoding length of the second instruction information; if the address difference is greater than the preset address difference threshold, then increasing the preset encoding length corresponding to the preset address difference threshold by a preset length as the encoding length of the second instruction information, and traversing the jump list again after the traversal is completed.

[0096] The jump between instruction information used in the embodiment of the present invention is a short jump instruction. Through the short jump instruction, under normal circumstances, the encoding length of each second instruction information can be determined by traversing the jump list once. In the case where at least one second instruction information is updated, it is necessary to traverse the jump list twice to obtain the encoding length of each second instruction information.

[0097] S104: In the process of sequentially executing multiple instruction information, when the instruction information to be executed is the first instruction information, the first encoded instruction of the first instruction information is transmitted to the corresponding memory space for execution; when the instruction information to be executed is the second instruction information, the second encoded instruction is generated according to the encoding length of the second instruction information, and the second encoded instruction is transmitted to the corresponding memory space for execution.

[0098] It can be seen that the steps in S101 and S102 are the preparation processes before compiling and linking, the process in S103 is the process of compiling and linking, and S104 is a step performed after compiling and linking, including the emission of coded instructions and the execution of coded instructions. It can be understood that the order of multiple instruction information is not the order of the instruction information in the jump list, but the order determined by the dependency relationship between the instruction information. For example, if instruction information A depends on instruction information B, it is restricted to execute instruction information B first and then execute instruction information A.

[0099] In the embodiment of the present invention, for the first instruction information, since its encoding length is fixed, the first encoding instruction has been generated in advance according to the encoding length, and the pre-generated first encoding instruction is directly executed during execution. For the second instruction information, since its encoding length is not fixed, it is necessary to traverse the jump list to determine its encoding length, and before executing the second instruction information, the second encoding instruction must first be generated according to the encoding length.

[0100] In the prior art, the lengths of the first coded instruction and the second coded instruction are determined after compiling and linking, so that memory space needs to be applied for after compiling and linking. In the embodiment of the present invention, the length of the first coded instruction is determined before compiling and linking, so that memory space can be applied for according to the length of the first coded instruction before compiling and linking. In this way, the delay of executing instructions can be further reduced.

[0101] Of course, since the length of the second encoding instruction still needs to be determined after compiling and linking, it is necessary to apply for corresponding memory space according to the length of the second encoding instruction after generating the second encoding instruction.

[0102] The instruction information to be executed is any one of the multiple instruction information, and the instruction information is to be executed at the current time. The size of the total memory space can be determined according to the sum of the lengths of the first coded instructions corresponding to all the first instruction information (referred to as the first length sum) and the sum of all the second coded lengths (referred to as the second length sum). Specifically, the size of the memory can be the sum of the first length sum and the second length sum.

[0103] Optionally, the first instruction information includes: third instruction information containing a function call, fourth instruction information containing an immediate value whose length is greater than or equal to a preset length threshold, and fifth instruction information other than the third instruction information and the fourth instruction information in the first instruction information, and the method further includes:

[0104] Determine a structure corresponding to each instruction information from at least one preset structure, wherein the at least one preset structure includes at least one of the following: a first structure for storing encoding instructions of fifth instruction information, a second structure for storing second instruction information, a third structure for storing encoding instructions of third instruction information, and a fourth structure for storing encoding instructions of fourth instruction information, wherein the second structure, the third structure, and the fourth structure inherit the first structure; store multiple instruction information in a transmission list in the corresponding structures respectively; execute multiple instruction information in the above order, including: executing multiple instruction information in the order in the transmission list.

[0105] It can be seen that the first structure is the most basic structure, which can store the basic information of instruction information. Based on the first structure, the second structure is used to store the additional information required for branch jump instructions with uncertain target addresses. Based on the first structure, the third structure is used to store the additional information required for function calls. Based on the first structure, the fourth structure is used to store the additional information required for immediate values ​​whose length is greater than or equal to the preset length threshold.

[0106] In this way, the storage space required for storing instruction information can be reduced as much as possible.

[0107] The above-mentioned first structure, second structure and third structure can exist in any architecture, for example, various types in RISC (reduced instruction set computing): RISC-V, MIPS, ARM, Loongarch, etc., and X86 in CISC (complex instruction set computing).

[0108] The fourth structure exists in some architectures. For example, when the preset length threshold is 64 bits, since the immediate value in the RISC-related processor architecture is usually less than 64 bits, the fourth structure does not exist in the architecture. For another example, in the CSIC-related processor architecture, the immediate value is usually greater than or equal to 64 bits, so the fourth structure needs to exist in the architecture.

[0109] In the prior art, there are eleven structures for storing instruction information, which is a large number and results in high complexity in managing the structures.

[0110] In the embodiment of the present invention, the instruction information is divided into four types according to the type of instruction information, which correspond to four structures respectively. In this way, the storage of various instruction information can be realized by using only the above four structures, which reduces the number of structures and reduces the management complexity of the structures.

[0111] In the embodiment of the present invention, each instruction information may be stored in the emission list as a structure, or multiple related instruction information may be stored in the emission list as a structure. When storing the structure in the emission list, according to the dependency relationship between the instruction information, the structure corresponding to the dependent instruction information may be stored in the emission list first, and the structure corresponding to the instruction information that depends on the other instruction information may be stored in the emission list later.

[0112] In the process of executing multiple instruction information in the order in the transmission list, when the instruction information to be executed is the first instruction information, the first encoding instruction of the first instruction information is executed; when the instruction information to be executed is the second instruction information, the second encoding instruction is generated according to the encoding length of the second instruction information, and the second encoding instruction is executed.

[0113] Optionally, the storing of the plurality of instruction information in the transmission list in corresponding structures respectively includes: storing at least two associated second instruction information in the transmission list in the same structure, the memory size of the structure being fixed; and storing the encoding instructions of at least two associated first instruction information in the transmission list in the same structure.

[0114] The associated instruction information may be multiple instruction information for realizing the same function. Since the memory size of each structure is fixed, storing multiple associated instruction information in the same structure can reduce the number of structures, thereby reducing the memory occupied by the structure, helping to save memory resources and simplify the steps of saving instruction information.

[0115] It is understandable that, since the first instruction information and the second instruction information correspond to different structures, the first instruction information and the second instruction information cannot be stored in the same structure. The associated first instruction information can be stored in the same structure, and the associated second instruction information can be stored in the same structure.

[0116] Optionally, the above-mentioned storing the encoding instructions of at least two associated first instruction information in the emission list in the same structure includes: storing the encoding instructions of at least two first instruction information that construct the same immediate value in the emission list in the same structure.

[0117] The instruction information for constructing the same immediate value is the associated first instruction information. In ARM (advanced reduced instruction set computer machine) and MIPS (microprocessor without interlocked piped stages architecture), immediate values ​​are widely used.

[0118] The embodiment of the present invention can reduce the number of structures used to construct instruction information of immediate values ​​in ARM and MIPS, thereby reducing the memory occupied by the structures, helping to save memory resources and simplifying the steps of saving instruction information.

[0119] In summary, the embodiment of the present invention provides a just-in-time compilation method, which can obtain multiple instruction information; generate and store a first coding instruction of at least one first instruction information among the multiple instruction information, and the coding length of the first instruction information is fixed; if there is at least one second instruction information among the multiple instruction information, the second instruction information is added to a jump list, and the coding length of the second instruction information is determined according to the position of the second instruction information in the jump list; in the process of sequentially executing multiple instruction information, when the instruction information to be executed is the first instruction information, the first coding instruction of the first instruction information is executed; when the instruction information to be executed is the second instruction information, the second coding instruction is generated according to the coding length of the second instruction information, and the second coding instruction is executed. Since the coding length of the first instruction information is fixed, the first instruction information can be encoded in advance to obtain the corresponding first coding instruction, thereby reducing the delay of executing the instruction.

[0120] Figure 2 The structural block diagram of a just-in-time compilation device provided by an embodiment of the present invention is exemplarily shown, and is applied to a coreCLR virtual machine. Figure 2 , the just-in-time compilation device 200 may include:

[0121] The instruction information acquisition module 201 is used to acquire multiple instruction information before compiling and linking.

[0122] The first coding instruction storage module 202 is used to generate and store a first coding instruction of at least one first instruction information among the multiple instruction information, and the coding length of the first instruction information is fixed.

[0123] The coding length determination module 203 is used to add the second instruction information to the jump list if there is at least one second instruction information among the multiple instruction information, and compile and link the jump list to determine the coding length of the second instruction information, and the coding length of the second instruction information is not fixed.

[0124] The encoding instruction execution module 204 is used to, during the process of sequentially executing the multiple instruction information, when the instruction information to be executed is the first instruction information, transmit the first encoding instruction of the first instruction information to the corresponding memory space for execution; if the instruction information to be executed is the second instruction information, generate a second encoding instruction according to the encoding length of the second instruction information, and transmit the second encoding instruction to the corresponding memory space for execution.

[0125] Optionally, the first instruction information does not include a branch jump instruction with an uncertain target address, and the second instruction information includes a branch jump instruction with an uncertain target address.

[0126] Optionally, the device further comprises:

[0127] The first memory application module is used to apply for corresponding memory space according to the length of the first encoding instruction before performing the compile and link.

[0128] The second memory application module is used to apply for corresponding memory space according to the length of the second encoding instruction after generating the second encoding instruction.

[0129] Optionally, the first instruction information includes: third instruction information indicating a function call, fourth instruction information indicating an immediate value having a length greater than or equal to a preset length threshold, and fifth instruction information other than the third instruction information and the fourth instruction information in the first instruction information, and the device further includes:

[0130] a structure determination module, used to determine a structure corresponding to each piece of the instruction information from at least one preset structure, wherein the at least one preset structure includes at least one of the following: a first structure for storing the encoding instruction of the fifth instruction information, a second structure for storing the second instruction information, a third structure for storing the encoding instruction of the third instruction information, and a fourth structure for storing the encoding instruction of the fourth instruction information, wherein the second structure, the third structure, and the fourth structure inherit the first structure;

[0131] The emission list generation module is used to store the plurality of instruction information in the emission list in the form of corresponding structures respectively.

[0132] Based on the above-mentioned emission list generation module, the encoding instruction execution module 204 is also used for:

[0133] The plurality of instruction information are executed in the order in the issue list.

[0134] Optionally, the emission list generation module is further used for:

[0135] At least two associated second instruction information are stored in the emission list in the same structure, and the memory size of the structure is fixed; and the encoding instructions of at least two associated first instruction information are stored in the emission list in the same structure.

[0136] Optionally, the emission list generation module is further used for:

[0137] When the encoding instructions of at least two associated first instruction information are stored in the emission list in the same structure, the encoding instructions of at least two first instruction information that construct the same immediate value are stored in the emission list in the same structure.

[0138] Optionally, the coding length determination module 203 is further used for:

[0139] In the process of traversing the jump list, for each piece of the second instruction information in the jump list, determining the address difference between the second instruction information and the target instruction information to which the second instruction information jumps in the jump list;

[0140] If the address difference is less than or equal to a preset address difference threshold, determining a preset coding length corresponding to the preset address difference threshold as the coding length of the second instruction information;

[0141] If the address difference is greater than a preset address difference threshold, the preset encoding length corresponding to the preset address difference threshold is increased by a preset length as the encoding length of the second instruction information, and the jump list is traversed again after the traversal is completed.

[0142] The electronic device provided in this embodiment can be used to perform the above Figure 1 The technical solution of the method embodiment in the embodiment has similar implementation principles and technical effects, and will not be repeated here in this embodiment.

[0143] Figure 3 The schematic diagram of the structure of a coreCLR virtual machine provided by an embodiment of the present invention is exemplarily shown. Figure 3 As shown, the coreCLR virtual machine 300 may include a language compiler 301 and a just-in-time compiler 302 .

[0144] The language compiler 301 is used to convert source code into instruction information of MSIL (Microsoft intermediate language).

[0145] The just-in-time compiler 302 is used to execute Figure 1 The method shown obtains the execution result.

[0146] The source code can be software code in any language, such as VB code or C#. MSIL includes some metadata and intermediate language instructions.

[0147] In actual applications, when the software code is run for the first time, the language compiler and the just-in-time compiler are run. When the software code is run again, only the just-in-time compiler can be run, and the input of the just-in-time compiler is the instruction information of the MSIL obtained by running the language compiler during the first run, which can help improve the efficiency of the subsequent running of the software code.

[0148] Figure 4 The structural block diagram of another electronic device 600 provided by an embodiment of the present invention is exemplarily shown. Figure 4 , the electronic device 600 includes a memory 602 and at least one processor 601;

[0149] The memory 602 stores computer-executable instructions.

[0150] At least one processor 601 executes the computer execution instructions stored in the memory 602, so that the electronic device implements the aforementioned Figure 1 The method in .

[0151] In addition, the electronic device may further include a receiver 603 and a transmitter 604, wherein the receiver 603 is used to receive information from other devices or equipment and forward it to the processor 601, and the transmitter 604 is used to send the information to other devices or equipment.

[0152] The electronic device provided in this embodiment can be used to perform the above Figure 1The technical solution of the method embodiment in the embodiment has similar implementation principles and technical effects, and will not be repeated here in this embodiment.

[0153] The embodiment of the present invention further provides a non-transitory computer-readable storage medium, wherein the computer-readable storage medium stores computer-executable instructions, which are used to implement the above-mentioned when the electronic components of the electronic device execute the computer-executable instructions. Figure 1 The method in .

[0154] The embodiment of the present invention also provides a computer program for implementing the above Figure 1 The method in .

[0155] Those skilled in the art will readily appreciate other embodiments of the present invention after considering the specification and practicing the invention disclosed herein. The present invention is intended to cover any variations, uses or adaptations of the present invention that follow the general principles of the present invention and include common knowledge or customary techniques in the art that are not disclosed by the present invention. The description and examples are to be considered exemplary only, and the true scope and spirit of the present invention is indicated by the following claims.

[0156] It should be understood that the present invention is not limited to the exact construction that has been described above and shown in the drawings, and that various modifications and changes may be made without departing from the scope thereof. The scope of the present invention is limited only by the appended claims.

Claims

1. A just-in-time compilation method, characterized in that: Applied to the coreCLR virtual machine, the method comprises: Get multiple instruction information before compiling and linking; Generate and store a first encoding instruction of at least one first instruction information among the multiple instruction information, wherein the encoding length of the first instruction information is fixed; If there is at least one second instruction information among the multiple instruction information, the second instruction information is added to the jump list, and the jump list is compiled and linked to determine the encoding length of the second instruction information, and the encoding length of the second instruction information is not fixed; In the process of sequentially executing the multiple instruction information, when the instruction information to be executed is the first instruction information, the first encoded instruction of the first instruction information is transmitted to the corresponding memory space for execution; if the instruction information to be executed is the second instruction information, a second encoded instruction is generated according to the encoding length of the second instruction information, and the second encoded instruction is transmitted to the corresponding memory space for execution.

2. The method according to claim 1, characterized in that The first instruction information does not include a branch jump instruction with an uncertain target address, and the second instruction information includes a branch jump instruction with an uncertain target address.

3. The method according to claim 1 or 2, characterized in that: The method further comprises: Before performing the compiling and linking, applying for corresponding memory space according to the length of the first encoding instruction; After the second encoding instruction is generated, corresponding memory space is applied for according to the length of the second encoding instruction.

4. The method according to claim 2, characterized in that: The first instruction information includes: third instruction information containing a function call, fourth instruction information containing an immediate value whose length is greater than or equal to a preset length threshold, and fifth instruction information other than the third instruction information and the fourth instruction information in the first instruction information, and the method further includes: Determine a structure corresponding to each of the plurality of instruction information from at least one preset structure, wherein the at least one preset structure includes at least one of the following: a first structure for storing the encoding instruction of the fifth instruction information, a second structure for storing the second instruction information, a third structure for storing the encoding instruction of the third instruction information, and a fourth structure for storing the encoding instruction of the fourth instruction information, wherein the second structure, the third structure, and the fourth structure inherit the first structure; The plurality of instruction information are stored in a transmission list in the form of corresponding structures respectively; The sequentially executing the plurality of instruction information includes: The plurality of instruction information are executed in the order in the issue list.

5. The method according to claim 4, characterized in that The storing the plurality of instruction information into the emission list in corresponding structures respectively includes: storing at least two associated second instruction information in the same structure into the transmission list, wherein the memory size of the structure is fixed; The encoding instructions of at least two associated first instruction information are stored in a transmission list in the same structure.

6. The method according to claim 5, characterized in that The step of storing the encoding instructions of at least two associated first instruction information in the same structure into the transmission list includes: The encoding instructions of at least two first instruction information for constructing the same immediate value are stored in the issue list in the same structure.

7. The method according to claim 1, characterized in that The determining the encoding length of the second instruction information includes: In the process of traversing the jump list, for each piece of the second instruction information in the jump list, determining the address difference between the second instruction information and the target instruction information to which the second instruction information jumps in the jump list; If the address difference is less than or equal to a preset address difference threshold, determining a preset coding length corresponding to the preset address difference threshold as the coding length of the second instruction information; If the address difference is greater than a preset address difference threshold, the preset encoding length corresponding to the preset address difference threshold is increased by a preset length as the encoding length of the second instruction information, and the jump list is traversed again after the traversal is completed.

8. A real-time compilation device, characterized in that: Applied to the coreCLR virtual machine, the device comprises: Instruction information acquisition module, used to obtain multiple instruction information before compiling and linking; A first coding instruction storage module, used for generating and storing a first coding instruction of at least one first instruction information among the plurality of instruction information, wherein the coding length of the first instruction information is fixed; A coding length determining module, configured to add the second instruction information to a jump list if there is at least one second instruction information among the plurality of instruction information, and to compile and link the jump list to determine the coding length of the second instruction information, wherein the coding length of the second instruction information is not fixed; A coding instruction execution module is used to, during the process of sequentially executing the multiple instruction information, when the instruction information to be executed is the first instruction information, transmit the first coding instruction of the first instruction information to the corresponding memory space for execution; if the instruction information to be executed is the second instruction information, generate a second coding instruction according to the coding length of the second instruction information, and transmit the second coding instruction to the corresponding memory space for execution.

9. A coreCLR virtual machine, characterized in that: include: Language compilers and just-in-time compilers; The language compiler is used to convert the source code into instruction information of micro intermediate language MSIL; The just-in-time compiler is used to execute the method according to any one of claims 1 to 7.

10. An electronic device, characterized in that: include: at least one processor and memory; The memory stores computer-executable instructions; The at least one processor executes the computer-executable instructions stored in the memory, so that the electronic device implements the method according to any one of claims 1 to 7.

11. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores computer-executable instructions, and when the computer-executable instructions are executed by a processor of an electronic device, the electronic device implements the method according to any one of claims 1 to 7.

12. A computer program product, comprising a computer program, characterized in that The computer program is used to implement the method according to any one of claims 1 to 7.

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