Functional memory generation method, device and electronic device

Abstract

The present disclosure provides a method, device and electronic device for generating a functional memory, belonging to the field of memory technology. The method comprises: obtaining description information of a functional memory to be designed, the description information comprising: target byte depth, target byte width, target operating frequency; determining the target type of the functional memory to be designed according to the target byte depth and target operating frequency; determining the target compiler information of at least one specification of physical memory included under the target type from the target database; determining the specification, quantity and location of the target physical memory constituting the functional memory to be designed according to the target compiler information and the description information. The functional memory can be automatically designed according to the description information.

Description

Technical Field

[0001] The present disclosure relates to the field of memory technology, and in particular to a method, device and electronic device for generating a functional memory. Background Art

[0002] In electronic devices, integrated circuits are key components for realizing various functions. As an important component of integrated circuits, the internal structure of chips is mainly composed of memory and other circuit structures. As the area of ​​memory in the chip increases, the design of functional memory (Function Memory) in chip design becomes particularly important.

[0003] The functional memory in the chip is composed of physical memories, but there are many types of physical memories. The area, power consumption and performance of different types of physical memories are also different. How to design the functional memory so that it can balance area and performance is crucial.

[0004] However, the existing design of functional memory mainly relies on the experience of designers, which results in that the design of functional memory is time-consuming and cannot guarantee a better design. Summary of the invention

[0005] The present disclosure provides a method, device and electronic device for generating a functional memory, which can automatically design a functional memory according to description information.

[0006] The technical solution of the present disclosure is achieved as follows:

[0007] In a first aspect, the present disclosure provides a method for generating a functional memory, the method comprising: obtaining description information of the functional memory to be designed, the description information comprising: a target byte depth, a target byte width, and a target operating frequency; determining a target type of the functional memory to be designed according to the target byte depth and the target operating frequency; determining target compiler information of at least one specification of a physical memory included under the target type from a target database; determining the specification, quantity, and location of the target physical memory constituting the functional memory to be designed according to the target compiler information and the description information.

[0008] In a second aspect, the present disclosure provides a functional memory generation device, which includes: an acquisition part and a determination part; the acquisition part is configured to acquire description information of the functional memory to be designed, the description information including: a target byte depth, a target byte width, and a target operating frequency; the determination part is configured to determine the target type of the functional memory to be designed according to the target byte depth and the target operating frequency; the determination part is also configured to determine target compiler information of at least one specification of a physical memory included under the target type from a target database; the determination part is also configured to determine the specification, quantity and location of the target physical memory constituting the functional memory to be designed according to the target compiler information and the description information.

[0009] In a third aspect, the present disclosure provides an electronic device comprising a processor, a memory, and a program or instruction stored in the memory and executable on the processor, wherein the program or instruction, when executed by the processor, implements the steps of the functional memory generation method as described in the first aspect.

[0010] In a fourth aspect, the present disclosure provides a computer-readable storage medium storing a program or instruction, which, when executed by a processor, implements the steps of the functional memory generation method as described in the first aspect.

[0011] In a fifth aspect, the present disclosure provides a computer program product, wherein the computer program product includes a computer program or instructions, and when the computer program product runs on a processor, the processor executes the computer program or instructions to implement the steps of the functional memory generation method as described in the first aspect.

[0012] In a sixth aspect, the present disclosure provides a chip, comprising a processor and a communication interface, wherein the communication interface is coupled to the processor, and the processor is used to run a program or instruction to implement the functional memory generation method as described in the first aspect.

[0013] The present disclosure provides a method for generating a functional memory, the method comprising: obtaining description information of a functional memory to be designed, the description information comprising: target byte depth, target byte width, target operating frequency; determining the target type of the functional memory to be designed according to the target byte depth and target operating frequency; determining target compiler information of at least one specification of physical memory included under the target type from a target database; determining the specification, quantity and location of the target physical memory constituting the functional memory to be designed according to the target compiler information and the description information. Without relying on manpower, the specification, quantity and location of the physical memory constituting the functional memory to be designed can be determined according to the description information of the functional memory, thereby improving the efficiency of generating the functional memory. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1 One of the flowcharts of the method for generating a functional memory provided by the present disclosure;

[0015] Figure 2a A schematic diagram of a function memory list interface provided by the present disclosure;

[0016] Figure 2b A schematic diagram of a description information input interface provided by the present disclosure;

[0017] Figure 3 A schematic diagram of design information of a functional memory displayed in a user interface provided by the present disclosure;

[0018] Figure 4 The second flowchart of the method for generating a functional memory provided by the present disclosure;

[0019] Figure 5 A schematic diagram of a process for determining target types provided by the present disclosure;

[0020] Figure 6 The third flowchart of the method for generating a functional memory provided by the present disclosure;

[0021] Figure 7a A schematic diagram arranged along the horizontal axis provided for the present disclosure;

[0022] Figure 7b A schematic diagram arranged along the vertical axis provided for the present disclosure;

[0023] Figure 7c A schematic diagram arranged along the horizontal and vertical axes provided for the present disclosure;

[0024] Figure 8 A schematic diagram of a process for determining an arrangement method provided by the present disclosure;

[0025] Fig. 9 The fourth flowchart of the method for generating a functional memory provided by the present disclosure;

[0026] Fig.10a One of the schematic diagrams of the physical memory provided by the present disclosure forming a functional memory;

[0027] Fig.10b The second schematic diagram of the physical memory provided by the present disclosure forming a functional memory;

[0028] Fig.10c The third schematic diagram of the physical memory provided by the present invention forming a functional memory;

[0029] Fig.11 A structural block diagram of a functional memory generating device provided by the present disclosure;

[0030] Fig.12 A schematic diagram of the hardware structure of an electronic device provided by the present invention. DETAILED DESCRIPTION

[0031] The following will be combined with the drawings in the present disclosure to clearly describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, rather than all the embodiments. All other embodiments obtained by ordinary technicians in this field based on the embodiments in the present application belong to the scope of protection of the present application.

[0032] The terms "first", "second", etc. in the specification of this application are used to distinguish similar objects, rather than to describe a specific order or precedence. It should be understood that the terms used in this way can be interchangeable where appropriate, so that the present disclosure can be implemented in an order other than those illustrated or described herein, and the objects distinguished by "first", "second", etc. are generally of one type, and the number of objects is not limited. For example, the first object can be one or more.

[0033] Memory is an integral part of a chip and occupies an increasing area in the chip. A chip is a small piece of semiconductor material, usually silicon, on which electronic circuits are integrated. In computers and other electronic devices, chips can perform a variety of functions, including processing data (such as a central processing unit or graphics processing unit), storing data (such as memory or flash memory), etc. Chips are the basic components that constitute the core functions of electronic devices.

[0034] Functional memory is part of the chip, and as the demand for storage capacity increases, the proportion of functional memory in the overall chip area is increasing. Functional memory is used to describe memory used for specific functions, such as cache, random access memory, read-only memory, hard disk drive or solid state drive. That is, functional memory defines the purpose and characteristics of storage.

[0035] Functional memory is composed of physical memory, which refers to the actual hardware device used to store data and program code. That is, physical memory is the specific hardware that implements the various functions of functional memory.

[0036] Therefore, in the design of functional memory, the selection and arrangement of physical memory are crucial. However, the design of existing functional memory is usually designed by memory designers based on design experience, which is not only time-consuming and labor-intensive, but the designed functional memory is not necessarily optimal.

[0037] The present disclosure aims to provide a method capable of automatically generating a functional memory. The executor of the method may be an electronic device (including a mobile electronic device and a non-mobile electronic device), or a functional module and / or functional entity in the electronic device capable of implementing the functional memory generation method. The specific method may be determined based on actual usage requirements and is not limited in the embodiments of the present application.

[0038] The functional memory generation method provided by the present disclosure is described in detail below through specific embodiments in conjunction with the accompanying drawings.

[0039] like Figure 1 As shown, it is a flowchart of a method for generating a functional memory according to the present disclosure, and the method may include the following steps S101 to S104.

[0040] In step S101, description information of a functional memory to be designed is obtained.

[0041] The description information includes: target byte depth, target byte width, target operating frequency, and the description information may also include: identification information (such as the name of the functional memory to be designed).

[0042] The capacity of the functional memory is determined by the byte depth and byte width. These two parameters directly affect the capacity of the functional memory, that is, the amount of data that can be stored. Among them, byte depth refers to the number of data rows that can be stored in the functional memory, or it can be understood as the number of storage locations, each storage location can store data of a certain width. Byte width refers to the number of data bits that can be stored in each storage location. Common byte widths are 8 bits (1 byte), 16 bits (2 bytes), 32 bits (4 bytes), etc. The total capacity of the functional memory is the product of the byte depth and the byte width. For example, if a functional memory has 1024 (i.e. 2 10 ) storage locations (that is, the byte depth is 1024), and each storage location can store 8 bits (1 byte) of data (the byte width is 8 bits), then the total capacity of this memory is 1024 times 8 bits, or 1024 bytes (1KB).

[0043] Optionally, description information of the design function memory input by the user is obtained from the user interface.

[0044] For example, Figure 2a The following is the interface of the function memory list. The function memory list includes four columns, namely name (name of the function memory), width (byte width of the function memory), depth (byte depth of the function memory) and frequency (operating frequency of the function memory). Click the "Delete" button to delete the selected cell in the function memory list; click the "Add" button to pop up the following Figure 2bThe description information input interface shown in the figure can be displayed alone or suspended on Figure 2a The interface shown is displayed, and the specific display method is not limited in this application. Figure 2b In the description information input interface shown, the user can enter the name (identifier), byte depth, byte width and operating frequency of the functional memory to be designed, click the "Submit" button to start the design, and click the "Cancel" button to cancel the input.

[0045] In step S102, the target type of the functional memory to be designed is determined according to the target byte depth and the target operating frequency.

[0046] Common types of functional memory include: High-Speed ​​Register File (HSRF), Ultra-High Density SRAM (UHDSRAM), High-Speed ​​SRAM (HSSRAM) and High-Density SRAM (HDSRAM). The types of functional memory may also include other types, which are not specifically limited in this application.

[0047] Among them, the high-speed register file is a very fast memory used to temporarily store data and instructions in a microprocessor, digital signal processor or other high-performance computing devices. It has the characteristics of low latency, high bandwidth and temporary storage. The high-speed register file is a functional memory designed to meet the speed and efficiency requirements of high-performance computing devices.

[0048] Ultra-high density static random access memory is a high-performance static random access memory (SRAM) that provides very high data storage density. Compared with traditional SRAM, ultra-high density static random access memory can store more data in the same physical space, and it has the characteristics of high density, high-speed access and low power consumption. In CPUs, GPUs and other high-performance processors, UHDSRAM can be used as a cache. In network devices such as routers and switches, UHDSRAM can be used for fast packet caching. UHDSRAM is also suitable for embedded systems and mobile devices.

[0049] High-speed static random access memory is a fast-access SRAM technology designed to provide fast data access in computers and other high-performance electronic devices. It features fast data access, low latency, easy integration, and static storage. HSSRAM is used as cache memory inside the central processing unit to help reduce the speed difference between the CPU and main memory and increase processing speed; it is also often used in network switches, routers and other devices to quickly process and forward data packets, and for cache or temporary storage in high-performance computing applications.

[0050] High-density static random access memory is a type of SRAM technology with high storage capacity. Compared with traditional SRAM, high-density SRAM provides more storage bits in the same physical size. High-density SRAM combines the high-speed access characteristics of SRAM with larger storage capacity, making it suitable for a variety of applications that require fast data access and large-capacity storage. It has the characteristics of high storage capacity, fast data access, low power consumption and high stability.

[0051] Specifically, the target type of the functional memory to be designed is determined according to the target byte depth and the target operating frequency. The correspondence between the byte depth and the operating frequency and the type of the functional memory may be pre-set, and the target type corresponding to the target byte depth and the target operating frequency may be determined by querying the correspondence. For example, in the description information input interface that pops up in the user interface, the input box corresponding to the byte depth includes a plurality of preset depth values ​​to be selected, and the input box corresponding to the operating frequency includes a plurality of preset frequency values ​​to be selected. The correspondence between the depth value and the frequency value included in the interface and the type is pre-set, and the corresponding type can be determined according to the depth value and the frequency value selected by the user. It is also possible to pre-set the correspondence between the byte depth range and the operating frequency range and the type of the functional memory, and determine the corresponding target type according to the range to which the target byte depth belongs and the range to which the target operating frequency belongs.

[0052] In step S103, target compiler information of at least one specification of physical memory included in the target type is determined from the target database.

[0053] The target database pre-stores compilation information of physical memories of at least one type and specification. The compilation information includes: byte depth step, byte width step, byte depth range, byte width range when center decoding is true, byte width range when center decoding is false, and the compilation information may also include: bit line multiplexer (Column Multiplexer, MUX) and block (Bank, BK). MUX is mainly used to balance the row-column ratio in physical memory, and center decoding (Center Decode) involves the layout and design of memory address decoding, which is true when the address decoding logic is placed in the center of the storage array, otherwise it is false.

[0054] Exemplarily, as shown in Table 1, compiler information of each type and at least one specification of physical memory stored in the target database. Among them, the type in the first column indicates the type of functional memory, the MUX in the second column indicates the selection of an input signal to pass to the output, the WD (Word Depth) step in the third column indicates the step of byte depth, the BK in the fourth column indicates the number of blocks, the WD min and WD max in the fifth and sixth columns indicate the minimum and maximum values ​​of byte depth, the WW (Word Width) step in the seventh column indicates the step of byte width, the WW min and WW max in the eighth and ninth columns indicate the minimum and maximum values ​​of byte width when the center decoding is true, and the WW min and WW max in the tenth and eleventh columns indicate the minimum and maximum values ​​of byte width when the center decoding is false.

[0055] Table 1 Correspondence between types and compiler information

[0056]

[0057] As shown in Table 1, type HSRF includes physical memories of different specifications of byte depth and byte width. For example, the specifications that can be obtained according to the step size increase are: 8*16, 8*20, 8*24...8*512, 12*16, 12*20, 12*24...12*512, etc.

[0058] In step S104, the specification, quantity and location of the target physical memory constituting the functional memory to be designed are determined according to the target compiler information and the description information.

[0059] Specifically, according to the target compiler information and description information, the specification, quantity and location of the target physical memory constituting the functional memory to be designed are determined. The physical memory of specification one that is closest to the target byte depth and target byte width can be selected from the target compiler information. The value obtained by dividing the target byte depth by the byte depth of the physical memory of specification one is rounded up to quantity one, and the value obtained by dividing the target byte width by the byte width of the physical memory of specification one is rounded up to quantity two. The product of quantity one and quantity two is the quantity of physical memory of specification one. The physical memory of specification one has a total of one row of quantity, and each row includes two columns of quantity. According to the target compiler information and description information, the specification, quantity and location of the target physical memory constituting the functional memory to be designed can be determined. Other strategies can also be used, which are not limited by the present disclosure.

[0060] For example, the target byte depth is 1000, the target byte width is 2000, the byte depth of the physical memory closest to the target byte depth and target byte width is 512, and the byte width is 256, 1000 divided by 512 is rounded up to 3, and 2000 divided by 256 is rounded up to 8, then the functional memory to be designed is composed of 3 times 8, which is equal to 24 physical memories of one specification, and each row has 8 physical memories of one specification, for a total of 3 rows. In this way, through the functional memory generation method disclosed in the present invention, according to the description information of the functional memory to be designed, the specifications and quantity of the physical memory can be automatically determined, and the functional memory to be designed can be arranged.

[0061] like Figure 3 As shown, the design information of the functional memory is displayed in the user interface, specifically including: description information, functional memory composition information, Figure 3 The functional memory shown in the figure is composed of 4 physical memories of type tp_uhsrf with a byte width and byte depth of 127*1024 and 1 physical memory of type tp_uhsrf with a byte width and byte depth of 128*8. The physical memory obtained by splicing is displayed in the virtual graphic area. Optionally, according to the area of ​​the physical memories constituting the functional memory, the area of ​​the functional memory can also be displayed in the functional memory information area.

[0062] If the type corresponding to the byte depth and the operating frequency is preset, then since it is impossible to enumerate all byte depths and operating frequencies, the target byte depth and the target operating frequency must be within the preset byte depth and operating frequency. Therefore, in order to determine the corresponding target type for any target byte depth and target operating frequency, the type corresponding to the depth range and the frequency range can be preset. Specifically, Figure 4As shown, in some embodiments of the present disclosure, the step S102 of determining the target type of the functional memory to be designed according to the target byte depth and the target operating frequency can be specifically implemented through the following steps S102a to S102e.

[0063] In step S102a, if the target byte depth is less than or equal to the first depth value, the target type is determined to be the first preset type.

[0064] In step S102b, if the target byte depth is greater than the first depth value, the range to which the target frequency belongs is determined.

[0065] In step S102c, when the target frequency belongs to the first frequency range, the target type is determined to be the second preset type.

[0066] In step S102d, when the target frequency belongs to the second frequency range, the target type is determined to be a third preset type.

[0067] In step S102e, when the target frequency belongs to the third frequency range, the target type is determined to be a fourth preset type.

[0068] Among them, any value in the first frequency range is smaller than any value in the second frequency range, and any value in the second frequency range is smaller than any value in the third frequency range.

[0069] It should be noted that the frequency ranges set in the present disclosure are three, but this is not a limitation of the present application. According to the number of actual physical memory types, other numbers of frequency ranges can be divided, such as setting four or five frequency ranges, etc. The settings of the division of different frequency ranges and the type correspondence are all within the protection scope of the present application.

[0070] For example, Figure 5 The figure shows a flowchart for determining the target type. Figure 5 The first preset type shown is HSRF, the second preset type is HSSRAM, the third preset type is HDSRAM, and the fourth preset type is UHDSRAM; the first depth value is 512, the first frequency range is greater than 700, the second frequency range is greater than 200 and less than or equal to 700, and the third frequency range is less than or equal to 200.

[0071] In order to optimize the arrangement of the physical memories constituting the functional memory to be designed and reduce the area of ​​the functional memory to be designed, in some embodiments of the present disclosure, Figure 6As shown, the above step S104 determines the specification, quantity and location of the target physical memory constituting the functional memory to be designed according to the target compiler information and the description information, which can be specifically implemented according to the following steps S104a and S104b.

[0072] In step S104a, the arrangement of the target physical memory is determined according to the target byte depth and the target byte width.

[0073] The arrangement modes include: arrangement along the horizontal axis, arrangement along the vertical axis, arrangement along the horizontal axis and the vertical axis, and single memory.

[0074] Specifically, the arrangement of the target physical memory is determined according to the target byte depth and the target byte width. When the target byte width is less than or equal to the width threshold and the target byte depth is greater than the depth threshold, the arrangement is determined to be arranged along the vertical axis; when the target byte width is greater than the width threshold and the target byte depth is less than or equal to the depth threshold, the arrangement is determined to be arranged along the horizontal axis; when the target byte width is greater than the width threshold and the target byte depth is greater than the depth threshold, the arrangement is determined to be arranged along the vertical axis; when the target byte width is less than or equal to the width threshold and the target byte depth is less than or equal to the depth threshold, the arrangement is determined to be a single memory (i.e., only one memory is required).

[0075] like Figure 7a As shown, it is a schematic diagram arranged along the horizontal axis, and the figure shows a functional memory composed of 6 physical memories from P1 to P6. Figure 7b It is a schematic diagram arranged along the vertical axis, showing a functional memory composed of 6 physical memories P1 to P6. Figure 7c It is a schematic diagram arranged along the horizontal axis and the vertical axis, showing a functional memory composed of 24 physical memories from P11 to P46.

[0076] In step S104b, the specification, quantity and location of the target physical memory are determined according to the arrangement mode, description information and target compiler information.

[0077] According to the arrangement mode, description information and target compiler information, the specification, quantity and position of the target physical memory are determined. Specifically, after the arrangement mode is determined, if the arrangement is arranged along the horizontal axis, the physical memory whose byte depth is closest to the target byte depth and greater than or equal to the target byte depth is selected from the target compiler information, and the number obtained by rounding up the target byte width divided by the byte width of the physical memory is the required number of physical memories; if the arrangement is arranged along the vertical axis, the physical memory whose byte width is closest to the target byte width and greater than or equal to the target byte width is selected from the target compiler information, and the number obtained by rounding up the target byte depth divided by the byte depth of the physical memory is the required number of physical memories; if the arrangement is arranged along the horizontal axis and the vertical axis, the physical memory whose byte width is closest to the target byte width and whose byte depth is closest to the target byte depth is selected from the target compiler information, and the product of the number 1 obtained by rounding up the target byte depth divided by the byte depth of the physical memory and the number 2 obtained by rounding up the target byte width divided by the byte width of the physical memory is the required number of physical memories, and the physical memories are arranged in the order of number 1 in rows and number 2 in columns. The specification, quantity and location of the target physical memory are determined according to the arrangement, description information and target compiler information. Other strategies may also be used and are not limited in the present disclosure.

[0078] As a strategy for determining a better arrangement, in some embodiments of the present disclosure, the above step S104a determines the arrangement of the target physical memory according to the target byte depth and the target byte width, and specifically includes the following steps S104c to S104q.

[0079] In step S104c, if the target byte depth belongs to the first depth range, the range to which the target byte width belongs is determined.

[0080] In step S104d, when the target byte width belongs to the first width range, the arrangement is determined to be arranged along the horizontal axis and the vertical axis.

[0081] In step S104e, when the target byte width does not belong to the first width range, the arrangement is determined to be arranged along the vertical axis.

[0082] In step S104f, if the target byte depth belongs to the second depth range, the range to which the target byte width belongs is determined.

[0083] In step S104g, when the target byte width belongs to the second width range, the arrangement is determined to be arranged along the horizontal axis and the vertical axis.

[0084] In step S104h, when the target byte width does not belong to the second width range, the arrangement is determined to be a single memory.

[0085] In step S104i, if the target byte depth belongs to the third depth range, the range to which the target byte width belongs is determined.

[0086] In step S104j, when the target byte width belongs to the third width range, the arrangement is determined to be arranged along the horizontal axis and the vertical axis.

[0087] In step S104k, when the target byte width does not belong to the third width range, the arrangement mode is determined to be a single memory.

[0088] In step S1041, if the target byte depth belongs to the fourth depth range, the range to which the target byte width belongs is determined.

[0089] In step S104m, when the target byte width belongs to the fourth width range, the arrangement is determined to be arranged along the horizontal axis.

[0090] In step S104n, when the target byte width does not belong to the fourth width range, the arrangement mode is determined to be a single memory.

[0091] In step S104o, if the target byte depth belongs to the fifth depth range, the range to which the target byte width belongs is determined.

[0092] In step S104p, when the target byte width belongs to the fifth width range, the arrangement mode is determined to be a single memory.

[0093] In step S104q, when the target byte width does not belong to the fifth width range, the arrangement is determined to be arranged along the horizontal axis.

[0094] It should be noted that the range division in the above steps S104c to S104q is only an optional implementation strategy and is not intended to limit the present application. In practice, other division ranges may be selected as needed.

[0095] Optionally, if the target byte width does not belong to the fifth width range, or the target byte depth does not belong to the fifth depth range, the arrangement mode is determined to be a single memory, or prompt information is output to prompt that it is less than the minimum depth value or less than the minimum width value.

[0096] For example, the first depth range is greater than 32768, the second depth range is greater than 16384 and less than or equal to 32768, the third depth range is greater than 8192 and less than or equal to 16384, the fourth depth range is greater than 512 and less than or equal to 8192, the fifth depth range is greater than 8 and less than or equal to 512, the first width range is greater than 64, the second width range is greater than 80, the third width range is greater than 160, the fourth width range is greater than 320, and the fifth width range is greater than 8 and less than or equal to 512. The specific process of determining the arrangement method is as follows: Figure 8 shown.

[0097] In order to obtain a functional memory that is finally determined with an area as small as possible while meeting the requirements, in some embodiments of the present disclosure, for example Fig. 9 As shown, the above step 104b determines the specification, quantity and location of the target physical memory according to the arrangement mode, description information and target compiler information, and specifically includes the following steps S901 to S910.

[0098] In step S901, a first physical memory corresponding to a target type is determined.

[0099] The byte width of the first physical memory is a target preset width, and the byte depth of the first physical memory is a target preset depth.

[0100] In some implementations of the present disclosure, information of preset physical memory corresponding to each type is pre-stored, the physical memory corresponding to the target type is the first physical memory, the byte width of the first physical memory determined by the query is the target preset width, and the byte depth is the target preset depth. The information of each physical memory may also include the area of ​​the physical memory. Thus, the area of ​​the functional memory may be determined based on the final determined physical memory.

[0101] In step S902, the target byte width is divided by the target preset width and the result is rounded down to obtain a first number.

[0102] In step S903, the target byte depth is divided by the target preset depth and the result is rounded down to obtain a second number.

[0103] In step S904, if the arrangement is along the horizontal axis, a second physical memory with a byte width greater than or equal to the first byte width, a byte depth greater than or equal to the target byte depth, and a smallest capacity is determined from the target compiler information.

[0104] The first byte width is the difference between the target byte width and the product of the first number of target preset widths. Under the same process, the smaller the capacity of the physical memory, the smaller the area, and the larger the capacity, the larger the area.

[0105] In step S905, if the first byte width is not 0, a first number of first physical memories and second physical memories are arranged in sequence along the horizontal axis.

[0106] In this case, the target physical memory determined is a first number of first physical memories and second physical memories.

[0107] In step S906 , if the first byte width is 0, the first number of first physical memories are arranged in sequence along the horizontal axis.

[0108] In this case, the determined target physical memory is a first number of first physical memories.

[0109] In step S907, if the arrangement is along the vertical axis, a third physical memory with a byte width greater than or equal to the target byte width, a byte depth greater than or equal to the first byte depth, and a smallest capacity is determined from the target compiler information.

[0110] The first byte depth is: the difference between the target byte depth and the product of the second number and the target preset depth.

[0111] In step S908, if the first byte depth is not 0, the second number of first physical memories and third physical memories are arranged in sequence along the vertical axis.

[0112] In this case, the determined target physical memory is the second number of the first physical memory and the third physical memory.

[0113] In step S909 , if the first byte depth is 0, the second number of first physical memories are arranged in sequence along the vertical axis.

[0114] In this case, the determined target physical memory is the second amount of first physical memory.

[0115] In step S910, if the arrangement is along the horizontal axis and the vertical axis, a fourth physical memory with a byte depth equal to the target preset depth, a byte width greater than or equal to the first byte width, and a smallest capacity is determined from the target compiler information.

[0116] In step S911, a fifth physical memory having a byte width equal to a target preset width, a byte depth greater than or equal to a first byte depth, and a smallest capacity is determined from the target compiler information.

[0117] In step S912, a sixth physical memory having a byte width greater than or equal to the first byte width, a byte depth greater than or equal to the first byte depth, and a smallest capacity is determined from the target compiler information.

[0118] In step S913, the first physical memories which are the product of the first number and the second number are arranged in the order of the second number of rows and the first number of columns to obtain a reference arrangement.

[0119] In step S914 , if the first byte width is not 0 and the first byte depth is 0, a second number of fourth physical memories are inserted into any column in the reference arrangement.

[0120] In this case, the target physical memory determined is the product of the first number and the second number of first physical memories and the second number of fourth physical memories.

[0121] In step S915 , if the first byte width is 0 and the first byte depth is not 0, the first number of fifth physical memories are inserted into any row in the reference arrangement.

[0122] In this case, the target physical memory determined is the first physical memory of the product of the first number and the second number and the first number of fifth physical memories.

[0123] In step S916, if the first byte width is not 0 and the first byte depth is not 0, the second number of fourth physical memories are inserted into any column in the reference arrangement, and the first number of fifth physical memories are inserted into any row in the reference arrangement to obtain the target arrangement.

[0124] The second quantity of fourth physical memories is inserted into any column of the reference arrangement, and the first quantity of fifth physical memories is inserted into any row of the reference arrangement, that is, one row and one column are inserted into the reference arrangement, to obtain the target arrangement.

[0125] In step S917 , the sixth physical memory is arranged at the upper right corner of the target arrangement.

[0126] In this case, the target physical memories determined are the first physical memories multiplied by the first number and the second number, the first number of fifth physical memories, the second number of fourth physical memories, and the sixth physical memories.

[0127] In step S918, if the arrangement is a single memory, the seventh memory with a byte width greater than or equal to the target byte width, a byte depth greater than or equal to the target byte depth, and the smallest capacity is determined as the target physical memory from the target compiler information.

[0128] For example, taking the target preset width as 64, the target preset depth as 8192, the target byte width as 60, the target byte depth as 60000, and the arrangement as along the vertical axis, the quotient of 60000 divided by 8192 and rounded down is 7, the product of 8192 and 7 is 57344, and the difference between 60000 and 57344 is 2656. The byte depth and byte width of the memory closest to 60*2656 are obtained from the target compiler information: 64*2656, that is, 7 64*8192 and 1 64*2656 physical memories are finally determined to be arranged along the vertical axis. Fig.10a As shown, reference numeral 1001 indicates a 64*8192 physical memory, and reference numeral 1002 indicates a 64*2656 physical memory. It should be noted that the figure only shows the physical memory for example, and it is not a scaled-down version of the actual physical memory. In addition, the arrangement order of the physical memories along the vertical axis is not limited.

[0129] For example, if the target preset width is 64, the target preset depth is 8192, the target byte depth is 8000, the target byte width is 1000, and the arrangement is along the horizontal axis, the quotient of 1000 divided by 64 and rounded down is 15, the product of 64 and 15 is 960, and the difference between 1000 and 960 is 40. The byte depth and byte width of the memory closest to 40*8000 obtained from the target compiler information are: 40*8192, that is, 15 64*8192 physical memories and one 40*8192 physical memory are finally determined to be arranged along the horizontal axis. Fig.10b As shown, reference numeral 1001 indicates a 64*8192 physical memory, and reference numeral 1003 indicates a 40*8192 physical memory. It should be noted that the arrangement order of the physical memories along the horizontal axis in the figure is not limited.

[0130] For example, the target preset width is 64, the target preset depth is 8192, the target byte depth is 60000, and the target byte width is 1000. The quotient of 1000 divided by 64 and rounded down is 15, the quotient of 60000 divided by 8192 and rounded down is 7, and the product of 15 and 7 is 105. The benchmark arrangement is: 105 64*8192 physical memories are arranged in 7 rows and 15 columns; the product of 64 and 15 is 960, and the difference between 1000 and 960 is 40. It is determined that the byte depth is equal to 8192, and the word The physical memory whose section width is closest to 40 is: 40*8192. Insert 7 40*8192 into any column of the base arrangement. The product of 8192 and 7 is 57344. The difference between 60000 and 57344 is 2656. The physical memory whose byte width is equal to 64 and whose byte depth is closest to 2656 is: 64*2656. Insert 15 64*2656 into any row of the base arrangement. The physical memory whose capacity is greater than or equal to 40 and greater than or equal to 2656 and smallest is: 40*2656. Fig.10c As shown, reference numeral 1001 indicates a 64*8192 physical memory, reference numeral 1002 indicates a 64*2656 physical memory, reference numeral 1003 indicates a 40*8192 physical memory, and reference numeral 1004 indicates a 40*2656 physical memory. The row composed of 1002 can be inserted into any row of the target arrangement, and the column composed of 1003 can be inserted into any column of the target arrangement.

[0131] In order to facilitate the acquisition of compilation information of the physical memory, in some embodiments of the present disclosure, before the above step S103 determines the target compiler information of at least one specification of physical memory included in the target type from the target database, the method also includes the following steps S105 and S106.

[0132] In step S105 , compiler information of at least one specification of physical memory included in each of the multiple types is obtained.

[0133] In step S106, compiler information of each type and corresponding at least one specification of physical memory is stored in the target database.

[0134] Each type of physical memory includes compiler information of at least one specification of physical memory. In order to save storage space, the compiler information of the physical memory is stored according to the range of maximum and minimum values, as shown in the above Table 1. In this way, the required compiler information can be directly obtained from the target database when in use, improving the acquisition efficiency.

[0135] In order to ensure that the acquired description information is legal and avoid exceeding the limit or including illegal characters, in some embodiments of the present disclosure, before the above step 102 determines the target type of the functional memory to be designed according to the target byte depth and the target operating frequency, the method also includes the following step 107. The above step 102 can be specifically implemented by the following step 102f.

[0136] In step S105, the description information is verified.

[0137] If the obtained description information fails the verification, an exception message is thrown. For example, the verification rules may be: the target byte depth is pure number and does not exceed the limit, the target byte width must be pure number and does not exceed the limit, and the target operating frequency is pure number and does not exceed the limit; if the description information includes identification information, the identification information is a preset type of character.

[0138] Fig.11 FIG. 1 is a structural block diagram of a functional memory generating device 1100 shown in the present disclosure, such as Fig.11 As shown, it includes: an acquisition part 1101 and a determination part 1102; the acquisition part 1101 is configured to acquire description information of the functional memory to be designed, and the description information includes: a target byte depth, a target byte width, and a target operating frequency; the determination part 1102 is configured to determine the target type of the functional memory to be designed according to the target byte depth and the target operating frequency; the determination part 1102 is also configured to determine the target compiler information of at least one specification of the physical memory included under the target type from the target database; the determination part 1102 is also configured to determine the specification, quantity and location of the target physical memory constituting the functional memory to be designed according to the target compiler information and the description information.

[0139] In some embodiments of the present disclosure, the determination part 1102 is specifically configured to determine that the target type is a first preset type if the target byte depth is less than or equal to a first depth value; if the target byte depth is greater than the first depth value, determine the range to which the target frequency belongs; when the target frequency belongs to the first frequency range, determine the target type to be a second preset type; when the target frequency belongs to the second frequency range, determine the target type to be a third preset type; when the target frequency belongs to the third frequency range, determine the target type to be a fourth preset type; wherein any value of the first frequency range is less than any value of the second frequency range, and any value of the second frequency range is less than any value of the third frequency range.

[0140] In some embodiments of the present disclosure, the determination part 1102 is specifically configured to determine the arrangement of the target physical memory according to the target byte depth and the target byte width, and the arrangement methods include: arrangement along the horizontal axis, arrangement along the vertical axis, arrangement along the horizontal and vertical axes, and single memory; determine the specifications, quantity, and location of the target physical memory according to the arrangement method, description information, and target compiler information.

[0141] In some embodiments of the present disclosure, the determination part 1102 is specifically configured to determine the range to which the target byte width belongs if the target byte depth belongs to the first depth range; when the target byte width belongs to the first width range, determine the arrangement mode to be arranged along the horizontal axis and the vertical axis; when the target byte width does not belong to the first width range, determine the arrangement mode to be arranged along the vertical axis; if the target byte depth belongs to the second depth range, determine the range to which the target byte width belongs; when the target byte width belongs to the second width range, determine the arrangement mode to be arranged along the horizontal axis and the vertical axis; when the target byte width does not belong to the second width range, determine the arrangement mode to be a single memory; if the target byte depth belongs to the third depth range, determine the range to which the target byte width belongs; in the target When the target byte width belongs to the third width range, the arrangement mode is determined to be arranged along the horizontal axis and the vertical axis; when the target byte width does not belong to the third width range, the arrangement mode is determined to be a single memory; if the target byte depth belongs to the fourth depth range, the range to which the target byte width belongs is determined; when the target byte width belongs to the fourth width range, the arrangement mode is determined to be arranged along the horizontal axis; when the target byte width does not belong to the fourth width range, the arrangement mode is determined to be a single memory; if the target byte depth belongs to the fifth depth range, the range to which the target byte width belongs is determined; when the target byte width belongs to the fifth width range, the arrangement mode is determined to be a single memory; when the target byte width does not belong to the fifth width range, the arrangement mode is determined to be arranged along the horizontal axis.

[0142] In some embodiments of the present disclosure, the determining part 1102 is specifically configured to determine a first physical memory corresponding to the target type, the byte width of the first physical memory is the target preset width, and the byte depth of the first physical memory is the target preset depth; the target byte width is divided by the target preset width and rounded down to obtain a first quantity; the target byte depth is divided by the target preset depth and rounded down to obtain a second quantity; if the arrangement is arranged along the horizontal axis, then from the target compiler information, determine a second physical memory with a byte width greater than or equal to the first byte width, a byte depth greater than or equal to the target byte depth, and a smallest capacity, the first byte width is: the target byte width and the target preset width of the first quantity the difference of the product of the first byte depth and the second quantity and the target preset depth; if the first byte depth is not 0, the first quantity of the first physical memory and the second physical memory are arranged in sequence along the horizontal axis; if the first byte width is 0, the first quantity of the first physical memory is arranged in sequence along the horizontal axis; if the arrangement is arranged along the vertical axis, then from the target compiler information, determine the third physical memory with a byte width greater than or equal to the target byte width, a byte depth greater than or equal to the first byte depth, and a smallest capacity, the first byte depth is: the difference of the target byte depth and the product of the second quantity and the target preset depth; if the first byte depth is not 0, the second quantity of the first physical memory and the third physical memory are arranged in sequence along the vertical axis; if the first byte depth is 0 , then the second number of first physical memories are arranged in sequence along the vertical axis; if the arrangement is arranged along the horizontal axis and the vertical axis, then from the target compiler information, a fourth physical memory whose byte depth is equal to the target preset depth, whose byte width is greater than or equal to the first byte width, and whose capacity is the smallest is determined; from the target compiler information, a fifth physical memory whose byte width is equal to the target preset width, whose byte depth is greater than or equal to the first byte depth, and whose capacity is the smallest is determined; from the target compiler information, a sixth physical memory whose byte width is greater than or equal to the first byte width, whose byte depth is greater than or equal to the first byte depth, and whose capacity is the smallest is determined; the product of the first number and the second number is arranged according to the second number The first number of rows and columns are arranged to obtain a benchmark arrangement; if the first byte width is 0 and the first byte depth is not 0, the first number of fifth physical memories are inserted into any row in the benchmark arrangement; if the first byte width is not 0 and the first byte depth is not 0, the second number of fourth physical memories are inserted into any column in the benchmark arrangement, and the first number of fifth physical memories are inserted into any row in the benchmark arrangement to obtain a target arrangement; the sixth physical memory is arranged in the upper right corner of the target arrangement; if the arrangement is a single memory, the seventh memory with a byte width greater than or equal to the target byte width, a byte depth greater than or equal to the target byte depth, and a smallest capacity is determined as the target physical memory from the target compiler information.

[0143] In some embodiments of the present disclosure, the device also includes: a storage part; the acquisition part 1101 is also configured to obtain compiler information of at least one specification of physical memory included in each of the multiple types before determining the target compiler information of at least one specification of physical memory included in the target type from the target database; the storage part is configured to store the compiler information of each type and the corresponding at least one specification of physical memory into the target database.

[0144] In some embodiments of the present disclosure, the device also includes: a verification part; the verification part is configured to verify the description information before determining the target type of the functional memory to be designed according to the target byte depth and the target operating frequency; the determination part 1102 is specifically configured to determine the target type of the functional memory to be designed according to the target byte depth and the target operating frequency when the description information is verified.

[0145] In some embodiments of the present disclosure, the acquisition part 1101 is specifically configured to acquire the description information of the design function memory input by the user from the user interface.

[0146] It should be noted that the above-mentioned functional memory generating device can be the electronic device in the above-mentioned method embodiment of the present application, or it can be a functional module and / or functional entity in the electronic device that can realize the function of the device embodiment, and the embodiment of the present application is not limited.

[0147] In the embodiment of the present application, each module can implement the functional memory generation method provided in the above method embodiment and can achieve the same technical effect. To avoid repetition, it will not be repeated here.

[0148] refer to Fig.12 , which shows a structural block diagram of an electronic device provided by an exemplary embodiment of the present disclosure. In some examples, the electronic device may be at least one of a smart phone, a smart watch, a desktop computer, a laptop, a virtual reality terminal, an augmented reality terminal, a wireless terminal, and a laptop computer. The electronic device has a communication function and can access a wired network or a wireless network. The electronic device may generally refer to one of a plurality of terminals, and those skilled in the art may know that the number of the above terminals may be more or less. It can be understood that the electronic device undertakes the calculation and processing work of the technical solution of the present disclosure, and the present disclosure does not limit this.

[0149] like Fig.12 As shown, the electronic device in the present disclosure may include one or more of the following components: a processor 1210 and a memory 1220 .

[0150] Optionally, the processor 1210 uses various interfaces and lines to connect various parts of the entire electronic device, and executes various functions of the electronic device and processes data by running or executing instructions, programs, code sets or instruction sets stored in the memory 1220, and calling data stored in the memory 1220. Optionally, the processor 1210 can be implemented in at least one hardware form of digital signal processing (DSP), field-programmable gate array (FPGA), and programmable logic array (PLA). The processor 1210 can integrate one or a combination of a central processing unit (CPU), a graphics processing unit (GPU), a neural network processor (NPU), and a baseband chip. Among them, the CPU mainly processes the operating system, user interface, and application programs; the GPU is responsible for rendering and drawing the content that needs to be displayed on the touch display; the NPU is used to implement artificial intelligence (AI) functions; and the baseband chip is used to process wireless communications. It is understandable that the above-mentioned baseband chip may not be integrated into the processor 1210, but may be implemented by a separate chip.

[0151] The memory 1220 may include a random access memory (RAM) or a read-only memory (ROM). Optionally, the memory 1220 includes a non-transitory computer-readable storage medium. The memory 1220 may be used to store instructions, programs, codes, code sets, or instruction sets. The memory 1220 may include a program storage area and a data storage area, wherein the program storage area may store instructions for implementing an operating system, instructions for at least one function (such as a touch function, a sound playback function, an image playback function, etc.), instructions for implementing the above various method embodiments, etc.; the data storage area may store data created according to the use of the electronic device, etc.

[0152] In addition, those skilled in the art will understand that the structure of the electronic device shown in the above drawings does not constitute a limitation on the electronic device, and the electronic device may include more or fewer components than shown, or combine certain components, or arrange the components differently. For example, the electronic device also includes a display screen, a camera assembly, a microphone, a speaker, a radio frequency circuit, an input unit, a sensor (such as an acceleration sensor, an angular velocity sensor, a light sensor, etc.), an audio circuit, a WiFi module, a power supply, a Bluetooth module and other components, which will not be described in detail here.

[0153] The present disclosure also provides a computer-readable storage medium storing at least one instruction, wherein the at least one instruction is used to be executed by a processor to implement the method for generating a functional memory as described in the above embodiments.

[0154] The present disclosure also provides a computer program product, which includes computer instructions stored in a computer-readable storage medium; a processor of an electronic device reads the computer instructions from the computer-readable storage medium, and the processor executes the computer instructions, so that the electronic device executes to implement the functional memory generation method described in the above-mentioned embodiments.

[0155] An embodiment of the present application further provides a chip, which includes a processor and a communication interface, wherein the communication interface is coupled to the processor, and the processor is used to run programs or instructions to implement the various processes of the above-mentioned functional memory generation method embodiment, and can achieve the same technical effect. To avoid repetition, it will not be repeated here.

[0156] It should be understood that the chip mentioned in the embodiments of the present application can also be called a system-level chip, a system chip, a chip system or a system-on-chip chip, etc.

[0157] In the several embodiments provided in the present disclosure, it should be understood that the disclosed systems, devices, servers and methods can be implemented in other ways. For example, the device embodiments described above are only schematic. For example, the division of the units is only a logical function division. There may be other division methods in actual implementation, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be an indirect coupling or communication connection through some interfaces, devices or units, which can be electrical, mechanical or other forms.

[0158] The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0159] In addition, each functional unit in each embodiment of the present disclosure may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit. The above-mentioned integrated unit may be implemented in the form of hardware or in the form of software functional units.

[0160] If the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application is essentially or the part that contributes to the prior art or all or part of the technical solution can be embodied in the form of a software product, and the computer software product is stored in a storage medium, including a number of instructions to enable a computer device (which can be a personal computer, a server, or a network device, etc.) to perform all or part of the steps of the method described in each embodiment of the present application. The aforementioned storage medium includes: various media that can store program codes, such as a USB flash drive, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a disk or an optical disk.

[0161] Those skilled in the art should be aware that in one or more of the above examples, the functions described in the present disclosure can be implemented using hardware, software, firmware, or any combination thereof. When implemented using software, these functions can be stored in a computer-readable medium or transmitted as one or more instructions or codes on a computer-readable medium. Computer-readable media include computer storage media and communication media, wherein communication media include any media that facilitates the transmission of computer programs from one place to another. Storage media can be any available media that can be accessed by a general or special-purpose computer.

[0162] It should be noted that the technical solutions described in the present disclosure can be combined arbitrarily without conflict.

[0163] The above description is only a specific implementation mode of the present invention, but the protection scope of the present invention is not limited thereto. Any technician familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed by the present invention, which should be covered by the protection scope of the present invention.

Claims

1. A method for generating a functional memory, characterized in that: The method comprises: Obtaining description information of the functional memory to be designed, the description information including: target byte depth, target byte width, and target operating frequency; Determining a target type of the functional memory to be designed according to the target byte depth and the target operating frequency; Determine, from the target database, target compiler information of at least one specification of physical memory included in the target type; Determining an arrangement of the target physical memory according to the target byte depth and the target byte width, the arrangement comprising: arranging along the horizontal axis, arranging along the vertical axis, arranging along the horizontal axis and the vertical axis, and a single memory; Determine a first physical memory corresponding to the target type, wherein the byte width of the first physical memory is a target preset width, and the byte depth of the first physical memory is a target preset depth; Dividing the target byte width by the target preset width and rounding down to obtain a first number; Dividing the target byte depth by the target preset depth and rounding down to obtain a second number; If the arrangement is along the horizontal axis, then determining from the target compiler information a second physical memory having a byte width greater than or equal to a first byte width, a byte depth greater than or equal to the target byte depth, and a minimum capacity, wherein the first byte width is a difference between the target byte width and the product of the first number and the target preset width; If the first byte width is not 0, arranging the first number of first physical memories and second physical memories in sequence along the horizontal axis; If the first byte width is 0, the first number of first physical memories are arranged in sequence along the horizontal axis; If the arrangement is along the vertical axis, then determining from the target compiler information a third physical memory having a byte width greater than or equal to the target byte width and a byte depth greater than or equal to a first byte depth and having the smallest capacity, wherein the first byte depth is a difference between the target byte depth and the product of the second number and the target preset depth; If the first byte depth is not 0, arranging the second number of first physical memories and third physical memories in sequence along the vertical axis; If the first byte depth is 0, arranging the second number of first physical memories in sequence along the vertical axis; If the arrangement is along the horizontal axis and the vertical axis, then determining from the target compiler information a fourth physical memory having a byte depth equal to the target preset depth, a byte width greater than or equal to the first byte width, and a smallest capacity; Determine, from the target compiler information, a fifth physical memory having a byte width equal to the target preset width, a byte depth greater than or equal to the first byte depth, and a smallest capacity; Determine, from the target compiler information, a sixth physical memory having a byte width greater than or equal to the first byte width, a byte depth greater than or equal to the first byte depth, and a smallest capacity; Arrange the first physical memories, which are the product of the first number and the second number, according to the second number of rows and the first number of columns to obtain a reference arrangement; If the first byte width is 0 and the first byte depth is not 0, inserting a first number of fifth physical memories into any row in the reference arrangement; If the first byte width is not 0 and the first byte depth is not 0, inserting the second number of fourth physical memories into any column of the reference arrangement, and inserting the first number of fifth physical memories into any row of the reference arrangement, to obtain a target arrangement; Arrange the sixth physical memory at the upper right corner of the target arrangement; If the arrangement is a single memory, the seventh memory with a byte width greater than or equal to the target byte width, a byte depth greater than or equal to the target byte depth, and the smallest capacity is determined as the target physical memory from the target compiler information.

2. The method according to claim 1, characterized in that The step of determining the target type of the functional memory to be designed according to the target byte depth and the target operating frequency includes: If the target byte depth is less than or equal to the first depth value, determining that the target type is a first preset type; If the target byte depth is greater than the first depth value, determining the range to which the target frequency belongs; When the target frequency belongs to the first frequency range, determining the target type to be a second preset type; When the target frequency belongs to the second frequency range, determining the target type to be a third preset type; When the target frequency belongs to the third frequency range, determining the target type to be a fourth preset type; Any value in the first frequency range is smaller than any value in the second frequency range, and any value in the second frequency range is smaller than any value in the third frequency range.

3. The method according to claim 1, characterized in that Determining the arrangement of the target physical memory according to the target byte depth and the target byte width includes: If the target byte depth belongs to the first depth range, determining the range to which the target byte width belongs; When the target byte width belongs to the first width range, determining the arrangement mode is to arrange along the horizontal axis and the vertical axis; When the target byte width does not belong to the first width range, determining the arrangement mode to be arranged along the vertical axis; If the target byte depth belongs to the second depth range, determining the range to which the target byte width belongs; When the target byte width belongs to the second width range, determining the arrangement mode is to arrange along the horizontal axis and the vertical axis; When the target byte width does not belong to the second width range, determining the arrangement mode as a single memory; If the target byte depth belongs to a third depth range, determining the range to which the target byte width belongs; When the target byte width belongs to a third width range, determining the arrangement mode to be arranged along the horizontal axis and the vertical axis; When the target byte width does not belong to the third width range, determining the arrangement mode as a single memory; If the target byte depth belongs to a fourth depth range, determining the range to which the target byte width belongs; When the target byte width belongs to a fourth width range, determining the arrangement mode to be arranged along the horizontal axis; When the target byte width does not belong to the fourth width range, determining the arrangement mode as a single memory; If the target byte depth belongs to the fifth depth range, determining the range to which the target byte width belongs; When the target byte width belongs to the fifth width range, determining the arrangement mode as a single memory; When the target byte width does not belong to the fifth width range, the arrangement is determined to be arranged along the horizontal axis.

4. The method according to any one of claims 1 to 3, characterized in that: Before determining, from the target database, target compiler information of at least one specification of physical memory included in the target type, the method further comprises: Obtain compiler information of at least one specification of physical memory included in each of the multiple types; The compiler information of each type and corresponding at least one specification of physical memory is stored in the target database.

5. The method according to any one of claims 1 to 3, characterized in that: Before determining the target type of the functional memory to be designed according to the target byte depth and the target operating frequency, the method further includes: Verifying the description information; The step of determining the target type of the functional memory to be designed according to the target byte depth and the target operating frequency includes: When the description information passes verification, the target type of the functional memory to be designed is determined according to the target byte depth and the target operating frequency.

6. The method according to any one of claims 1 to 3, characterized in that: The step of obtaining description information of the functional memory to be designed includes: The description information of the design function memory input by the user is obtained from the user interface.

7. A functional memory generating device, characterized in that: The device comprises: an acquisition part, a determination part; The acquisition part is configured to acquire description information of the functional memory to be designed, wherein the description information includes: target byte depth, target byte width, and target operating frequency; The determining part is configured to determine the target type of the functional memory to be designed according to the target byte depth and the target operating frequency; The determining part is further configured to determine target compiler information of at least one specification of physical memory included in the target type from the target database; The determining part is further configured to determine an arrangement of the target physical memory according to the target byte depth and the target byte width, the arrangement comprising: arrangement along the horizontal axis, arrangement along the vertical axis, arrangement along the horizontal axis and the vertical axis, and a single memory; Determine a first physical memory corresponding to the target type, wherein the byte width of the first physical memory is a target preset width, and the byte depth of the first physical memory is a target preset depth; Dividing the target byte width by the target preset width and rounding down to obtain a first number; Dividing the target byte depth by the target preset depth and rounding down to obtain a second number; If the arrangement is along the horizontal axis, then determining from the target compiler information a second physical memory having a byte width greater than or equal to a first byte width, a byte depth greater than or equal to the target byte depth, and a minimum capacity, wherein the first byte width is a difference between the target byte width and the product of the first number and the target preset width; If the first byte width is not 0, arranging the first number of first physical memories and second physical memories in sequence along the horizontal axis; If the first byte width is 0, the first number of first physical memories are arranged in sequence along the horizontal axis; If the arrangement is along the vertical axis, then determining from the target compiler information a third physical memory having a byte width greater than or equal to the target byte width and a byte depth greater than or equal to a first byte depth and having the smallest capacity, wherein the first byte depth is a difference between the target byte depth and the product of the second number and the target preset depth; If the first byte depth is not 0, arranging the second number of first physical memories and third physical memories in sequence along the vertical axis; If the first byte depth is 0, arranging the second number of first physical memories in sequence along the vertical axis; If the arrangement is along the horizontal axis and the vertical axis, then determining from the target compiler information a fourth physical memory having a byte depth equal to the target preset depth, a byte width greater than or equal to the first byte width, and a smallest capacity; Determine, from the target compiler information, a fifth physical memory having a byte width equal to the target preset width, a byte depth greater than or equal to the first byte depth, and a smallest capacity; Determine, from the target compiler information, a sixth physical memory having a byte width greater than or equal to the first byte width, a byte depth greater than or equal to the first byte depth, and a smallest capacity; Arrange the first physical memories, which are the product of the first number and the second number, according to the second number of rows and the first number of columns to obtain a reference arrangement; If the first byte width is 0 and the first byte depth is not 0, inserting a first number of fifth physical memories into any row in the reference arrangement; If the first byte width is not 0 and the first byte depth is not 0, inserting the second number of fourth physical memories into any column of the reference arrangement, and inserting the first number of fifth physical memories into any row of the reference arrangement, to obtain a target arrangement; Arrange the sixth physical memory at the upper right corner of the target arrangement; If the arrangement is a single memory, the seventh memory with a byte width greater than or equal to the target byte width, a byte depth greater than or equal to the target byte depth, and the smallest capacity is determined as the target physical memory from the target compiler information.

8. An electronic device, characterized in that: The method comprises a processor, a memory, and a program or instruction stored in the memory and executable on the processor, wherein the program or instruction, when executed by the processor, implements the steps of the functional memory generation method as claimed in any one of claims 1 to 6.

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