PCIe bandwidth allocation method and basic input / output system

Abstract

The application discloses a PCIe bandwidth allocation method and a basic input and output system, wherein the method comprises the following steps: when the basic input and output system is powered on and self-checked, a PCIe root port is divided into a first number of sub-ports according to a minimum bandwidth unit; whether an external device is connected under each sub-port in the first number of sub-ports is identified, and a bit identification of each sub-port is generated according to an identification result; a bandwidth configuration table is read, the bandwidth configuration table is used for representing a matching relationship between the bit identification and a bandwidth allocation strategy; a target bandwidth allocation strategy matched with the first number of bit identifications is inquired from the bandwidth configuration table; and the PCIe root port is divided into a second number of sub-ports according to the target bandwidth allocation strategy, and a port bandwidth is allocated to each sub-port in the second number of sub-ports. The technical scheme provided by the application can efficiently and conveniently allocate PCIe bandwidth resources.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of computer, and particularly relates to a PCIe bandwidth allocation method and a basic input / output system. BACKGROUND

[0002] At present, in order to improve the performance of a server, a high-performance PCIe (Peripheral Component Interconnect express) device is usually mounted in the server. The PCIe device can include a graphics processor, a network card, a solid state disk, a host bus adapter and the like.

[0003] Generally, a plurality of PCIe modules are integrated in a CPU, and each PCIe module can provide a certain number of physical channels. For example, a PCIe module can provide 16 physical channels. Each physical channel has a corresponding bandwidth, which can represent the data throughput that the physical channel can carry.

[0004] The physical channels provided by the PCIe module can be connected through a PCIe Riser card. One or more slots can be arranged on the PCIe Riser card, and the slots can jointly divide the physical channels provided by the PCIe module. For example, three slots can be arranged on the PCIe Riser card, and the three slots correspond to X4, X4 and X8 physical channels respectively. In this way, the 16 physical channels provided by the PCIe module are distributed to the three groups of slots through the PCIe Riser card. The three groups of slots can be externally connected to respective PCIe devices, so as to realize mounting of high-performance PCIe devices in the server.

[0005] As can be seen from the above, when mounting the PCIe device, the bandwidth resource provided by the PCIe module needs to be divided, and the bandwidth resource provided by the PCIe module can be represented by the number of physical channels. At present, the PCIe Riser card can be distinguished by Riser ID, and different Riser IDs correspond to different bandwidth allocation strategies. For example, when the Riser ID is 1, it corresponds to the X16 bandwidth allocation strategy; when the Riser ID is 2, it corresponds to the X8X8 bandwidth allocation strategy. The Riser ID is usually represented by the impedance value of the resistance welded on the PCIe Riser card. The BIOS obtains the Riser ID of the PCIe Riser card through the IPMI interface (Intelligent Platform Management Interface) or the LPC (Low Pin Count bus) interface, so that the bandwidth allocation strategy matched with the Riser ID can be used to allocate the bandwidth resource provided by the PCIe module.

[0006] However, the existing PCIe bandwidth allocation method needs to design a resistance circuit on the PCIe Riser card, which causes waste of hardware resources and cost; on the other hand, when obtaining the Riser ID through the IPMI instruction, it often needs to send the instruction multiple times, which causes the boot time to be prolonged. Therefore, at present, a more efficient and convenient PCIe bandwidth allocation method is needed. SUMMARY

[0007] Therefore, the embodiments of the present application provide a PCIe bandwidth allocation method and a basic input and output system, which can efficiently and conveniently allocate PCIe bandwidth resources.

[0008] The present application provides a PCIe bandwidth allocation method, which is applied to a basic input and output system, and includes the following steps: when the basic input and output system is powered on and self-checked, the PCIe root port is divided into a first number of sub-ports according to a minimum bandwidth unit; whether an external device is connected under each sub-port in the first number of sub-ports is identified, and according to the identification result, an in-place identifier of each sub-port is generated; a bandwidth configuration table is read, the bandwidth configuration table being used to represent the matching relationship between the in-place identifier and the bandwidth allocation strategy; from the bandwidth configuration table, a target bandwidth allocation strategy matched with the first number of in-place identifiers is queried; according to the target bandwidth allocation strategy, the PCIe root port is divided into a second number of sub-ports, and a port bandwidth is allocated to each sub-port in the second number of sub-ports.

[0009] In one embodiment, the identifying whether a network device is connected to each of the first quantity of sub-ports comprises: querying a link layer flag bit in a configuration space register corresponding to the sub-port; if a parameter value in the link layer flag bit is 1, it indicates that the sub-port is connected to an external device, and if the parameter value is 0, it indicates that the sub-port is not connected to an external device.

[0010] In one embodiment, the first quantity of in-bit identifiers are generated in the following manner: arranging in-bit identifiers of each of the sub-ports in sequence according to a naming order of the sub-ports, and taking the arrangement result as the first quantity of in-bit identifiers.

[0011] In one embodiment, the bandwidth configuration table comprises standard in-bit identifiers and other in-bit identifiers in addition to the standard in-bit identifiers; wherein the standard in-bit identifiers are pre-configured with respective bandwidth allocation strategies, and the bandwidth allocation strategies corresponding to the other in-bit identifiers are determined in the following manner: for any other in-bit identifier, performing a bit operation on the other in-bit identifier and each of the standard in-bit identifiers, the bit operation being used to convert each value bit in the standard in-bit identifier into a corresponding value bit in the other in-bit identifier; based on a bit operation result, identifying one or more standard in-bit identifiers that match the other in-bit identifier; and taking the bandwidth allocation strategies corresponding to the one or more standard in-bit identifiers as the bandwidth allocation strategies corresponding to the other in-bit identifier.

[0012] In one embodiment, the bit operation on the other in-bit identifier and each of the standard in-bit identifiers comprises: for any standard in-bit identifier, judging whether there is a value bit that changes from a first value to a second value in the process of changing from the standard in-bit identifier to the other in-bit identifier, and taking the judgment result as the bit operation result; wherein the first value indicates that a sub-port is not connected to an external device, and the second value indicates that the sub-port is connected to an external device.

[0013] In one embodiment, the identifying one or more standard in-bit identifiers that match the other in-bit identifier based on the bit operation result comprises: if the bit operation result indicates that there is no value bit that changes from the first value to the second value, taking the standard in-bit identifier as one standard in-bit identifier that matches the other in-bit identifier.

[0014] In one embodiment, the method further comprises: if there are multiple target bandwidth allocation strategies that match the first quantity of in-bit identifiers, selecting an optional target bandwidth allocation strategy from the multiple target bandwidth allocation strategies, and dividing the PCIe root port into a second quantity of sub-ports according to the optional target bandwidth allocation strategy, and allocating port bandwidth to each of the second quantity of sub-ports.

[0015] In another aspect, the application provides a basic input / output system, comprising: a sub-port initialization unit, configured to divide a PCIe root port into a first number of sub-ports according to a minimum bandwidth unit when the basic input / output system is powered on and self-checked; an in-place identification generation unit, configured to identify whether an external device is connected to each of the first number of sub-ports and generate an in-place identification of each of the sub-ports according to the identification result; a reading unit, configured to read a bandwidth configuration table, the bandwidth configuration table being used to represent a matching relationship between in-place identifications and bandwidth allocation strategies; a querying unit, configured to query a target bandwidth allocation strategy matching the first number of in-place identifications from the bandwidth configuration table; and a re-allocation unit, configured to divide the PCIe root port into a second number of sub-ports according to the target bandwidth allocation strategy and allocate port bandwidth to each of the second number of sub-ports.

[0016] In one embodiment, the in-place identification generation unit comprises: a flag bit querying module, configured to query a link layer flag bit in a configuration space register corresponding to the sub-port; and an external device judging module, configured to judge that the sub-port is connected to an external device if a parameter value in the link layer flag bit is 1, and judge that the sub-port is not connected to an external device if the parameter value is 0.

[0017] In one embodiment, the querying unit is further configured to arrange the in-place identification of each of the sub-ports in sequence according to a naming order of the plurality of sub-ports, and take the arrangement result as the first number of in-place identifications.

[0018] In one embodiment, the bandwidth configuration table comprises standard in-place identifications and other in-place identifications except the standard in-place identifications, and the system further comprises: a bit operation unit, configured to perform bit operation on each of the other in-place identifications and each of the standard in-place identifications, the bit operation being used to convert each value bit in the standard in-place identification into a corresponding value bit in the other in-place identification; an identification unit, configured to identify one or more standard in-place identifications matching the other in-place identification based on a bit operation result; and a bandwidth allocation unit, configured to take a bandwidth allocation strategy corresponding to the one or more standard in-place identifications as a bandwidth allocation strategy corresponding to the other in-place identification.

[0019] In one embodiment, the bit operation unit comprises: a judging module, configured to judge whether there is a value bit changing from a first value to a second value in a process of changing from the standard in-place identification to the other in-place identification, and take a judgment result as a bit operation result; wherein the first value represents that a sub-port is not connected to an external device, and the second value represents that the sub-port is connected to an external device.

[0020] In one embodiment, the bit operation unit comprises an identification matching module, configured to, if the bit operation result represents that there is no bit transition from the first value to the second value, take the standard in-bit identification as one standard in-bit identification matched with the other in-bit identifications.

[0021] In one embodiment, the re-distribution unit is further configured to, if there are multiple target bandwidth allocation strategies matched with the first number of in-bit identifications, select one target bandwidth allocation strategy from the multiple target bandwidth allocation strategies, and divide the PCIe root port into a second number of sub-ports according to the selected target bandwidth allocation strategy, and allocate port bandwidth to each of the second number of sub-ports.

[0022] Another aspect of the present application provides a computer device, wherein the computer device is deployed with the basic input / output system.

[0023] Another aspect of the present application provides a computer storage medium, wherein the computer storage medium is configured to store a computer program, and the computer program is configured to, when executed by a processor, implement the PCIe bandwidth allocation method.

[0024] The technical scheme provided by one or more embodiments of the present application can allocate PCIe bandwidth resources without relying on Riser ID. Specifically, during the power-on self-test of the BIOS, the root port (RP) of the PCIe can be first initialized into a first number of sub-ports, and then in-bit identifications of each sub-port can be generated according to whether an external device is connected to each sub-port. The first number of sub-ports can correspond to the first number of in-bit identifications. In the present application, a bandwidth configuration table can be provided in advance, in which various in-bit identifications that can occur can be listed, and corresponding bandwidth allocation strategies for these in-bit identifications that can occur can be set. In this way, in an actual application scenario, when the current in-bit identifications of the multiple sub-ports are obtained, the corresponding bandwidth allocation strategy of the in-bit identification can be determined by table lookup. Finally, according to the determined bandwidth allocation strategy, the PCIe root port can be divided into a second number of sub-ports, and port bandwidth can be allocated to each of the second number of sub-ports, thereby completing the PCIe bandwidth allocation process.

[0025] In this way, the additional resistance on the PCIe Riser card can be avoided, and the Riser ID does not need to be read through the IPMI, thereby reducing the consumption of hardware resources and the boot time, and the PCIe bandwidth resources can be allocated efficiently and conveniently. BRIEF DESCRIPTION OF DRAWINGS

[0026] The features and advantages of the present application will be appreciated upon reference to the following detailed description and drawings, in which:

[0027] Figure 1 A schematic diagram of steps of a PCIe bandwidth allocation method in an embodiment of the application is shown;

[0028] Figure 2 A schematic diagram of the structure of a device identification field in a configuration space register in an embodiment of the application is shown;

[0029] Figure 3 A first schematic diagram of a bit operation in an embodiment of the application is shown;

[0030] Figure 4 A second schematic diagram of a bit operation in an embodiment of the application is shown;

[0031] Figure 5 A schematic diagram of functional modules of a basic input / output system in an embodiment of the application is shown. DETAILED DESCRIPTION

[0032] In order to make the objectives, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are some but not all of the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work fall within the scope of the present application.

[0033] The PCIe bandwidth allocation method provided in the present application can be applied in the BIOS of a server, and the PCIe bandwidth allocation can be implemented in the power-on self-test process of the BIOS.

[0034] One or more PCIe modules are usually integrated in a CPU. Taking a CPU with a model number of Ice Lake as an example, four PCIe modules can be integrated in the CPU, and each PCIe module can provide 16 physical channels, that is, X16 bandwidth resources. In actual application, each PCIe module can be used as a root port (RP), and according to the type and quantity of external devices (external PCIe devices), the root port can be divided into multiple sub-ports, so that the bandwidth resources corresponding to the root port can be distributed to each sub-port, and the external devices can be connected through the sub-ports.

[0035] In an actual application scenario, a root port with a bandwidth resource of X16 usually has five bandwidth allocation strategies: X16, X8X8, X4X4X8, X8X4X4, and X4X4X4X4. That is, the root port can be divided into four sub-ports, or three sub-ports, or two sub-ports, or one sub-port. Among them, the four sub-ports correspond to the bandwidth allocation strategy of X4X4X4X4, the three sub-ports correspond to the bandwidth allocation strategy of X4X4X8 or X8X4X4, the two sub-ports correspond to the bandwidth allocation strategy of X8X8, and the one sub-port corresponds to the bandwidth allocation strategy of X16.

[0036] According to the different bandwidth allocation strategies corresponding to the sub-ports, the naming rules of the sub-ports will also be different. For example, the naming rules of each sub-port corresponding to the PCIe root port identified as 0 can be as shown in Table 1.

[0037] Table 1: Naming rules of sub-ports

[0038] Bandwidth allocation strategy Subport naming Number of subports X16 port 0a 1 X8 X8 port 0a port 0c 2 X4 X4 X8 port 0a port 0b port 0c 3 X8 X4 X4 port 0a port 0c port 0d 3 X4 X4 X4 X4 port 0a Port 0b Port 0c Port 0d 4

[0039] It can be seen that the minimum bandwidth allocated to the sub-ports is X4, and the bandwidth corresponding to each sub-port is an integer multiple of X4. Of course, as the bandwidth resource corresponding to the PCIe root port changes (for example, from X16 to X32), the minimum bandwidth allocated to the sub-ports may also change, resulting in different numbers of divided sub-ports and bandwidths corresponding to each sub-port from the results shown in Table 1. Here, we will not list them one by one. Those skilled in the art can deform or transform part of the schemes after understanding the essence of the technical solutions of the present application, but it should be understood that such deformation or transformation without creative labor should be within the protection scope of the present application.

[0040] The PCIe bandwidth allocation method provided by an embodiment of the present application can be applied in the BIOS of a server, and in the power-on self-test process of the BIOS, the allocation of the PCIe bandwidth resource can be dynamically completed. Please refer to Figure 1 The method can include the following steps.

[0041] S1: In the power-on self-test of the basic input and output system, according to the minimum bandwidth unit, divide the PCIe root port into a first number of sub-ports.

[0042] In this embodiment, when the BIOS enters a power on self test (POST) process, the allocation of PCIe bandwidth resources can be started. Specifically, the BIOS can first preliminarily divide a PCIe root port into a preset number of sub-ports according to a minimum bandwidth unit. For example, if the PCIe root port corresponds to a bandwidth resource of X16, the minimum bandwidth unit is X4, and at this time, the root port can be preliminarily divided into 4 sub-ports.

[0043] It should be noted that the root port is only preliminarily divided into the first number of sub-ports, and the first number of sub-ports are not allocated with actual bandwidth.

[0044] S3: Identifying whether an external device is connected to each of the first number of sub-ports, and generating an in-place identifier of each sub-port according to the identification result.

[0045] In this embodiment, each of the sub-ports obtained by the division has a respective configuration space register (Link Control Register). The configuration space register is initialized by a hardware link, and thus can be directly used when the BIOS is powered on for self test. In the configuration space register, a device identification field of the sub-port can be recorded. The device identification field can be as shown in Figure 2 Generally, the length of the device identification field can be 16 bits (from 0 to 15), and in the device identification field, a plurality of different flag bits can be included, and the different flag bits can occupy respective bit numbers according to different implementation functions. For example, in Figure 2 , a data link layer flag bit (Data Link Layer Link Active) can be represented by bit 13. The parameter value in the data link layer flag bit can represent whether the sub-port is currently connected to an external device. Specifically, if the parameter value is 1, it represents that the sub-port is connected to an external device, and if the parameter value is 0, it represents that the sub-port is not connected to an external device.

[0046] As shown in Figure 2As shown, the device identification field can also contain other flag bits in addition to the link layer flag bit, which can collectively represent various status information of the sub-ports in actual application. For example, the flag bits can include a link autonomous bandwidth status flag bit (Link Autonomous Bandwidth Status), a link bandwidth management status flag bit (Link Bandwidth Management Status), a slot clock configuration flag bit (Slot Clock Configuration), a link training flag bit (Link Training), an undefined flag bit (Undefined), a negotiated link width flag bit (Negotiated Link Width), and a current link speed flag bit (Current Link Speed).

[0047] In the embodiment, the parameter value in the link layer flag bit can be obtained by querying the configuration space register corresponding to the sub-port, and the parameter value in the link layer flag bit can be used as the current in-situ identification of the sub-port. According to the naming order of the sub-ports (according to the alphabetical order in the naming, for example, from a to d as described above), the in-situ identifications of the sub-ports can be arranged in sequence, and the arrangement result can be used as the first number of in-situ identifications corresponding to the first number of sub-ports.

[0048] For example, the names of the four sub-ports are port0a, port0b, port0c, and port0d, and the parameter values of the link layer flag bits obtained from the configuration space registers of the four sub-ports are 1, 1, 1, and 0, respectively. Then, 1110 can be used as the in-situ identification corresponding to the four sub-ports, which indicates that the sub-ports of port0a, port0b, and port0c are all connected to external devices, and the sub-port of port0d is not connected to an external device.

[0049] S5: reading a bandwidth configuration table, which is used to represent the matching relationship between the in-situ identification and the bandwidth allocation strategy.

[0050] In the embodiment, in order to determine the final bandwidth allocation strategy of the root port, a bandwidth configuration table can be set in advance. In the bandwidth configuration table, each in-situ identification that can exist in the sub-ports can be listed, and then a corresponding bandwidth allocation strategy can be set for each in-situ identification. In this way, the actual obtained in-situ identification can be queried in the bandwidth configuration table in a subsequent table lookup manner, and the final bandwidth allocation strategy can be determined.

[0051] In actual application, the content in the bandwidth configuration table can be set artificially or automatically by an algorithm. Specifically, part of the content in the bandwidth configuration table can be as shown in Table 2.

[0052] Part of the content in the bandwidth configuration table

[0053] port 0a port 0b port 0c port 0d Bandwidth allocation strategy 1 1 1 1 X4 X4 X4 X4 1 1 1 0 X4 X4 X8 1 0 1 1 X8 X4 X4 1 0 0 0 X16 1 0 1 0 X8 X8 1 1 0 1 X4 X4 X4 X4 0 0 1 0 X8 X8 or X4 X4 X8

[0054] It can be seen that although the in-bit identification is determined according to four sub-ports, the final bandwidth allocation strategy is likely to divide less than four sub-ports. For example, for the in-bit identification "1000", only the sub-port named port0a is connected with the external device, and according to the naming rule of the sub-ports in Table 1, the bandwidth allocation strategy X16 is applicable to the case where only port0a is connected with the external device.

[0055] In practical application, the first five in-bit identifications in Table 2 can be standard in-bit identifications, which are strictly according to the naming rule of the sub-ports corresponding to the bandwidth allocation strategy to set the value position 1 or 0. For example, 1010 indicates that only port0a and port0c are connected with the external device, which is consistent with the naming of the sub-ports corresponding to the bandwidth allocation strategy X8X8.

[0056] In Table 2, in addition to the standard in-bit identifications, other in-bit identifications can also be included. For example, 0010 in the last row is an other in-bit identification. Since the in-bit identification is obtained according to the actual connection of the external device, it leads to that after the sub-ports are divided according to the bandwidth allocation strategy, some sub-ports are allocated with bandwidth but not connected with the external device, so that the parameter value read from the configuration space register is 0. For example, the in-bit identification 0010, the bandwidth allocation strategy can be X8X8, that is, only two sub-ports need to be finally divided, but only the second sub-port is connected with the external device and the first sub-port is in idle state, so the first value bit is set to 0. In addition, for this in-bit identification, the bandwidth allocation strategy can also be X4X4X8, that is, three sub-ports can be finally divided, but only the third sub-port is connected with the external device and the first sub-port and the second sub-port are in idle state, so the first value bit and the second value bit are both set to 0. Such in-bit identification which is not consistent with the naming rule of the sub-ports corresponding to the bandwidth allocation strategy can be used as other in-bit identification in addition to the standard in-bit identification.

[0057] In practical applications, the number of standard in-place identifiers is usually limited and small, and it is feasible to manually set the bandwidth allocation strategy. However, the number of other in-place identifiers is relatively large, and it will consume a large amount of human resources if the bandwidth allocation strategy is manually set for each of the other in-place identifiers. In view of this, in an embodiment, for a standard in-place identifier, a corresponding bandwidth allocation strategy can be pre-set. For other in-place identifiers, the other in-place identifiers can be subjected to a bit operation with each of the standard in-place identifiers, and based on the bit operation result, one or more standard in-place identifiers matched with the other in-place identifier can be identified. Finally, the bandwidth allocation strategy corresponding to the identified one or more standard in-place identifiers can be taken as the bandwidth allocation strategy corresponding to the other in-place identifier. In this way, the bandwidth allocation strategy of the other in-place identifier can be automatically set through the bit operation.

[0058] Specifically, refer to Figure 3 The bit operation between the other in-place identifier and the standard in-place identifier can be a process of converting each value bit in the standard in-place identifier into a corresponding value bit in the other in-place identifier one by one. In the process of converting the standard in-place identifier into the other in-place identifier, it can be determined whether there is a value bit that is converted from a first value to a second value, where the first value represents that the sub-port is not connected to an external device (for example, can be 0), and the second value represents that the sub-port is connected to an external device (for example, can be 1). Finally, the determination result can be taken as the bit operation result. If the bit operation result represents that there is no value bit that is converted from the first value to the second value, the standard in-place identifier can be taken as one standard in-place identifier matched with the other in-place identifier.

[0059] For example, Figure 3 The other in-place identifier is 0010, and the standard in-place identifier is 1010. In the process of converting the standard in-place identifier into the other in-place identifier, there is only a case of converting "1" to "0", and there is no case of converting "0" to "1". Therefore, the standard in-place identifier 1010 can be taken as one standard in-place identifier matched with the other in-place identifier 0010.

[0060] In Figure 4 , in the process of converting the standard in-place identifier 1010 into the other in-place identifier 1111, there are two cases of converting "0" to "1". Therefore, the standard in-place identifier 1010 is not matched with the other in-place identifier 1111.

[0061] Through the bit operation, the bandwidth allocation strategy corresponding to the matched one or more standard in-place identifiers can be taken as the bandwidth allocation strategy corresponding to the other in-place identifier. In this way, the bandwidth allocation strategy of the other in-place identifier can be automatically set, thereby forming a final bandwidth configuration table.

[0062] S7: querying, from the bandwidth configuration table, a target bandwidth allocation strategy matching the first quantity of in-place identifiers, and dividing the PCIe root port into a second quantity of sub-ports according to the target bandwidth allocation strategy, and assigning port bandwidths to each of the second quantity of sub-ports.

[0063] In the embodiment, after reading the bandwidth configuration table, the first quantity of in-place identifiers corresponding to the first quantity of sub-ports can be used as index conditions to query the bandwidth configuration table, so as to obtain a target bandwidth allocation strategy matching the in-place identifiers.

[0064] It should be noted that since the in-place identifiers in the bandwidth configuration table can correspond to multiple different bandwidth allocation strategies (for example, in-place identifier 0010 in Table 2), the target bandwidth allocation strategy queried according to the in-place identifier can also have multiple. In actual application, one of the multiple target bandwidth allocation strategies can be selected. Of course, in order to ensure the compatibility of the finally selected target bandwidth allocation strategy, a bandwidth allocation strategy with fewer sub-ports can be selected from the multiple target bandwidth allocation strategies. The purpose of such processing is that the fewer the sub-ports, the more bandwidths are allocated, which can better provide data throughput for the external device to ensure the normal operation of the external device.

[0065] In the embodiment, after determining the target bandwidth allocation strategy matching the current in-place identifier, the PCIe root port can be re-divided into sub-ports according to the target bandwidth allocation strategy, and the port bandwidths of the re-divided sub-ports can be set. In this way, during the BIOS power-on self-test process, the initial sub-ports are divided, and the in-place identifier at the current time is identified, and finally the actual division of the root port and the actual allocation of the bandwidth can be completed.

[0066] It can be seen that the technical scheme provided by one or more embodiments of the present application can allocate PCIe bandwidth resources without relying on Riser ID. Specifically, when the BIOS is powered on for self-checking, the PCIe root port can be first initialized as a plurality of sub-ports, and then according to whether an external device is connected under each sub-port, an in-place identifier of each sub-port can be generated. The first number of sub-ports can correspond to the first number of in-place identifiers. Each value bit in the in-place identifier can represent whether the corresponding sub-port is connected with an external device. In the present application, a bandwidth configuration table can be provided in advance, in which various in-place identifiers that can occur can be listed, and corresponding bandwidth allocation strategies for these possible in-place identifiers can be set. In this way, in an actual application scenario, when the current in-place identifier of the above-mentioned plurality of sub-ports is obtained, the corresponding bandwidth allocation strategy of the in-place identifier can be determined by table lookup. Finally, according to the determined bandwidth allocation strategy, the PCIe root port can be divided into a second number of sub-ports, and a port bandwidth can be allocated to each sub-port in the second number of sub-ports, thereby completing the PCIe bandwidth allocation process.

[0067] In the above manner, the additional resistance can be avoided to be welded on the PCIe Riser card, and the Riser ID does not need to be read through the IPMI, thereby reducing the consumption of hardware resources and the boot time, and the PCIe bandwidth resources can be efficiently and conveniently allocated. In addition, in the prior art, the Riser ID is often obtained by relying on the BMC (Baseboard Management Controller) or the CPLD (Complex Programmable Logic Device), and the technical scheme provided by the present application has no correlation with the two, thereby reducing the coupling degree with the BMC or the CPLD and improving the stability of the system as a whole.

[0068] Referring to Figure 5 The present application also provides a basic input and output system, which comprises:

[0069] A sub-port initialization unit is configured to divide the PCIe root port into a first number of sub-ports according to a minimum bandwidth unit when the basic input and output system is powered on for self-checking.

[0070] An in-place identifier generation unit is configured to identify whether an external device is connected under each sub-port in the first number of sub-ports, and generate an in-place identifier of each sub-port according to the identification result.

[0071] A reading unit is configured to read a bandwidth configuration table, and the bandwidth configuration table is configured to represent the matching relationship between the in-place identifier and the bandwidth allocation strategy.

[0072] The query unit is configured to query, from the bandwidth configuration table, a target bandwidth allocation strategy that matches the first quantity of in-place identifiers.

[0073] The re-allocation unit is configured to divide the PCIe root port into a second quantity of sub-ports according to the target bandwidth allocation strategy, and allocate port bandwidth for each of the second quantity of sub-ports.

[0074] In an embodiment, the in-place identifier generation unit comprises: a flag bit query module configured to query a link layer flag bit in a configuration space register corresponding to the sub-port; and an external device determination module configured to determine that the sub-port is connected to an external device if a parameter value in the link layer flag bit is 1, and determine that the sub-port is not connected to an external device if the parameter value is 0.

[0075] In an embodiment, the query unit is further configured to arrange the in-place identifier of each of the plurality of sub-ports in sequence according to a naming order of the plurality of sub-ports, and take the arrangement result as the first quantity of in-place identifiers.

[0076] In an embodiment, the bandwidth configuration table comprises standard in-place identifiers and other in-place identifiers in addition to the standard in-place identifiers, and the system further comprises: a bit operation unit configured to perform bit operation on each of the other in-place identifiers and each of the standard in-place identifiers, the bit operation being configured to convert each value bit in the standard in-place identifier into a corresponding value bit in the other in-place identifier; an identification unit configured to identify one or more standard in-place identifiers that match the other in-place identifier based on a bit operation result; and a bandwidth allocation unit configured to take a bandwidth allocation strategy corresponding to the one or more standard in-place identifiers as a bandwidth allocation strategy corresponding to the other in-place identifier.

[0077] In an embodiment, the bit operation unit comprises: a determination module configured to determine, for each of the standard in-place identifiers, whether there is a value bit that is converted from a first value to a second value in a process of converting from the standard in-place identifier to the other in-place identifier, and take the determination result as the bit operation result; wherein the first value represents that a sub-port is not connected to an external device, and the second value represents that the sub-port is connected to an external device.

[0078] In an embodiment, the bit operation unit comprises: an identifier matching module configured to take the standard in-place identifier as one standard in-place identifier that matches the other in-place identifier if the bit operation result represents that there is no value bit that is converted from the first value to the second value.

[0079] In one embodiment, the re-allocation unit is further configured to: if there are multiple target bandwidth allocation strategies matching the first number of in-place identifiers, select one of the multiple target bandwidth allocation strategies, and divide the PCIe root port into a second number of sub-ports according to the selected target bandwidth allocation strategy, and allocate port bandwidth to each of the second number of sub-ports.

[0080] One embodiment of the present application further provides a computer device, in which the basic input / output system is deployed.

[0081] One embodiment of the present application further provides a computer storage medium, in which a computer program is stored, and the computer program is executed by a processor to implement the PCIe bandwidth allocation method.

[0082] The processor can be a central processing unit (CPU). The processor can also be other general-purpose processors, a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field-programmable gate array (FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, or a combination thereof.

[0083] The memory is a non-transitory computer readable storage medium, and can be used to store non-transitory software programs, non-transitory computer executable programs and modules, such as program instructions / modules corresponding to the method in the embodiments of the present application. The processor executes various functions and data processing of the processor by running the non-transitory software programs, instructions and modules stored in the memory, that is, implements the method in the method embodiments.

[0084] The memory can include a program storage area and a data storage area. The program storage area can store an operating system and at least one application required by a function. The data storage area can store data created by the processor and the like. In addition, the memory can include a high-speed random access memory, and can also include a non-transitory memory, such as at least one magnetic disk storage device, a flash memory device, or other non-transitory solid-state memory device. In some embodiments, the memory can optionally include a memory remotely disposed relative to the processor, and these remote memories can be connected to the processor through a network. Examples of the network include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network, and a combination thereof.

[0085] Those skilled in the art can understand that all or part of the processes in the above-mentioned embodiments can be completed by instructing the relevant hardware through a computer program, and the program can be stored in a computer readable storage medium. When the program is executed, it can include the processes of the above-mentioned embodiments of the method. The storage medium can be a magnetic disk, an optical disk, a read-only memory (ROM), a random access memory (RAM), a flash memory, a hard disk drive (HDD) or a solid-state drive (SSD), etc. The storage medium can also include a combination of the above-mentioned types of memories.

[0086] Although the embodiments of the present application are described in conjunction with the drawings, various modifications and changes can be made by those skilled in the art without departing from the spirit and scope of the present application, and such modifications and changes fall within the scope defined by the appended claims.

Claims

1. A PCIe bandwidth allocation method, characterized by, The method is applied to a basic input output system, and the method comprises: In a power-on self-test of the basic input output system, PCIe root ports are divided into a first number of sub-ports according to minimum bandwidth units; It is identified whether an external device is connected to each of the first number of sub-ports, and a bit position identifier of each of the sub-ports is generated according to an identification result; A bandwidth configuration table is read, and the bandwidth configuration table is used to represent a matching relationship between the bit position identifier and a bandwidth allocation strategy; From the bandwidth configuration table, a target bandwidth allocation strategy matching the first number of bit position identifiers is queried; According to the target bandwidth allocation strategy, the PCIe root ports are divided into a second number of sub-ports, and each of the second number of sub-ports is allocated a port bandwidth.

2. The method of claim 1, wherein, The identification whether a network device is connected to each of the first number of sub-ports comprises: A link layer flag bit in a configuration space register corresponding to the sub-port is queried; If a parameter value in the link layer flag bit is 1, it is represented that the sub-port is connected to an external device, and if the parameter value is 0, it is represented that the sub-port is not connected to an external device.

3. The method according to claim 1 or 2, characterized in that, The first number of bit position identifiers are generated in the following manner: Bit position identifiers of each of the sub-ports are arranged in sequence according to a naming order of the plurality of sub-ports, and the arrangement result is taken as the first number of bit position identifiers.

4. The method of claim 1, wherein, The bandwidth configuration table comprises standard bit position identifiers and other bit position identifiers except the standard bit position identifiers; The standard bit position identifiers are pre-configured with respective bandwidth allocation strategies, and the bandwidth allocation strategies corresponding to the other bit position identifiers are determined in the following manner: For any other bit position identifier, the other bit position identifier is subjected to a bit operation with each of the standard bit position identifiers, and the bit operation is used to convert each value bit in the standard bit position identifier into a corresponding value bit in the other bit position identifier; Based on a bit operation result, one or more standard bit position identifiers matching the other bit position identifier are identified; The bandwidth allocation strategies corresponding to the one or more standard bit position identifiers are taken as the bandwidth allocation strategies corresponding to the other bit position identifier.

5. The method of claim 4, wherein, The bit operation of the other bit position identifier with each of the standard bit position identifiers comprises: For any standard bit position identifier, it is judged whether there is a value bit changing from a first value to a second value in a process of changing from the standard bit position identifier to the other bit position identifier, and the judgment result is taken as a bit operation result; The first value represents that a sub-port is not connected to an external device, and the second value represents that the sub-port is connected to an external device.

6. The method of claim 5, wherein, The identification of one or more standard bit position identifiers matching the other bit position identifier based on the bit operation result comprises: If the bit operation result represents that there is no value bit changing from the first value to the second value, the standard bit position identifier is taken as one standard bit position identifier matching the other bit position identifier.

7. The method of claim 1, wherein, The method further comprises: If there are multiple target bandwidth allocation strategies matching the first number of in-situ identifiers, an optional target bandwidth allocation strategy is selected from the multiple target bandwidth allocation strategies, the PCIe root port is divided into a second number of sub-ports according to the optional target bandwidth allocation strategy, and port bandwidth is allocated to each of the second number of sub-ports.

8. A basic input / output system, characterized by, The basic input and output system comprises: A sub-port initialization unit configured to divide the PCIe root port into a first number of sub-ports according to a minimum bandwidth unit when the basic input and output system is powered on and self-checked. An in-situ identifier generation unit configured to identify whether an external device is connected to each of the first number of sub-ports, and generate an in-situ identifier for each of the sub-ports according to the identification result. A reading unit configured to read a bandwidth configuration table, the bandwidth configuration table being used to represent a matching relationship between in-situ identifiers and bandwidth allocation strategies. A querying unit configured to query, from the bandwidth configuration table, a target bandwidth allocation strategy matching the first number of in-situ identifiers. A reallocation unit configured to divide the PCIe root port into a second number of sub-ports according to the target bandwidth allocation strategy, and allocate port bandwidth to each of the second number of sub-ports.

9. The basic input / output system of claim 8, wherein, The in-situ identifier generation unit comprises: A flag bit querying module configured to query a link layer flag bit in a configuration space register corresponding to the sub-port. An external device determination module configured to determine that the sub-port is connected to an external device if a parameter value in the link layer flag bit is 1, and determine that the sub-port is not connected to an external device if the parameter value is 0.

10. The basic input / output system of claim 8, wherein, The querying unit is further configured to arrange the in-situ identifiers of the sub-ports in sequence according to a naming order of the sub-ports, and take the arrangement result as the first number of in-situ identifiers.

11. The basic input / output system of claim 8, wherein, The bandwidth configuration table comprises standard in-situ identifiers and other in-situ identifiers except the standard in-situ identifiers. The basic input and output system further comprises: A bit operation unit configured to perform bit operation on each of the other in-situ identifiers and each of the standard in-situ identifiers, the bit operation being used to convert each value bit in the standard in-situ identifier into a corresponding value bit in the other in-situ identifier. An identification unit configured to identify one or more standard in-situ identifiers matching the other in-situ identifier based on a bit operation result. A bandwidth allocation unit configured to take a bandwidth allocation strategy corresponding to the one or more standard in-situ identifiers as a bandwidth allocation strategy corresponding to the other in-situ identifier.

12. The basic input / output system of claim 11, wherein, The bit operation unit comprises a judgment module configured to judge whether there is a value bit changing from a first value to a second value in a process of changing from the standard in-situ identifier to the other in-situ identifier, and take a judgment result as a bit operation result, wherein the first value represents that a sub-port is not connected to an external device, and the second value represents that the sub-port is connected to an external device.

13. The basic input / output system of claim 12, wherein, The bit operation unit comprises an identification matching module, configured to, if the bit operation result represents that there is no bit of a number value changing from a first number value to a second number value, take the standard in-bit identification as one standard in-bit identification matching the other in-bit identifications.

14. The basic input / output system of claim 8, wherein, The re-distribution unit is further configured to, if there are multiple target bandwidth allocation strategies matching the first number of in-bit identifications, select one target bandwidth allocation strategy from the multiple target bandwidth allocation strategies, and divide the PCIe root port into a second number of sub-ports according to the selected target bandwidth allocation strategy, and allocate port bandwidth to each of the second number of sub-ports.

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