Method for manufacturing semiconductor device

Abstract

A method for manufacturing a semiconductor device includes: a first step of providing a first wiring (3) on a first surface (2a) of a semiconductor substrate (2); a second step of installing a light-transmitting substrate (5) on the first surface (2a); a third step of thinning the semiconductor substrate (2) in such a manner that the thickness of the semiconductor substrate (2) is smaller than the thickness of the light-transmitting substrate (5); a fourth step of forming a through hole (7) in the semiconductor substrate (2); a fifth step of providing a resin insulating layer (10) by dip coating using a first resin material; a sixth step of forming a contact hole (16) in the resin insulating layer (10); and a seventh step of providing a second wiring (8) on a surface (10b) of the resin insulating layer (10) and electrically connecting the first wiring (3) and the second wiring (8) in the contact hole (16).

Description

[0001] (This application is a divisional application of a patent application filed on March 31, 2016, with application number 201680019440.9 and title “Method for manufacturing a semiconductor device.”) Technical Field

[0002] The present invention relates to a method for manufacturing a semiconductor device. Background Art

[0003] In semiconductor devices such as optical devices and electronic devices, electrical connection is sometimes made between the front and back sides of a semiconductor substrate via through-holes formed in the semiconductor substrate (see, for example, Patent Document 1).

[0004] Prior art literature

[0005] Patent Literature

[0006] Patent Document 1: Japanese Patent Application Laid-Open No. 2004-57507 Summary of the Invention

[0007] Problems to be solved by the invention

[0008] In semiconductor devices such as those described above, the trend is towards thinner thicknesses as they become increasingly miniaturized and highly integrated. Consequently, during semiconductor device manufacturing, damage is easily incurred around the through-holes, and it is difficult to ensure electrical insulation between the wiring within the through-holes and the semiconductor substrate.

[0009] Therefore, an object of the present invention is to provide a method for manufacturing a semiconductor device that can reduce the thickness of a semiconductor substrate while preventing damage to the periphery of a through-hole and ensuring electrical insulation between wiring in the through-hole and the semiconductor substrate.

[0010] Technical means to solve the problem

[0011] A method for manufacturing a semiconductor device according to one embodiment of the present invention includes: a first step of providing a first wiring on the first surface of a semiconductor substrate having a first surface and a second surface facing each other; a second step of mounting a support substrate on the first surface after the first step; a third step of thinning the semiconductor substrate by removing a portion of the second surface side of the semiconductor substrate after the second step, thereby making the thickness of the semiconductor substrate smaller than the thickness of the support substrate; and a fourth step of forming a through hole in the semiconductor substrate extending from the first surface to the second surface, and forming a through hole on the first surface of the through hole. a fifth process, after the fourth process, providing a resin insulating layer continuous with the second opening on the second surface side of the through hole on the inner surface and the second surface of the through hole by performing a dip coating method using the first resin material; a sixth process, after the fifth process, forming a contact hole in the resin insulating layer, and exposing a portion of the first wiring at the opening on the first surface side of the contact hole; and a seventh process, after the sixth process, providing a second wiring on the surface of the resin insulating layer, and electrically connecting the first wiring and the second wiring in the opening on the first surface side of the contact hole.

[0012] In this semiconductor device manufacturing method, all subsequent steps after the step of thinning the semiconductor substrate are performed with the support substrate mounted on the semiconductor substrate. This prevents damage to the periphery of the through-hole. Furthermore, the resin insulation layer is formed by dip coating. This reliably forms a resin insulation layer of sufficient thickness to ensure electrical insulation. Therefore, according to this semiconductor device manufacturing method, the semiconductor substrate can be thinned while preventing damage to the periphery of the through-hole and ensuring electrical insulation between the wiring within the through-hole and the semiconductor substrate.

[0013] In a semiconductor device manufacturing method according to one embodiment of the present invention, in the fifth step, the semiconductor substrate, to which the support substrate is attached, may be impregnated with the stored first resin material so that the liquid level of the stored first resin material intersects the first surface, and the semiconductor substrate, to which the support substrate is attached, may be pulled up from the stored first resin material so that the liquid level of the stored first resin material intersects the first surface. This reduces stress generated in the peripheral portion of the through-hole compared to, for example, a case where the impregnation and pull-up are performed with the liquid level of the stored first resin material parallel to the first surface of the semiconductor substrate. Furthermore, it is possible to suppress the presence of bubbles in the resin insulation layer formed on the inner surface of the through-hole compared to, for example, a case where the impregnation and pull-up are performed with the liquid level of the stored first resin material parallel to the first surface of the semiconductor substrate.

[0014] In the semiconductor device manufacturing method according to one embodiment of the present invention, a dip coating method may be performed using a first resin material having a viscosity of 10 cp or higher in the fifth step. This allows for more reliable formation of a resin insulating layer having a sufficient thickness to ensure electrical insulation.

[0015] In the semiconductor device manufacturing method according to one embodiment of the present invention, the first resin material attached to the surface of the support substrate opposite to the semiconductor substrate in the fifth step may be removed in the sixth step. Thus, for example, when the semiconductor device is an optical device, even if a light-transmitting substrate is used as the support substrate, the first resin material can be removed from the support substrate, thereby enabling the support substrate to effectively function as a light-transmitting substrate.

[0016] The semiconductor device manufacturing method according to one embodiment of the present invention may further include: an eighth step of, after the seventh step, applying a dip coating method using a second resin material to form a resin protective layer on the surface of the resin insulating layer so as to cover the second wiring; and a ninth step of, after the eighth step, forming an opening in the resin protective layer and exposing a portion of the second wiring in the opening. This ensures that a resin protective layer of sufficient thickness to protect the second wiring can be formed. Furthermore, a portion of the second wiring can be used as a pad for external electrical connection.

[0017] In a method for manufacturing a semiconductor device according to one embodiment of the present invention, in step 8, the semiconductor substrate, to which a support substrate is attached, may be impregnated with the stored second resin material so that the liquid level of the stored second resin material intersects the first surface, and the semiconductor substrate, to which the support substrate is attached, may be pulled up from the stored second resin material so that the liquid level of the stored second resin material intersects the first surface. This reduces stress generated in the periphery of the through-hole compared to, for example, a case where the impregnation and pull-up process is performed with the liquid level of the stored second resin material parallel to the first surface of the semiconductor substrate. Furthermore, compared to, for example, a case where the impregnation and pull-up process is performed with the liquid level of the stored second resin material parallel to the first surface of the semiconductor substrate, it is possible to suppress the presence of bubbles in the resin protective layer formed in the region corresponding to the through-hole.

[0018] In the semiconductor device manufacturing method according to one embodiment of the present invention, a second resin material having a viscosity of 10 cp or higher may be dip-coated in step 8. This allows for more reliable formation of a resin protective layer having a sufficient thickness to protect the second wiring.

[0019] In the semiconductor device manufacturing method according to one embodiment of the present invention, the second resin material attached to the surface of the support substrate opposite to the semiconductor substrate in the eighth step may be removed in the ninth step. Thus, for example, when the semiconductor device is an optical device, even if a light-transmitting substrate is used as the support substrate, the second resin material can be removed from the support substrate, thereby enabling the support substrate to effectively function as a light-transmitting substrate.

[0020] In the semiconductor device manufacturing method according to one embodiment of the present invention, the first resin material and the second resin material may be the same. Thus, even if the resin insulating layer and the resin protective layer deform due to temperature changes, the extent of their deformation is equal, thereby preventing damage to the second wiring due to significantly different degrees of deformation.

[0021] Effects of the Invention

[0022] According to the present invention, a method for manufacturing a semiconductor device can be provided that can reduce the thickness of a semiconductor substrate while preventing damage to the periphery of a through-hole and ensuring electrical insulation between wiring in the through-hole and the semiconductor substrate. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1 This is a cross-sectional view of a semiconductor device according to one embodiment of the present invention.

[0024] Figure 2 yes Figure 1 A cross-sectional view of a through hole and its surrounding portion of a semiconductor device.

[0025] Figure 3 yes Figure 1 A top view of a through hole and its surrounding area of ​​a semiconductor device.

[0026] Figure 4 (a) and (b) are used to illustrate Figure 1 A cross-sectional view illustrating one step of a method for manufacturing a semiconductor device.

[0027] Figure 5 (a) and (b) are used to illustrate Figure 1 A cross-sectional view illustrating one step of a method for manufacturing a semiconductor device.

[0028] Figure 6 (a) and (b) are used to illustrate Figure 1 A cross-sectional view illustrating one step of a method for manufacturing a semiconductor device.

[0029] Figure 7 (a) and (b) are used to illustrate Figure 1 A cross-sectional view illustrating one step of a method for manufacturing a semiconductor device.

[0030] Figure 8 (a) and (b) are used to illustrate Figure 1 A cross-sectional view illustrating one step of a method for manufacturing a semiconductor device.

[0031] Figure 9 Is used to illustrate Figure 1 A cross-sectional view illustrating one step of a method for manufacturing a semiconductor device.

[0032] Figure 10 yes Figure 1 A partial cross-sectional view of a semiconductor device.

[0033] Figure 11 yes Figure 1 A partial cross-sectional view of a modified example of a semiconductor device.

[0034] Figure 12 yes Figure 1 A partial cross-sectional view of a modified example of a semiconductor device.

[0035] Figure 13 yes Figure 12 A top view of a through hole and its surrounding area of ​​a semiconductor device.

[0036] Figure 14 yes Figure 1 A cross-sectional view of a modified example of a through hole and its surrounding portion of a semiconductor device. DETAILED DESCRIPTION

[0037] Hereinafter, the embodiment of the present invention will be described in detail with reference to the accompanying drawings. In addition, the same or corresponding parts are marked with the same reference numerals in each figure, and repeated description is omitted.

[0038] like Figure 1 As shown, the semiconductor device 1 includes a semiconductor substrate 2 having a first surface 2a and a second surface 2b facing each other. The semiconductor device 1 is an optical device such as a silicon photodiode. In the semiconductor device 1, a p-type region 2c in which p-type impurities are selectively diffused is provided in a predetermined area on the first surface 2a side of the semiconductor substrate 2 composed of, for example, n-type silicon. On the first surface 2a of the semiconductor substrate 2, a first wiring 3 composed of, for example, aluminum is provided via an oxide film 4. An opening 4a is formed in the oxide film 4 in a portion corresponding to the pad portion 3a of the first wiring 3. An opening 4b is formed in the oxide film 4 in a portion corresponding to the end of the p-type region 2c. The first wiring 3 is electrically connected to the p-type region 2c via the opening 4b. In addition, an insulating film composed of another insulating material such as SiN may be provided instead of the oxide film 4.

[0039] A light-transmitting substrate 5 made of a light-transmitting material such as glass is disposed on the first surface 2a of the semiconductor substrate 2. The semiconductor substrate 2 and the light-transmitting substrate 5 are optically and physically connected by an adhesive layer 6 made of an optical adhesive. In the semiconductor device 1, light enters the p-type region 2c via the light-transmitting substrate 5 and the adhesive layer 6. In addition, the thickness of the semiconductor substrate 2 is smaller (thinner) than the thickness of the light-transmitting substrate 5. As an example, the thickness of the semiconductor substrate 2 is about tens of μm, and the thickness of the light-transmitting substrate 5 is about hundreds of μm.

[0040] A through hole 7 is formed in the semiconductor substrate 2, extending from the first surface 2a to the second surface 2b. The first opening 7a of the through hole 7 is located on the first surface 2a of the semiconductor substrate 2, and the second opening 7b of the through hole 7 is located on the second surface 2b of the semiconductor substrate 2. The first opening 7a is continuous with the opening 4a of the oxide film 4 and is covered by the pad portion 3a of the first wiring 3. The inner surface 7c of the through hole 7 is a tapered surface that expands from the first surface 2a toward the second surface 2b. For example, the through hole 7 is formed in the shape of a quadrangular pyramid that expands from the first surface 2a toward the second surface 2b. In addition, when viewed from a direction parallel to the center line CL of the through hole 7, the edge of the first opening 7a of the through hole 7 does not need to coincide with the edge of the opening 4a of the oxide film 4. For example, the edge of the opening 4a of the oxide film 4 may be located inside the edge of the first opening 7a of the through hole 7.

[0041] The aspect ratio of through-hole 7 is 0.2 to 10. The aspect ratio is the value obtained by dividing the depth of through-hole 7 (the distance between first opening 7a and second opening 7b) by the width of second opening 7b (the distance between opposite sides of second opening 7b if second opening 7b is rectangular, or the diameter of second opening 7b if second opening 7b is circular). As an example, the depth of through-hole 7 is 30 μm, and the width of second opening 7b is 130 μm. In this case, the aspect ratio is 0.23.

[0042] A resin insulating layer 10 is provided on the inner surface 7c of the through-hole 7 and the second surface 2b of the semiconductor substrate 2. The resin insulating layer 10 is continuous through the second opening 7b of the through-hole 7. Inside the through-hole 7, the resin insulating layer 10 reaches the pad 3a of the first wiring 3 through the opening 4a of the oxide film 4, and has an opening 10a on the first surface 2a side of the semiconductor substrate 2.

[0043] A second wiring 8, for example, made of aluminum, is provided on the surface 10b of the resin insulating layer 10 (the surface opposite to the inner surface 7c of the through-hole 7 and the second surface 2b of the semiconductor substrate 2). The second wiring 8 is electrically connected to the pad 3a of the first wiring 3 within the opening 10a of the resin insulating layer 10. Furthermore, a third wiring 22, for example, made of aluminum, is provided on the surface 10b of the resin insulating layer 10 (the surface opposite to the second surface 2b of the semiconductor substrate 2). The third wiring 22 is electrically connected to the second surface 2b of the semiconductor substrate 2 within the opening 10c formed in the resin insulating layer 10.

[0044] The second wiring 8 and the third wiring 22 are covered by a resin protective layer 21. A shallow recess 21a having a smooth inner surface is formed in the portion of the resin protective layer 21 corresponding to the through hole 7. An opening 21b is formed in the portion of the resin protective layer 21 corresponding to the pad 8a of the second wiring 8, exposing the pad 8a. An opening 21c is formed in the portion of the resin protective layer 21 corresponding to the pad 22a of the third wiring 22, exposing the pad 22a. A bump electrode, i.e., a lead-out electrode 9, is disposed in the opening 21b of the resin protective layer 21. The lead-out electrode 9 is electrically connected to the pad 8a of the second wiring 8. A bump electrode, i.e., a lead-out electrode 23, is disposed in the opening 21c of the resin protective layer 21. The lead-out electrode 23 is electrically connected to the pad 22a of the third wiring 22. The semiconductor device 1 is mounted on the circuit board via the extraction electrodes 9 and 23, and the extraction electrodes 9 and 23 function as an anode electrode and a cathode electrode, respectively. Alternatively, a protective layer made of another insulating material (e.g., an oxide film, a nitride film, etc.) may be provided in place of the resin protective layer 21. Furthermore, the thickness of the resin protective layer 21 may be approximately the same as the thickness of the resin insulating layer 10, or may be smaller than the thickness of the resin insulating layer 10. In particular, if the thickness of the resin protective layer 21 is approximately the same as the thickness of the resin insulating layer 10, the stress acting on the second wiring 8 and the third wiring 22 can be reduced.

[0045] Regarding the resin insulating layer 10, Figure 2 , while explaining in more detail. Figure 2 In the embodiment, the light-transmitting substrate 5, the adhesive layer 6 and the resin protective layer 21 are omitted.

[0046] like Figure 2 As shown, the surface 10b of the resin insulating layer 10 includes: a first region 11, which reaches the first opening 7a on the inner side of the through hole 7; a second region 12, which reaches the second opening 7b on the inner side of the through hole 7; and a third region 13, which is opposite to the second surface 2b of the semiconductor substrate 2 on the outer side of the through hole 7.

[0047] The first region 11 is a tapered region that expands from the first surface 2a of the semiconductor substrate 2 toward the second surface 2b. The first region 11 has an average tilt angle α. The average tilt angle α of the first region 11 is the average value of the angles formed by the intersection of a plane containing the center line CL of the through-hole 7 and the first region 11 with respect to the first surface 2a, with the focus on the area on one side of the center line CL. If the intersection is a straight line, the angle formed by the straight line and the first surface 2a is the average tilt angle α of the first region 11. If the intersection is a curve, the average value of the angles formed by the connecting line of the curve and the first surface 2a is the average tilt angle α of the first region 11. The average tilt angle α of the first region 11 is greater than 0° and less than 90°.

[0048] The second region 12 is a tapered region that expands from the first surface 2a of the semiconductor substrate 2 toward the second surface 2b. The second region 12 has an average tilt angle β. The average tilt angle β of the second region 12 is the average value of the angles formed by the intersection of the plane containing the center line CL of the through-hole 7 and the second region 12 with respect to the first surface 2a, with the focus on the area on one side of the center line CL. If the intersection is a straight line, the angle formed by the straight line and the first surface 2a is the average tilt angle β of the second region 12. If the intersection is a curve, the average value of the angles formed by the connecting line of the curve and the first surface 2a is the average tilt angle β of the second region 12. The average tilt angle β of the second region 12 is greater than 0° and less than 90°.

[0049] The average inclination angle β of the second region 12 is smaller than the average inclination angle α of the first region 11. That is, the second region 12 has a slope that is gentler than that of the first region 11. In addition, the average inclination angle β of the second region 12 is smaller than the average inclination angle γ of the inner surface 7c of the through-hole 7. That is, the second region 12 has a slope that is gentler than that of the inner surface 7c of the through-hole 7. In this embodiment, the average inclination angle α of the first region 11 is closer to the average inclination angle γ of the inner surface 7c of the through-hole 7 than the average inclination angle β of the second region 12. Here, the average inclination angle α of the first region 11 > the average inclination angle γ of the inner surface 7c of the through-hole 7 > the average inclination angle β of the second region 12. The so-called average inclination angle γ of the inner surface 7c of the through-hole 7 is the average value of the angles formed by the intersection of a plane containing the center line CL of the through-hole 7 and the inner surface 7c with respect to the first surface 2a, with the focus on the area on one side of the center line CL. When the intersection line is a straight line, the angle formed by the straight line and the first surface 2a becomes the average inclination angle γ of the inner surface 7c of the through-hole 7. When the intersection line is a curve, the average value of the angles formed by the connecting line of the curve and the first surface 2a becomes the average inclination angle γ of the inner surface 7c of the through-hole 7.

[0050] The surface 10b of the resin insulating layer 10 further includes a fourth region 14 having a maximum curvature that is convex toward the side opposite to the inner surface 7c of the through-hole 7, and a fifth region 15 that extends along the edge of the second opening 7b of the through-hole 7. The maximum curvature that is convex toward the side opposite to the inner surface 7c of the through-hole 7 refers to the maximum curvature of the portion of the intersection of a plane containing the center line CL of the through-hole 7 and the surface 10b that curves convexly toward the side opposite to the inner surface 7c of the through-hole 7, with the focus on the area on one side of the center line CL. Furthermore, the first region 11 is a region of the surface 10b of the resin insulating layer 10 provided on the inner surface 7c of the through-hole 7 that is closer to the first opening 7a of the through-hole 7 (the first opening 7a side in a direction parallel to the center line CL of the through-hole 7) than the fourth region 14. The second region 12 is a region on the surface 10b of the resin insulation layer 10 arranged on the inner surface 7c of the through hole 7, which is closer to the second opening 7b side of the through hole 7 (the second opening 7b side in a direction parallel to the center line CL of the through hole 7) than the fourth region 14 (i.e., the region between the fourth region 14 and the fifth region 15).

[0051] The fourth region 14 is curved so as to continuously connect the first region 11 and the second region 12. That is, the fourth region 14 is a curved surface with rounded corners that smoothly connects the first region 11 and the second region 12. Assuming that the fourth region 14 does not exist, and that the first region 11 extends toward the second surface 2b of the semiconductor substrate 2, and the second region 12 extends toward the first surface 2a of the semiconductor substrate 2, an intersection line (corner, curved portion) is formed by the first region 11 and the second region 12. The fourth region 14 corresponds to the curved surface formed when this intersection line (corner, curved portion) is rounded. The fourth region 14 is the portion of the intersection line between the plane containing the center line CL of the through-hole 7 and the surface 10b, between the portion corresponding to the first region 11 and the portion corresponding to the second region 12, that curves convexly toward the side opposite to the inner surface 7c of the through-hole 7.

[0052] The fifth region 15 is curved so as to continuously connect the second region 12 and the third region 13. That is, the fifth region 15 is a curved surface with rounded corners that smoothly connects the second region 12 and the third region 13. Assuming that the fifth region 15 does not exist, and that the second region 12 extends toward the second surface 2b of the semiconductor substrate 2, and the third region 13 extends toward the center line CL of the through-hole 7, an intersection line (corner, curved portion, etc.) is formed by the second region 12 and the third region 13. The fifth region 15 corresponds to the curved surface formed when this intersection line (corner, curved portion, etc.) is rounded. The fifth region 15 is a portion that curves convexly toward the side opposite to the edge of the second opening 7b of the through-hole 7, between the portion corresponding to the second region 12 and the portion corresponding to the third region 13 of the intersection line of the plane containing the center line CL of the through-hole 7, with the focus on the area on one side of the center line CL.

[0053] In this embodiment, the first region 11, the fourth region 14, and the fifth region 15 are curved surfaces that curve convexly toward the side opposite to the inner surface 7c of the through-hole 7. The second region 12 is a curved surface that curves convexly toward the inner surface 7c of the through-hole 7 (i.e., a curved surface that curves concavely when viewed from the side opposite to the inner surface 7c of the through-hole 7). The third region 13 is a plane that is substantially parallel to the second surface 2b of the semiconductor substrate 2. As described above, the fourth region 14 is curved to continuously connect the first region 11 and the second region 12, and the fifth region 15 is curved to continuously connect the second region 12 and the third region 13. As a result, the surface 10b of the resin insulating layer 10 is a continuous surface (a surface in which the regions 11, 12, 13, 14, and 15 are smoothly connected, with no discontinuous areas such as intersections (corners, bends, etc.) between the surfaces).

[0054] The average thickness of resin insulating layer 10 provided on inner surface 7c of through-hole 7 is greater than the average thickness of resin insulating layer 10 provided on second surface 2b of semiconductor substrate 2. The average thickness of resin insulating layer 10 provided on inner surface 7c of through-hole 7 is the average thickness of resin insulating layer 10 in a direction perpendicular to inner surface 7c. The average thickness of resin insulating layer 10 provided on second surface 2b of semiconductor substrate 2 is the average thickness of resin insulating layer 10 in a direction perpendicular to second surface 2b.

[0055] In a direction parallel to the first surface 2a and the second surface 2b of the semiconductor substrate 2, the average thickness of the portion of the resin insulating layer 10 corresponding to the first region 11 is greater than the average thickness of the portion of the resin insulating layer 10 corresponding to the second region 12. The average thickness of the portion of the resin insulating layer 10 corresponding to the first region 11 in a direction parallel to the first surface 2a and the second surface 2b of the semiconductor substrate 2 is the average value of the distance between the first region 11 and the inner surface 7c of the through-hole 7 in that direction. The average thickness of the portion of the resin insulating layer 10 corresponding to the second region 12 in a direction parallel to the first surface 2a and the second surface 2b of the semiconductor substrate 2 is the average value of the distance between the second region 12 and the inner surface 7c of the through-hole 7 in that direction.

[0056] In the resin insulating layer 10, the first region 11 is a portion of the resin insulating layer 10 provided on the inner surface 7c of the through-hole 7, the portion having a height H from the first surface 2a of the semiconductor substrate 2. The height H is equal to or less than 1 / 2 of the sum D of the thickness of the semiconductor substrate 2 (i.e., the distance between the first surface 2a and the second surface 2b) and the average thickness of the resin insulating layer 10 provided on the second surface 2b of the semiconductor substrate 2.

[0057] In the resin insulating layer 10, a surface S passing through the edge of the opening 10a of the resin insulating layer 10 and the edge of the second opening 7b of the through-hole 7 is set as a boundary surface. If the portion P1 on the inner surface 7c side of the through-hole 7 relative to the surface S and the portion P2 on the opposite side of the inner surface 7c of the through-hole 7 relative to the surface S are considered, the volume of the portion P1 is larger than the volume of the portion P2. In addition, in the resin insulating layer 10, if the area on one side of the center line CL of the plane including the center line CL of the through-hole 7 is considered, the area of ​​the triangle T1 is larger than the area of ​​the triangle T2. The triangle T1 is in the plane including the center line CL of the through-hole 7 (i.e., in the plane including the center line CL of the through-hole 7). Figure 2 The triangle T2 is formed in a plane including the center line CL of the through hole 7 (i.e., Figure 2 ), a triangle having the edge of the opening 10a of the resin insulating layer 10, the edge of the second opening 7b of the through-hole 7, and the top of the fourth region 14 as vertices.

[0058] The resin insulating layer 10 has a first bent portion 101, a second bent portion 102, and a third bent portion 103. The first bent portion 101 covers the inner surface 7c of the through-hole 7 between the first opening 7a and the second opening 7b. The second bent portion 102 covers the edge of the second opening 7b of the through-hole 7 (i.e., the intersection of the second surface 2b of the semiconductor substrate 2 and the inner surface 7c of the through-hole). The second bent portion 102 is formed so as to span the second surface 2b of the semiconductor substrate 2 and the inner surface 7c of the through-hole. In this embodiment, regardless of whether the shape of the edge of the second opening 7b is rectangular or circular, the edge of the second opening 7b does not become chamfered, but becomes a corner (edge). The second bent portion 102 covers the corner. The third bent portion 103 covers the inner surface 7c of the through-hole 7 between the first bent portion 101 and the second bent portion 102. The first curved portion 101 and the third curved portion 103 are separated from each other, and the second curved portion 102 and the third curved portion 103 are separated from each other. The surface 10b of the resin insulating layer 10 in the first curved portion 101 (corresponding to the fourth region 14 in this embodiment) is convexly curved toward the side opposite to the inner surface 7c of the through-hole 7. The surface 10b of the resin insulating layer 10 in the second curved portion 102 (corresponding to the fifth region 15 in this embodiment) is convexly curved toward the side opposite to the inner surface 7c of the through-hole 7. The surface 10b of the resin insulating layer 10 in the third curved portion 103 (corresponding to the second region 12 in this embodiment) is convexly curved toward the inner surface 7c of the through-hole 7 (i.e., concavely curved when viewed from the side opposite to the inner surface 7c of the through-hole 7). The curvature of the surface 10b of the resin insulating layer 10 in the first curved portion 101 is different from the curvature of the surface 10b of the resin insulating layer 10 in the second curved portion 102.

[0059] The term "curving convexly toward the side opposite to the inner surface 7c of the through-hole 7" means that, with respect to a plane including the center line CL of the through-hole 7 and focusing on a region on one side of the center line CL, the intersection line of the plane and the surface 10b curves convexly toward the side opposite to the inner surface 7c of the through-hole 7. The term "curving convexly toward the side of the inner surface 7c of the through-hole 7" means that, with respect to a plane including the center line CL of the through-hole 7 and focusing on a region on one side of the center line CL, the intersection line of the plane and the surface 10b curves convexly toward the side of the inner surface 7c of the through-hole 7.

[0060] like Figure 3 As shown in FIG. 1 , when viewed from a direction parallel to the center line CL of the through hole 7, the outer edge of the second wiring 8 is located outside the second opening 7b of the through hole 7. That is, the outer edge of the second wiring 8 is located on the surface 10b of the resin insulating layer 10 that is opposite to the second surface 2b of the semiconductor substrate 2. Figure 3 In FIG. 1 , the resin insulating layer 10 is shown by a dotted line, and the second wiring 8 is shown by a two-dot chain line.

[0061] When the through-hole 7 is formed in a quadrangular pyramid shape that expands from the first surface 2a toward the second surface 2b, the distance from each corner of the second opening 7b of the through-hole 7 to the surface 10b of the resin insulating layer 10 (corresponding to the fifth region 15 in this embodiment) in the second curved portion 102, when viewed from a direction parallel to the center line CL of the through-hole 7, is greater than the distance from each side of the second opening 7b of the through-hole 7 to the surface 10b. As a result, the second curved portion 102 forms a more gently curved surface at each corner of the second opening 7b of the through-hole 7, thereby reliably preventing the edge of the second opening 7b of the through-hole 7 from being exposed and further reliably suppressing the occurrence of current leakage between the second wiring 8 and the semiconductor substrate 2.

[0062] Furthermore, on the surface 10b of the resin insulating layer 10 in the first bent portion 101 (corresponding to the fourth region 14 in this embodiment), when viewed from a direction parallel to the center line CL of the through-hole 7, the distance from each corner of the first opening 7a of the through-hole 7 to the surface 10b is greater than the distance from each side of the first opening 7a of the through-hole 7 to the surface 10b. Furthermore, when viewed from a direction parallel to the center line CL of the through-hole 7, the distance from the surface 10b of the resin insulating layer 10 in the second bent portion 102 (corresponding to the fifth region 15 in this embodiment) to the surface 10b of the resin insulating layer 10 in the second bent portion 102 (corresponding to the fifth region 15 in this embodiment) is greater at each corner of the first opening 7a of the through-hole 7 than at each side of the first opening 7a of the through-hole 7. Thus, although the corners (valleys) of the quadrangular pyramid-shaped through-holes 7 are portions where the insulating film is more likely to become thinner, the thickness of the resin insulating layer 10 can be sufficiently ensured in these corners (valleys).

[0063] As described above, in semiconductor device 1, resin insulating layer 10 includes second curved portion 102 covering the edge of second opening 7b of through-hole 7. Surface 10b of second curved portion 102 curves convexly toward the side opposite to inner surface 7c of through-hole 7. This ensures smooth connection between surface 10b of resin insulating layer 10 located on inner surface 7c of through-hole 7 and surface 10b of resin insulating layer 10 located on second surface 2b of semiconductor substrate 2. Consequently, disconnection of second wiring 8 in the second opening 7b of through-hole 7 can be prevented both during and after manufacturing. Furthermore, resin insulating layer 10 includes first curved portion 101 between first opening 7a and second opening 7b, covering inner surface 7c of through-hole 7. Surface 10b of first curved portion 101 curves convexly toward the side opposite to inner surface 7c of through-hole 7. Thus, even when the diameter of through-hole 7 is reduced, for example, the width of opening 10a of resin insulating layer 10 on the first surface 2a side of semiconductor substrate 2 can be sufficiently ensured. Therefore, disconnection of first wiring 3 and second wiring 8 in the opening 10a of resin insulating layer 10 can be prevented both during and after manufacturing. Therefore, according to semiconductor device 1, electrical connection of semiconductor substrate 2 via through-hole 7 can be made reliable.

[0064] In the semiconductor device 1, the resin insulating layer 10 further includes a third curved portion 103, which covers the inner surface 7c of the through-hole 7 between the first curved portion 101 and the second curved portion 102. The surface 10b of the third curved portion 103 is convexly curved toward the inner surface 7c of the through-hole 7. Thus, even if some external force acts from the second opening 7b side of the through-hole 7 toward the first opening 7a side, the third curved portion 103 functions as a buffer region. Consequently, stress generated at the connection between the first wiring 3 and the second wiring 8 can be reduced, further reliably preventing disconnection of the first wiring 3 and the second wiring 8.

[0065] In semiconductor device 1, the average thickness of resin insulating layer 10 provided on inner surface 7c of through-hole 7 is greater than the average thickness of resin insulating layer 10 provided on second surface 2b. Consequently, even when semiconductor substrate 2 is thinned, resin insulating layer 10 provided on inner surface 7c of through-hole 7 can function as a reinforcement layer, thereby ensuring sufficient strength around through-hole 7. Furthermore, the average tilt angles of first region 11 and second region 12 can be set to desired angles, resulting in a resin insulating layer 10 having a continuous surface 10b (a surface in which regions 11, 12, 13, 14, and 15 are smoothly connected, with no discontinuous areas such as intersections (corners, bends, etc.)). For example, if resin insulating layer 10 is formed with a uniform thickness along inner surface 7c of through-hole 7, it is impossible to obtain a resin insulating layer 10 having a continuous surface 10b.

[0066] In the semiconductor device 1 , the inner surface 7 c of the through hole 7 is a tapered surface that widens from the first surface 2 a toward the second surface 2 b . In this case, the electrical connection of the semiconductor substrate 2 through the through hole 7 can also be made more reliable.

[0067] In semiconductor device 1, first region 11 on surface 10b of resin insulating layer 10, which reaches first opening 7a of through-hole 7, and second region 12 on surface 10b of through-hole 7, which reaches second opening 7b of through-hole 7, are tapered regions that expand from first surface 2a toward second surface 2b of semiconductor substrate 2. Furthermore, the average inclination angle of second region 12 is smaller than the average inclination angle of inner surface 7c of through-hole 7. Consequently, the angle formed between third region 13 on surface 10b of resin insulating layer 10, which faces second surface 2b of semiconductor substrate 2, and second region 12 on surface 10b of through-hole 7, which reaches second opening 7b of through-hole 7, is larger (i.e., more gradual) than the angle formed between second surface 2b of semiconductor substrate 2 and inner surface 7c of through-hole 7. Consequently, disconnection of second wiring 8 in the second opening 7b of through-hole 7 is prevented both during and after manufacturing. Furthermore, compared to, for example, a case where the resin insulating layer 10 is formed with a uniform thickness along the inner surface 7c of the through-hole 7, the inclination of the second region 12 is gentler, allowing for easy and reliable formation of the second wiring 8. Furthermore, since the second wiring 8 can be formed independently of the shape of the inner surface 7c of the through-hole 7, even if, for example, sharp portions remain on the inner surface 7c of the through-hole 7, disconnection of the second wiring 8 due to such portions can be prevented. Furthermore, the average inclination angle of the second region 12 is smaller than that of the first region 11. In other words, the average inclination angle of the first region 11 reaching the first opening 7a of the through-hole 7 is greater than the average inclination angle of the second region 12. Consequently, even when the through-hole 7 is reduced in diameter, for example, the width of the opening 10a of the resin insulating layer 10 on the first surface 2a side of the semiconductor substrate 2 can be sufficiently ensured. Consequently, disconnection of the first wiring 3 and the second wiring 8 in the opening 10a of the resin insulating layer 10 can be prevented both during and after manufacturing. Furthermore, on the surface 10b of the resin insulating layer 10, the fourth region 14 is curved to continuously connect the first region 11 and the second region 12, and the fifth region 15 is curved to continuously connect the second region 12 and the third region 13. Therefore, both during and after manufacturing, disconnection of the second wiring 8 is prevented across the entire surface 10b of the resin insulating layer 10. Especially after manufacturing, stress concentration is alleviated across the entire surface 10b of the resin insulating layer 10, effectively preventing disconnection of the second wiring 8. As described above, the semiconductor device 1 can ensure reliable electrical connection of the semiconductor substrate 2 via the through-hole 7.

[0068] In the semiconductor device 1, the surface 10b of the resin insulating layer 10 is a continuous surface (a surface in which the regions 11, 12, 13, 14, and 15 are smoothly connected, with no discontinuous portions such as intersections (corners, bends, etc.) between the surfaces). This alleviates stress concentration and prevents disconnection of the second wiring 8.

[0069] In the semiconductor device 1, the average tilt angle of the first region 11 is closer to the average tilt angle of the inner surface 7c of the through-hole 7 than the average tilt angle of the second region 12. This provides an opening 10a having a sufficient width to expose the pad portion 3a of the first wiring 3. As a result, disconnection of the first wiring 3 and the second wiring 8 in the opening 10a of the resin insulating layer 10 can be reliably prevented both during and after manufacturing.

[0070] In the semiconductor device 1, the average tilt angle α of the first region 11 is greater than the average tilt angle γ of the inner surface 7c of the through-hole 7, and the average tilt angle β of the second region 12. This prevents disconnection of the second wiring 8 and provides an opening 10a having a sufficient width for exposing the pad portion 3a of the first wiring 3.

[0071] In the semiconductor device 1, the average thickness of the portion of the resin insulating layer 10 corresponding to the first region 11 is greater than the average thickness of the portion of the resin insulating layer 10 corresponding to the second region 12 in a direction parallel to the first surface 2a and the second surface 2b of the semiconductor substrate 2. Thus, the resin insulating layer 10 can be obtained with a shape that is less likely to cause disconnection of the second wiring 8 and less likely to cause disconnection of the first wiring 3 and the second wiring 8.

[0072] In the semiconductor device 1, even if a protrusion or the like remains at the edge of the second opening 7b of the through-hole 7, the protrusion or the like is covered by the resin insulating layer 10, and the second wiring 8 is provided in the convexly curved surface, i.e., the fifth region 15. Thus, disconnection of the second wiring 8 in the portion of the second opening 7b of the through-hole 7 can be reliably prevented.

[0073] In the semiconductor device 1, a portion of the surface of the resin insulating layer 10 provided on the inner surface 7c of the through-hole 7, which has a height H that is less than or equal to 1 / 2 of the sum D of the thickness of the semiconductor substrate 2 and the average thickness of the resin insulating layer 10 provided on the second surface 2b, serves as the first region 11. Thus, on the surface 10b of the resin insulating layer 10, the first region 11 and the second region 12 can be smoothly connected, thereby reliably preventing disconnection of the second wiring 8 at the boundary between the first region 11 and the second region 12.

[0074] In the resin insulation layer 10 of the semiconductor device 1, with the plane S passing through the edge of the opening 10a of the resin insulation layer 10 and the edge of the second opening 7b of the through-hole 7 as the boundary plane, the volume of portion P1 on the inner surface 7c side of the through-hole 7 relative to plane S and portion P2 on the opposite side of the inner surface 7c of the through-hole 7 relative to plane S is greater than the volume of portion P2. Furthermore, with respect to a plane including the center line CL of the through-hole 7, the area of ​​triangle T1 on one side of the center line CL is greater than the area of ​​triangle T2. This allows the first region 11 and the second region 12 to be smoothly connected on the surface 10b of the resin insulation layer 10, reliably preventing disconnection of the second wiring 8 at the boundary between the first region 11 and the second region 12.

[0075] In the semiconductor device 1, the surface 10b of the resin insulating layer 10 provided on the inner surface 7c of the through-hole 7 has a first region 11 located closer to the first opening 7a than the fourth region 14 having the maximum curvature convex toward the side opposite to the inner surface 7c of the through-hole 7, and a second region 12 located closer to the second opening 7b than the fourth region 14. This shape of the resin insulating layer 10 is particularly effective in ensuring reliable electrical connection of the semiconductor substrate 2 via the through-hole 7.

[0076] Next, the method for manufacturing the semiconductor device 1 is described with reference to Figures 4 to 9 , while explaining. First, Figure 4 As shown in (a), a p-type region 2c is formed on the semiconductor substrate 2, and an oxide film 4 and a first wiring 3 are provided on the first surface 2a of the semiconductor substrate 2 (first step). Figure 4 As shown in (b), a light-transmitting substrate (support substrate) 5 is mounted on the first surface 2a of the semiconductor substrate 2 via an adhesive layer 6 (second step).

[0077] Then, if Figure 5 As shown in (a), by grinding the second surface 2b of the semiconductor substrate 2 on which the light-transmitting substrate 5 is mounted (i.e., by removing the portion on the second surface 2b side of the semiconductor substrate 2), the semiconductor substrate 2 can be thinned (the third step) in such a manner that the thickness of the semiconductor substrate 2 is smaller than the thickness of the light-transmitting substrate 5. In this way, by thinning the semiconductor substrate 2, the through hole 7 can be easily formed in the subsequent steps. In addition, even in the completed semiconductor device 1, the response speed can be improved. Next, as shown in FIG. Figure 5 As shown in (b), a through hole 7 is formed in the semiconductor substrate 2 by anisotropic wet etching, and then, as shown in Figure 6As shown in (a), the portion of the oxide film 4 corresponding to the pad portion 3a of the first wiring 3 is removed, thereby forming an opening 4a in the oxide film 4. This exposes the pad portion 3a of the first wiring 3 at the first opening 7a of the through-hole 7 (step 4). Furthermore, when viewed from a direction parallel to the center line CL of the through-hole 7, the opening 4a in the oxide film 4 does not need to be formed so that the edge of the first opening 7a of the through-hole 7 coincides with the edge of the opening 4a of the oxide film 4. For example, the opening 4a in the oxide film 4 may be formed so that the edge of the opening 4a of the oxide film 4 is located inward relative to the edge of the first opening 7a of the through-hole 7.

[0078] Next, a positive first resin material having a viscosity of 10 cp or more is prepared, and a dip coating method (a method of dipping an object into a resin coating and pulling the object from the resin coating to form a resin layer on the object) is performed using the first resin material. Figure 6 As shown in (b), a resin insulating layer 10 is provided on the inner surface 7c of the through-hole 7 and the second surface 2b of the semiconductor substrate 2 (step 5). Consequently, a recess 17 having an inner surface that follows the second region 12, the third region 13, and the fifth region 15 is formed in the resin insulating layer 10. Furthermore, a first resin material is also applied to the surface of the light-transmitting substrate 5 opposite the semiconductor substrate 2, forming a resin layer 100. Examples of the first resin material include phenolic resin, polyimide resin, and epoxy resin.

[0079] Then, if Figure 7 As shown in (a), a mask (not shown) is used to irradiate light only on the portion corresponding to the contact hole 16 and the portion corresponding to the opening 10c in the resin insulating layer 10, and only these portions are exposed. Figure 6 (b)) is also irradiated with light, and the resin layer 100 is also exposed. Then, the portion of the resin insulating layer 10 corresponding to the contact hole 16 and the portion corresponding to the opening 10c, as well as the resin layer 100, are developed, thereby forming the contact hole 16 and the opening 10c in the resin insulating layer 10, and removing the resin layer 100 (i.e., the first resin material attached to the surface of the light-transmitting substrate 5 opposite to the semiconductor substrate 2). As a result, the pad portion 3a of the first wiring 3 is exposed in the opening 10a of the resin insulating layer 10, and a portion of the second surface 2b of the semiconductor substrate 2 is exposed in the opening 10c of the resin insulating layer 10 (sixth step). Furthermore, an ashing process or the like may be used in conjunction with the formation of the contact hole 16.

[0080] During exposure, a gap is formed by recess 17 formed in resin insulating layer 10 between the light-transmitting portion of the mask (not shown) and the portion of resin insulating layer 10 corresponding to contact hole 16. As a result, light is diffracted and irradiated onto resin insulating layer 10. Consequently, during development, contact hole 16 is formed having the inner surfaces of first region 11 and second region 12 that follow the tapered shape that expands from first surface 2a to second surface 2b of semiconductor substrate 2.

[0081] Then, if Figure 7 As shown in step (b), aluminum is sputtered, for example, to form the second wiring 8 and the third wiring 22 on the surface 10b of the resin insulating layer 10. The first wiring 3 and the second wiring 8 are electrically connected in the opening 10a of the resin insulating layer 10, and the third wiring 22 is electrically connected to the second surface 2b of the semiconductor substrate 2 in the opening 10c of the resin insulating layer 10 (step 7). At this time, the contact hole 16 has an inner surface that follows the tapered first region 11 that expands from the first surface 2a to the second surface 2b of the semiconductor substrate 2. Therefore, a metal film is reliably formed on this inner surface as well. Furthermore, the first wiring 3 and the second wiring 8 are reliably connected in the opening 10a of the resin insulating layer 10.

[0082] Next, a positive type second resin material having a viscosity of 10 cp or more is prepared, and a dip coating method is performed using the second resin material. Figure 8 As shown in (a), a resin protective layer 21 is provided on the surface 10b of the resin insulating layer 10 so as to cover the second wiring 8 and the third wiring 22 (step 8). This forms a recess 21a in the resin protective layer 21. Furthermore, a second resin material is also applied to the surface of the light-transmitting substrate 5 opposite to the semiconductor substrate 2, forming a resin layer 210. Examples of the second resin material include phenolic resin, polyimide resin, and epoxy resin.

[0083] Then, if Figure 8 As shown in (b), a mask (not shown) is used to irradiate light only on the portion corresponding to the pad portion 8a of the second wiring 8 and the portion corresponding to the pad portion 22a of the third wiring 22 in the resin protective layer 21, and only these portions are exposed. Figure 8(a)) is also irradiated with light to expose the resin layer 210. Then, the portion of the resin protective layer 21 corresponding to the pad 8a of the second wiring 8 and the portion corresponding to the pad 22a of the third wiring 22, as well as the resin layer 210, are developed, thereby forming openings 21b and 21c in the resin protective layer 21, and removing the resin layer 210 (i.e., the second resin material attached to the surface of the light-transmitting substrate 5 opposite to the semiconductor substrate 2). As a result, the pad 8a of the second wiring 8 is exposed in the opening 21b of the resin protective layer 21, and the pad 22a of the third wiring 22 is exposed in the opening 21c of the resin protective layer 21 (ninth step). Finally, the extraction electrode 9 is arranged on the pad 8a of the second wiring 8 not covered by the resin protective layer 21, and the extraction electrode 23 is arranged on the pad 22a of the third wiring 22 not covered by the resin protective layer 21, thereby obtaining the above-mentioned semiconductor device 1.

[0084] The dip coating process described above will be described in further detail. In this embodiment, the first resin material used to form the resin insulating layer 10 is the same as the first resin material used to form the resin protective layer 21. Therefore, both the dip coating process for forming the resin insulating layer 10 and the dip coating process for forming the resin protective layer 21 are performed as follows. Furthermore, each process of the above-described method for manufacturing the semiconductor device 1 is performed at the wafer level, and finally, the wafer containing multiple semiconductor devices 1 is diced to obtain individual semiconductor devices 1.

[0085] like Figure 9 As shown, a wafer W including portions corresponding to a plurality of semiconductor devices 1 is immersed in a resin material F stored in a container C. When the wafer W is immersed in the resin material F, a liquid level FL of the resin material F stored in the container C is maintained so as to intersect the first surface 2a of the semiconductor substrate 2 (in this embodiment, a state of being orthogonal, that is, a state in which the first surface 2a of the semiconductor substrate 2 is parallel to the vertical direction).

[0086] Next, the wafer W including the portion corresponding to the plurality of semiconductor devices 1 is pulled up from the resin material F stored in the container C. When the wafer W is pulled up from the resin material F, the liquid level FL of the resin material F stored in the container C is maintained so as to intersect the first surface 2a of the semiconductor substrate 2 (in the present embodiment, this is an orthogonal state, that is, the first surface 2a of the semiconductor substrate 2 is parallel to the vertical direction).

[0087] Thereafter, the resin material F applied to the wafer W is pre-baked. During this pre-baking, it is preferred that the orientation of the wafer W be maintained in the same orientation as that used when the semiconductor substrate 2 was dipped into and pulled up into the resin material F. The reason for this is as follows. Specifically, if the orientation of the wafer is changed during pre-baking to a different orientation than that used when the semiconductor substrate 2 was dipped into and pulled up into the resin material F, the adhesion state of the resin material F may change, potentially causing variations in the formation state of the resin insulating layer 10 and the resin protective layer 21 within each through-hole 7.

[0088] A detailed example of the patterning process for the resin insulating layer 10 and the resin protective layer 21 is described below. Specifically, a resin material is applied by dip coating, the resin material is pre-dried, the resin material is exposed, the resin material is dried, the resin material is developed, and the resin material is dried. Drying the resin material after the exposure and before the development of the resin material is not necessarily performed.

[0089] As described above, in the method for manufacturing the semiconductor device 1, each step after the step of thinning the semiconductor substrate 2 can be performed with the light-transmitting substrate 5 attached to the semiconductor substrate 2. This prevents damage to the periphery of the through-hole 7. Furthermore, the resin insulating layer 10 is formed by dip coating. This reliably forms the resin insulating layer 10 with a sufficient thickness to ensure electrical insulation. Therefore, according to the method for manufacturing the semiconductor device 1, the semiconductor substrate 2 can be thinned while preventing damage to the periphery of the through-hole 7 and ensuring electrical insulation between the wiring within the through-hole 7 and the semiconductor substrate 2.

[0090] In the method for manufacturing the semiconductor device 1, in each of the dip coating method for forming the resin insulating layer 10 and the dip coating method for forming the resin protective layer 21, dipping into and pulling up the resin material F are performed as follows. Specifically, the semiconductor substrate 2, on which the light-transmitting substrate 5 is mounted, is dipped into the stored resin material F so that the liquid level FL of the stored resin material F intersects the first surface 2a of the semiconductor substrate 2. Furthermore, the semiconductor substrate 2, on which the light-transmitting substrate 5 is mounted, is pulled up from the stored resin material F so that the liquid level FL of the stored resin material F intersects the first surface 2a of the semiconductor substrate 2. This reduces stress generated in the periphery of the through-hole 7 compared to, for example, performing dipping into and pulling up the resin material F while the liquid level FL of the stored resin material F is parallel to the first surface 2a of the semiconductor substrate 2. In addition, for example, compared with the case where the resin material F is impregnated and pulled up in a state where the liquid surface FL of the stored resin material F is parallel to the first surface 2a of the semiconductor substrate 2, it is possible to suppress the residual bubbles in the resin insulating layer 10 formed on the inner surface 7c of the through hole 7.

[0091] In the method for manufacturing semiconductor device 1, the same resin material having a viscosity of 10 cp or greater is used in both the dip coating method for forming resin insulating layer 10 and the dip coating method for forming resin protective layer 21. By using a resin material having a viscosity of 10 cp or greater, it is possible to reliably form resin insulating layer 10 having a sufficient thickness to ensure electrical insulation, and to reliably form resin protective layer 21 having a sufficient thickness to protect second wiring 8 and third wiring 22. Furthermore, by using the same resin material, even if resin insulating layer 10 and resin protective layer 21 deform due to temperature changes, the extent of their deformation is equal, thereby preventing damage to second wiring 8 and third wiring 222 caused by significantly different degrees of deformation.

[0092] Furthermore, in the dip coating method, generally, a resin material with low viscosity (e.g., a resin material used for waterproof coating, for example, a resin material with a viscosity of 1 cp or less) is used. However, even when the dip coating method is performed using such a resin material, the resin insulating layer 10 is formed with a substantially uniform thickness along the inner surface 7 c of the through-hole 7. Therefore, in the above-described method for manufacturing the semiconductor device 1, by performing the dip coating method using a resin material with a viscosity of 10 cp or more, the resin insulating layer 10 having the above-described shape can be easily and reliably obtained.

[0093] In the method for manufacturing the semiconductor device 1, the resin layer 100 (i.e., the first resin material attached to the surface of the light-transmitting substrate 5 opposite to the semiconductor substrate 2) is removed when the contact hole 16 and the opening 10c are formed in the resin insulating layer 10. Furthermore, the resin layer 210 (i.e., the second resin material attached to the surface of the light-transmitting substrate 5 opposite to the semiconductor substrate 2) is removed when the openings 21b and 21c are formed in the resin protective layer 21. Thus, even when the light-transmitting substrate 5 is used as a support substrate, the resin layers 100 and 210 can be removed from the support substrate, allowing the support substrate to effectively function as the light-transmitting substrate 5.

[0094] In addition, it is preferable not to remove the resin layer 100 and the resin layer 210 collectively, but to remove each of the resin layer 100 and the resin layer 210 during the respective development. After the development, the resin material is also dried, and the resin material cannot be completely removed after the drying. Therefore, for example, the resin layer 100 remains in a residual state. Even if the resin layer 100 is to be removed together with the resin layer 210 in the final process, the resin layer 100 cannot be completely removed. Therefore, the resin layer 100 and the resin layer 210 are removed individually during the respective development. Reliably removing the resin layer 100 and the resin layer 210 is of course effective when the support substrate is used as the light-transmitting substrate 5. In addition, when the support substrate is not used as the light-transmitting substrate 5 (when it is finally removed), if the resin layer 100 and the resin layer 210 are not reliably removed, there will be unevenness on the fixing surface during the wafer process, the processing will become unstable, and stress will act on the semiconductor substrate 2. Therefore, the resin layer 100 and the resin layer 210 can be reliably removed, which is also effective when the support substrate is not used as the light-transmitting substrate 5 (when it is finally removed).

[0095] In the method for manufacturing semiconductor device 1, a resin protective layer 21 is formed on surface 10b of resin insulating layer 10 by dip coating so as to cover second wiring 8 and third wiring 22. Consequently, a shallow recess 21a having a smooth inner surface is formed in the portion of resin protective layer 21 corresponding to through-hole 7. Therefore, when semiconductor device 1 is mounted on a circuit board via extraction electrodes 9 and 23 and underfill resin is applied between semiconductor device 1 and the circuit board, the underfill resin easily flows into recess 21a, and bubbles are less likely to remain inside recess 21a.

[0096] In the above-described method for manufacturing semiconductor device 1, a positive-type resin material is used to form resin insulating layer 10 on inner surface 7c of through-hole 7 and second surface 2b of semiconductor substrate 2. Then, the portion of resin insulating layer 10 corresponding to contact hole 16 is exposed and developed, thereby forming contact hole 16 in resin insulating layer 10. This allows resin insulating layer 10 having the aforementioned shape to be easily and reliably obtained. Furthermore, during exposure and development, recess 17 formed in resin insulating layer 10 reduces the thickness of the portion of resin insulating layer 10 corresponding to contact hole 16 (i.e., the portion of resin insulating layer 10 corresponding to contact hole 16 is a portion of resin insulating layer 10 having a height H that is less than or equal to 1 / 2 of the sum D of the thickness of semiconductor substrate 2 and the average thickness of resin insulating layer 10 provided on second surface 2b). Therefore, contact hole 16 having the desired shape can be easily and reliably obtained.

[0097] While one embodiment of the present invention has been described above, the present invention is not limited to the aforementioned embodiment. For example, in the aforementioned embodiment, the first opening 7a of the through hole 7 is covered by the pad portion 3a of the first wiring 3. However, as long as a portion of the first wiring 3 is located above the first opening 7a, the first wiring 3 does not need to cover the entire area of ​​the first opening 7a.

[0098] In addition, in the above embodiment, the average inclination angle of the first region 11 is closer to the average inclination angle of the inner surface 7c of the through hole 7 than the average inclination angle of the second region 12, but the average inclination angle of the second region 12 may also be closer to the average inclination angle of the inner surface 7c of the through hole 7 than the average inclination angle of the first region 11.

[0099] In the above embodiment, a light-transmitting substrate 5 is used as a support substrate. However, if the semiconductor device 1 does not include a light-transmitting substrate 5, another substrate may be used as a support substrate. When another substrate is used as a support substrate, the support substrate may be removed from the semiconductor substrate 2 after the extraction electrodes 9 and 23 are provided during the manufacturing process of the semiconductor device 1. Furthermore, when another substrate is used as a support substrate, the resin layer 100 and the resin layer 210 attached to the support substrate may be removed by performing a dip coating method, or they may remain. Furthermore, when another substrate is used as a support substrate, it is not necessary to use an optical adhesive as the adhesive layer 6.

[0100] In addition, in the above-described embodiment, when viewed from a direction parallel to the center line CL of the through-hole 7, the pad portion 8a of the second wiring 8 and the extraction electrode 9 are located near the outside of the second opening 7b of the through-hole 7. However, the pad portion 8a of the second wiring 8 and the extraction electrode 9 may be located on the surface 10b of the resin insulating layer 10 opposite to the second surface 2b of the semiconductor substrate 2 in a state sufficiently separated from the second opening 7b of the through-hole 7. However, even if the pad portion 8a of the second wiring 8 and the extraction electrode 9 are located near the outside of the second opening 7b of the through-hole 7 when viewed from a direction parallel to the center line CL of the through-hole 7, Figure 10 As shown, the stress generated when the extraction electrode 9 expands due to heat or the like is dispersed in the directions of the arrows A1, A2, and A3. This is because the side wall (inner surface) of the opening 21b of the resin protective layer 21 in which the extraction electrode 9 is provided is curved. In addition, this is because the surface 10b of the resin insulating layer 10 provided on the inner surface 7c of the through-hole 7 is smoothly connected to the surface 10b of the resin insulating layer 10 provided on the second surface 2b of the semiconductor substrate 2. Furthermore, the stress acting in the direction of arrow A3 acts along the second wiring 8 in the direction of arrow A4. Therefore, even if the pad portion 8a of the second wiring 8 and the extraction electrode 9 are located near the outside of the second opening 7b of the through-hole 7, the second wiring 8 is prevented from being disconnected near the second opening 7b of the through-hole 7. If the stress is applied only in the direction of arrow A3, the opening 21b of the resin protective layer 21 will be pushed open, and there is a concern that the second wiring 8 will be disconnected.

[0101] In addition, if Figure 11As shown, the extraction electrode 9 can also be arranged inside the through-hole 7 so as to protrude from the second surface 2b of the semiconductor substrate 2. When the extraction electrode 9 is arranged inside the through-hole 7, the inner surface 7c of the through-hole 7 forms a tapered surface that widens from the first surface 2a toward the second surface 2b. This facilitates the flow of molten solder or other metal material (the material used to form the extraction electrode 9) into the through-hole 7, and reduces the likelihood of bubbles remaining inside the through-hole 7. Furthermore, even if some external force acts on the extraction electrode 9 from the second opening 7b side of the through-hole 7 toward the first opening 7a side, the resin insulating layer 10 (particularly the third bent portion 103 described above) functions as a buffer region. Consequently, stress generated in the extraction electrode 9 can be reduced, and the electrical connection between the first wiring 3, the second wiring 8, and the extraction electrode 9 can be reliably maintained. Furthermore, when the extraction electrode 9 is disposed inside the through-hole 7, it is not necessary to lead the second wiring 8 outside the second opening 7b of the through-hole 7. Therefore, when viewed from a direction parallel to the center line CL of the through-hole 7, the outer edge of the second wiring 8 may be located inside the second opening 7b of the through-hole 7. In other words, the outer edge of the second wiring 8 may be located on the surface 10b of the resin insulating layer 10 opposite to the inner surface 7c of the through-hole 7.

[0102] In addition, if Figure 12 and Figure 13 As shown, when viewed from a direction parallel to the center line CL of the through-hole 7, the outer edge of the second wiring 8 may be located on the inner side of the second opening 7b of the through-hole 7 in addition to the portion extending to the pad portion 8a. That is, the outer edge of the second wiring 8 may be located on the surface 10b of the resin insulating layer 10 on the opposite side to the inner surface 7c of the through-hole 7 in addition to the portion extending to the pad portion 8a. In this case, the portion of the second wiring 8 that only extends to the pad portion 8a crosses the second opening 7b of the through-hole 7, and thus, in the second opening 7b portion of the through-hole 7, leakage of current between the second wiring 8 and the semiconductor substrate 2 can be further reliably suppressed. In particular, when the shape of the second opening 7b of the through-hole 7 is rectangular, the portion of the second wiring 8 that extends to the pad portion 8a is constructed in a manner that crosses the side portion of the corner of the rectangle, and thus, in the second opening 7b portion of the through-hole 7, leakage of current between the second wiring 8 and the semiconductor substrate 2 can be further reliably suppressed. In addition, in Figure 13 In FIG. 1 , the resin insulating layer 10 is shown by a dotted line, and the second wiring 8 is shown by a two-dot chain line.

[0103] In addition, if Figure 14As shown, the inner surface 7c of the through hole 7 (when the inner surface 7c of the through hole 7 is a curved surface such as a cylindrical surface, it is a tangent plane of the curved surface) can also be a surface orthogonal to the first surface 2a and the second surface 2b. In this case, the electrical connection of the semiconductor substrate 2 through the through hole 7 can also be made reliable. Here, the aspect ratio of the through hole 7 is 0.2 to 10. As an example, the depth of the through hole 7 is 40 μm and the width of the second opening 7b is 30 μm. In this case, the aspect ratio becomes 1.3. In addition, the through hole 7 having a cylindrical shape, a quadrangular prism shape, etc. is formed, for example, by dry etching.

[0104] about Figure 14 In the through-hole 7 shown, the average tilt angle β of the second region 12 is also smaller than the average tilt angle α of the first region 11, and smaller than the average tilt angle γ of the inner surface 7c of the through-hole 7 (90° in this case). In other words, the second region 12 has a gentler inclination than the first region 11, and a gentler inclination than the inner surface 7c of the through-hole 7. Furthermore, the average tilt angle α of the first region 11 is closer to the average tilt angle γ of the inner surface 7c of the through-hole 7 than the average tilt angle β of the second region 12. Here, the average tilt angle γ of the inner surface 7c of the through-hole 7 > the average tilt angle α of the first region 11 > the average tilt angle β of the second region 12. This prevents disconnection of the second wiring 8 and provides an opening 10a having a sufficient width to expose the pad portion 3a of the first wiring 3. Furthermore, the surface 10b of the resin insulating layer 10 is a continuous surface (a surface in which the regions 11, 12, 13, 14, and 15 are smoothly connected, with no discontinuous areas such as intersections (corners, bends, etc.) between the surfaces). Furthermore, in the resin insulating layer 10, with a surface S passing through the edge of the opening 10a of the resin insulating layer 10 and the edge of the second opening 7b of the through-hole 7 as the boundary surface, the volume of portion P1 on the inner surface 7c side of the through-hole 7 relative to surface S and portion P2 on the opposite side of the inner surface 7c of the through-hole 7 relative to surface S is greater than the volume of portion P2. Furthermore, in the resin insulating layer 10, with respect to a plane including the center line CL of the through-hole 7, the area of ​​triangle T1 is greater than the area of ​​triangle T2 when focusing on the region on one side of the center line CL. Furthermore, in a direction parallel to the first surface 2 a and the second surface 2 b of the semiconductor substrate 2 , the average thickness of the portion of the resin insulating layer 10 corresponding to the first region 11 is greater than the average thickness of the portion of the resin insulating layer 10 corresponding to the second region 12 .

[0105] Alternatively, the first region 11 may be a surface 10b of the resin insulating layer 10 provided on the inner surface 7c of the through hole 7 having a height H that is less than or equal to 2 / 3 of the sum D of the thickness of the semiconductor substrate 2 and the average thickness of the resin insulating layer 10 provided on the second surface 2b of the semiconductor substrate 2 (see FIG. Figure 14 In this case, the first region 11 and the second region 12 are smoothly connected on the surface 10b of the resin insulating layer 10, and disconnection of the second wiring 8 at the boundary between the first region 11 and the second region 12 can be reliably prevented. In addition, during exposure and development, the thickness of the portion of the resin insulating layer 10 corresponding to the contact hole 16 is reduced by the recess 17 formed in the resin insulating layer 10 (that is, the portion corresponding to the contact hole 16 is a portion of the resin insulating layer 10 having a height H that is less than 2 / 3 of the sum D of the thickness of the semiconductor substrate 2 and the average thickness of the resin insulating layer 10 provided on the second surface 2b), thereby easily and reliably obtaining a contact hole 16 having a desired shape.

[0106] In the above-described method for manufacturing semiconductor device 1, a positive-type resin material is used to form resin insulating layer 10 on inner surface 7c of through-hole 7 and second surface 2b of semiconductor substrate 2. The portions of resin insulating layer 10 corresponding to contact hole 16 and opening 10c are exposed and developed, thereby forming contact hole 16 and opening 10c in resin insulating layer 10. However, the present invention is not limited to this embodiment. For example, a negative-type resin material may be used to form resin insulating layer 10 on inner surface 7c of through-hole 7 and second surface 2b of semiconductor substrate 2. In this case, portions of resin insulating layer 10 other than portions corresponding to contact hole 16 and opening 10c may be exposed, and portions of resin insulating layer 10 corresponding to contact hole 16 and opening 10c may be developed, thereby forming contact hole 16 and opening 10c in resin insulating layer 10. Due to light attenuation, light diffraction, etc., a conical contact hole 16 that expands from the second surface 2b of the semiconductor substrate 2 to the first surface 2a can be formed only by development, but by further performing heat treatment, etc., a conical contact hole 16 that expands from the first surface 2a of the semiconductor substrate 2 to the second surface 2b can be obtained.

[0107] In addition, in the above embodiment, a p-type region 2c in which p-type impurities are selectively diffused is provided in a predetermined region on the first surface 2a side of a semiconductor substrate 2 composed, for example, of n-type silicon. However, the conductivity types may be reversed. In this case, the extraction electrode 9 and the extraction electrode 23 function as a cathode electrode and an anode electrode, respectively. Furthermore, the present invention is not limited to forming a region of the second conductivity type (the other of the p-type and n-type) within a semiconductor substrate 2 of the first conductivity type (one of the p-type and n-type). A semiconductor layer of the second conductivity type (the other of the p-type and n-type) may be formed on a semiconductor substrate 2 of the first conductivity type (one of the p-type and n-type). Alternatively, a semiconductor layer of the first conductivity type (one of the p-type and n-type) may be formed on a substrate, and a semiconductor layer of the second conductivity type (the other of the p-type and n-type) may be formed on the first conductivity type semiconductor layer. That is, it is sufficient as long as a second conductive type region is formed in a first conductive type region of the semiconductor substrate 2. In addition, in the above embodiment, the semiconductor device 1 is an optical device such as a silicon photodiode, but the semiconductor device 1 can also be other optical devices or electronic devices.

[0108] In the above-described method for manufacturing the semiconductor device 1, the resin insulating layer 10 and the resin protective layer 21 are formed by dip coating. However, the present invention is not limited thereto. For example, the resin insulating layer 10 and / or the resin protective layer 21 may be formed by other methods such as lamination using a resin sheet or spin coating using a resin coating.

[0109] Industrial applicability

[0110] According to the present invention, a method for manufacturing a semiconductor device can be provided that can reduce the thickness of a semiconductor substrate while preventing damage to the periphery of a through-hole and ensuring electrical insulation between wiring in the through-hole and the semiconductor substrate.

[0111] Explanation of symbols

[0112] 1…semiconductor device, 2…semiconductor substrate, 2a…first surface, 2b…second surface, 3…first wiring, 5…light-transmitting substrate (support substrate), 7…through hole, 7a…first opening, 7b…second opening, 7c…inner surface, 8…second wiring, 10…resin insulating layer, 10a…opening, 10b…surface, 16…contact hole, 21…resin protective layer.

Claims

1. A method for manufacturing a semiconductor device, wherein: Include: a preparation step of preparing a semiconductor substrate having a first surface and a second surface facing each other, a support substrate mounted on the first surface, and a first wiring provided between the first surface and the support substrate; a first forming step of forming, after the preparation step, a through hole extending from the first surface to the second surface in the semiconductor substrate, wherein a first opening of the through hole on the first surface side exposes a portion of the first wiring; a first dip coating step of performing a dip coating method using a first resin material after the first forming step, thereby providing a resin insulating layer continuous with a second opening on the second surface side of the through hole on the inner surface of the through hole and the second surface; a second forming step of forming a contact hole in the resin insulating layer after the first dip coating step, wherein an opening of the contact hole on the first surface side exposes a portion of the first wiring; and A connecting step of providing a second wiring on the surface of the resin insulating layer after the second forming step, and electrically connecting the first wiring and the second wiring in the opening on the first surface side of the contact hole.

2. The method for manufacturing a semiconductor device according to claim 1, wherein: In the first dip coating process, the semiconductor substrate on which the supporting substrate is mounted is immersed in the stored first resin material in a manner such that the liquid surface of the stored first resin material intersects the first surface, and the semiconductor substrate on which the supporting substrate is mounted is pulled up from the stored first resin material in a manner such that the liquid surface of the stored first resin material intersects the first surface.

3. The method for manufacturing a semiconductor device according to claim 1 or 2, wherein: In the first dip coating step, the dip coating method is performed using the first resin material having a viscosity of 10 cp or more.

4. The method for manufacturing a semiconductor device according to any one of claims 1 to 3, wherein: In the second forming step, the first resin material adhering to the surface of the support substrate on the side opposite to the semiconductor substrate in the first dip coating step is removed.

5. The method for manufacturing a semiconductor device according to any one of claims 1 to 4, wherein: Also includes: a second dip coating step of performing a dip coating method using a second resin material after the connecting step to form a resin protection layer on the surface of the resin insulating layer so as to cover the second wiring; and A third forming step is performed after the second dip coating step, forming an opening in the resin protective layer and exposing a portion of the second wiring in the opening.

6. The method for manufacturing a semiconductor device according to claim 5, wherein: In the second dip coating process, the semiconductor substrate on which the supporting substrate is mounted is immersed in the stored second resin material in a manner such that the liquid surface of the stored second resin material intersects the first surface, and the semiconductor substrate on which the supporting substrate is mounted is pulled up from the stored second resin material in a manner such that the liquid surface of the stored second resin material intersects the first surface.

7. The method for manufacturing a semiconductor device according to claim 5 or 6, wherein: In the second dip coating step, the dip coating method is performed using the second resin material having a viscosity of 10 cp or more.

8. The method for manufacturing a semiconductor device according to any one of claims 5 to 7, wherein: In the third forming step, the second resin material adhering to the surface of the support substrate on the side opposite to the semiconductor substrate in the second dip coating step is removed.

9. The method for manufacturing a semiconductor device according to any one of claims 5 to 8, wherein: The first resin material is the same as the second resin material.

10. The method for manufacturing a semiconductor device according to any one of claims 1 to 9, wherein: In the first dip coating step, the semiconductor substrate on which the support substrate is mounted is immersed in the stored first resin material so that a liquid level of the stored first resin material intersects the first surface.

11. The method for manufacturing a semiconductor device according to any one of claims 1 to 10, wherein: In the first dip coating step, the semiconductor substrate on which the support substrate is mounted is pulled up from the stored first resin material so that a liquid surface of the stored first resin material intersects the first surface.

12. The method for manufacturing a semiconductor device according to any one of claims 1 to 11, wherein: The method further includes a removing step of removing the supporting substrate from the semiconductor substrate after the connecting step.

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