Semiconductor package structure and method of manufacturing the same

Abstract

The semiconductor packaging structure and manufacturing method disclosed herein allow the bridging chip to be fabricated using through-mold via (TMV) technology, meaning the bridging chip is made of plastic packaging material, which reduces insertion loss compared to semiconductor materials. Furthermore, photolithography can be used to directly form conductive pillars of a larger diameter, thereby improving power transmission capabilities.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, specifically to semiconductor packaging structures and their manufacturing methods. Background Technology

[0002] In a system-on-chip (SoC) architecture that integrates different chips, a bridge chip is an auxiliary chip whose main function is to connect and transmit signals between two different interface specifications. Furthermore, bridge chips can be fabricated using through-silicon-via (TSV) technology to achieve the shortest interconnect path and highest integration density, improving power transmission efficiency. However, limited by the fabrication capabilities of TSVs, currently only 10μm diameter TSVs can be designed (increasing the diameter would cause silicon cracks), resulting in limited power transmission capacity. Additionally, bridge chips fabricated using TSV technology are made of semiconductor materials, which experience a certain degree of insertion loss at high frequencies. Summary of the Invention

[0003] This disclosure provides a semiconductor packaging structure and a method for manufacturing the same.

[0004] In a first aspect, this disclosure provides a semiconductor packaging structure, including:

[0005] First chip;

[0006] The second chip is disposed adjacent to the first chip;

[0007] A bridging chip electrically connects the first chip and the second chip. The bridging chip includes a vertical conductive path, and the plastic encapsulation material is epoxy molding compound.

[0008] In some alternative implementations, the vertical conductive path is used to provide a signal interconnection path between the first chip and the second chip, and the vertical conductive path is used to provide a conductive path for the first chip and / or the second chip.

[0009] In some optional embodiments, the semiconductor package structure further includes:

[0010] A redistribution layer is provided, through which the first chip and the second chip are electrically connected to the bridging chip.

[0011] In some alternative embodiments, the plastic encapsulation material is an epoxy molding compound.

[0012] In some alternative embodiments, the epoxy molding compound includes fillers.

[0013] In some alternative implementations, the vertical conductive path includes a first conductive post, a second conductive post, and a bridging redistribution layer, wherein the first conductive post is electrically connected to the second conductive post through the bridging redistribution layer, and the second conductive post is electrically connected to the redistribution layer.

[0014] In some alternative implementations, the semiconductor package structure includes:

[0015] The third conductive post is disposed adjacent to the bridging chip, and the height of the first conductive post is less than the height of the third conductive post.

[0016] In some alternative embodiments, the center of the first conductive post and the center of the second conductive post are located on the same vertical line.

[0017] In some alternative embodiments, the center of the first conductive post and the center of the second conductive post are located on different vertical lines.

[0018] In some alternative implementations, the diameter of the second conductive post tapers in the direction of the bridging chip toward the redistribution layer.

[0019] In some alternative embodiments, the sidewall of the second conductive post is an arc-shaped curved surface.

[0020] Secondly, this disclosure provides a method for manufacturing a semiconductor packaging structure, including:

[0021] A third conductive post is placed on the carrier plate;

[0022] A bridging chip is disposed on the carrier board, the bridging chip comprising a plastic encapsulation material and a vertical conductive path penetrating the plastic encapsulation material;

[0023] A first molding layer is formed to cover the third conductive pillar and the bridging chip, and the first molding layer is thinned.

[0024] A redistribution layer is formed on the first molding layer;

[0025] A first chip and a second chip are disposed on the redistribution layer;

[0026] A bottom filler material is formed to cover the bottom of the first chip and the bottom of the second chip;

[0027] A second encapsulation layer is formed to cover the first chip and the second chip;

[0028] Form external connectors.

[0029] In some alternative implementations, the bridging chip is pre-formed through the following steps:

[0030] A first conductive post is formed on a carrier plate, a first plastic encapsulation material is formed to cover the first conductive post, and the first plastic encapsulation material is thinned to expose the first conductive post.

[0031] A bridging redistribution layer is formed on the first plastic encapsulation material;

[0032] A second conductive post is formed on the bridging redistribution layer;

[0033] The bridging chip is formed by monomerization and dicing.

[0034] In some alternative embodiments, after forming the second conductive post on the bridging redistribution layer, the method further includes:

[0035] A second plastic encapsulation material is formed to cover the second conductive post, and the second plastic encapsulation material is thinned.

[0036] In some alternative implementations, the bridging chip is pre-formed through the following steps:

[0037] A second conductive pillar is formed on a carrier plate, a second plastic encapsulation material is formed to cover the second conductive pillar, and the second plastic encapsulation material is thinned to expose the second conductive pillar;

[0038] A bridging redistribution layer is formed on the second plastic encapsulation material;

[0039] A first conductive post is formed on the bridging redistribution layer;

[0040] The bridging chip is formed by monomerization and dicing.

[0041] In some alternative implementations, after forming the first conductive post on the bridging redistribution layer, the method further includes:

[0042] A first plastic encapsulation material is formed to cover the first conductive post, and the first plastic encapsulation material is thinned.

[0043] The semiconductor packaging structure and manufacturing method disclosed herein allow the bridging chip to be fabricated using through-mold via (TMV) technology, meaning the bridging chip is made of plastic packaging material, which reduces insertion loss compared to semiconductor materials. Furthermore, photolithography can be used to directly form conductive pillars of a larger diameter, thereby improving power transmission capabilities. Attached Figure Description

[0044] Other features, objects, and advantages of this disclosure will become more apparent from the following detailed description of non-limiting embodiments with reference to the accompanying drawings:

[0045] Figure 1 This is a schematic diagram of a semiconductor packaging structure according to an embodiment of the present disclosure;

[0046] Figures 2 to 6 This is a schematic diagram of the structure during the first manufacturing process of the bridge chip according to an embodiment of the present disclosure;

[0047] Figures 7 to 11 This is a schematic diagram of the structure during the second manufacturing process of the bridge chip according to an embodiment of the present disclosure;

[0048] Figures 12 to 16 This is a schematic diagram of the manufacturing process of a semiconductor packaging structure according to an embodiment of the present disclosure.

[0049] Symbol explanation:

[0050] 1-First chip, 2-Second chip, 3-Bridge chip, 31-Vertical conductive path, 311-First conductive post, 312-Bridge redistribution layer, 313-Second conductive post, 32-First plastic encapsulation material, 33-Second plastic encapsulation material, 34-Interconnection structure, 4-Redistribution layer, 5-Third conductive post, 6-First molding layer, 7-Second molding layer, 8-Bottom filler, 9-External electrical connector, 10-First carrier board, 11-Second carrier board. Detailed Implementation

[0051] The specific embodiments of this disclosure will be described below with reference to the accompanying drawings and examples. Those skilled in the art can easily understand the technical problems solved by this disclosure and the resulting technical effects through the content described herein. It is understood that the specific embodiments described herein are merely illustrative of the relevant invention and not intended to limit the invention. Furthermore, for ease of description, only the parts relevant to the invention are shown in the accompanying drawings.

[0052] It should be noted that the structures, proportions, sizes, etc., depicted in the accompanying drawings are only for illustrative purposes to aid those skilled in the art in understanding and reading the content described herein, and are not intended to limit the implementation conditions of this disclosure. Therefore, they have no substantial technical significance. Any modifications to the structure, changes in proportions, or adjustments to size, without affecting the effectiveness and purpose of this disclosure, should still fall within the scope of the technical content disclosed herein. Furthermore, terms such as "above," "first," "second," and "a" used in this specification are merely for clarity of description and are not intended to limit the scope of this disclosure. Changes or adjustments to their relative relationships, without substantially altering the technical content, should also be considered within the scope of this disclosure's implementation.

[0053] It should be readily understood that the meanings of “on,” “above,” and “on top of” in this disclosure should be interpreted in the broadest sense, such that “on” means not only “directly on something,” but also “on something” including intermediate components or layers existing between the two.

[0054] Furthermore, for ease of description, spatial relative terms such as “below,” “under,” “lower,” “above,” and “upper” may be used in this disclosure to describe the relationship of one element or component to another element or component shown in the accompanying drawings. In addition to the orientations described in the figures, the spatial relative terms are also intended to cover different orientations of the device during use or operation. The device may be oriented in other ways (rotated 90° or otherwise), and the spatial relative descriptive terms used in this disclosure may be interpreted accordingly.

[0055] Furthermore, the embodiments and features described herein can be combined with each other, unless otherwise specified. This disclosure will now be described in detail with reference to the accompanying drawings and embodiments.

[0056] Figure 1 This is a schematic diagram of a semiconductor packaging structure according to an embodiment of the present disclosure. Figure 1 As shown, the semiconductor package structure includes a first chip 1, a second chip 2, a bridging chip 3, a redistribution layer 4, a third conductive pillar 5, a first molding layer 6, a second molding layer 7, an underfill material 8, and external electrical connectors 9. The second chip 2 can be disposed adjacent to the first chip 1. The bridging chip 3 can electrically connect the first chip 1 and the second chip 2. The first chip 1 and the second chip 2 can be electrically connected to the bridging chip 3 through the redistribution layer 4. The underfill material 8 can cover the bottom of the first chip 1, the bottom of the second chip 2, and the bottom of the bridging chip 3, respectively. The first molding layer 6 can cover the third conductive pillar 5 and the bridging chip 3. The second molding layer 7 can cover the first chip 1 and the second chip 2.

[0057] In this embodiment, the first chip 1 and the second chip 2 can be chips with various functions. The first chip 1 can be, for example, a high-bandwidth memory (HBM) chip. The second chip 2 can be, for example, an application-specific integrated circuit (ASIC) chip.

[0058] In this embodiment, the bridging chip 3 may include a vertical conductive path 31. The vertical conductive path 31 can be used not only to provide a signal interconnection path between the first chip 1 and the second chip 2, but also to provide a conductive path between the first chip 1 and / or the second chip 2. The vertical conductive path 31 may include a first conductive post 311, a second conductive post 313, and a bridging redistribution layer 312. The first conductive post 311 can be electrically connected to the second conductive post 313 through the bridging redistribution layer 312. A third conductive post 5 may be disposed adjacent to the bridging chip 3, and the height of the first conductive post 311 may be less than the height of the third conductive post 5.

[0059] An external power supply can supply power to the first chip 1 and the second chip 2 in sequence through the third conductive post 5 and the redistribution layer 4 (first conductive path), or it can choose to supply power to the first chip 1 and the second chip 2 in sequence through the vertical conductive path 31 in the bridging chip 3 and the redistribution layer 4 (second conductive path). The second power supply path is shorter than the first conductive path.

[0060] In a scenario, such as Figure 1 As shown in Figure (a), the center of the first conductive post 311 and the center of the second conductive post 313 of the bridging chip 3 can be located on the same vertical line. In another scenario, such as Figure 1 As shown in Figure (b), the center of the first conductive post 311 and the center of the second conductive post 313 of the bridging chip 3 can be located on different vertical lines.

[0061] In this embodiment, the bridging chip 3 may include a plastic encapsulation material. The plastic encapsulation material may be an epoxy molding compound (EMC). The epoxy molding compound may include epoxy resin and fillers. The filler may, for example, be silicon dioxide (silicon micropowder). Plastic encapsulation materials can reduce insertion loss compared to semiconductor materials (e.g., silicon). In practice, at high frequencies of 70 GHz, the insertion loss of a semiconductor material with a plastic encapsulation material can be four times that of a plastic encapsulation material. Specifically, as... Figure 1 As shown in Figure (a), the plastic encapsulation material included in the bridging chip 3 can be the first plastic encapsulation material 32. Figure 1 As shown in Figure (c), the plastic encapsulation material included in the bridging chip 3 may include a first plastic encapsulation material 32 and a second plastic encapsulation material 33.

[0062] In this embodiment, as Figure 1As shown in Figure (c), the diameter of the second conductive post 313 tapers in the direction from the bridging chip 3 toward the redistribution layer 4. The sidewall of the second conductive post 313 is an arc-shaped curved surface. In the manufacturing process, a larger diameter second conductive post 313 can be directly formed using photolithography, thereby improving power transmission capability.

[0063] In this embodiment, the external electrical connector 9 may be, for example, a solder ball, a ball grid array (BGA) ball, a controlled collapse chip connection (C4) bump, or a microbump.

[0064] The semiconductor packaging structure disclosed herein allows the bridging chip to be fabricated using through-mold via (TMV) technology, meaning the bridging chip is made of plastic packaging material, which reduces insertion loss compared to semiconductor materials. Furthermore, photolithography can be used to directly form larger diameter conductive pillars, thereby improving power transmission capabilities.

[0065] Figures 2 to 6 This is a schematic diagram of the structure of the bridge chip 3 in the first manufacturing process according to an embodiment of the present disclosure.

[0066] Please refer to Figure 2 A first conductive post 311 is formed on the first carrier plate 10, and a first plastic encapsulation material 32 is formed to cover the first conductive post 311. The first plastic encapsulation material 32 is thinned to expose the first conductive post 311.

[0067] Please refer to Figure 3 A bridging redistribution layer 312 is formed on the first plastic encapsulation material 32.

[0068] Please refer to Figure 4 A second conductive post 313 and an interconnect structure 34 are formed on the bridging and rewiring layer 312.

[0069] Here, the first conductive post 311 and the second conductive post 313 can be formed directly using photolithography.

[0070] Please refer to Figure 5 This forms a second plastic encapsulation material 33 that covers the second conductive post 313.

[0071] Please refer to Figure 6 The second plastic encapsulation material 33 is thinned to expose the second conductive post 313.

[0072] Here, the thinning process can be, for example, grinding or chemical mechanical polishing (CMP).

[0073] Figures 7 to 11 This is a schematic diagram of the structure of the bridge chip 3 in the second manufacturing process according to an embodiment of the present disclosure.

[0074] Please refer to Figure 7 A second conductive post 313 is formed on the first carrier plate 10, and a second plastic encapsulation material 33 is formed to cover the second conductive post 313. The second plastic encapsulation material 33 is thinned to expose the second conductive post 313.

[0075] Please refer to Figure 8 A bridging redistribution layer 312 is formed on the second plastic encapsulation material 33.

[0076] Here, the redistribution layer formation technology currently known or developed in the future can be used in the process. This disclosure does not make specific limitations on this. For example, the bridging redistribution layer 312 can be formed by methods including but not limited to photolithography, electroplating, and electroless plating.

[0077] Please refer to Figure 9 A first conductive post 311 and an interconnect structure 34 are formed on the bridging and rewiring layer 312.

[0078] Please refer to Figure 10 A first plastic encapsulation material 32 is formed to cover the first conductive post 311.

[0079] Please refer to Figure 11 The first plastic encapsulation material 32 is thinned to expose the first conductive post 311.

[0080] Figures 12 to 16 This is a schematic diagram of the manufacturing process of a semiconductor packaging structure according to an embodiment of the present disclosure.

[0081] Please refer to Figure 12 A third conductive post 5 is provided on the second carrier plate 11.

[0082] Please refer to Figure 13 The bridging chip 3 is placed on the second carrier board 11. A bottom filler 8 is formed to cover the bottom of the bridging chip 3.

[0083] The bridge chip 3 here can be Figure 4 or Figure 6 or Figure 9 or Figure 11 The bridge chip 3 shown is shown.

[0084] Please refer to Figure 14 A first mold sealing layer 6 is formed to cover the third conductive pillar 5 and the bridging chip 3, and the first mold sealing layer 6 is thinned.

[0085] Please refer to Figure 15A redistribution layer 4 is formed on the first molding layer 6. A first chip 1 and a second chip 2 are disposed on the redistribution layer 4. Bottom fillers 8 are formed to cover the bottom of the first chip 1 and the bottom of the second chip 2, respectively. A second molding layer 7 is formed to cover the first chip 1 and the second chip 2.

[0086] Please refer to Figure 16 This forms an external connector.

[0087] The method for manufacturing the semiconductor packaging structure in this embodiment can achieve similar technical effects to the aforementioned semiconductor packaging structure, and will not be described in detail here.

[0088] Although this disclosure has been described and illustrated with reference to specific embodiments thereof, such descriptions and illustrations are not limiting of this disclosure. It will be readily understood by those skilled in the art that various changes can be made and equivalent elements can be substituted within embodiments without departing from the true spirit and scope of this disclosure as defined by the appended claims. Illustrations may not be drawn to scale. Differences may exist between the technical representation in this disclosure and actual equipment due to variables in the manufacturing process, etc. Other embodiments of this disclosure may exist that are not specifically described. The description and drawings should be considered illustrative rather than restrictive. Modifications can be made to adapt particular circumstances, materials, composition, methods, or processes to the objectives, spirit, and scope of this disclosure. All such modifications fall within the scope of the appended claims. While the methods disclosed in this disclosure have been described with reference to specific operations performed in a particular order, it should be understood that these operations can be combined, subdivided, or reordered to form equivalent methods without departing from the teachings of this disclosure. Therefore, unless specifically indicated in this disclosure, the order and grouping of operations do not limit this disclosure.

Claims

1. A semiconductor package structure, comprising: First chip; The second chip is disposed adjacent to the first chip; A bridging chip electrically connects the first chip and the second chip, the bridging chip includes a vertical conductive path, and the bridging chip includes a plastic encapsulation material; The semiconductor packaging structure further includes: A redistribution layer, through which the first chip and the second chip are electrically connected to the bridging chip; The vertical conductive path includes a first conductive post, a second conductive post, and a bridging redistribution layer. The first conductive post is electrically connected to the second conductive post through the bridging redistribution layer. The diameter of the second conductive post gradually decreases in the direction of the bridging chip toward the redistribution layer, and the second conductive post is electrically connected to the redistribution layer.

2. The semiconductor package structure of claim 1, wherein, The vertical conductive path is used to provide a signal interconnection path between the first chip and the second chip, and the vertical conductive path is used to provide a conductive path for the first chip and / or the second chip.

3. The semiconductor package structure of claim 1, wherein, The plastic encapsulation material is epoxy molding compound.

4. The semiconductor packaging structure according to claim 3, wherein, The epoxy molding compound includes fillers.

5. The semiconductor packaging structure according to claim 1, wherein, The semiconductor packaging structure includes: The third conductive post is disposed adjacent to the bridging chip, and the height of the first conductive post is less than the height of the third conductive post.

6. The semiconductor packaging structure according to claim 1, wherein, The center of the first conductive post and the center of the second conductive post are located on different vertical lines.

7. The semiconductor packaging structure according to claim 1, wherein, The sidewall of the second conductive post is an arc-shaped curved surface.

8. A method for manufacturing a semiconductor package structure, comprising: A third conductive post is placed on the carrier plate; A bridging chip is disposed on the carrier board, the bridging chip comprising a plastic encapsulation material and a vertical conductive path penetrating the plastic encapsulation material; A first molding layer is formed to cover the third conductive pillar and the bridging chip, and the first molding layer is thinned. A redistribution layer is formed on the first molding layer; A first chip and a second chip are disposed on the redistribution layer; A bottom filler material is formed to cover the bottom of the first chip and the bottom of the second chip; A second encapsulation layer is formed to cover the first chip and the second chip; Form external connectors; The bridging chip is pre-formed through the following steps: A first conductive post is formed on a carrier plate, a first plastic encapsulation material is formed to cover the first conductive post, and the first plastic encapsulation material is thinned to expose the first conductive post. A bridging redistribution layer is formed on the first plastic encapsulation material; A second conductive pillar is formed on the bridging and redistribution layer, wherein the vertical conductive path includes a first conductive pillar, a second conductive pillar, and the bridging and redistribution layer, the first conductive pillar is electrically connected to the second conductive pillar through the bridging and redistribution layer, the diameter of the second conductive pillar gradually decreases in the direction of the bridging chip toward the redistribution layer, and the second conductive pillar is electrically connected to the redistribution layer; The bridging chip is formed by monomerization and dicing.

9. The method according to claim 8, wherein, After forming the second conductive post on the bridging redistribution layer, the method further includes: A second plastic encapsulation material is formed to cover the second conductive post, and the second plastic encapsulation material is thinned.

10. The method according to claim 8, wherein, The bridging chip is pre-formed through the following steps: A second conductive pillar is formed on a carrier plate, a second plastic encapsulation material is formed to cover the second conductive pillar, and the second plastic encapsulation material is thinned to expose the second conductive pillar; A bridging redistribution layer is formed on the second plastic encapsulation material; A first conductive post is formed on the bridging redistribution layer; The bridging chip is formed by monomerization and dicing.

11. The method according to claim 10, wherein, After forming the first conductive post on the bridging redistribution layer, the method further includes: A first plastic encapsulation material is formed to cover the first conductive post, and the first plastic encapsulation material is thinned.

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