A method, system, device, and medium for decoding based on LZ77

Abstract

The application discloses a decoding method based on LZ77, comprising the following steps: in response to receiving a plurality of characters, judging whether there is a matching pair in the plurality of characters; in response to the existence of the matching pair, obtaining data corresponding to the matching pair according to a distance parameter and a length parameter in the matching pair; in response to all the matching pairs in the plurality of to-be-decoded characters being decoded, splicing the obtained data with other received characters; using the spliced data to shift the data already cached in the buffer to update the invalid data in the buffer into the valid spliced data, and using a pointer to mark the number of bits of the valid data in the buffer; in response to the number of bits of the valid data marked by the pointer reaching a threshold, writing all the valid data in the buffer into a RAM, and clearing the number of bits of the valid data marked by the pointer to make all the valid data in the buffer become invalid data. The application further discloses a system, a computer device and a readable storage medium.

Description

Technical Field

[0001] This invention relates to the field of decoding, and specifically to a decoding method, system, device, and storage medium based on LZ77. Background Technology

[0002] Huffman compression is currently the most commonly used compression algorithm in the field of data compression. The algorithm encodes characters by counting their frequency of occurrence; characters with higher frequency have shorter code lengths, and vice versa. However, due to the diversity of text formats, different texts need to be pre-compressed into a unified format using an algorithm before Huffman compression. The LZ77 algorithm is used here.

[0003] The LZ77 algorithm is a dictionary-based "sliding window" lossless compression algorithm. During compression, the hardware searches within the sliding window to see if the current text content has appeared before. If it has, it records the distance from the previous occurrence and the length of the repeating text, combining them into a matching pair stored at the current position. During encoding, LZ77 encoding is only meaningful when the length of the repeating text is greater than or equal to 3; text with a length less than 3 is not encoded.

[0004] The size of the sliding window has a significant impact on the efficiency of LZ77 encoding. Theoretically, the larger the sliding window, the greater the compression ratio. However, as the sliding window increases, the compression process becomes very time-consuming, and the improvement in compression ratio is not ideal. Therefore, choosing a suitable sliding window that matches the application scenario can greatly help improve compression efficiency.

[0005] The following is through Figures 1-4 Let me explain a simple LZ77 encoding process:

[0006] like Figure 1 As shown in the diagram, the letters represent the bitstream to be encoded, and the sliding window encompasses the search buffer and the region to be decoded. In this example, it is assumed that the length of the region to be decoded is 3, and the length of the search buffer is 8. Figure 2 As shown, Figure 2 The result of encoding the first character 'A' is shown. Since the search buffer is empty during 'A' encoding, 'A' will be encoded in its original form. Then the sliding window moves one byte to the right. (Example...) Figure 3 As shown, Figure 3 This is a diagram illustrating the encoding of the following four bytes, BCBC. The minimum length is 3; when the length is 2, encoding is considered meaningless, so the second BC is also encoded in its original form.

[0007] Next, encoding begins for the CBCs in the area to be decoded. Since an encoded sequence of CBCs is found in the search buffer, and the first C is at position 3, with an overlap length of 3, the encoding length is 3, and the distance is 3, represented as (3, 3) in matching pairs. After encoding, the sliding window moves three bytes to the right. Figure 4 As shown, consistent with the previous encoding method, the ABC sequence in the encoding region is encoded, since the sequence ABC exists in the search encoding region. The sign of the matching pair in this encoding is (3, 8). That is, the distance is 8 and the length is 3.

[0008] After encoding using the LZ77 algorithm described above, the original sequence becomes ABCBC(3,3)(3,8). Therefore, the compressed data is represented in two forms: one is the original sequence, such as the ABCBC sequence above; the other is matching pairs, such as (3,3) and (3,8) above. The first character of a matching pair represents the length, i.e., the length of the sequence repetition. The second character represents the distance, i.e., the distance between the first character of the sequence in the sliding window and the current position.

[0009] In practical applications, the sliding window size can be up to 32KB, so a 32KB RAM is needed to store the decoded data during the decoding process. This allows the system to read and write to RAM to find the matching character during decoding. However, frequent RAM reads and writes will degrade decoding performance. Summary of the Invention

[0010] In view of this, in order to overcome at least one aspect of the above problems, embodiments of the present invention propose a decoding method based on LZ77, comprising the following steps:

[0011] In response to receiving a number of characters, determine whether there is a matching pair among the characters;

[0012] In response to the existence of the matching pair, data corresponding to the matching pair is obtained based on the distance parameter and length parameter in the matching pair;

[0013] In response to the completion of decoding all matching pairs among the plurality of characters to be decoded, the acquired data is concatenated with the other received characters;

[0014] The concatenated data is used to shift the cached data in the buffer to update the invalid data in the buffer with the valid concatenated data, and a pointer is used to mark the number of bits of valid data in the buffer;

[0015] In response to the pointer marker reaching a threshold number of valid data bits, all valid data in the buffer is written to RAM, and the pointer marker is cleared to zero so that all valid data in the buffer becomes invalid data.

[0016] In some embodiments, in response to the existence of the matching pair, data corresponding to the matching pair is obtained based on the distance parameter and length parameter in the matching pair, further comprising:

[0017] In response to the distance parameter being less than the number of received characters, data corresponding to the matching pair is obtained from the received characters based on the distance parameter and the length parameter.

[0018] In some embodiments, it also includes:

[0019] In response to the fact that the number of distance parameters greater than the plurality of characters is less than the sum of the threshold and the plurality of characters, data is read from the buffer;

[0020] Based on the distance parameter and the length parameter, data corresponding to the matching pair is obtained from the data read from the cache and the received characters.

[0021] In some embodiments, it also includes:

[0022] In response to the distance parameter being greater than the sum of the threshold and the number of the plurality of characters, data is read from the buffer and the RAM;

[0023] Based on the distance parameter and the length parameter, data corresponding to the matching pair is obtained from the data read from the buffer, the data in the RAM, and the received characters.

[0024] In some embodiments, shifting cached data in a buffer using the concatenated data to update invalid data in the buffer with valid concatenated data further includes:

[0025] The number of valid data bits that can still be written is determined based on the number of bits of valid data in the data already cached by the cache and the threshold.

[0026] The bit width of the shift is determined based on the number of bits of valid data that can still be written and the size of the concatenated data;

[0027] Several enable signals are generated based on the bit width of the shift, and then the corresponding bit width is shifted based on the several enable signals.

[0028] In some embodiments, shifting cached data in a buffer using the concatenated data to update invalid data in the buffer with valid concatenated data further includes:

[0029] In response to the distance parameter in the matching pair being less than the length parameter, the identical parts of the concatenated data are continuously written into the buffer.

[0030] In some embodiments, it also includes:

[0031] The number of characters received each time is determined based on the preset first parameter.

[0032] Based on the same inventive concept, according to another aspect of the present invention, embodiments of the present invention also provide an LZ77-based decoding system, comprising:

[0033] The receiving module is configured to, in response to receiving a number of characters, determine whether there is a matching pair among the characters;

[0034] The acquisition module is configured to, in response to the existence of the matching pair, acquire data corresponding to the matching pair based on the distance parameter and length parameter in the matching pair;

[0035] The concatenation module is configured to concatenate the acquired data with other received characters in response to the completion of decoding all matching pairs among the plurality of characters to be decoded;

[0036] The update module is configured to use the concatenated data to shift the cached data in the buffer to update the invalid data in the buffer with the valid concatenated data, and to use a pointer to mark the number of bits of valid data in the buffer;

[0037] The write module is configured to, in response to the number of valid data bits in the pointer mark reaching a threshold, write all valid data in the buffer to RAM and clear the number of valid data bits in the pointer mark to zero so that all valid data in the buffer becomes invalid data.

[0038] Based on the same inventive concept, according to another aspect of the present invention, embodiments of the present invention also provide a computer device, comprising:

[0039] At least one processor; and

[0040] A memory storing a computer program executable on the processor, characterized in that the processor executes the program by performing the steps of any of the LZ77-based decoding methods described above.

[0041] Based on the same inventive concept, according to another aspect of the present invention, embodiments of the present invention also provide a computer-readable storage medium storing a computer program that, when executed by a processor, performs the steps of any of the LZ77-based decoding methods described above.

[0042] The present invention has one of the following beneficial technical effects: the solution proposed in the present invention enables the control terminal to remotely control the controlled terminal by simply logging into the email and sending emails, without the need to install any programs. Attached Figure Description

[0043] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other embodiments can be obtained based on these drawings without creative effort.

[0044] Figures 1-4 This is a schematic diagram of the encoding process based on LZ77;

[0045] Figure 5 A flowchart illustrating the LZ77-based decoding method provided for embodiments of the present invention;

[0046] Figure 6 A schematic diagram of a hardware architecture for implementing a decoding method based on LZ77, provided for embodiments of the present invention;

[0047] Figure 7 A schematic diagram of the structure of an external handshake module provided for an embodiment of the present invention;

[0048] Figure 8 A schematic diagram of the control module provided in an embodiment of the present invention;

[0049] Figure 9 A schematic diagram illustrating the decoding of matching pairs under different distance parameters, provided for embodiments of the present invention;

[0050] Figure 10 A schematic diagram illustrating the shift width of a shifter module provided in an embodiment of the present invention under different enable signals;

[0051] Figure 11 A schematic diagram of the structure of a decoding system based on LZ77 provided for an embodiment of the present invention;

[0052] Figure 12 A schematic diagram of the structure of a computer device provided for an embodiment of the present invention;

[0053] Figure 13A schematic diagram of the structure of a computer-readable storage medium provided for an embodiment of the present invention. Detailed Implementation

[0054] To make the objectives, technical solutions, and advantages of the present invention clearer, the embodiments of the present invention will be further described in detail below with reference to specific examples and the accompanying drawings.

[0055] It should be noted that all uses of "first" and "second" in the embodiments of the present invention are for the purpose of distinguishing two entities or parameters with the same name but different names. It is clear that "first" and "second" are only for the convenience of expression and should not be construed as limiting the embodiments of the present invention. Subsequent embodiments will not explain this in detail.

[0056] According to one aspect of the present invention, embodiments of the present invention propose a decoding method based on LZ77, such as... Figure 5 As shown, it may include the following steps:

[0057] S1, in response to receiving a number of characters, determine whether there is a matching pair among the number of characters;

[0058] S2, in response to the existence of the matching pair, obtain the data corresponding to the matching pair according to the distance parameter and length parameter in the matching pair;

[0059] S3, in response to the completion of decoding all matching pairs among the plurality of characters to be decoded, the acquired data is concatenated with the other received characters;

[0060] S4, the data already cached in the buffer is shifted using the concatenated data to update the invalid data in the buffer with the valid concatenated data, and a pointer is used to mark the number of bits of valid data in the buffer;

[0061] S5, in response to the number of bits of valid data in the pointer mark reaching a threshold, write all valid data in the buffer to RAM, and clear the number of bits of valid data in the pointer mark to zero so that all valid data in the buffer becomes invalid data.

[0062] The proposed solution can achieve parallel decoding of matching pairs and the original text. When decoding short matching pairs, the original text data can be obtained directly without accessing RAM, thereby effectively reducing the frequency of reading data in RAM and greatly improving the hardware's decoding capability to meet the throughput requirements of the upstream engine.

[0063] In some embodiments, Figure 6A schematic diagram of a hardware architecture for implementing the LZ77-based decoding method proposed in this invention is shown. It mainly comprises five modules: an external interface handshake module, a control module, a shifter module, a data buffer module, and a 32KB sliding window RAM. The following section combines... Figure 6 The hardware architecture diagram shown illustrates the LZ77-based decoding method proposed in this invention in detail.

[0064] In some embodiments, in step S1, in response to receiving a plurality of characters, it is determined whether there is a matching pair among the plurality of characters. Specifically, for example... Figure 7 As shown, character reception can be achieved through an external interface handshake module. This module mainly performs two functions: one is to handshake with the upstream Huffman decoding engine, sending a Ready signal after internal decoding is completed, and obtaining the next LZ77 format symbol to be decoded from the Huffman decoding engine. The other function is to select different data paths according to the application scenario. During normal compression and decompression, the data is input into this module in LZ77 format. However, in some application scenarios, the data may not have been compressed or decompressed, but rather the original data may be directly input into this module. In this case, the data still needs to be written to the sliding window RAM in a certain format and then output.

[0065] In some embodiments, in step S2, in response to the existence of the matching pair, data corresponding to the matching pair is obtained according to the distance parameter and length parameter in the matching pair. Specifically, the decoding can be controlled using a control module. The control module controls the decoding process through a state machine. When the character to be decoded is obtained, the control module calculates the position of the matching pair that needs to be decoded and whether RAM needs to be accessed. During the shifting and concatenation process, the module calculates the shift length and the address information to be accessed next.

[0066] In some embodiments, Figure 8The diagram shows the state machine transitions in the control module. Before decoding, initialization is performed first. The purpose of initialization is to restore the state at the end of the previous operation, ensuring correct decoding of the incoming data. After initialization, the system enters the ST_RCV_WAIT state. The handshake module generates an Rdy signal to retrieve a certain number of LZ77 format symbols to be decoded from the upstream Huffman decoding engine. Depending on the retrieved symbols, the state machine transitions to different states for decoding. If all the retrieved symbols are literals, the state machine enters the ST_RCV_LIT state, directly concatenating the original text with the existing original text in the data buffer. If a matching pair exists among the retrieved symbols, the state machine enters ST_RCV_MCH to begin decoding the first matching pair. If another matching pair remains after the first pair, decoding continues in this state. If the remaining symbols are all literals, the system directly enters the ST_RCV_LIT state for data concatenation. During ST_RCV_WAIT decoding of matching pairs, the system determines the position pointed to by the current matching pair and uses the distance parameter in the matching pair to determine the location for data retrieval.

[0067] In some embodiments, S2, in response to the existence of the matching pair, obtaining data corresponding to the matching pair based on the distance parameter and length parameter in the matching pair, further includes:

[0068] In response to the distance parameter being less than the number of received characters, data corresponding to the matching pair is obtained from the received characters based on the distance parameter and the length parameter.

[0069] In some embodiments, it also includes:

[0070] In response to the fact that the number of distance parameters greater than the plurality of characters is less than the sum of the threshold and the plurality of characters, data is read from the buffer;

[0071] Based on the distance parameter and the length parameter, data corresponding to the matching pair is obtained from the data read from the cache and the received characters.

[0072] In some embodiments, it also includes:

[0073] In response to the distance parameter being greater than the sum of the threshold and the number of the plurality of characters, data is read from the buffer and the RAM;

[0074] Based on the distance parameter and the length parameter, data corresponding to the matching pair is obtained from the data read from the buffer, the data in the RAM, and the received characters.

[0075] Specifically, if the distance parameter in the matching pair is less than the number of received characters, the data corresponding to the matching pair can be directly obtained from the received characters; if the distance parameter is greater than the number of characters but less than the sum of the threshold and the number of characters, the data in the buffer needs to be read; if the distance parameter is greater than the sum of the threshold and the number of characters, the data in the buffer and the RAM needs to be read.

[0076] For example, such as Figure 9 As shown, the current received character count is 5, where the first 4 characters are the original text and the 5th character is the matching pair. If the distance parameter D in the matching pair is less than 5, the matching pair can be directly decoded based on the first 4 characters. If the distance parameter in the matching pair is greater than 5 but less than 16, the matching pair needs to be decoded based on the first 4 characters and the data in the buffer. If the distance parameter in the matching pair is greater than 16, the buffer and the sliding window RAM need to be accessed to decode the matching pair based on the first 4 characters, the data in the buffer, and the data in the sliding window RAM.

[0077] The length parameter of the matching pair determines whether data needs to be read from the buffer or RAM, thereby obtaining the data corresponding to the matching pair. After all matching pairs are decoded, step S3 is performed, that is, in response to the completion of decoding all matching pairs among the several characters to be decoded, the obtained data is concatenated with other received characters to obtain the decoded data corresponding to the character received this time.

[0078] In some embodiments, shifting cached data in a buffer using the concatenated data to update invalid data in the buffer with valid concatenated data further includes:

[0079] The number of valid data bits that can still be written is determined based on the number of bits of valid data in the data already cached by the cache and the threshold.

[0080] The bit width of the shift is determined based on the number of bits of valid data that can still be written and the size of the concatenated data;

[0081] Several enable signals are generated based on the bit width of the shift, and then the corresponding bit width is shifted according to the several enable signals.

[0082] Specifically, the data cached in the buffer includes invalid data already written to RAM and valid data not yet written to RAM. Valid data refers to the data that has been concatenated but not yet written to the sliding window. It should be noted that data concatenation here refers to combining the concatenated data obtained in step S3 with the currently valid data in the buffer.

[0083] When the number of valid data bits marked by the pointer in the buffer reaches a threshold, the data in the buffer is written to RAM, and the number of valid data bits marked by the pointer is cleared to zero, making all valid data in the buffer invalid. Thus, when the concatenated data is written to the buffer, a shift operation can be performed to replace invalid data of the same length with the concatenated valid data, and the pointer is updated.

[0084] In some embodiments, such as Figure 10 As shown, the shifter module calculates the required data shift in the data buffer before concatenation based on the current configuration and control information. This invention employs a bucket-type shift circuit, which enables configurable shift operations. The shift width and direction can be selected using real-time configuration data. The control information, i.e., the enable signal, is generated by the controller module. In this invention, the shift operation can always be a left shift, so the value of `direct` on the right side is always 0. The shifter module triggers different enable signals based on the shift width to complete the shift operation of the specified width. Concatenating data in the buffer requires checking two things: the amount of data to be written upstream and the amount of valid data still available in the data buffer. The minimum of these two values ​​is used as the number of bytes for this shift operation.

[0085] For example, if the concatenated data obtained in step S3 is 6 bits, and the buffer still has 5 bits of valid data that can be written, then enable signals 1 and 3 can be generated, resulting in a 5-bit shift. After the 5-bit shift, the number of valid data bits in the buffer has reached the threshold, generating a RAM write signal to write the data into the sliding window. Simultaneously, the data is output as valid data. At this point, all data in the buffer is invalid, and only 5 bits of the concatenated data have been written. Therefore, enable signal 1 needs to be generated, and the buffer needs to be shifted by 1 bit again, writing the last bit of the concatenated data into the buffer. At the same time, the pointer marking the number of valid data bits is updated to 1, indicating that there is now 1 bit of valid data in the buffer.

[0086] In some embodiments, shifting cached data in a buffer using the concatenated data to update invalid data in the buffer with valid concatenated data further includes:

[0087] In response to the distance parameter being less than the length parameter in the matching pair, the identical parts of the concatenated data are continuously written into the buffer.

[0088] Specifically, as described above, when concatenating data in the buffer, the shift width of the shifter is taken as the minimum value of the upstream and downstream data amounts. If the length of a matching pair is greater than the distance, for example, the length is 50 and the distance is 1, then simply continue filling the downstream data buffer with the same data. Similar processing can be performed for distance values ​​of 1, 2, 3, and 4.

[0089] In some embodiments, it also includes:

[0090] The number of characters received each time is determined based on the preset first parameter.

[0091] Specifically, the number of input characters can be changed by configuring input parameters, thereby improving decoding efficiency.

[0092] The proposed solution enables parallel decoding of matching pairs and the original text. It caches the most recently decoded characters using a data buffer, allowing short matching pairs to directly access the data buffer without reading from RAM. This effectively reduces the frequency of RAM reads, significantly improving the hardware's decoding capabilities and meeting the throughput requirements of the upstream engine.

[0093] Based on the same inventive concept, according to another aspect of the present invention, embodiments of the present invention also provide an LZ77-based decoding system 400, such as... Figure 11 As shown, it includes:

[0094] The receiving module 401 is configured to, in response to receiving a plurality of characters, determine whether there is a matching pair among the plurality of characters;

[0095] The acquisition module 402 is configured to, in response to the existence of the matching pair, acquire data corresponding to the matching pair based on the distance parameter and length parameter in the matching pair;

[0096] The splicing module 403 is configured to splice the acquired data with other received characters in response to the completion of decoding all matching pairs among the plurality of characters to be decoded;

[0097] The update module 404 is configured to use the concatenated data to shift the cached data in the buffer to update the invalid data in the buffer to the valid concatenated data, and to use a pointer to mark the number of bits of the valid data in the buffer;

[0098] The write module 405 is configured to, in response to the number of bits of valid data in the pointer mark reaching a threshold, write all valid data in the buffer to RAM and clear the number of bits of valid data in the pointer mark to zero so that all valid data in the buffer becomes invalid data.

[0099] In some embodiments, the acquisition module 402 is further configured to:

[0100] In response to the distance parameter being less than the number of received characters, data corresponding to the matching pair is obtained from the received characters based on the distance parameter and the length parameter.

[0101] In some embodiments, the acquisition module 402 is further configured to:

[0102] In response to the fact that the number of distance parameters greater than the plurality of characters is less than the sum of the threshold and the plurality of characters, data is read from the buffer;

[0103] Based on the distance parameter and the length parameter, data corresponding to the matching pair is obtained from the data read from the cache and the received characters.

[0104] In some embodiments, the acquisition module 402 is further configured to:

[0105] In response to the distance parameter being greater than the sum of the threshold and the number of the plurality of characters, data is read from the buffer and the RAM;

[0106] Based on the distance parameter and the length parameter, data corresponding to the matching pair is obtained from the data read from the buffer, the data in the RAM, and the received characters.

[0107] In some embodiments, the update module 404 is further configured to:

[0108] The number of valid data bits that can still be written is determined based on the number of bits of valid data in the data already cached by the cache and the threshold.

[0109] The bit width of the shift is determined based on the number of bits of valid data that can still be written and the size of the concatenated data;

[0110] Several enable signals are generated based on the bit width of the shift, and then the corresponding bit width is shifted based on the several enable signals.

[0111] In some embodiments, the update module 404 is further configured to:

[0112] In response to the distance parameter being less than the length parameter in the matching pair, the identical parts of the concatenated data are continuously written into the buffer.

[0113] In some embodiments, a parameter module is also included, configured as follows:

[0114] The number of characters received each time is determined based on the preset first parameter.

[0115] The proposed solution enables parallel decoding of matching pairs and the original text. It caches the most recently decoded characters using a data buffer, allowing short matching pairs to directly access the data buffer without reading from RAM. This effectively reduces the frequency of RAM reads, significantly improving the hardware's decoding capabilities and meeting the throughput requirements of the upstream engine.

[0116] Based on the same inventive concept, according to another aspect of the present invention, such as Figure 12 As shown, embodiments of the present invention also provide a computer device 501, comprising:

[0117] At least one processor 520; and

[0118] The memory 510 stores a computer program 511 that can run on the processor. When the processor 520 executes the program, it performs the steps of any of the LZ77-based decoding methods described above.

[0119] Based on the same inventive concept, according to another aspect of the present invention, such as Figure 13 As shown, embodiments of the present invention also provide a computer-readable storage medium 601, which stores computer program instructions 610. When the computer program instructions 610 are executed by a processor, they perform the steps of any of the LZ77-based decoding methods described above.

[0120] Finally, it should be noted that those skilled in the art will understand that all or part of the processes in the above embodiments can be implemented by a computer program instructing related hardware. The program can be stored in a computer-readable storage medium, and when executed, it can include the processes of the embodiments of the above methods.

[0121] Furthermore, it should be understood that the computer-readable storage medium (e.g., memory) described herein may be volatile memory or non-volatile memory, or may include both volatile memory and non-volatile memory.

[0122] Those skilled in the art will also understand that the various exemplary logic blocks, modules, circuits, and algorithm steps described in conjunction with the disclosure herein can be implemented as electronic hardware, computer software, or a combination of both. To clearly illustrate this interchangeability between hardware and software, the functionality of various illustrative components, blocks, modules, circuits, and steps has been generally described. Whether this functionality is implemented as software or as hardware depends on the specific application and the design constraints imposed on the system as a whole. Those skilled in the art can implement the functionality in various ways for each specific application, but such implementation decisions should not be construed as departing from the scope of the embodiments disclosed herein.

[0123] The above are exemplary embodiments disclosed in this invention. However, it should be noted that various changes and modifications can be made without departing from the scope of the embodiments of this invention as defined by the claims. The functions, steps, and / or actions of the methods according to the disclosed embodiments described herein do not need to be performed in any particular order. Furthermore, although the elements disclosed in the embodiments of this invention may be described or claimed individually, they may be understood as multiple unless explicitly limited to a singular number.

[0124] It should be understood that, as used herein, the singular form “a” is intended to include the plural form as well, unless the context clearly supports an exception. It should also be understood that, as used herein, “and / or” refers to any and all possible combinations of one or more of the associated listed items.

[0125] The embodiment numbers disclosed in the above embodiments of the present invention are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments.

[0126] Those skilled in the art will understand that all or part of the steps of the above embodiments can be implemented by hardware or by a program instructing related hardware. The program can be stored in a computer-readable storage medium, such as a read-only memory, a disk, or an optical disk.

[0127] Those skilled in the art should understand that the discussion of any of the above embodiments is merely exemplary and is not intended to imply that the scope of the invention (including the claims) is limited to these examples. Within the framework of the invention, technical features of the above embodiments or different embodiments can be combined, and many other variations of different aspects of the invention exist, which are not provided in the details for the sake of brevity. Therefore, any omissions, modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the invention should be included within the protection scope of the invention.

Claims

1. A decoding method based on LZ77, characterized in that, Includes the following steps: In response to receiving a number of characters, determine whether there is a matching pair among the characters; In response to the existence of the matching pair, data corresponding to the matching pair is obtained based on the distance parameter and length parameter in the matching pair; In response to the completion of decoding all matching pairs among the aforementioned characters, the acquired data is concatenated with the other received characters; The concatenated data is used to shift the cached data in the buffer to update the invalid data in the buffer with the valid concatenated data, and a pointer is used to mark the number of bits of valid data in the buffer; In response to the pointer marking the number of valid data bits reaching a threshold, all valid data in the cache is written to RAM, and the pointer marking the number of valid data bits is cleared to make all valid data in the cache invalid.

2. The method as described in claim 1, characterized in that, In response to the existence of the matching pair, data corresponding to the matching pair is obtained based on the distance parameter and length parameter in the matching pair, further including: In response to the distance parameter being less than the number of received characters, data corresponding to the matching pair is obtained from the received characters based on the distance parameter and the length parameter.

3. The method as described in claim 2, characterized in that, Also includes: In response to the fact that the number of distance parameters greater than the plurality of characters is less than the sum of the threshold and the plurality of characters, data is read from the buffer; Based on the distance parameter and the length parameter, data corresponding to the matching pair is obtained from the data read from the cache and the received characters.

4. The method as described in claim 3, characterized in that, Also includes: In response to the distance parameter being greater than the sum of the threshold and the number of the plurality of characters, data is read from the buffer and the RAM; Based on the distance parameter and the length parameter, data corresponding to the matching pair is obtained from the data read from the buffer, the data in the RAM, and the received characters.

5. The method as described in claim 1, characterized in that, The method of shifting cached data in a buffer using the concatenated data to update invalid data in the buffer with valid concatenated data further includes: The number of valid data bits that can still be written is determined based on the number of bits of valid data in the data already cached by the cache and the threshold. The bit width of the shift is determined based on the number of bits of valid data that can still be written and the size of the concatenated data; Several enable signals are generated based on the bit width of the shift, and then the corresponding bit width is shifted based on the several enable signals.

6. The method as described in claim 1, characterized in that, The method of shifting cached data in a buffer using the concatenated data to update invalid data in the buffer with valid concatenated data further includes: In response to the distance parameter being less than the length parameter in the matching pair, the identical parts of the concatenated data are continuously written into the buffer.

7. The method as described in claim 1, characterized in that, Also includes: The number of characters received each time is determined based on the preset first parameter.

8. A decoding system based on LZ77, characterized in that, include: The receiving module is configured to, in response to receiving a number of characters, determine whether there is a matching pair among the characters; The acquisition module is configured to, in response to the existence of the matching pair, acquire data corresponding to the matching pair based on the distance parameter and length parameter in the matching pair; The concatenation module is configured to concatenate the acquired data with other received characters in response to the completion of decoding all matching pairs among the aforementioned characters; The update module is configured to use the concatenated data to shift the cached data in the buffer to update the invalid data in the buffer with the valid concatenated data, and to use a pointer to mark the number of bits of valid data in the buffer; The write module is configured to, in response to the number of valid data bits in the pointer mark reaching a threshold, write all valid data in the buffer to RAM and clear the number of valid data bits in the pointer mark to zero so that all valid data in the buffer becomes invalid data.

9. A computer device, comprising: At least one processor; as well as A memory storing a computer program executable on the processor, characterized in that the processor executes the program by performing the steps of the method as described in any one of claims 1-7.

10. A computer-readable storage medium storing a computer program, characterized in that, When the computer program is executed by a processor, it performs the steps of the method as described in any one of claims 1-7.

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