Integrated assemblies with rough material fill and methods of forming integrated assemblies

Abstract

Some embodiments include a structure having an opening extending into an integrated configuration. A first material is located within the opening and configured to create a wavy configuration relative to the sidewalls of the opening. The wavy configuration has a shape determined by an average roughness parameter R. mean Characterized surface roughness, the R mean It is the average peak-to-valley distance along the wavy configuration. The R... mean It is at least about 4 nm. The second material is located within the opening and along at least a portion of the wavy configuration. The first material and the second material are compositionally different from each other. Some embodiments include an integrated assembly. Some embodiments include a method of forming an integrated assembly.

Description

[0001] Relevant patent data

[0002] This application relates to U.S. Patent Application Serial No. 16 / 542,645, filed August 16, 2019, entitled "Integrated Assemblies Having Rugged Material Fill, and Methods of Forming Integrated Assemblies," the entire contents of which are incorporated herein by reference. Technical Field

[0003] Integrated assemblies (e.g., integrated NAND (“NAND”) assemblies) and methods of forming integrated assemblies. This disclosure relates to assemblies having a rough material filling in the gaps (grooves) and / or other openings. Background Technology

[0004] Memory provides data storage for electronic systems. Flash memory is a type of memory with numerous uses in modern computers and devices. For example, modern personal computers may have a BIOS stored on flash memory chips. As another example, it is becoming increasingly common for computers and other devices to use flash memory in solid-state drives to replace conventional hard drives. As yet another example, flash memory is popular in wireless electronic devices because, as wireless electronic devices become standardized, it enables manufacturers to support new communication protocols and provides the ability to remotely upgrade devices to enhance features.

[0005] NAND can be the basic architecture for flash memory and can be configured to include vertically stacked memory cells.

[0006] Before describing NAND in detail, it may be helpful to describe more generally the relationships of memory arrays within an integrated arrangement. Figure 1 shows a block diagram of a prior art device 1000, which includes a memory array 1002 having a plurality of memory cells 1003 arranged in rows and columns, and access lines 1004 (e.g., word lines WL0 to WLm for conducting signals) and first data lines 1006 (e.g., bit lines BL0 to BLn for conducting signals). The access lines 1004 and the first data lines 1006 are used to transmit information back and forth between the memory cells 1003. Row decoders 1007 and column decoders 1008 decode address signals A0 to AX on address lines 1009 to determine which memory cells 1003 will be accessed. Sensing amplifier circuitry 1015 operates to determine the value of the information read from the memory cells 1003. I / O circuitry 1017 transmits the value of the information between the memory array 1002 and the input / output (I / O) lines 1005. Signals DQ0 to DQN on I / O lines 1005 can represent values ​​of information read from or written to memory cell 1003. Other devices can communicate with device 1000 via I / O line 1005, address line 1009, or control line 1020. Memory control unit 1018 controls memory operations performed on memory cell 1003 and utilizes signals on control line 1020. Device 1000 can receive supply voltage signals Vcc and Vss on first supply line 1030 and second supply line 1032, respectively. Device 1000 includes selection circuit 1040 and input / output (I / O) circuit 1017. Selection circuit 1040 can respond to signals CSEL1 to CSELn via I / O circuit 1017 to select signals on first data line 1006 and second data line 1013 that represent values ​​of information read from or programmed into memory cell 1003. The column decoder 1008 can selectively activate the CSEL1 to CSELn signals based on the address signals A0 to AX on the address lines 1009. The selection circuit 1040 can select the signals on the first data line 1006 and the second data line 1013 to provide communication between the memory array 1002 and the I / O circuit 1017 during read and programming operations.

[0007] The memory array 1002 of Figure 1 may be a NAND memory array, and Figure 2 shows a schematic diagram of a three-dimensional NAND memory device 200 that can be used with the memory array 1002 of Figure 1. Device 200 includes multiple strings of charge storage devices. In a first direction (Z-Z'), each string of charge storage devices may include, for example, 32 charge storage devices stacked one on top of the other, wherein each charge storage device corresponds to, for example, one of 32 layers (e.g., layers 0 to 31). The charge storage devices of the respective strings may share a common channel region, such as a channel region formed in a corresponding pillar of a semiconductor material (e.g., polysilicon) around which the charge storage device string is formed. In a second direction (X-X'), each of the multiple strings in, for example, 16 first groups may include, for example, eight strings sharing multiple (e.g., 32) access lines (i.e., “global control gate (CG) lines”, also called word lines WL). Each of the access lines may couple to a charge storage device within a layer. When each charge storage device includes a cell capable of storing two bits of information, charge storage devices coupled by the same access line (and therefore corresponding to the same level) can logically be grouped into (e.g.) two pages, such as P0 / P32, P1 / P33, P2 / P34, etc. In the third direction (Y-Y'), each of the (e.g.) eight second groups of multiple strings can include 16 strings coupled by corresponding ones of the eight data lines. The size of the memory block can include 1,024 pages and approximately 16 MB in total (e.g., 16 WL × 32 levels × 2 bits = 1,024 pages / block, block size = 1,024 pages × 16 KB / page = 16 MB). The number of strings, levels, access lines, data lines, first groups, second groups, and / or pages can be greater than or less than the number shown in Figure 2.

[0008] Figure 3 shows a cross-sectional view of a memory block 300 of the 3D NAND memory device 200 of Figure 2 along the X-X' direction. The memory block 300 includes 15 strings of charge storage devices from one of 16 first groups of strings described in Figure 2. The multiple strings of the memory block 300 can be divided into multiple subsets 310, 320, 330 (e.g., stacked blocks). I , block column j and block list KEach subset (e.g., a chip column) comprises a “partial block” of memory block 300. A global drain-side select-gate (SGD) line 340 may be coupled to multiple strings of SGDs. For example, the global SGD line 340 may be coupled to multiple (e.g., three) sub-SGD drivers 332, 344, 346 via corresponding sub-SGD drivers 332, 334, 336, each sub-SGD line corresponding to a corresponding subset (e.g., a chip column). Each of the sub-SGD drivers 332, 334, 336 may simultaneously couple or disconnect the SGD of the corresponding partial block (e.g., a chip column) of strings independently of the SGDs of the strings of other partial blocks. A global source-side select-gate (SGS) line 360 ​​may be coupled to multiple strings of SGSs. For example, a global SGS line 360 ​​can be coupled to multiple sub-SGS lines 362, 364, and 366 via corresponding ones of multiple sub-SGS drivers 322, 324, and 326, where each sub-SGS line corresponds to a corresponding subset (e.g., a block column). Each of the sub-SGS drivers 322, 324, and 326 can simultaneously couple or disconnect the SGS of the corresponding sub-block (e.g., a block column) string, independent of the SGS of the strings of other sub-blocks. A global access line (e.g., a global CG line) 350 can couple to the charge storage device corresponding to the corresponding level of each of the multiple strings. Each global CG line (e.g., global CG line 350) can be coupled to multiple sub-access lines (e.g., sub-CG lines) 352, 354, and 356 via corresponding ones of multiple sub-string drivers 312, 314, and 316. Each of the sub-string drivers can simultaneously couple or disconnect the charge storage device corresponding to the corresponding sub-block and / or level, independent of the charge storage devices of other sub-blocks and / or other levels. The charge storage device corresponding to the corresponding subset (e.g., partial block) and the corresponding level may include a “partial level” of the charge storage device (e.g., a single “piece”). The string corresponding to the corresponding subset (e.g., partial block) may be coupled to the corresponding one in sub-sources 372, 374 and 376 (e.g., “piece source”), wherein each sub-source is coupled to a corresponding power source.

[0009] Alternatively, the NAND memory device 200 is described with reference to the schematic illustration of FIG4.

[0010] Memory array 200 includes word lines 2021 to 202 N and position lines 2281 to 228 M .

[0011] Memory array 200 also includes NAND strings 2061 to 206 M Each NAND string contains 2081 to 208 charge storage transistors. NCharge storage transistors can use floating gate materials (such as polysilicon) to store charge, or they can use charge trapping materials (such as silicon nitride, metal nanodots, etc.) to store charge.

[0012] A charge storage transistor 208 is located at the intersection of word line 202 and string 206. The charge storage transistor 208 represents a non-volatile memory cell used for storing data. The charge storage transistor 208 of each NAND string 206 is connected in series from source to drain between a source select device (e.g., source-side select gate SGS) 210 and a drain select device (e.g., drain-side select gate SGD) 212. Each source select device 210 is located at the intersection of string 206 and source select line 214, and each drain select device 212 is located at the intersection of string 206 and drain select line 215. Select devices 210 and 212 can be any suitable access device and are generally illustrated in boxes in FIG. 4.

[0013] The source of each source select device 210 is connected to a common source line 216. The drain of each source select device 210 is connected to the source of the first charge storage transistor 208 corresponding to the NAND string 206. For example, the drain of source select device 2101 is connected to the source of the charge storage transistor 2081 corresponding to the NAND string 2061. The source select device 210 is connected to the source select line 214.

[0014] The drain of each drain selector 212 is connected to the bit line (i.e., digital line) 228 at its drain contact. For example, the drain of drain selector 2121 is connected to bit line 2281. The source of each drain selector 212 is connected to the drain of the last charge storage transistor 208 of the corresponding NAND string 206. For example, the source of drain selector 2121 is connected to the charge storage transistor 208 of the corresponding NAND string 2061. N The drain electrode.

[0015] The charge storage transistor 208 includes a source 230, a drain 232, a charge storage region 234, and a control gate 236. The charge storage transistor 208 couples its control gate 236 to a word line 202. A row of charge storage transistors 208 are transistors coupled to a given word line 228 within a NAND string 206. A row of charge storage transistors 208 are transistors that are collectively coupled to a given word line 202.

[0016] Figures 5 and 5A illustrate a region of an instance prior art integration assembly 10, which is part of an instance NAND configuration. Assembly 10 includes a pair of sub-blocks within a tile region. The sub-blocks may be referred to as block regions 11. The sub-blocks and tiles may be incorporated into a three-dimensional NAND architecture of the type described in Figures 1 to 4 above.

[0017] Partition 12 extends around the sub-blocks and separates the sub-blocks from each other and from other sub-blocks. Partition 12 includes partition material 14. Partition material 14 may include silicon dioxide, is substantially composed of silicon dioxide, or is composed of silicon dioxide.

[0018] The cross-sectional view of Figure 5A shows assembly 10, which includes a stack 16 of alternating conductive layers 18 and insulating layers 20. Layers 18 include conductive material 19, and layers 20 include insulating material 21.

[0019] Block 11 is laterally offset from the stepped region (labeled "step" in Figure 5), which is the region that is in electrical contact with at least some of the stacked conductive layers 18.

[0020] The conductive material 19 may include any suitable conductive composition, such as one or more of various metals (e.g., titanium, tungsten, cobalt, nickel, platinum, ruthenium, etc.), metal-containing compositions (e.g., metal silicides, metal nitrides, metal carbides, etc.), and / or conductive doped semiconductor materials (e.g., conductive doped silicon, conductive doped germanium, etc.). In some embodiments, the conductive material 19 may include a metal (e.g., tungsten) and a metal nitride (e.g., tantalum nitride, titanium nitride, etc.).

[0021] The insulating material 21 may include any suitable composition, and in some embodiments may include silicon dioxide, be substantially composed of silicon dioxide, or be composed of silicon dioxide.

[0022] Layers 18 and 20 may have any suitable thickness and may have the same thickness as each other or different thicknesses relative to each other. In some embodiments, layers 18 and 20 may have a vertical thickness ranging from about 10 nanometers (nm) to about 400 nm.

[0023] In some embodiments, the lowest conductive layer 18 may represent a source select device (e.g., a source-side select gate SGS), and the upper conductive layer 18 may represent a word line layer. The source select device layer may or may not include the same conductive material as the word line layer.

[0024] Although Figure 5A shows eight conductive levels 18, there can actually be more than eight conductive levels in the stack 16. For example, word line levels can ultimately correspond to memory cell levels in a NAND configuration. The NAND configuration will contain memory cell strings (i.e., NAND strings), where the number of memory cells in a string is determined by the number of vertically stacked word line levels. NAND strings can include any suitable number of memory cell levels. For example, NAND strings can have 8 memory cell levels, 16 memory cell levels, 32 memory cell levels, 64 memory cell levels, 512 memory cell levels, 1024 memory cell levels, and so on. Furthermore, the source selection device can contain more than one conductive level.

[0025] Stack 16 and partition 12 are supported above conductive structure 22. This conductive structure may include a semiconductor material (not specifically depicted in the figure) above a metallic material (not specifically depicted in the figure). The semiconductor material may include any suitable composition and, in some embodiments, may include one or more of, substantially consist of one or more of, or consist of one or more of the following: silicon, germanium, group III / V semiconductor materials (e.g., gallium phosphide), semiconductor oxides, etc., wherein the term "group III / V semiconductor material" refers to a semiconductor material comprising elements selected from groups III and V of the periodic table (where group III and V are older designations and are now referred to as groups 13 and 15). In some embodiments, the semiconductor material may include conductive doped silicon, such as, for example, n-type doped polycrystalline silicon. The metallic material may include any suitable composition, such as, for example, one or more of various metals (e.g., titanium, tungsten, cobalt, nickel, platinum, ruthenium, etc.) and / or metallic compositions (e.g., metal silicides, metal nitrides, metal carbides, etc.).

[0026] In some embodiments, conductive structure 22 may correspond to a source structure (e.g., a structure including the so-called common source line 216 of FIG4). According to conventional nomenclature, the source structures of FIG1 to 4 are referred to as “lines”, but such lines may consist of broad rather than simple wiring lines.

[0027] A channel material pillar 24 extends through the stack 16. The pillar 24 includes a channel material 26. The channel material 26 may be a suitably doped semiconductor material, and in some embodiments may include silicon. The channel material 26 is spaced from the materials 19 and 21 of the stack 16 by a region 28. Such regions may include one or more of a dielectric barrier material, a charge blocking material, a charge storage material, and a gate dielectric material (i.e., a tunneling material).

[0028] The described channel material structure 24 is a hollow channel configuration, wherein the channel material 26 laterally surrounds the insulating material 29. The insulating material 29 may include any suitable composition, and in some embodiments may include silicon dioxide. In other embodiments (not shown), the channel material structure 24 may be a solid column.

[0029] Memory cell 30 (partially labeled) is the region along conductive layer 18 that includes channel material 26 and the materials within region 28 (i.e., dielectric barrier material, charge blocking material, charge storage material, and gate dielectric material). Memory cell 30 may be arranged as a vertical NAND string of the type described in Figures 1 to 4. Memory cell 30 may be referred to as a NAND memory cell, and conductive layer 18 may be referred to as a NAND word line layer.

[0030] The conductive structure 22 may be supported by a semiconductor substrate 32. The term "semiconductor substrate" means any construction comprising semiconducting materials, including (but not limited to) bulk semiconducting materials (e.g., a semiconducting wafer) (alone or in a combination including other materials) and layers of semiconducting materials (alone or in a combination including other materials). The term "substrate" refers to any support structure comprising (but not limited to) the aforementioned semiconductor substrate. A gap is provided between the substrate 32 and the structure 22 to indicate that other materials and components may be provided between the substrate 32 and the structure 22.

[0031] The conductive structure 22 is shown to be electrically coupled to a CMOS (Complementary Metal-Oxide-Semiconductor). The CMOS may be located in any suitable position relative to the conductive structure 22, and in some embodiments may be located below this conductive structure and supported by a substrate 32. The CMOS may include logic or other suitable circuitry for driving the source structure 22 during memory operations associated with the stack 16. Although the circuitry is specifically identified as CMOS in the embodiment of FIG. 5A, it should be understood that in other embodiments, this circuitry may be replaced by any other suitable circuitry.

[0032] Figures 5 and 5A show the desired arrangement in which block 11 is properly oriented above structure 22. However, in practice, it is sometimes found that the actual arrangement has inclined block areas due to reasons described in Figures 6 to 8 (as shown in Figure 8).

[0033] Figure 6 illustrates assembly 10 in a prior art process stage that can be used to form the assembly of Figure 5A. A slot (trench) 34 through the stack 16 has been formed in the location where the panel 12 of Figure 5A will eventually be formed. In some applications, the conductive layer 18 is formed by replacing the sacrificial material (e.g., silicon nitride) with a conductive material 19 (so-called gate substitution), and the slot 34 provides an entrance and exit point for this substitution.

[0034] Referring to Figure 7, material 14 is formed within slot 34. Material 14 can be one or more of a dielectric, semiconductor, metal, etc., and in some applications may include amorphous silicon. Figure 7 illustrates a process stage where material 14 has only partially filled the slots. A potential problem is that as slot 34 is filled by material 14, various forces (stress, cohesion, etc.) can cause bulk 11 to bend, resulting in the undesired configuration of Figure 8. Specifically, one of the slots 34 has collapsed (the central slot shown in Figure 8), and the other slots 34 have widened. Material 14 within the collapsed slot has coalesced across the slot, clamping it. The configuration of Figure 8 can lead to overturning and / or other uncertain structural problems and ultimately device failure. In some applications, the large void at the bottom of the central slot in Figure 8 can be primarily filled. Cohesion along the smooth surface of material 14 is partly responsible for the bulk bending problem.

[0035] This is expected to alleviate or prevent the gap collapse (and associated block bending) problem shown in Figure 8. Attached Figure Description

[0036] Figure 1 shows a block diagram of a prior art memory device having a memory array containing memory cells.

[0037] Figure 2 shows a schematic diagram of the prior art memory array of Figure 1 in the form of a 3D NAND memory device.

[0038] Figure 3 shows a cross-sectional view of the prior art 3D NAND memory device of Figure 2 along the X-X' direction.

[0039] Figure 4 is a schematic diagram of a conventional NAND memory array.

[0040] Figure 5 is a schematic top view of the area illustrating the existing technology integration components of the instance architecture.

[0041] Figure 5A is a schematic cross-sectional side view of the prior art integrated assembly of Figure 5 along line AA of Figure 5.

[0042] Figure 6 is a schematic cross-sectional side view of a prior art integrated assembly in a prior art process stage that can be used to form the assembly of Figure 5A.

[0043] Figures 7 and 8 are schematic cross-sectional side views of the prior art integrated assembly of Figure 6 in the prior art process stage following the process stage of Figure 6.

[0044] Figure 9 This is a schematic cross-sectional side view of the assembly in an example process stage following the process stage shown in Figure 6.

[0045] Figure 10 It is possible Figure 9 Example process stages after the process stage Figure 9 A schematic cross-sectional side view of the assembly.

[0046] Figure 11 It is possible Figure 9 Example process stages after the process stage Figure 9 A schematic cross-sectional side view of the assembly.

[0047] Figure 12A It is a description similar to Figure 10 A graph showing the roughness of an embodiment relative to the horizontal dimension of depth.

[0048] Figure 12B It is a description similar to Figure 11 A graph showing the roughness of an embodiment relative to the horizontal dimension of depth.

[0049] Figure 13 It is possible Figure 10 Example process stages after the process stage Figure 9 A schematic cross-sectional side view of the assembly.

[0050] Figure 14 This is a schematic cross-sectional side view of another example of an integrated assembly.

[0051] Figure 15 This is a schematic cross-sectional side view of another example of an integrated assembly.

[0052] Figure 16 It is possible Figure 15 Example process stages after the process stage Figure 15 A schematic cross-sectional side view of the assembly.

[0053] Figure 17 This is a schematic cross-sectional side view of another example of an integrated assembly.

[0054] Figure 18A and 18B This is a schematic cross-sectional top view of another example of an integrated assembly. Figure 18A ) and a rough cross-sectional side view ( Figure 18B ). Figure 18A The cross section is along Figure 18B Line AA, and Figure 18B The cross section is along Figure 18A BB line. Detailed Implementation

[0055] Some embodiments include methods of forming integrated assemblies in which a roughening material is provided within slots (grooves) (e.g., slots in a three-dimensional NAND flash memory that separate adjacent block regions from each other). The roughening material can mitigate or eliminate block bending problems, such as those described above with reference to Figures 6-8. The roughening material may only partially fill the slots, and additional material may be deposited within the slots to fill around the roughening material. Some embodiments include integrated assemblies having a roughening-filling material within the grooves and / or other openings. The roughening-filling material can provide a roughness determined by the average roughness (R0). mean ) and / or maximum roughness (R max Characterized roughening configurations, where roughness is measured as the peak-valley size along the configuration. The roughening-filling material may have an average particle size of at least about 4 nanometers (nm). Reference Figure 9 Example implementations will be described up to 18.

[0056] refer to Figure 9The diagram illustrates an integrated assembly (configuration, construction, structure, architecture, memory device, etc.) 10 that can be performed in a process stage following the prior art processing stage discussed above in Figure 6. A stack 16 has been formed with alternating insulating layers 20 and conductive layers 18, and channel material pillars 24 extending through the stack 16 have been formed. Gaps (openings, recesses, trenches, etc.) 34 extending through the stack 16 and subdividing the stack into blocks 11 have also been formed.

[0057] The gap 34 includes sidewalls 35 and a bottom 37, wherein the bottom 37 is adjacent to the conductive structure 22, and the sidewalls 35 are adjacent to the conductive material 19 and the insulating material 21 of layers 18 and 20. Optional insulating material 38 is formed within the gap 34 to line the sidewalls and bottom of the gap. The insulating material 38 can be considered as configured as an insulating liner 40 provided within the gap 34.

[0058] The insulating material 38 may include any suitable composition, and in some embodiments may include one or more of silicon dioxide, silicon nitride, high-k dielectric materials (e.g., alumina), and low-k dielectric materials (e.g., porous silicon dioxide). The term "high-k dielectric material" means a dielectric material having a dielectric constant greater than that of silicon dioxide, and the term "low-k dielectric material" means a dielectric material having a dielectric constant less than that of silicon dioxide.

[0059] The insulating material 38 has a thickness “T”. This thickness can range from about 10 nm to about 100 nm, and in some embodiments it can be less than or equal to about 40 nm.

[0060] refer to Figure 10 A first material 42 is formed within a liner-lined slot (liner-lined opening) 34. The first material 42 partially fills the liner-lined slot 34, leaving an unfilled area 50 within the slot 34. In the illustrated embodiment, the first material 42 is configured as large particles 44 (only a portion of them are labeled). In some embodiments, particles 44 may correspond to individual (discrete) crystalline particles. In other embodiments, particles 44 may be polycrystalline, amorphous, etc.

[0061] The first material 42 can be referred to as the granular first material. This granular first material has the following characteristics: Figure 10 The average maximum particle size of the cross section (Dmax) mean The average maximum particle size corresponds to the average of the maximum cross-sectional dimensions of the individual particles along the cross-section passing through the particle. Any suitable method can be used to determine the average maximum particle size. An example of the maximum cross-sectional dimension 46 of one of the particles 44 within the central gap 34 is illustrated. The maximum cross-sectional dimension 46 is exactly along the cross-section relative to the particle size. Figure 10The maximum cross-sectional size is perpendicular to the cross-section. Other particles may have the maximum cross-sectional size extending in other directions. If the particles are individual particles, then the average maximum particle size (Dmax) is... mean This can correspond to the average particle size (Gr) mean ).

[0062] In some embodiments, the maximum horizontal size of the particles can be used to quantify the roughness characteristics of the particles relative to the sidewall 35 of the slit 34. An example of the maximum horizontal particle size 48 relative to one of the particles 44 within the central slit 34 is illustrated.

[0063] In some embodiments, along Figure 10 The average maximum particle size (Dmax) of the cross-section of the particles is 44. mean The average particle size will be at least about 4 nm. In some embodiments, the maximum average particle size may be at least about 10 nm, at least about 20 nm, at least about 50 nm, at least about 100 nm, etc.

[0064] In some embodiments, along Figure 10 The average horizontal particle size 48 of the cross-section of the particles 44 can be at least about 4 nm, at least about 10 nm, at least about 20 nm, at least about 50 nm, at least about 100 nm, etc.

[0065] In some embodiments, the average maximum particle size of particle 44 may be related to the width W of slit 34. This width may, for example, be in the range of about 100 nm to about 500 nm. Figure 10 The average maximum particle size of the cross-section of the particles 44 may be at least about 1% of the width W, at least about 2% of the width W, at least about 5% of the width W, at least about 10% of the width W, at least about 25% of the width W, at least about 40% of the width W, etc.

[0066] exist Figure 10 In the illustrated embodiment, the unfilled region 50 is located between the particles 44 of the granular first material 42.

[0067] The granular first material 42 may be formed by any suitable method including, for example, atomic layer deposition (ALD), chemical vapor deposition (CVD), sputtering, physical vapor deposition (PVD), etc.

[0068] The first material 42 may include any suitable composition, and in some embodiments may include insulating materials, conductive materials, and / or semiconductor materials.

[0069] If the first material 42 includes a conductive material, then this conductive material may include one or more of any suitable conductive composition, such as (e.g.) various metals (e.g., titanium, tungsten, cobalt, nickel, platinum, ruthenium, etc.), metal-containing compositions (e.g., metal silicides, metal nitrides, metal carbides, etc.), and / or conductive doped semiconductor materials (e.g., conductive doped silicon, conductive doped germanium, etc.). In some embodiments, the conductive material may include one or more metals. Such metals may include one or more of copper (Cu), aluminum (Al), silver (Ag), gold (Au), and iron (Fe), and particles 44 may be formed by sputtering deposition of such metals. In some embodiments, the conductive material may include one or both of tungsten (W) and titanium (Ti), and may further include one or both of silicon (Si) and nitrogen (N). Thus, the conductive material may include one or more of W, Ti, WN, TiN, WSi, TiSi, WSiN, and TiSiN, wherein the chemical formula indicates the major component rather than a specific stoichiometry.

[0070] In some embodiments, the first material may comprise a combination of one or more metals and one or more of boron (B), carbon (C), silicon (Si), germanium (Ge), nitrogen (N), and oxygen (O).

[0071] In some embodiments, the first material may comprise one or both of silicon (Si) and germanium (Ge). If the first material comprises both silicon and germanium, the relative proportion of silicon to germanium may range from about 1 atomic percentage (at%) to about 99 at%. The first material may be a semiconductor material composed of one or both of Si and Ge, or substantially composed of one or both of Si and Ge. Alternatively, the first material may be a conductive material incorporating one or more of boron (B), phosphorus (P), and arsenic (As) into silicon and / or germanium. In some exemplary embodiments, the first material may comprise silicon and / or germanium, and may further comprise one or more additional components selected from the group consisting of boron, phosphorus, and arsenic. The total concentration of the additional components in the first material may range from about 0.5 at% to about 5 at%. In such embodiments, the first material may be formed by CVD to produce the illustrated particles 44.

[0072] In embodiments where the granular first material is an insulating material, the first material may include, for example, silicon dioxide, silicon nitride, aluminum oxide, etc.

[0073] The large particles of the first material 42 can alleviate the problems described above with reference to Figure 8 of the prior art. For example, the large particles can redistribute force along the inner wall of the gap 34 to prevent gap collapse, and / or can eliminate the problem of material agglomeration from one side of the gap 34 with material along the other side of the gap.

[0074] Figure 10The configuration presents particles 44 as discrete particles within the slit 34. In other embodiments, at least some particles may aggregate and / or otherwise merge. For example, Figure 11 The configuration in which particles 44 (partially marked) have been merged along the inner surface with lining gaps 34 is shown.

[0075] In some embodiments, Figure 10 and 11 The particles 44 can be considered to produce a wavy configuration relative to the sidewalls 35 of the slot 34. In the illustrative embodiment in which the slot 34 is lined by an optional lining material 38, the lined slot can be considered to have sidewalls 51. A wavy configuration relative to the sidewalls 51 can be described.

[0076] Figure 12A Using curves to illustrate similar concepts to those mentioned above. Figure 10 The described embodiment illustrates the relationship between the horizontal dimension and depth of the granular material 42 within one of the slots 34. Figure 10 The horizontal dimensions (H) and depth (D) of the rightmost slit 34. Figure 12A Displaying particle 44 ( Figure 12A (Only a portion of it is marked) protrudes horizontally to form a wavy configuration 52 extending along the surface 44 and sidewall surface 51 of the particle 44. The wavy configuration 52 has peaks (P) and troughs (V), and has a surface roughness quantifiable according to the peak-trough distance 54. Relative to Figure 12A To illustrate, consider two examples with a peak-to-valley distance of 54. The wavy configuration can have a peak-to-valley distance determined by the average roughness parameter (R). mean Characterized surface roughness, R mean It is the average peak-to-valley distance along the entire wavy configuration 52. In some embodiments, R mean It can be at least about 4nm, at least about 10nm, at least about 20nm, at least about 50nm, at least about 100nm, etc.

[0077] In some embodiments, surface roughness can also be determined by the maximum roughness parameter (R). max ) Attributed, R max This is the maximum peak-to-valley distance along the wavy configuration 52. In the illustrated embodiment, this maximum peak-to-valley distance is... Figure 12A The particle marked 44a is associated with it. In some embodiments, R max It can be at least about 10nm, at least about 20nm, at least about 50nm, at least about 100nm, at least about 150nm, at least about 200nm, etc.

[0078] Figure 12B Using curves to illustrate similar concepts to those mentioned above. Figure 11The described embodiment illustrates the relationship between the horizontal dimension and depth of the granular material 42 within the embodiment. It shows the relationship relative to... Figure 11 The horizontal dimensions (H) and depth (D) of the rightmost slit 34. Figure 12B Displaying particle 44 ( Figure 12B (Only a portion of it is marked) protrudes along the horizontal dimension to form a wavy configuration 52. This wavy configuration has crests (P) and troughs (V), and has a surface roughness quantifiable according to the peak-to-trough distance 54. Relative to Figure 12B To demonstrate two examples, the peak-to-valley distance is 54. Figure 12B The average roughness parameter (R) of the embodiment mean The wavelengths can be at least about 4nm, at least about 10nm, at least about 20nm, at least about 50nm, at least about 100nm, etc.

[0079] Figure 12B The wavy configuration 52 can also be determined by the maximum roughness parameter (R). max Characterization, and in the illustrated embodiments, this corresponds to... Figure 12B The peak-valley distance associated with the particle marked 44a. Figure 12B R in the embodiment max It can be at least about 10nm, at least about 20nm, at least about 50nm, at least about 100nm, at least about 150nm, at least about 200nm, etc.

[0080] This describes the surface 51 of the lining 40 relative to the lining gap 34. Figure 12A and 12B The wavy configuration 52. It should be understood that the wavy configuration can also be described relative to the sidewall 35 of the slot 34 and can be composed of at least the wavy configuration relative to the sidewall 35 of the slot 34. Figure 12A and 12B The described average roughness parameter (R) mean ) and maximum roughness parameter (R) max The same size R mean and R max Characterization.

[0081] refer to Figure 13 The display can be found Figure 10 The integrated assembly (memory device) 10 in the process stage following the process stage. The second material 56 is formed in the space 50 between the particles 44. Figure 10 The second material 56 is a portion that fills (or at least partially fills) the gaps 34 between the particles 44. The second material may have a composition different from the first material 42. In some embodiments, the second material 56 may be considered as being formed along at least a portion of the wavy configuration 52 (wherein showing relative to...) Figure 13The leftmost slit 34 is an example of the region of the wavy configuration 52. The wavy configuration 52 can be considered as a rough configuration extending across the surface of the rough granular material 42. In some embodiments, the second material 56 may be omitted, such that voids remain within the space between the particles 44. In some embodiments, the second material 56 may be used only along the top region of the slit 34 to seal the voids within the slit and between the particles 44.

[0082] In some embodiments, Figure 13 Individual particles 44 can be considered to be at least partially surrounded by the second material 56. In embodiments where particles 44 correspond to discrete particles, such discrete particles can be considered to be at least partially surrounded by the second material 56.

[0083] The second material 56 may include any suitable composition and, in some embodiments, may include an insulating material, a conductive material, and / or a semiconducting material. For example, in some embodiments, the second material 56 may include silicon dioxide formed by a spin-on dielectric (SOD) process. In some embodiments, the second material may include one or more of titanium nitride, silicon nitride, aluminum oxide, tungsten, silicon dioxide, semiconductor materials (e.g., silicon, germanium, etc.). The second material 56 may be formed by one or more of ALD, CVD, PVD, etc.

[0084] If the second material 56 includes a semiconductor material (e.g., silicon), then the semiconductor material may be in any suitable physical form (e.g., one or more of polycrystalline, amorphous, etc.).

[0085] In some embodiments, the second material may include one or more of titanium, tungsten, and silicon. In some embodiments, the second material may include a combination of one or both of oxygen and nitrogen with one or more of titanium, tungsten, and silicon (e.g., may include TiO, SiO, SiN, TiN, TiSiN, WN, etc., wherein the chemical formula indicates the major component rather than a specific stoichiometry).

[0086] In some embodiments, the large particles 44 may be considered as providing support to the block region 11 to prevent it from bending during the formation of the filler material 56.

[0087] The first material 42 and the second material 56 can be considered together as a composite filler formed within the gap 34.

[0088] In applications where one or both of the first material 42 and the second material 56 are conductive, the liner 40 can serve as an insulating barrier. If materials 42 and 56 are insulating, then the liner 40 can be omitted. Figure 14 The first material 42 and the second material 56 are shown to be insulating, and the liner 40 is omitted. Figure 13The integrated assembly (memory device) 10 in the application. Therefore, the first material 42 and the second material 56 directly abut against the materials 19 and 21 of the stack 16.

[0089] In some embodiments, the gaps 34 may be partially filled before the particles 44 forming the first material 42. For example, Figure 15 An embodiment is shown in which gap 34 is partially filled by material 58. Material 58 may be referred to as a third material to distinguish it from the previously described first material 42 and second material 56.

[0090] Material 58 may include any suitable composition. In some embodiments, material 58 may include one or more of the materials described above as suitable for the second material 56 (e.g., may include silicon dioxide, silicon nitride, semiconductor materials, etc.).

[0091] In the illustrated embodiment, an optional barrier material (liner material) 38 is provided within the gap 34. In other embodiments, this barrier material may be omitted.

[0092] The gap 34 can be filled horizontally by material 58, which reduces the total volume of the gap that will subsequently be filled by the first material 42 and the second material 56, and does not cause the block bending problem described above with reference to FIG8. In some embodiments, material 58 can fill about 1% to about 99% of the volume of the lined gap 34.

[0093] refer to Figure 16 A first material 42 and a second material 56 are formed within the gap 34 to fill the area of ​​the gap above the material 58. In some embodiments, the second material 56 and the third material 58 may comprise the same composition as each other. In other embodiments, the second material 56 and the third material 58 may comprise different compositions as each other. The first material 42, the second material 56, and the third material 58 may be considered together as a composite filler formed within the gap 34.

[0094] In some embodiments, the particles 44 may clamp the area of ​​the gap 34, such that the void remains within the area of ​​the gap after the second material 56 is formed. For example, Figure 17 This demonstrates an application similar to that in which particles 44 clamp the region of gap 34 before the formation of the second material 56. Figure 13 The example integrated assembly (memory device) 10 is part of the process stage of the process. Therefore, voids 60 are retained in some areas of the slot 34. Voids 60 are at least partially surrounded by the first material 42 of the particles 44. It should be noted that the opposing walls of the slot 34, which allow the particles 44 to contact the slot 34, can provide the desired structural support to alleviate or prevent bulk bending, such as relative to... Figure 17 The central gap 34 is shown. It should also be noted that even though particle 44 appears to be along... Figure 17The cross-section cuts off the gap, but the gap can be relative to... Figure 17 The cross section extends into and out of the page and can have Figure 17 The exposed area outside the plane (not interrupted by particle 44).

[0095] Slit 34 is an example of an opening that can be filled using the composite filler described above. In other applications, other types of openings can be filled using this type of composite filler. Figure 18A and 18B An example opening 62 is schematically described as being formed by material 64 extending through the integrated structure 66. A composite filler 68 is located within the opening. The composite filler includes the first material 42 and the second material 56 described above, wherein the first material 42 is configured as particles 44.

[0096] The assemblies and structures discussed above can be used within integrated circuits (where the term "integrated circuit" means electronic circuitry supported by a semiconductor substrate) and incorporated into electronic systems. Such electronic systems can be used in, for example, memory modules, device drivers, power supply modules, communication modems, processor modules, and special-purpose modules, and can comprise multi-layer, multi-chip modules. Electronic systems can be any of a variety of systems, such as, for example, cameras, wireless devices, displays, chipsets, video converters, games, lighting equipment, vehicles, clocks, televisions, cellular phones, personal computers, automobiles, industrial control systems, aircraft, and so on.

[0097] Unless otherwise stated, any suitable method now known or yet to be developed (including, for example, atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), etc.) may be used to form the various materials, substances, compositions, etc. described herein.

[0098] The terms “dielectric” and “insulating” are used to describe materials having insulating electrical properties. These terms are considered synonymous in this disclosure. The use of the term “dielectric” in some instances and the term “insulating” (or “electrically insulating”) in others is a linguistic variation within this disclosure to simplify the pre-basis of the appended claims and is not intended to indicate any chemical or electrical differences.

[0099] The terms “electrical connection” and “electrical coupling” are both used in this disclosure. The terms are considered synonymous. The use of one term in some instances and another in others provides linguistic variation within this disclosure to simplify the pre-basis of the following claims.

[0100] The specific orientations of the various embodiments in the drawings are for illustrative purposes only, and in some applications, embodiments may be rotated relative to the shown orientation. Regardless of whether the structure is in or rotated relative to the specific orientation shown in the drawings, the descriptions provided herein and the following claims are suitable for any structure having various descriptive relationships.

[0101] The cross-sectional views in the accompanying drawings show only the features within the cross-sectional plane and do not show the material behind the cross-sectional plane (unless otherwise indicated) to simplify the illustration.

[0102] When a structure is referred to above as "on another structure," "adjacent to another structure," or "against another structure," it may be directly on said other structure or there may be an intermediate structure present. In contrast, when a structure is referred to as "directly on another structure," "directly adjacent to another structure," or "directly against another structure," there is no intermediate structure. The terms "directly below," "directly above," etc., do not indicate direct physical contact (unless explicitly stated otherwise), but rather indicate vertical alignment.

[0103] A structure (such as a layer, material, etc.) may be described as “vertically extending” to indicate that the structure generally extends upward from the underlying substrate (such as a base plate). A vertically extending structure may extend generally orthogonally relative to the upper surface of the substrate or not.

[0104] Some embodiments include a structure having an opening extending into an integrated configuration. Material is located within the opening and configured to create a wavy configuration relative to the sidewalls of the opening. The wavy configuration has a shape determined by an average roughness parameter R. mean Characterized surface roughness, the R mean It is the average peak-to-valley distance along the wavy configuration. The R... mean It is at least about 4nm.

[0105] Some embodiments include a structure having an opening extending into an integrated configuration. A first material is located within the opening and configured to create a wavy configuration relative to the sidewalls of the opening. The wavy configuration has a shape determined by an average roughness parameter R. mean Characterized surface roughness, the R mean It is the average peak-to-valley distance along the wavy configuration. The R... mean It is at least about 4 nm. The second material is located within the opening and along at least a portion of the wavy configuration. The first material and the second material are different from each other in composition.

[0106] Some embodiments include an integrated assembly having a vertically stacked arrangement of alternating insulating and conductive layers. A gap extends through the stack. A granular first material is located within the gap and has an average maximum particle size (Dmax) of at least about 4 nm along the cross-section.mean The granular first material partially fills the opening, leaving unfilled areas between the particles of the granular first material. A second material is located within at least a portion of these unfilled areas. The first material and the second material are compositionally different from each other.

[0107] Some embodiments include a method of forming an integrated assembly. A vertical stack of alternating insulating and conductive layers is formed. A channel material pillar extending through the stack is formed. A slot extending through the stack is formed. A panel is formed within the slot. The formation of the panel includes forming a first material within the slot to partially fill the slot and forming a second material within the partially filled slot. The surface of the first material is characterized by an average roughness parameter R. mean Characterized wavy external configuration, the R mean It is the average peak-valley distance along the wavy outer configuration. The R... mean It is at least about 4nm.

[0108] In accordance with regulations, this disclosure has been described in language that is more or less specific to structural and methodological features. However, it should be understood that the claims are not limited to the specific features shown and described, as the components disclosed herein include exemplary embodiments. Therefore, the claims are given the full scope as literal and should be properly interpreted in accordance with the doctrine of equivalence.

Claims

1. A structure comprising: An opening that extends into the integrated configuration, the opening having sidewalls; Material, which is located within the opening; The material comprises structures of different sizes, which are configured to produce a wavy configuration relative to the sidewalls; the wavy configuration has a mean roughness parameter R. mean Characterized surface roughness, the R mean It is the average peak-to-valley distance along the wavy configuration; the R mean It is at least 4nm, and the different-sized structures include a first dimension along the sidewall and a second dimension perpendicular to the first dimension, wherein the first dimension is the larger dimension among the different-sized structures, and the different-sized structures include amorphous structures; A liner located in the opening between the sidewall and the material; The material is a first material, and the structure further includes a second material located within the opening and along at least a portion of the wavy configuration; the second material is compositionally different from the first material, and The first material comprises a combination of one or more metals and one or more of boron, carbon, silicon, germanium, nitrogen and oxygen.

2. The structure of claim 1, wherein the first material comprises at least one discrete particle that is at least partially surrounded by the second material.

3. The structure according to claim 1, wherein the first material is an insulating material.

4. The structure according to claim 1, wherein the first material is a conductive material.

5. The structure according to claim 1, wherein the first material is a semiconductive material.

6. The structure according to claim 1, wherein the first material comprises one or more metals.

7. The structure according to claim 1, wherein the first material comprises one or more of Cu, Al, Ag, Au, W, Ti and Fe.

8. The structure according to claim 7, wherein the second material comprises one or more of titanium nitride, silicon nitride, aluminum oxide, tungsten, silicon dioxide, and semiconductor materials.

9. The structure according to claim 1, wherein the second material comprises one or more of Ti, W and Si.

10. The structure of claim 9, wherein the second material further comprises one or both of O and N.

11. The structure according to claim 1, wherein the first material comprises one or both of Si and Ge.

12. The structure of claim 11, wherein the first material further comprises one or more additional components selected from the group consisting of B, P and As; wherein the total concentration of the additional components in the first material is in the range of 0.5 at% to 5 at%.

13. The structure according to claim 1, wherein the surface roughness is further determined by the maximum roughness parameter R. max Characterization, the R max It is the maximum peak-to-valley distance along the wavy configuration; and wherein R max It is at least 10nm.

14. The structure according to claim 1, wherein the R mean It is at least 10nm.

15. The structure according to claim 1, wherein the R mean It is at least 10nm.

16. The structure according to claim 1, wherein the R mean It is at least 50nm.

17. The structure of claim 1, wherein the integrated configuration comprises a vertical stack of alternating insulating and conductive layers, and wherein the opening extends through the stack.

18. The structure of claim 17, wherein the liner is insulating, and wherein the first material and the second material are located within the liner-filled opening.

19. A memory device comprising: Vertical stacking of alternating insulating and conductive layers; A gap that extends through the stack; A granular first material, located within the gap and having an average maximum particle size (Dmax) along the cross-section of at least 4 nm. mean The granular first material partially fills the opening to leave unfilled areas between the particles of the granular first material. Each particle of the granular first material includes a peripheral surface in the gap, the peripheral surface being non-curved and having corners, each particle being spaced apart from other particles and no particle contacting another particle; A second material is located within at least a portion of the unfilled area; the second material differs in composition from the first material. Channel material columns that extend through the stack; and Memory cell, which is located along the channel material column.

20. The memory device of claim 19, wherein the gap separates the first block area from the second block area.

21. The memory device of claim 19, wherein the granular first material directly abuts one or more of the conductive layers.

22. The memory device of claim 19, comprising one or more voids at least partially surrounded by the first material.

23. The memory device of claim 19, wherein the gap is lined by an insulating liner, and wherein the first material and the second material are located within the liner-lined gap.

24. The memory device of claim 19, wherein Dmax mean It is at least 10nm.

25. The memory device of claim 19, wherein the slit has a width along the cross-section, and wherein Dmax mean It is at least 2% of the stated width.

26. The memory device of claim 19, wherein the slit has a width along the cross-section, and wherein Dmax mean It is at least 5% of the stated width.

27. The memory device of claim 19, wherein the slit has a width along the cross-section, and wherein Dmax mean It is at least 10% of the stated width.

28. The memory device of claim 19, wherein the first material comprises one or more of Cu, Al, Ag, Au, W, Ti and Fe.

29. The memory device of claim 19, wherein the first material comprises one or both of Si and Ge and further comprises one or more additional components selected from the group consisting of B, P and As; wherein the total concentration of the additional components in the first material is in the range of 0.5 at% to 5 at%.

30. A method of forming an integrated assembly, comprising: This forms a vertical stack of alternating insulating and conductive layers; Forming columns of channel material extending through the stack; Forming a gap extending through the stack, the gap including opposing sidewalls extending from the bottom wall; and A panel is formed within the gap; the formation of the panel includes forming a granular first material within the gap to partially fill the gap and forming a second material within the partially filled gap; the granular first material comprises structures of different sizes, each structure of a different size being structurally different from any other structure of a different size, and having a surface composed of a wavy outer configuration; the wavy outer configuration is determined by an average roughness parameter R. mean Characterization, the R mean It is the average peak-to-valley distance along the wavy outer configuration; the R mean It is at least 4nm; At least one of the different sized structures is formed in the gap, without contacting the opposing sidewalls of the gap or the bottom wall of the gap; And, wherein the first material is sputtered deposited metal.

31. The method of claim 30, wherein the sputtered deposited metal comprises one or more of Cu, Al, Ag, Au and Fe.

32. The method of claim 30, wherein the first material comprises at least one discrete particle that is at least partially surrounded by the second material.

33. The method of claim 30, wherein the first material comprises one or both of Si and Ge.

34. The method of claim 33, wherein the first material further comprises one or more additional components selected from the group consisting of B, P and As; wherein the total concentration of the additional components in the first material is in the range of 0.5 at% to 5 at%.

35. The method of claim 30, wherein one or more voids remain within the voids after the second material is formed within the partially filled voids.

36. The method of claim 30, further comprising: The gap is lined with an insulating liner; and The first material and the second material are formed within the lining gap.

37. The method of claim 36, wherein the insulating liner comprises one or both of silicon dioxide and silicon nitride.

38. The method of claim 36, further comprising filling the gap with a second material, wherein the second material and the granular first material are the only two materials that completely fill the gap.

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