Test pad structure of a chip

Abstract

This invention provides a test pad structure for a chip, comprising a plurality of first inner test pads, a plurality of second inner test pads, a plurality of first extended test pads, and a plurality of second extended test pads. The plurality of first inner test pads and the plurality of second inner test pads are disposed on a chip, with a distance between them. The plurality of first extended test pads are connected to the plurality of first inner test pads, and the plurality of second extended test pads are connected to the plurality of second inner test pads. The plurality of first extended test pads and the plurality of second extended test pads increase the contact area with probes. Probes transmit signals or power to the plurality of first inner test pads and the plurality of second inner test pads through the plurality of first extended test pads and the plurality of second extended test pads to test the chip.

Description

Technical Field

[0001] This invention relates to a test pad structure for a chip, and more particularly to a structure that ensures probe contact with the test pad. Background Technology

[0002] With the development of technology, chip design companies design related circuits and circuit layouts according to customer needs and product functions, and provide them to wafer fabs for chip production. Before the chips are cut from the wafer, chip probing (CP) is performed to ensure the quality of each chip in order to determine whether the circuits on the chip on the wafer can function properly and perform the expected functions.

[0003] Continuing from the above, the testing device for the wafer has a probe card with multiple probes. These probes contact the test pads of the chip to transmit signals or power to the chip in order to test whether the chip can function properly.

[0004] Please see Figure 1 This is a cross-sectional schematic diagram of a conventional test pad structure. As shown, a wafer 70 includes multiple chips 80, each chip 80 including multiple test pads 82 and multiple openings 84. The multiple test pads 82 are located within the chip 80, and the multiple openings 84 correspond to the multiple test pads 82 and communicate with the surface of the multiple test pads 82 and the chip 80. Two probes 42 of a detection device 40 enter the multiple openings 84 and contact the multiple test pads 82 to transmit signals or power to the chip 80, thereby testing the chip 80. However, due to process errors, such as etching errors and photomask alignment errors, the cross-sectional area of ​​the opening 84 may be close to the cross-sectional area of ​​the probe 42. In this case, the probe 42 may not easily enter the opening 84 and may not easily contact the test pads 82, or may not make proper contact with the test pads 82, thus reducing the test quality. Furthermore, the cross-sectional area of ​​the opening 84 may even be smaller than the cross-sectional area of ​​the probe 42. In this case, the probe 42 may not be able to enter the opening 84 and may not be able to contact the test pads 82, thus preventing the testing of the chip 80. Furthermore, if the location of the opening 84 is slightly off, the distance between the two adjacent openings 84 will deviate by a predetermined distance. As a result, the two probes 42 cannot be simultaneously aligned with the two adjacent openings 84 and cannot enter the opening 84, thus making it impossible to test the chip 80.

[0005] As described above, conventional test pad structures can affect the testing quality of detection devices, and may even prevent the devices from testing chips. Therefore, the industry needs a test pad structure that ensures probes can reliably contact the chip to improve testing quality. Summary of the Invention

[0006] One objective of this invention is to provide a chip test pad structure comprising multiple inner test pads and multiple extended test pads, wherein the multiple extended test pads are connected to the multiple inner test pads to increase the area that can be contacted by probes. In this way, the probes can reliably contact the extended test pads and transmit signals or power to the inner test pads through the extended test pads to test the chip, thereby improving the test quality.

[0007] One objective of this invention is to provide a test pad structure for a chip, which increases the area that can be contacted by a probe. Even when the cross-sectional area of ​​the probe increases due to wear, the probe can still contact the test pad structure without needing to be replaced. This increases the lifespan of the probe and reduces testing costs.

[0008] One objective of this invention is to provide a test pad structure for a chip, which increases the area that can be contacted by a probe, thereby having a larger alignment range, facilitating probe alignment, and improving the situation where probe alignment is difficult.

[0009] This invention provides a test pad structure for a chip, comprising a plurality of first inner test pads, a plurality of second inner test pads, a plurality of first extended test pads, and a plurality of second extended test pads. The plurality of first inner test pads and the plurality of second inner test pads are disposed on a chip, and a distance is maintained between the plurality of second inner test pads and the plurality of first inner test pads. The plurality of first extended test pads and the plurality of second extended test pads are disposed on the chip, with the first extended test pads connected to the plurality of first inner test pads and located above the plurality of first inner test pads, and the plurality of second extended test pads connected to the plurality of second inner test pads and located above the plurality of second inner test pads. The plurality of first extended test pads and the plurality of second extended test pads increase the contact area of ​​the probes, allowing the probes to reliably contact the plurality of first extended test pads and the plurality of second extended test pads, and transmitting signals or power to the plurality of first inner test pads and the plurality of second inner test pads through the plurality of first extended test pads and the plurality of second extended test pads to test the chip. Attached Figure Description

[0010] Figure 1 It is a cross-sectional schematic diagram of a conventional test pad structure;

[0011] Figure 2 This is a top view schematic diagram of the first embodiment of the test pad structure of the chip of the present invention;

[0012] Figure 3 This is a cross-sectional schematic diagram of the first embodiment of the test pad structure of the chip of the present invention;

[0013] Figure 4A and Figure 4B It is Figure 3 A magnified view of a portion of the image;

[0014] Figure 5 This is a top view schematic diagram of a second embodiment of the test pad structure of the chip of the present invention;

[0015] Figure 6 This is a cross-sectional schematic diagram of a second embodiment of the test pad structure of the chip of the present invention;

[0016] Figure 7 It is Figure 6 A partially enlarged schematic diagram; and

[0017] Figure 8 This is a cross-sectional schematic diagram of an embodiment of the test pad structure of the chip of the present invention, in which a portion of the extended test pad has been removed.

[0018] [Figure Number Reference Guide]

[0019] 1. Wafer

[0020] 10 chips

[0021] 11 First side view

[0022] 13 Second side view

[0023] 14 First Internal Test Pad

[0024] 141 First side view

[0025] 143 Second side view

[0026] 15 First perforation

[0027] 16 Second Internal Test Pad

[0028] 161 First side view

[0029] 163 Second side view

[0030] 17 Second perforation

[0031] 20 First Extension Test Mat

[0032] 22 First ontology

[0033] 221 First side view

[0034] 223 Second side view

[0035] 24 First connector

[0036] 30 Second Extension Test Pad

[0037] 32 Second Body

[0038] 321 First side view

[0039] 323 Second side view

[0040] 34 Second connector

[0041] 40 Detection Device

[0042] 42 probes

[0043] 50 cutting channels

[0044] 70 wafers

[0045] 80 chips

[0046] 82 Test pad

[0047] 84 openings

[0048] D0 Distance

[0049] D1 aperture

[0050] D2 Length

[0051] D3 Length

[0052] D4 Distance

[0053] D5 Distance

[0054] D6 Distance

[0055] D7 Distance

[0056] D8 Distance

[0057] D9 Distance

[0058] D10 Distance

[0059] D11 Distance

[0060] D12 Distance

[0061] D13 First Test Distance

[0062] D14 Second Test Distance

[0063] D15 probe distance

[0064] W1 width

[0065] W2 width Detailed Implementation

[0066] To provide a better understanding of the structural features and effects achieved by the present invention, preferred embodiments and detailed descriptions are provided below:

[0067] Please see Figure 2 and Figure 3 , Figure 2 and Figure 3 These are top and cross-sectional views of a first embodiment of the test pad structure for the chip of the present invention. As shown, a wafer 1 includes a plurality of chips 10 and a plurality of dicing channels 50 located between the plurality of chips 10. A dicing apparatus can cut the wafer 1 along the dicing channels 50 to obtain the plurality of chips 10.

[0068] See again Figure 2 and Figure 3 And please see Figure 4A , Figure 4A for Figure 3 A partially enlarged schematic diagram. The test pad structure of the present invention includes a plurality of first inner test pads 14, a plurality of second inner test pads 16, a plurality of first extended test pads 20, and a plurality of second extended test pads 30, all disposed on a chip 10. In one embodiment, the plurality of first inner test pads 14 and the plurality of second inner test pads 16 are located within the chip 10, with the plurality of first inner test pads 14 located on a first side of the chip 10 and the plurality of second inner test pads 16 located on a second side of the chip 10. The plurality of first inner test pads 14 have a first side surface 141 and a second side surface 143, and the plurality of second inner test pads 16 have a first side surface 161 and a second side surface 163. The second side surface 143 and the second side surface 163 are opposite to each other and have a distance D0 between them, which indicates that there is a distance D0 between the plurality of first inner test pads 14 and the plurality of second inner test pads 16. The plurality of first extended test pads 20 are respectively connected to the plurality of first inner test pads 14 and are located above the plurality of first inner test pads 14. The plurality of second extended test pads 30 are respectively connected to the plurality of second inner test pads 16 and are located above the plurality of second inner test pads 16.

[0069] See again Figure 2 and Figure 4A In this embodiment, the chip 10 includes a plurality of first through holes 15 and a plurality of second through holes 17. The plurality of first through holes 15 correspond to the plurality of first inner test pads 14 and are located above the plurality of first inner test pads 14. The plurality of second through holes 17 correspond to the plurality of second inner test pads 16 and are located above them. Each of the plurality of first extended test pads 20 includes a first body 22 and a first connector 24. The first body 22 is located on the surface of the chip 10. The first connector 24 is inserted into the first through hole 15 and connects the first body 22 and the first inner test pad 14. The plurality of second extended test pads 30 are spaced apart from the plurality of first extended test pads 20. Each of the plurality of second extended test pads 30 includes a second body 32 and a second connector 34. The second body 32 is located on the surface of the chip 10. The second connector 34 is inserted into the second through hole 17 and connects the second body 32 and the second inner test pad 16.

[0070] In this embodiment, the first body 22 extends toward the second body 32, meaning the first extension test pad 20 extends toward the second extension test pad 30. The second body 32 extends toward the first body 22, meaning the second extension test pad 30 extends toward the first extension test pad 20. Figure 4A As shown, the second side 143 of the first inner test pad 14 is farther away from the first side 11 of the chip 10 compared to the first side 141 of the first inner test pad 14. The first body 22 of the first extended test pad 20 has a first side 221 and a second side 223, the second side 223 being farther away from the first side 11 of the chip 10 compared to the first side 221. There is a distance D4 between the second side 143 of the first inner test pad 14 and the first side 11 of the chip 10, and there is a distance D5 between the second side 223 of the first extended test pad 20 and the first side 11 of the chip 10, and distance D5 is greater than distance D4. The second side 163 of the second inner test pad 16 is farther away from the second side 13 of the chip 10 compared to the first side 161 of the second inner test pad 16. The second body 32 of the second extended test pad 30 has a first side 321 and a second side 323, the second side 323 being farther away from the second side 13 of the chip 10 compared to the first side 321, and the second side 323 is relative to the second side 223. The second side 163 of the second inner test pad 16 has a distance D6 between it and the second side 13 of the chip 10, and the second side 323 of the second extended test pad 30 has a distance D7 between it and the second side 13 of the chip 10, and the distance D7 is greater than the distance D6.

[0071] See again Figure 4A A distance D8 exists between the first side 141 of the first inner test pad 14 and the first side 11 of the chip 10. A distance D9 exists between the first side 221 of the first extended test pad 20 and the first side 11 of the chip 10, and distance D9 is less than distance D8, indicating that the first extended test pad 20 also extends away from the second extended test pad 30. A distance D10 exists between the first side 161 of the second inner test pad 16 and the second side 13 of the chip 10. A distance D11 exists between the first side 321 of the second extended test pad 30 and the second side 13 of the chip 10, and distance D11 is less than distance D10, indicating that the second extended test pad 30 also extends away from the first extended test pad 20.

[0072] like Figure 4AAs shown, the first perforation 15 and the second perforation 17 each have a diameter D1, representing the opening size of the first perforation 15 and the second perforation 17. The first inner test pad 14 and the second inner test pad 16 each have a length D2, and the lengths of the first inner test pad 14 and the second inner test pad 16 may be different. The first body 22 and the second body 32 each have a length D3, and the length D3 is greater than the diameter D1 and the length D2, which represents the area of ​​the upper surface of the first body 22, that is, the surface area of ​​the first extended test pad 20, which is greater than the opening area of ​​the first perforation 15 and the surface area of ​​the first inner test pad 14 (e.g., ...). Figure 3 (as shown); similarly, the area of ​​the upper surface of the second body 32, that is, the area of ​​the surface of the second extended test pad 30, is greater than the opening area of ​​the second perforation 17 and the surface area of ​​the second inner test pad 16 (as shown). Figure 3 (As shown). In one embodiment, the length of the first body 22 and the length of the second body 32 may also be different. Furthermore, as... Figure 2 As shown, the first inner test pad 14 and the second inner test pad 16 each have a width W1. The width of the first inner test pad 14 and the width of the second inner test pad 16 may also be different. The first body 22 and the second body 32 each have a width W2, and the width W2 is greater than the width W1. In one embodiment, the width W2 may be equal to the width W1, and the width of the first body 22 and the width of the second body 32 may also be different.

[0073] See again Figure 2 And see Figure 4B , Figure 4B Same as Figure 4A for Figure 3 A partially enlarged schematic diagram is shown. As shown, a detection device 40 is used to detect chip 10. The detection device 40 includes two probes 42, which can contact the first body 22 of the first extended test pad 20 and the second body 32 of the second extended test pad 30. A distance D12 exists between the first through hole 15 and the second through hole 17. A first test distance D13 exists between the first side surface 221 of the first extended test pad 20 and the first side surface 321 of the second extended test pad 30. A second test distance D14 exists between the second side surface 223 of the first extended test pad 20 and the second side surface 323 of the second extended test pad 30. The first test distance D13 is greater than the second test distance D14. A probe distance D15 exists between the two probes 42. In this embodiment, distances D12 and the second test distance D14 are less than probe distance D15, and the first test distance D13 is greater than probe distance D15. The two probes 42 can contact the surfaces of the first extended test pad 20 and the second extended test pad 30, and transmit signals or power to the first inner test pad 14 and the second inner test pad 16 through the first extended test pad 20 and the second extended test pad 30 to detect the chip 10.

[0074] As explained above, probe 42 does not need to enter the vias 15 and 17; it only needs to contact the first extended test pad 20 and the second extended test pad 30 to test the chip 10, which is equivalent to increasing the area that probe 42 can contact. Furthermore, the areas of the first extended test pad 20 and the second extended test pad 30 can be larger than the areas of the first inner test pad 14 and the second inner test pad 16, further increasing the area that probe 42 can contact. In addition, the large contact area of ​​the first extended test pad 20 and the second extended test pad 30 with probe 42 provides a larger alignment range, facilitating probe 42 alignment. Even if the probe distance D15 between the two probes 42 increases or decreases after prolonged use, alignment with the first extended test pad 20 and the second extended test pad 30 is still possible without replacing probe 42. Even if the cross-sectional area of ​​probe 42 increases due to wear, probe 42 can still reliably contact the first extended test pad 20 and the second extended test pad 30 without needing replacement, thus increasing the lifespan of probe 42 and reducing testing costs.

[0075] Please see Figure 5 , Figure 6 and Figure 7 , Figure 5 and Figure 6 These are a top view and a cross-sectional view of a second embodiment of the test pad structure of the chip of the present invention; Figure 7 for Figure 6 A partially enlarged schematic diagram. As shown in the figure, the first body 22 of the first extended test pad 20 extends away from the second extended test pad 30 and can extend the chip 10 to the cutting channel 50, further increasing the area of ​​the first body 22. Similarly, the second body 32 of the second extended test pad 30 extends away from the first extended test pad 20 and can extend the chip 10 to the cutting channel 50, increasing the area of ​​the second body 32.

[0076] Please see Figure 8This is a cross-sectional schematic diagram of an embodiment of the chip test pad structure of the present invention with a portion of the extended test pad removed. After the testing device has tested the plurality of chips 10 located on wafer 1, a portion of the first body 22 of the first extended test pad 20 and a portion of the second body 32 of the second extended test pad 30 can be removed. Thus, the plurality of chips 10 cut from wafer 1 still retain the first extended test pad 20 and the second extended test pad 30, and can be tested. In another embodiment, the first extended test pad 20 and the second extended test pad 30 can be completely removed, that is, the first body 22, the first connector 24, the second body 32, and the second connector 34 can be completely removed. In one embodiment, the materials of the first extended test pad 20 and the second extended test pad 30 may be different from the materials of the first inner test pad 14 and the second inner test pad 16, so that the first extended test pad 20 and the second extended test pad 30 can be removed using a specific etchant without removing the first inner test pad 14 and the second inner test pad 16.

[0077] In summary, the present invention provides a test pad structure for a chip, which includes an extended test pad connected to an inner test pad. Thus, when a probe contacts the extended test pad, a signal or power can be transmitted to the inner test pad through the extended test pad to test the chip.

[0078] The above description is merely a preferred embodiment of the present invention and is not intended to limit the scope of the present invention. All equivalent variations and modifications made in accordance with the shape, structure, features and spirit described in the claims of the present invention should be included within the scope of the claims of the present invention.

Claims

1. A test pad structure for a chip, characterized in that, It includes: Multiple first internal test pads are disposed on a chip; Multiple second inner test pads are disposed on the chip and are spaced apart from the multiple first inner test pads; Multiple first extended test pads are disposed on the chip and connected to the multiple first inner test pads, and are located above the multiple first inner test pads; as well as Multiple second extended test pads are disposed on the chip and connected to the multiple second inner test pads, and are located above the multiple second inner test pads; The plurality of first extended test pads have a first side and a second side, and the plurality of second extended test pads have a first side and a second side. The second side of the plurality of first extended test pads is relative to the second side of the plurality of second extended test pads. There is a first test distance between the first side of the plurality of first extended test pads and the first side of the plurality of second extended test pads. There is a second test distance between the second side of the plurality of first extended test pads and the second side of the plurality of second extended test pads. The first test distance is greater than the second test distance. A detection device includes two probes. There is a probe distance between the two probes. The first test distance is greater than the probe distance. The second test distance is less than the probe distance. The materials of the first extended test pads and the second extended test pads are different from the materials of the first inner test pads and the second inner test pads.

2. The test pad structure for the chip as described in claim 1, characterized in that, The area of ​​one of the plurality of first extended test pads is larger than the area of ​​one of the plurality of first inner test pads.

3. The test pad structure for the chip as described in claim 1, characterized in that, The area of ​​one of the plurality of second extended test pads is larger than the area of ​​one of the plurality of second inner test pads.

4. The test pad structure for the chip as described in claim 1, characterized in that, The length of one of the plurality of first extended test pads is greater than the length of one of the plurality of first inner test pads.

5. The test pad structure for the chip as described in claim 1, characterized in that, The length of one of the plurality of second extended test pads is greater than the length of one of the plurality of second inner test pads.

6. The test pad structure for the chip as described in claim 1, characterized in that, The width of one of the plurality of first extended test pads is equal to or greater than the width of one of the plurality of first inner test pads.

7. The test pad structure for the chip as described in claim 1, characterized in that, The width of one of the plurality of second extended test pads is equal to or greater than the width of one of the plurality of second inner test pads.

8. The test pad structure for the chip as described in claim 1, characterized in that, The plurality of first extension test pads extend toward the plurality of second extension test pads.

9. The test pad structure for the chip as described in claim 1, characterized in that, The plurality of second extended test pads extend toward the plurality of first extended test pads.

10. The test pad structure for the chip as described in claim 1, characterized in that, The plurality of first extended test pads extend in a direction away from the plurality of second extended test pads.

11. The test pad structure for the chip as described in claim 1, characterized in that, The plurality of second extended test pads extend in a direction away from the plurality of first extended test pads.

12. The test pad structure for the chip as described in claim 1, characterized in that, The distance between one side of the plurality of first extended test pads and one side of the chip is less than the distance between one side of the plurality of first inner test pads and that side of the chip.

13. The test pad structure for the chip as described in claim 1, characterized in that, The distance between one side of the plurality of second extended test pads and one side of the chip is less than the distance between one side of the plurality of second inner test pads and that side of the chip.

14. The test pad structure for the chip as described in claim 1, characterized in that, The plurality of first extended test pads and / or the plurality of second extended test pads extend out of the chip, and the plurality of first inner test pads and the plurality of second inner test pads are located inside the chip.

15. The test pad structure for the chip as described in claim 1, characterized in that, Each of the plurality of first extension test pads comprises: A first entity; and A first connector that connects the first body to the first inner test pad.

16. The test pad structure for the chip as described in claim 1, characterized in that, Each of the plurality of second extension test pads contains: A second entity; and A second connector that connects the second body to the second inner test pad.

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