A verification board, a test system and a test method

Abstract

The present invention provides a verification board, a test system and a test method. The verification board includes a circuit board. An interface, a system control unit, a PWM generator, a power device and a sampling circuit are arranged on the circuit board. The first interface is connected to the VID power management interface to be tested. The system control unit receives a test instruction and generates voltage regulation data. The PWM generator receives the voltage regulation data and generates a driving waveform. The power device receives the driving waveform and generates an output voltage. The sampling circuit collects the voltage data output by the power device; the system control unit transmits the voltage data through the interface. The behavior code of the VID power management communication protocol controller is placed in the system control unit environment, and programming is used to adapt to the behaviors of different VID power management communication protocol controllers, so as to achieve the purpose of verifying the performance of multiple VID power management interfaces. To verify the performance of the VID power management interface and ensure that a high-performance chip can operate normally under high-frequency and high-performance conditions.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular, to a verification board, a test system, and a test method. Background Art

[0002] With the development of science and technology, the market has higher and higher requirements for the performance of processors. In order to improve the performance of processors, more transistors need to be integrated into the processors, so that the number scale of transistors integrated in the processors is getting larger and larger. With the increase in the number of transistors in the processors, the clock frequency in the processors is also getting higher and higher, resulting in an increasing power consumption of the processors. The dynamic voltage switching rate directly affects the clock frequency, so the requirement for the dynamic voltage switching rate is getting faster and faster. The performance of the VID (Voltage Identification Signal, a voltage identification and regulation technology) power management interface directly reflects the dynamic voltage switching rate. Therefore, the performance requirements for the VID power management interface supplying power to the processor are also getting higher and higher. Currently, the main method for testing the power management interface is still the way of welding connection using pads and leads. Each test system is only for one type of voltage management interface, which not only causes a larger volume, but also cannot meet the requirements for testing the VID power management interface with a faster dynamic voltage switching rate. Summary of the Invention

[0003] The present invention provides a verification board, a test system, and a test method to fully and effectively verify the performance of the VID power management interface, ensuring that high-performance chips such as processors can operate normally under high-frequency and high-performance conditions.

[0004] In a first aspect, the present invention provides a verification board for testing a VID power management interface. The verification board includes a circuit board. An interface is provided on the circuit board, and the interface at least includes a first interface for connecting to the VID power management interface to be tested. A system control unit, a PWM generator, a power device composed of MOS transistors, and a sampling circuit are also provided on the circuit board. The system control unit is connected to the interface to receive a test instruction transmitted externally and generate voltage adjustment data according to the test instruction. The PWM generator is connected to the system control unit to receive the voltage adjustment data and generate a driving waveform according to the voltage adjustment data. The power device is connected to the PWM generator to receive the driving waveform and generate an output voltage according to the driving waveform. The sampling circuit is connected to the power device to collect voltage data output by the power device; and the sampling circuit is also connected to the system control unit to transmit the voltage data to the system control unit, and the system control unit transmits the voltage data out through the interface.

[0005] In the above solution, a verification board is formed by integrating a system control unit, a PWM generator, a power device composed of MOS transistors, a sampling circuit, and an interface on a circuit board. The VID power management interface to be tested is connected to the first interface, and test instructions are input into the system control unit. The verification board responds to the test instructions, thereby generating an output voltage. The sampling circuit captures the voltage data and transmits the voltage data. The external part compares the test instructions and the voltage data to confirm whether each VID power management interface to be tested can pass the verification. That is, the behavioral code of the VID power management communication protocol controller is placed in the system control unit environment, and different VID power management communication protocol controllers' behaviors are adapted through programming to achieve the purpose of verifying the performance of multiple VID power management interfaces. To fully and effectively verify the performance of the VID power management interface and ensure that high-performance chips such as processors can operate normally under high-frequency and high-performance conditions. And by integrating the system control unit, a PWM (Pulse Width Modulation) generator, a power device composed of MOS transistors (abbreviation of MOSFET, metal-oxide-semiconductor field-effect transistor), and a sampling circuit on a circuit board, it can be flexibly configured according to requirements to verify different types of VID power management interfaces, thereby enabling a verification board to verify multiple different types of VID power management interfaces, reducing the volume of the test tool, shortening the response feedback time to test instructions, and meeting the requirements for testing VID power management interfaces with a relatively fast dynamic voltage switching rate.

[0006] In a specific embodiment, the test instructions are transmitted from the first interface to the system control unit, and the system control unit transmits the voltage data through the first interface. By generating test instructions and receiving voltage data in the chip under test integrated with the VID power management interface to be tested, self-testing of the chip under test for each VID power management interface is realized.

[0007] In a specific embodiment, the interface further includes at least a second interface connected to the system control unit. The second interface is used to connect to a host computer to receive test instructions transmitted by the host computer; the system control unit transmits the voltage data through the second interface. By adding the second interface to connect to the host computer, testers can write and modify test instructions through the host computer and receive voltage data, enabling the host computer to verify the VID power management interface to be tested according to the test instructions and voltage data by itself, and also enabling testers to manually monitor and verify. At the same time, when both the host computer and the chip under test are performing verification tests, comparative verification can be carried out to ensure the consistency of the test results.

[0008] In a specific embodiment, the second interface is an I2C (Inter-Integrated Circuit, a simple, two-way, two-wire synchronous serial bus) interface, and the host computer is connected to the I2C interface through the I2C bus. This facilitates the connection between the verification board and any type of host computer.

[0009] In a specific embodiment, the interface further includes at least a third interface connected to the system control unit. The third interface is used to connect to a digital oscilloscope, and the system control unit also transmits voltage data to the digital oscilloscope through the third interface. By setting the third interface to connect to the digital oscilloscope, an observation terminal is provided for the signals of the VID power management interface protocol, and a display interface can be provided for the waveforms of the VID power management interface protocol signals and the output voltage data, to assist in determining the correctness of the test results.

[0010] In a specific embodiment, the system control unit includes a field programmable gate array, and the field programmable gate array contains registers for temporarily storing test instructions and voltage data. This facilitates the system control unit to receive test instructions and voltage data, and at the same time improves the data transmission efficiency between the verification board and the chip under test or the host computer.

[0011] In a specific embodiment, the sampling circuit is also used to collect current data flowing through the power device and / or temperature data of the power device. To obtain current data and temperature data as verification auxiliary parameters and improve the comprehensiveness of the verification.

[0012] In a specific embodiment, the first interface is a power management bus interface, enabling the first interface on the verification board to have more types of VID power management interface functions, to support the verification of more types of VID power management interfaces.

[0013] Second aspect, the present invention further provides a test system for testing the VID power management interface. The test system includes a chip under test and a verification board. Among them, the chip under test is provided with a VID power management communication protocol controller and a VID power management interface to be tested connected to the VID power management communication protocol controller. The verification board includes a circuit board. An interface is provided on the circuit board, and the interface at least includes a first interface connected to the VID power management interface to be tested. A system control unit, a PWM generator, a power device composed of MOS transistors, and a sampling circuit are also provided on the circuit board. The system control unit is connected to the interface to receive test instructions transmitted externally and generate voltage adjustment data according to the test instructions. The PWM generator is connected to the system control unit to receive the voltage adjustment data and generate a drive waveform according to the voltage adjustment data. The power device is connected to the PWM generator to receive the drive waveform and generate an output voltage according to the drive waveform. The sampling circuit is connected to the power device to collect voltage data output by the power device; and the sampling circuit is also connected to the system control unit to transmit the voltage data to the system control unit, and the system control unit transmits the voltage data out through the interface.

[0014] In the above solution, by integrating a system control unit, a PWM generator, a power device composed of MOS transistors, a sampling circuit, and an interface on a circuit board to form a verification board, connecting the VID power management interface to be tested to the first interface, inputting the test instructions into the system control unit, and having the verification board respond to the test instructions, thereby generating an output voltage, capturing the voltage data by the sampling circuit, and transmitting the voltage data out, and comparing the test instructions and the voltage data externally to confirm whether each VID power management interface to be tested can pass the verification. That is, putting the behavior code of the VID power management communication protocol controller into the system control unit environment and adapting to the behaviors of different VID power management communication protocol controllers through programming to achieve the purpose of verifying the performance of multiple VID power management interfaces. To fully and effectively verify the performance of the VID power management interface and ensure that high-performance chips such as processors can operate normally under high-frequency and high-performance conditions. And by integrating the system control unit, the PWM generator, the power device composed of MOS transistors, and the sampling circuit on a circuit board, it can be flexibly configured according to requirements to verify different types of VID power management interfaces, so as to realize that one verification board can verify multiple different types of VID power management interfaces, which can reduce the volume of the test tool, shorten the response feedback time to the test instructions, and meet the requirements for testing VID power management interfaces with a relatively fast dynamic voltage switching rate.

[0015] In a specific embodiment, a verification module is further provided in the chip under test and is connected to the VID power management interface under test. The verification module generates test instructions and transmits the test instructions to the system control unit from the first interface; the system control unit transmits voltage data to the verification module through the first interface. The verification module is further configured to confirm whether the VID power management interface under test can pass the verification according to the test instructions and the voltage data. By generating test instructions and receiving voltage data in the chip under test integrated with the VID power management interface under test, self-testing of the chip under test for each VID power management interface is realized.

[0016] In a specific embodiment, the test system further includes a host computer for generating the test instructions; the interface further includes at least a second interface connected to the system control unit; the second interface is connected to the host computer to receive the test instructions generated by the host computer; the system control unit transmits voltage data to the host computer through the second interface. The host computer is further configured to confirm whether the VID power management interface under test can pass the verification according to the test instructions and the voltage data. By adding the second interface and the host computer, testers can write and modify test instructions through the host computer and receive voltage data, enabling the host computer to verify the VID power management interface under test according to the test instructions and the voltage data by itself, and also enabling testers to manually monitor and verify. At the same time, when verification tests are performed on both the host computer and the chip under test, comparative verification can be carried out to ensure the consistency of test results.

[0017] In a specific embodiment, the test system further includes a digital oscilloscope. The interface further includes at least a third interface connected to the system control unit, and the third interface is connected to the digital oscilloscope. The system control unit also transmits voltage data to the digital oscilloscope through the third interface. By providing the third interface and the digital oscilloscope, an observation terminal is provided for the signals of the VID power management interface protocol, and a display interface is provided for the waveforms of the VID power management interface protocol signals and the output voltage data to assist in determining the correctness of the test results.

[0018] In a specific embodiment, the chip under test is a processor chip to fully and effectively verify the performance of the VID power management interface on the processor and ensure that the processor can operate normally under high-frequency and high-performance conditions.

[0019] Thirdly, the present invention also provides a test method based on any of the above test systems, and this test method is used to test the VID power management interface. This test method includes: generating a test instruction and transmitting the test instruction from the interface to the system control unit; the system control unit generating voltage regulation data according to the test instruction and transmitting the voltage regulation data to the PWM generator; the PWM generator generating a driving waveform according to the voltage regulation data and transmitting the driving waveform to the power device; the power device generating an output voltage according to the driving waveform; the sampling circuit collecting the voltage data output by the power device and transmitting the voltage data to the system control unit, and the system control unit transmitting the voltage data out through the interface.

[0020] In the above solution, by integrating the system control unit, the PWM generator, the power device composed of MOS transistors, the sampling circuit and the interface on a circuit board to form a verification board, connecting the VID power management interface to be tested with the first interface, inputting the test instruction into the system control unit, the verification board responds to the test instruction to generate an output voltage, the sampling circuit captures the voltage data and transmits the voltage data out, and the external performs a comparison according to the test instruction and the voltage data to confirm whether each VID power management interface to be tested can pass the verification. That is, putting the behavior code of the VID power management communication protocol controller into the system control unit environment and adapting to the behaviors of different VID power management communication protocol controllers through programming to achieve the purpose of verifying the performance of multiple VID power management interfaces. To fully and effectively verify the performance of the VID power management interface and ensure that high-performance chips such as processors can operate normally under high-frequency and high-performance conditions. And by integrating the system control unit, the PWM generator, the power device composed of MOS transistors, and the sampling circuit on a circuit board, it can be flexibly configured according to requirements to verify different types of VID power management interfaces, so as to realize that one verification board can verify multiple different types of VID power management interfaces, which can reduce the volume of the test tool, shorten the response feedback time to the test instruction, and meet the requirements for testing VID power management interfaces with a relatively fast dynamic voltage switching rate.

[0021] In a specific embodiment, a verification module connected to the to-be-tested VID power management interface is further provided in the to-be-tested chip. Generating a test instruction and transmitting the test instruction from the interface to the system control unit includes: the verification module generates a test instruction and transmits the test instruction from the first interface to the system control unit. The system control unit transmitting the voltage data out through the interface includes: the system control unit transmits the voltage data to the verification module through the first interface. The test method further includes: the verification module determines whether the to-be-tested VID power management interface can pass the verification according to the test instruction and the voltage data. By generating a test instruction and receiving voltage data in the to-be-tested chip integrated with the to-be-tested VID power management interface, self-testing of the to-be-tested chip for each VID power management interface is realized.

[0022] In a specific embodiment, the test system further includes a host computer for generating test instructions; the interface further includes at least a second interface connected to the system control unit, and the second interface is connected to the host computer. Generating a test instruction and transmitting the test instruction from the interface to the system control unit includes: the host computer generates a test instruction and transmits the test instruction to the system control unit through the second interface. The system control unit transmitting the voltage data out through the interface includes: the system control unit transmits the voltage data to the host computer through the second interface. The test method further includes: the host computer determines whether the to-be-tested VID power management interface can pass the verification according to the test instruction and the voltage data. By adding the second interface and the host computer, testers can write and modify test instructions through the host computer and receive voltage data, which can not only enable the host computer to verify the to-be-tested VID power management interface according to the test instruction and the voltage data by itself, but also enable testers to monitor and verify manually. At the same time, when both the host computer and the to-be-tested chip perform verification tests, comparative verification can be carried out to ensure the consistency of test results.

[0023] In a specific embodiment, the test system further includes a digital oscilloscope; the interface further includes at least a third interface connected to the system control unit, and the third interface is connected to the digital oscilloscope. The system control unit transmitting the voltage data out through the interface further includes: the system control unit also transmits the voltage data to the digital oscilloscope through the third interface. By providing the third interface and the digital oscilloscope, an observation terminal is provided for the signals of the VID power management interface protocol, and a display interface is provided for the waveforms of the VID power management interface protocol signals and the output voltage data to assist in determining the correctness of the test results. Description of the Drawings

[0024] Figure 1 It is a structural block diagram of a verification board and a test system provided by an embodiment of the present invention;

[0025] Figure 2Another structural block diagram of the verification board and the test system provided by the embodiments of the present invention;

[0026] Figure 3 Another overall structural block diagram of the verification board and the test system provided by the embodiments of the present invention;

[0027] Figure 4 For Figure 3 The specific structural block diagram of the verification board and the test system shown;

[0028] Figure 5 The flowchart of a test method provided by the embodiments of the present invention.

[0029] Reference numerals:

[0030] 10 - Verification board, 11 - Chip under test, 12 - Host computer

[0031] 13 - Digital oscilloscope, 20 - Circuit board, 21 - First interface

[0032] 22 - Second interface, 23 - Third interface, 30 - System control unit

[0033] 31 - Register, 40 - PWM generator

[0034] 50 - Power device, 60 - Sampling circuit Detailed implementation manners

[0035] To make the objectives, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part rather than all of the embodiments of the present invention. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts shall fall within the protection scope of the present invention.

[0036] To facilitate the understanding of the verification board provided by the embodiments of the present invention, the application scenario of the verification board provided by the embodiments of the present invention will be first described below. This verification board is applied in the process of testing the VID power management interface. The verification board will be described in detail below with reference to the accompanying drawings.

[0037] Refer to Figure 1, the verification board provided by the embodiment of the present invention includes a circuit board 20. An interface is provided on the circuit board 20, and the interface at least includes a first interface 21 for connecting to the VID power management interface to be tested. A system control unit 30, a PWM generator 40, a power device 50 composed of MOS transistors, and a sampling circuit 60 are also provided on the circuit board 20. Among them, the system control unit 30 is connected to the interface to receive test instructions transmitted externally and generate voltage adjustment data according to the test instructions. The PWM generator 40 is connected to the system control unit 30 to receive the voltage adjustment data and generate a drive waveform according to the voltage adjustment data. The power device 50 is connected to the PWM generator 40 to receive the drive waveform and generate an output voltage according to the drive waveform. The sampling circuit 60 is connected to the power device 50 to collect the voltage data output by the power device 50; and the sampling circuit 60 is also connected to the system control unit 30 to transmit the voltage data to the system control unit 30, and the system control unit 30 transmits the voltage data out through the interface.

[0038] In the above solution, by integrating the system control unit 30, the PWM generator 40, the power device 50 composed of MOS transistors, the sampling circuit 60 and the interface on a circuit board 20 to form a verification board, connecting the VID power management interface to be tested to the first interface 21, inputting the test instructions into the system control unit 30, and the verification board responding to the test instructions to generate an output voltage, the sampling circuit 60 captures the voltage data and transmits the voltage data out, and the external compares according to the test instructions and the voltage data to confirm whether each VID power management interface to be tested can pass the verification. That is, putting the behavior code of the VID power management communication protocol controller into the environment of the system control unit 30 and adapting to the behaviors of different VID power management communication protocol controllers through programming to achieve the purpose of verifying the performance of multiple VID power management interfaces. To fully and effectively verify the performance of the VID power management interface and ensure that high-performance chips such as processors can work properly under high-frequency and high-performance conditions. And by integrating the system control unit 30, the PWM generator 40, the power device 50 composed of MOS transistors, and the sampling circuit 60 on a circuit board 20, it can be flexibly configured according to requirements to verify different types of VID power management interfaces, so as to realize that a verification board verifies multiple different types of VID power management interfaces, which can reduce the volume of the test tool, shorten the response feedback time to the test instructions, and meet the requirements for testing VID power management interfaces with a relatively fast dynamic voltage switching rate. The following will introduce the above various structures in detail with reference to the drawings.

[0039] When setting the circuit board 20, the circuit board 20, as a carrier for other devices, can adopt a printed circuit board 20 including a wiring layer, wirings and pins. Refer to Figure 1, an interface is provided on the circuit. The verification board is externally connected through the interface for information interaction. The interface can adopt a plug-in connector formed by a male socket and a female socket, etc., to facilitate plug-in connection with the outside. When setting the interface, the interface includes a first interface 21, and the first interface 21 is connected to the VID power management interface on the chip under test 11 to achieve electrical connection with the VID power management interface under test. The VID power management interface under test can be, for example, but not limited to, the power management interface of a processor chip, etc. Of course, the chip under test 11 can also be a dedicated power supply chip, and the VID power management interface under test is the power management interface on the power supply chip. When setting the first interface 21, the power management bus interface can be used as the first interface 21, so that the first interface 21 on the verification board has functions of multiple types of VID power management interfaces to support the verification of multiple types of VID power management interfaces such as SVI2 / SVI3 (a type of power line), VR12 / VR13 / VR14 (a type of power line), PMBUS (a type of power line), etc.

[0040] As Figure 1 shown, a system control unit 30 is also provided on the circuit board 20. Among them, the system control unit 30 is connected to the interface to receive the test instructions transmitted from the outside and generate voltage adjustment data according to the test instructions. That is, the system control unit 30 can receive the test instructions transmitted from the outside through the interface on the circuit board 20, and specifically can receive the test instructions through the first interface 21 shown above. At this time, the test instructions can be generated by the chip under test 11; or can be generated by the host computer connected to the chip under test 11 and transmitted to the system control unit 30 through the chip under test 11.

[0041] Of course, referring to Figure 2 , a second interface 22 connected to the system control unit 30 can also be provided on the circuit board 20, and the second interface 22 is connected to other devices outside the chip under test 11. For example, the second interface 22 can be connected to the host computer 12, the test instructions are generated by the host computer 12, and the test instructions are transmitted to the system control unit 30 through the second interface 22. That is, the system control unit 30 receives the test instructions transmitted from the outside through the second interface 22 at this time. When setting the second interface 22, the second interface 22 can be an I2C interface, so that the host computer 12 is connected to the I2C interface through the I2C bus. To utilize the strong versatility of the I2C interface to facilitate the connection between the verification board and any type of host computer 12. Of course, the second interface 22 can also adopt other types of interfaces other than the I2C interface to achieve connection with the host computer 12.

[0042] Moreover, the system control unit 30 can also generate voltage regulation data according to the test instruction, that is, the test instruction can cause the program function variables of the system control unit 30 to change, so as to ultimately cause changes in the output voltage, current and other behaviors of the verification board of the VID power management interface. When setting the system control unit 30, the system control unit 30 can include a field programmable gate array, and the field programmable gate array contains a register 31 for temporarily storing test instructions and voltage data. Refer to Figure 2 , when the system control unit 30 receives a test instruction through the interface, it can first temporarily store the test instruction in the register 31, or temporarily store the generated voltage regulation data in the register 31. The PWM generator 40 reads the voltage regulation data stored in the register 31 as an input signal to generate a drive waveform, causing a change in the output voltage of the power device 50. When the system control unit 30 receives the voltage data collected by the sampling circuit 60, it can temporarily store the voltage data in the register 31, so that the host computer 12 or the chip under test 11 reads the voltage data stored in the register 31, facilitating the reception of test instructions and voltage data, and improving the data transmission efficiency between the verification board and the chip under test 11 or the host computer 12. Of course, the system control unit 30 is not limited to the above-described method of using a field programmable gate array. In addition, other methods can also be adopted.

[0043] As Figure 1 shown, a PWM generator 40 and a power device 50 composed of MOS transistors are also provided on the circuit board 20. Among them, the PWM generator 40 is connected to the system control unit 30, and the power device 50 is connected to the PWM generator 40. The PWM generator 40 can receive voltage regulation data from the system control unit 30 and generate a drive waveform according to the voltage regulation data. The power device 50 can receive the drive waveform from the PWM generator 40 and generate an output voltage according to the drive waveform. That is, the PWM generator 40 is used to generate a drive waveform with a certain frequency, duty cycle, and amplitude, and provide the drive waveform to the gate of the MOS transistor in the power device 50 to control the on and off of the MOS transistor, so as to achieve the purpose of controlling the magnitude of the output voltage.

[0044] Refer to Figure 1, a sampling circuit 60 is also integrated on the circuit board 20. The sampling circuit 60 is connected to the power device 50 to collect the voltage data output by the power device 50. The internal device type and connection method of the sampling circuit 60 can also be adjusted so that the sampling circuit 60 can also collect the current data flowing through the power device 50, or can collect the temperature data of the power device 50. Even the sampling circuit 60 can both collect the current data flowing through the power device 50 and collect the temperature data of the power device 50 to obtain the current data and temperature data as verification auxiliary parameters to improve the comprehensiveness of verification.

[0045] Reference Figure 1 , the sampling circuit 60 is also connected to the system control unit 30 to transmit the collected voltage data to the system control unit 30, and the system control unit 30 transmits test data such as voltage data through the interface. After receiving the voltage data, current data, and temperature data collected by the sampling circuit 60, the system control unit 30 can temporarily store them in the register 31 of the system control unit 30. Then, the external chip under test 11 or the host computer 12 reads the voltage data, current data, and temperature data stored in the register 31 through the interface to transmit test data such as voltage data through the interface.

[0046] For example, reference Figure 1 , when the test instruction is transmitted to the system control unit 30 through the first interface 21, the system control unit 30 can transmit test data such as voltage data through the first interface 21. When the chip under test 11 can generate a test instruction and receive voltage data for verification, the system control unit 30 can transmit test data such as voltage data to the chip under test 11 through the first interface 21. The above method generates a test instruction and receives voltage data in the chip under test 11 integrated with the VID power management interface to be tested, thereby realizing the self-test of the chip under test 11 for each VID power management interface. When the chip under test 11 is connected to a host computer, the host computer generates a test instruction and transmits the test instruction to the system control unit 30 through the chip under test 11, and the system control unit 30 can also transmit test data such as voltage data to the host computer through the first interface 21 and the chip under test 11.

[0047] Reference Figure 2, when the system control unit 30 directly receives a test instruction from the host computer 12 through the second interface 22, the system control unit 30 can directly transmit voltage data to the host computer 12 through the second interface 22. The above method of adding the second interface 22 to connect to the host computer 12 enables the tester to write and modify test instructions through the host computer 12 and receive voltage data. This not only allows the host computer 12 to verify the VID power management interface to be tested according to the test instructions and voltage data by itself, but also enables the tester to monitor and verify manually. At the same time, when both the host computer 12 and the chip 11 to be tested are performing verification tests, a comparative verification can be carried out to ensure the consistency of the test results.

[0048] Furthermore, referring to Figure 3 and Figure 4 , the interface provided on the circuit board 20 may further include at least a third interface 23 connected to the system control unit 30, and the third interface 23 is used to connect to the digital oscilloscope 13. The system control unit 30 can also transmit voltage data to the digital oscilloscope 13 through the third interface 23. When specifically implementing the connection between the verification board and the digital oscilloscope 13, referring to Figure 4 , it can be connected to the digital oscilloscope 13 through the VID protocol signal line and the voltage output signal line. By providing the third interface 23 to connect to the digital oscilloscope 13, an observation terminal is provided for the signals of the VID power management interface protocol, and a display interface is provided for the waveforms of the VID power management interface protocol signals and the output voltage data to assist in determining the correctness of the test results.

[0049] By integrating a system control unit 30, a PWM generator 40, a power device 50 composed of MOS transistors, a sampling circuit 60 and interfaces on a circuit board 20, a verification board is formed. The VID power management interface to be tested is connected to the first interface 21, and test instructions are input into the system control unit 30. The verification board responds to the test instructions, thereby generating an output voltage. The voltage data is captured by the sampling circuit 60 and transmitted. The external part compares according to the test instructions and the voltage data to confirm whether each VID power management interface to be tested can pass the verification. That is, the behavior code of the VID power management communication protocol controller is placed in the environment of the system control unit 30, and different VID power management communication protocol controllers' behaviors are adapted through programming to achieve the purpose of verifying the performance of multiple VID power management interfaces. To fully and effectively verify the performance of the VID power management interface and ensure that high-performance chips such as processors can operate normally under high-frequency and high-performance conditions. And by integrating the system control unit 30, the PWM generator 40, the power device 50 composed of MOS transistors, and the sampling circuit 60 on a circuit board 20, it can be flexibly configured according to requirements to verify different types of VID power management interfaces. Thus, a verification board can verify multiple different types of VID power management interfaces, which can reduce the volume of the test tool and shorten the response feedback time to test instructions, meeting the requirements for testing VID power management interfaces with a relatively fast dynamic voltage switching rate.

[0050] In addition, an embodiment of the present invention further provides a test system, which is used to test the VID power management interface. Refer to Figure 1 and Figure 3, the test system includes a chip under test 11 and a verification board 10. Among them, the chip under test 11 is provided with a VID power management communication protocol controller and a VID power management interface under test connected to the VID power management communication protocol controller. The verification board 10 includes a circuit board 20. An interface is provided on the circuit board 20, and the interface at least includes a first interface 21 connected to the VID power management interface under test. A system control unit 30, a PWM generator 40, a power device 50 composed of MOS transistors, and a sampling circuit 60 are also provided on the circuit board 20. The system control unit 30 is connected to the interface to receive test instructions transmitted externally and generate voltage adjustment data according to the test instructions. The PWM generator 40 is connected to the system control unit 30 to receive the voltage adjustment data and generate a drive waveform according to the voltage adjustment data. The power device 50 is connected to the PWM generator 40 to receive the drive waveform and generate an output voltage according to the drive waveform. The sampling circuit 60 is connected to the power device 50 to collect voltage data output by the power device 50; and the sampling circuit 60 is also connected to the system control unit 30 to transmit the voltage data to the system control unit 30, and the system control unit 30 transmits the voltage data through the interface.

[0051] In the above solution, by integrating the system control unit 30, the PWM generator 40, the power device 50 composed of MOS transistors, the sampling circuit 60 and the interface on a circuit board 20 to form the verification board 10, connecting the VID power management interface under test to the first interface 21, inputting the test instructions into the system control unit 30, and the verification board 10 responding to the test instructions, thereby generating an output voltage, the sampling circuit 60 capturing the voltage data and transmitting the voltage data, and the external comparing according to the test instructions and the voltage data to confirm whether each VID power management interface under test can pass the verification. That is, putting the behavior code of the VID power management communication protocol controller into the environment of the system control unit 30, and adapting to the behaviors of different VID power management communication protocol controllers through programming, so as to achieve the purpose of verifying the performance of multiple VID power management interfaces. To fully and effectively verify the performance of the VID power management interface, ensure that high-performance chips such as processors can work properly under high-frequency and high-performance conditions. And by integrating the system control unit 30, the PWM generator 40, the power device 50 composed of MOS transistors, and the sampling circuit 60 on a circuit board 20, it can be flexibly configured according to requirements to verify different types of VID power management interfaces, so as to realize that one verification board 10 verifies multiple different types of VID power management interfaces, which can reduce the volume of the test tool, shorten the response feedback time of the test instructions, and meet the requirements for testing VID power management interfaces with a relatively fast dynamic voltage switching rate. The following will introduce the above various devices in detail with reference to the accompanying drawings.

[0052] First, it should be noted that for the specific structure of the verification board 10, reference can be made to the specific description of the verification board 10 part mentioned above, and it will not be elaborated here in detail. What will be mainly introduced next is the connection and working mode between other devices in the test system and the verification board 10.

[0053] As shown above, the chip 11 to be tested can be a high-performance chip such as, but not limited to, a processor chip, so as to fully and effectively verify the performance of the VID power management interface on the processor and ensure that the processor can operate normally under high-frequency and high-performance conditions. At this time, the VID power management interface to be tested can be different types of VID power management interfaces on high-performance chips such as, but not limited to, processor chips. Of course, the chip 11 to be tested can also be a power chip dedicated to power supply, and the VID power management interface to be tested is the VID power management interface on the power chip.

[0054] The types of the VID power management interfaces to be tested on the chip 11 to be tested can be one or multiple; the number of the VID power management interfaces to be tested on the chip 11 to be tested can be one or multiple. For different types of VID power management interfaces to be tested, just put different behavior codes of the VID power management communication protocol controller into the environment of the system control unit 30, and adapt the behavior of different VID power management communication protocol controllers through programming to achieve the purpose of verifying the performance of multiple VID power management interfaces. To fully and effectively verify the performance of different types of VID power management interfaces and ensure that high-performance chips such as processors can operate normally under high-frequency and high-performance conditions.

[0055] In addition, a verification module connected to the VID power management interface to be tested can also be set in the chip 11 to be tested, and the verification module is used to perform self-test on the VID power management interface to be tested on the chip 11 to be tested. Specifically, the verification module can generate test instructions, and transmit the test instructions from the first interface 21 to the system control unit 30. The system control unit 30, PWM generator 40, power device 50 and sampling circuit 60 on the verification board 10 work, and form voltage data as feedback data, and transfer it to the system control unit 30. Then, as Figure 1As shown, the system control unit 30 transmits voltage data to the verification module through the first interface 21. At this time, the verification module can also confirm whether the to-be-tested VID power management interface can pass the verification according to the test instruction and the voltage data. For example, when it is confirmed that the to-be-tested VID power management interface passes the verification, a mark indicating passing the verification is generated for this to-be-tested VID power management interface; when it is confirmed that the to-be-tested VID power management interface fails to pass the verification, a mark indicating failing to pass the verification is generated for this to-be-tested VID power management interface. Then, the verification test is performed on the next to-be-tested VID power management interface. By generating test instructions and receiving voltage data in the to-be-tested chip 11 integrated with the to-be-tested VID power management interface, the self-test of each VID power management interface of the to-be-tested chip 11 is realized.

[0056] Furthermore, referring to Figure 2 , the test system may further include a host computer 12 for generating the test instructions, and the test instructions are generated by the host computer 12. As described in the foregoing verification board 10, the interface may at least further include a second interface 22 connected to the system control unit 30. The second interface 22 is connected to the host computer 12 to receive the test instructions generated by the host computer 12 and transmit the test instructions to the system control unit 30. The system control unit 30, the PWM generator 40, the power device 50 and the sampling circuit 60 on the verification board 10 work to form voltage data as feedback data and transfer it to the system control unit 30. The system control unit 30 transmits the voltage data to the host computer 12 through the second interface 22. At this time, the host computer 12 can also confirm whether the to-be-tested VID power management interface can pass the verification according to the test instruction and the voltage data. For example, when it is confirmed that the to-be-tested VID power management interface passes the verification, the host computer 12 can generate a mark indicating passing the verification for this to-be-tested VID power management interface; when it is confirmed that the to-be-tested VID power management interface fails to pass the verification, the host computer 12 can generate a mark indicating failing to pass the verification for this to-be-tested VID power management interface. Then, the verification test is performed on the next to-be-tested VID power management interface. By adding the second interface 22 and the host computer 12, the tester can write and modify test instructions through the host computer 12 and receive voltage data, which can not only enable the host computer 12 to verify the to-be-tested VID power management interface according to the test instruction and the voltage data by itself, but also enable the tester to monitor and verify manually. At the same time, when both the host computer 12 and the to-be-tested chip 11 perform the verification test, a comparative verification can be performed to ensure the consistency of the test results.

[0057] It should be noted that the host computer 12 is not limited to the direct connection method with the verification board 10 shown above. In addition, other methods can also be adopted. For example, the host computer can also be indirectly connected to the verification board 10 through the chip under test 11. The test instruction can still be generated by the host computer, the voltage data can still be transmitted to the host computer, and the process of confirming whether the verification can pass can still be completed by the host computer.

[0058] In addition, referring to Figure 3 and Figure 4 , the test system may further include a digital oscilloscope 13. At this time, the interface further includes at least a third interface 23 connected to the system control unit 30. The third interface 23 is connected to the digital oscilloscope 13, and the system control unit 30 also transmits the voltage data to the digital oscilloscope 13 through the third interface 23. By setting the third interface 23 and the digital oscilloscope 13, an observation terminal is provided for the signals of the VID power management interface protocol, and a display interface is provided for the waveforms of the VID power management interface protocol signals and the output voltage data to assist in determining the correctness of the test results. For the specific implementation of the connection method between the digital oscilloscope 13 and the verification board 10, refer to the description in the foregoing verification board 10 section, which will not be elaborated here.

[0059] By integrating the system control unit 30, the PWM generator 40, the power device 50 composed of MOS transistors, the sampling circuit 60, and the interface on a circuit board 20, the verification board 10 is formed. The VID power management interface under test is connected to the first interface 21, and the test instruction is input into the system control unit 30. The verification board 10 responds to the test instruction, thereby generating an output voltage. The sampling circuit 60 captures the voltage data and transmits the voltage data. The external part compares the test instruction and the voltage data to confirm whether each VID power management interface under test can pass the verification. That is, the behavior code of the VID power management communication protocol controller is placed in the environment of the system control unit 30, and different VID power management communication protocol controller behaviors are adapted through programming to achieve the purpose of verifying the performance of multiple VID power management interfaces. To fully and effectively verify the performance of the VID power management interface and ensure that high-performance chips such as processors can operate normally under high-frequency and high-performance conditions. And by integrating the system control unit 30, the PWM generator 40, the power device 50 composed of MOS transistors, and the sampling circuit 60 on a circuit board 20, it can be flexibly configured according to requirements to verify different types of VID power management interfaces. Thus, one verification board 10 can verify multiple different types of VID power management interfaces, which can reduce the volume of the test tool, shorten the response feedback time of the test instruction, and meet the requirements for testing VID power management interfaces with a relatively fast dynamic voltage switching rate.

[0060] In addition, an embodiment of the present invention further provides a test method based on any one of the above test systems, and this test method is used to test the VID power management interface. Refer to Figure 1 , Figure 3 and Figure 5 , and this test method includes:

[0061] S10: Generate a test instruction and transmit the test instruction from the interface to the system control unit 30;

[0062] S20: The system control unit 30 generates voltage regulation data according to the test instruction and transmits the voltage regulation data to the PWM generator 40;

[0063] S30: The PWM generator 40 generates a drive waveform according to the voltage regulation data and transmits the drive waveform to the power device 50;

[0064] S40: The power device 50 generates an output voltage according to the drive waveform;

[0065] S50: The sampling circuit 60 collects the voltage data output by the power device 50 and transmits the voltage data to the system control unit 30, and the system control unit 30 transmits the voltage data out through the interface.

[0066] In the above solution, a verification board 10 is formed by integrating a system control unit 30, a PWM generator 40, a power device 50 composed of MOS transistors, a sampling circuit 60, and an interface on a circuit board 20. The VID power management interface to be tested is connected to the first interface 21, and a test instruction is input into the system control unit 30. The verification board 10 responds to the test instruction, thereby generating an output voltage. The sampling circuit 60 captures the voltage data and transmits the voltage data. The external part compares the test instruction with the voltage data to confirm whether each VID power management interface to be tested can pass the verification. That is, the behavior code of the VID power management communication protocol controller is placed in the environment of the system control unit 30, and different VID power management communication protocol controllers are adapted through programming to achieve the purpose of verifying the performance of multiple VID power management interfaces. To fully and effectively verify the performance of the VID power management interface and ensure that high-performance chips such as processors can operate normally under high-frequency and high-performance conditions. And by integrating the system control unit 30, the PWM generator 40, the power device 50 composed of MOS transistors, and the sampling circuit 60 on a circuit board 20, it can be flexibly configured according to requirements to verify different types of VID power management interfaces. Thus, a verification board 10 can verify multiple different types of VID power management interfaces, which can reduce the volume of the test tool, shorten the response feedback time to the test instruction, and meet the requirements for testing VID power management interfaces with a relatively fast dynamic voltage switching rate. The following will introduce each of the above steps in detail with reference to the accompanying drawings.

[0067] Before the introduction, it should be emphasized that regarding the operation methods of each step in S20 - S50 above, specific details can refer to the description of the verification board 10 part above, and will not be introduced in detail here. What will be mainly introduced below is the method of generating test instructions and receiving voltage data by devices other than the verification board 10 in the test system.

[0068] Refer to Figure 1 and Figure 5 , when generating test instructions, different devices can generate test instructions.

[0069] For example, as described in the test system part above, when a verification module connected to the VID power management interface to be tested is also provided in the chip 11 to be tested. The verification module can generate test instructions and transmit the test instructions from the first interface 21 to the system control unit 30. After passing through S20 - S50, the system control unit 30 receives the voltage data, refer to Figure 1, when the system control unit 30 transmits voltage data through the interface, the system control unit 30 can transmit the voltage data to the verification module through the first interface 21. At this time, the test method can further include: the verification module confirms whether the to-be-tested VID power management interface can pass the verification according to the test instruction and the voltage data. By generating the test instruction and receiving the voltage data in the to-be-tested chip 11 integrated with the to-be-tested VID power management interface, the self-test of the to-be-tested chip 11 for each VID power management interface is realized.

[0070] As described in the foregoing test system part, in the test system, there is also a host computer 12 for generating test instructions. Refer to Figure 2 , when the host computer 12 is connected to the verification board 10, the interface at least further includes a second interface 22 connected to the system control unit 30, and the second interface 22 is connected to the host computer 12. The test instruction can be generated by the host computer 12 and transmitted to the system control unit 30 through the second interface 22. After S20 - S50, refer to Figure 2 , the system control unit 30 receives the voltage data. When the system control unit 30 transmits the voltage data through the interface, the system control unit 30 can transmit the voltage data to the host computer 12 through the second interface 22. At this time, the test method can further include: the host computer 12 confirms whether the to-be-tested VID power management interface can pass the verification according to the test instruction and the voltage data. By adding the second interface 22 and the host computer 12, the tester can write and modify the test instruction through the host computer 12 and receive the voltage data. It can not only enable the host computer 12 to verify the to-be-tested VID power management interface according to the test instruction and the voltage data by itself, but also enable the tester to monitor and verify manually. At the same time, when both the host computer 12 and the to-be-tested chip 11 perform the verification test, a comparative verification can be carried out to ensure the consistency of the test results.

[0071] In addition, as described in the foregoing test system part, refer to Figure 3 and Figure 4 , when the test system further includes a digital oscilloscope 13, the interface at least further includes a third interface 23 connected to the system control unit 30, and the third interface 23 is connected to the digital oscilloscope 13. At this time, when the system control unit 30 transmits the voltage data through the interface, the system control unit 30 can also transmit the voltage data to the digital oscilloscope 13 through the third interface 23 at the same time. By setting the third interface 23 and the digital oscilloscope 13, an observation terminal is provided for the signal of the VID power management interface protocol, and a display interface is provided for the waveform of the VID power management interface protocol signal and the output voltage data to assist in determining the correctness of the test result.

[0072] As described above, it is only the specific implementation manner of the present invention, but the protection scope of the present invention is not limited thereto. Any changes or substitutions that can be easily thought of by those skilled in the art within the technical scope disclosed by the present invention should be covered within the protection scope of the present invention. Therefore, the protection scope of the present invention should be subject to the protection scope of the claims.

Claims

1. A verification board for testing the VID power management interface, characterized in that, Comprising: A circuit board; An interface disposed on the circuit board, the interface at least including a first interface for connecting to a VID power management interface to be tested; A system control unit disposed on the circuit board; the system control unit is connected to the interface to receive a test instruction transmitted externally and generate voltage regulation data according to the test instruction; A PWM generator disposed on the circuit board; and the PWM generator is connected to the system control unit to receive the voltage regulation data temporarily stored in a register as an input signal and generate a drive waveform according to the voltage regulation data; A power device composed of MOS transistors disposed on the circuit board, the power device is connected to the PWM generator to receive the drive waveform and generate an output voltage according to the drive waveform; A sampling circuit disposed on the circuit board and connected to the power device to collect voltage data output by the power device; and the sampling circuit is further connected to the system control unit to transmit the voltage data to the system control unit, and the system control unit transmits the voltage data through the first interface.

2. The verification board according to claim 1, wherein The test instruction is transmitted from the first interface to the system control unit.

3. The verification board according to claim 1, characterized in that, The interface further at least includes a second interface connected to the system control unit, the second interface is used to connect to a host computer to receive the test instruction transmitted by the host computer; and the system control unit transmits the voltage data through the second interface.

4. The verification board according to claim 2 or 3, characterized in that, The interface further at least includes a third interface connected to the system control unit, the third interface is used to connect to a digital oscilloscope, and the system control unit also transmits the voltage data to the digital oscilloscope through the third interface.

5. The verification board according to claim 1, characterized in that, The system control unit includes a field programmable gate array; the field programmable gate array contains a register for temporarily storing the test instruction and the voltage data.

6. The verification board according to claim 1, characterized in that, The sampling circuit is further used to collect current data flowing through the power device and / or temperature data of the power device.

7. The verification board according to claim 1, characterized in that, The first interface is a power management bus interface.

8. A test system for testing a VID power management interface, characterized in that, Comprising: A chip to be tested, the chip to be tested is provided with a VID power management communication protocol controller and a VID power management interface to be tested connected to the VID power management communication protocol controller; A verification board, the verification board includes: A circuit board; An interface disposed on the circuit board, the interface at least including a first interface connected to the VID power management interface to be tested; A system control unit disposed on the circuit board; the system control unit is connected to the interface to receive a test instruction transmitted externally and generate voltage regulation data according to the test instruction; A PWM generator disposed on the circuit board; and the PWM generator is connected to the system control unit to receive the voltage regulation data temporarily stored in a register as an input signal and generate a drive waveform according to the voltage regulation data; A power device disposed on the circuit board and composed of MOS transistors, the power device being connected to the PWM generator to receive the drive waveform and generate an output voltage according to the drive waveform; A sampling circuit disposed on the circuit board and connected to the power device to collect voltage data output by the power device; and the sampling circuit is also connected to the system control unit to transmit the voltage data to the system control unit, and the system control unit transmits the voltage data through the first interface.

9. The test system according to claim 8, characterized in that, A verification module is further disposed in the chip under test and connected to the VID power management interface under test; The verification module generates the test instruction and transmits the test instruction from the first interface to the system control unit; The system control unit transmits the voltage data through the first interface to the verification module; The verification module is further configured to confirm whether the VID power management interface under test can pass the verification according to the test instruction and the voltage data.

10. The test system according to claim 8, characterized in that, Further included are: A host computer for generating the test instruction; The interface further includes at least a second interface connected to the system control unit; The second interface is connected to the host computer to receive the test instruction generated by the host computer; the system control unit transmits the voltage data through the second interface to the host computer; The host computer is further configured to confirm whether the VID power management interface under test can pass the verification according to the test instruction and the voltage data.

11. The test system according to claim 9 or 10, characterized in that, Further included are: A digital oscilloscope; The interface further includes at least a third interface connected to the system control unit, the third interface is connected to the digital oscilloscope, and the system control unit also transmits the voltage data through the third interface to the digital oscilloscope.

12. A testing method based on the testing system according to any one of claims 8 to 11, for testing a VID power management interface, characterized in that, Including: Generating a test instruction and transmitting the test instruction from the interface to the system control unit; The system control unit generates voltage adjustment data according to the test instruction and transmits the voltage adjustment data to the PWM generator; The PWM generator generates a drive waveform according to the voltage adjustment data and transmits the drive waveform to the power device; The power device generates an output voltage according to the drive waveform; The sampling circuit collects the voltage data output by the power device and transmits the voltage data to the system control unit, and the system control unit transmits the voltage data through the interface.

13. The test method according to claim 12, characterized in that, A verification module is further disposed in the chip under test and connected to the VID power management interface under test; The generating a test instruction and transmitting the test instruction from the interface to the system control unit includes: the verification module generates the test instruction and transmits the test instruction from the first interface to the system control unit; The system control unit transmitting the voltage data through the interface includes: the system control unit transmitting the voltage data through the first interface to the verification module; The described test method further includes: the verification module determines whether the to-be-tested VID power management interface can pass the verification according to the test instruction and the voltage data.

14. The testing method according to claim 12, characterized in that, The described test system further includes a host computer for generating the test instruction; the interface further includes at least a second interface connected to the system control unit, and the second interface is connected to the host computer; Generating the test instruction and transmitting the test instruction from the interface to the system control unit includes: the host computer generates the test instruction and transmits the test instruction to the system control unit through the second interface; The system control unit transmitting the voltage data out through the interface includes: the system control unit transmits the voltage data to the host computer through the second interface; The described test method further includes: the host computer determines whether the to-be-tested VID power management interface can pass the verification according to the test instruction and the voltage data.

15. The test method according to claim 13 or 14, characterized in that The described test system further includes a digital oscilloscope; the interface further includes at least a third interface connected to the system control unit, and the third interface is connected to the digital oscilloscope; The system control unit transmitting the voltage data out through the interface further includes: the system control unit also transmits the voltage data to the digital oscilloscope through the third interface.

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