A memory failure handling method and apparatus

Abstract

This application discloses a memory fault handling method and apparatus, relating to the field of computer technology, which solves the problem of system crashes caused by memory faults in the prior art. The specific solution is as follows: a management module obtains memory error information; based on the memory error information, the management module uses a machine learning algorithm to determine the memory fault characteristic pattern or the isolation repair technology used to repair the memory; based on the memory fault characteristic pattern or the isolation repair technology used to repair the memory, the management module determines whether to use at least one of hardware isolation or software isolation to repair the memory.

Description

[0001] This application claims priority to Chinese Patent Application No. 202010778351.0, filed with the State Intellectual Property Office of China on August 5, 2020, entitled “A Memory Fault Prediction, Repair Method and Apparatus”, the entire contents of which are incorporated herein by reference. Technical Field

[0002] This application relates to the field of computer technology, and in particular to a method and apparatus for handling memory faults. Background Technology

[0003] Dynamic random access memory (DRAM) is a common type of random access memory widely used in the storage field. As DRAM memory capacity increases, its basic failure rate also rises. Normally, when memory errors occur, error checking and correction (ECC) algorithms can be used to correct them. However, frequent error correction can impact system performance. Furthermore, as memory failures become more severe, the error correction algorithms become overwhelmed, significantly increasing the probability of failure and potentially leading to uncorrectable errors, thus causing system crashes.

[0004] One memory repair method involves accumulating the number of corrected errors (CEs) in memory. When the number of CEs reaches a threshold, the Basic Input / Output System (BIOS) issues a command to trigger a low-level memory isolation and replacement operation built into the Central Processing Unit (CPU). This isolates the faulty area, preventing further access to and from rewriting that memory region. However, this method cannot accurately determine the severity or exact location of the memory fault, resulting in poor accuracy and coverage of fault isolation, and a higher likelihood of system crashes. Summary of the Invention

[0005] This application provides a memory fault handling method and apparatus, which can reduce the probability of system crashes due to memory faults.

[0006] To achieve the above objectives, the embodiments of this application adopt the following technical solutions:

[0007] A first aspect of this application provides a memory fault handling method, comprising: a management module acquiring memory error information; the management module determining, based on the memory error information, a machine learning algorithm to identify a memory fault characteristic pattern or an isolation repair technique for repairing the memory; and the management module determining, based on the memory fault characteristic pattern or the isolation repair technique for repairing the memory, to repair the memory using at least one of hardware isolation or software isolation. Based on this solution, the memory fault characteristic pattern or the isolation repair technique determined by the machine learning algorithm using the memory error information is relatively accurate. Furthermore, the management module can determine the specific isolation method to be used for different fault characteristic patterns or different isolation repair techniques, thus resulting in a high accuracy rate for fault repair and reducing the probability of system downtime.

[0008] For example, the management module, based on the memory error information, may use a machine learning algorithm to determine the memory's fault characteristic patterns. This may include: combining the current memory error information with the memory's historical error information, sequentially determining which fault mode conditions the current memory meets, and generating a fault mode code for the current memory. This fault mode code indicates which fault mode conditions the current memory meets. Based on multiple fault mode codes, the management module uses a machine learning algorithm to predict the memory's fault patterns and the probability that each fault mode will lead to a system-level failure, and determines the memory's fault characteristic patterns based on these probabilities.

[0009] In conjunction with the first aspect, in one possible implementation, the aforementioned memory error information includes at least one of the following: the status of correctable errors (CEs), the time of CE occurrence, the number of CE errors, the physical address information of the CE; the status of uncorrectable errors, the time of uncorrectable errors, the number of uncorrectable errors, the physical address information of uncorrectable errors, the number of memory inspection errors, the address of the row with memory inspection errors, the address of the column with memory inspection errors, and the address of the row with the most memory inspection errors. The physical address information of the CE is used to indicate the physical location of the CE in memory, and the physical address information of uncorrectable errors is used to indicate the physical location of the uncorrectable errors in memory. Based on this scheme, the specific location of memory faults can be accurately located based on detailed memory error information, improving the accuracy of memory fault location. It is understood that the physical address information of the CE can indicate the specific physical location of the CE in memory. For example, the physical address information of the CE may include one or more of the following: the CPU node number, Channel number, DIMM slot number, logical Rank number, Bank group number, bank number, row number, column number, chip number, or bit position. For example, the physical address information of an uncorrectable error may include one or more of the following: CPU node number, Channel number, DIMM slot number, logical Rank number, Bank group number, bank number, row number, column number, chip number, or bit position.

[0010] Combining the first aspect and the aforementioned possible implementations, in another possible implementation, the aforementioned fault characteristic modes include at least one of the following: Page fault mode, single-bit fault mode, Cell fault mode, Row fault mode, Column fault mode, Bank fault mode, Device fault mode, Rank fault mode, Channel fault mode, Dual In-line Memory Module (DIMM) fault mode, a small number of continuous errors fault mode, and a short-term sudden large number of errors fault mode. Based on this solution, the fault characteristic modes of the memory are located more accurately, and the specific isolation method is determined for each fault characteristic mode. Therefore, the accuracy of fault repair is high, and the probability of system downtime is reduced.

[0011] In conjunction with the first aspect and the aforementioned possible implementations, in another possible implementation, the method further includes: a management module acquiring memory operating status data; the memory operating status data includes at least one of: CPU utilization information, temperature information, running program information, and memory health status information. Based on this solution, by acquiring memory operating status-related data, it is possible to predict memory failure modes or repair isolation and repair techniques used to repair the memory based on this data, further improving the accuracy of failure mode prediction.

[0012] Combining the first aspect and the aforementioned possible implementations, in another possible implementation, the management module uses machine learning algorithms based on memory error information to determine the memory fault characteristic pattern or the isolation repair technique used to repair the memory. This includes: the management module using machine learning algorithms based on memory error information and memory operating status data to determine the memory fault characteristic pattern or the isolation repair technique used to repair the memory. Based on this solution, determining the memory fault characteristic pattern or the isolation repair technique used to repair the memory through memory error information and memory operating status data can further improve the accuracy of predicting memory fault characteristic patterns.

[0013] In conjunction with the first aspect and the aforementioned possible implementations, in another possible implementation, the method further includes: if the management module determines to use hardware isolation to repair the memory, the management module sends a first fault repair request to the processor firmware. This first fault repair request requests the processor firmware to repair the memory. The first fault repair request includes at least one of the fault characteristic mode of the memory or the isolation repair technology used to repair the memory. Based on this scheme, when the management module determines to use hardware isolation to repair the memory, it can notify the processor firmware of the current memory fault characteristic mode or the isolation repair technology used to repair the memory. This allows the processor firmware to use the isolation repair technology to repair the faulty area, resulting in higher accuracy in fault repair and reducing the probability of system crashes. Optionally, the first fault repair request sent by the management module to the processor firmware may also include fault address information of the memory (e.g., bank address information) to indicate the specific area to be repaired by the processor firmware.

[0014] In conjunction with the first aspect and the aforementioned possible implementations, in another possible implementation, the method further includes: the management module receiving a first fault repair response from the processor firmware, the first fault repair response carrying the repair result after the processor firmware repairs the memory. Based on this solution, after the processor firmware repairs the memory, by feeding back the repair result to the management module, the success rate of fault repair can be further improved. Moreover, the management module can predict the severity of the memory fault based on the repair result fed back by the processor firmware.

[0015] In conjunction with the first aspect and the aforementioned possible implementations, in another possible implementation, the method further includes: the management module sending a first fault repair information table to the processor firmware. This first fault repair information table indicates a fault characteristic mode and one or more hardware isolation repair technologies corresponding to that fault characteristic mode. Based on this solution, the processor firmware can learn about the hardware isolation repair technologies that can be used for the fault characteristic mode based on the first fault repair information table, thereby improving the processor firmware's repair capabilities.

[0016] Combining the first aspect and the aforementioned possible implementations, in another possible implementation, the hardware isolation repair technology includes at least one of the following: bit isolation replacement, cell isolation replacement, row isolation replacement, column isolation replacement, bank isolation replacement, device isolation replacement, rank isolation replacement, channel isolation replacement, single-particle data correction (SDDC), single-particle error correction (SDEC), adaptive dual-particle data correction - multi-region ADDDC-MR, adaptive data correction - single-region ADC-SR, adaptive dual-particle error correction (ADDEC), partial cache data replacement (PCLS), adaptive cache row replacement (ACLS), hardware row replacement (hPPR), software row replacement (sPPR), row replacement (PPR), or hardware isolation repair technology that replaces a specific address range of memory. Based on this solution, the processor firmware can employ different hardware isolation repair technologies for different fault characteristic modes, resulting in a high repair accuracy.

[0017] Combining the first aspect and the aforementioned possible implementations, in another possible implementation, the processor firmware includes firmware, a basic input / output system (BIOS), a management engine (ME), or an intelligent management unit (IMU). Based on this solution, the firmware, BIOS, ME, or IMU can all repair faulty areas of the memory, demonstrating strong repair capabilities.

[0018] In conjunction with the first aspect and the above possible implementations, in another possible implementation, the method further includes: if the management module determines to use software isolation to repair the memory, the management module sends a second fault repair request to the operating system (OS) management unit. This second fault repair request requests the OS management unit to repair the memory. The second fault repair request includes at least one of the fault characteristic mode of the memory or the isolation repair technique used to repair the memory. Based on this scheme, when the management module determines to use software isolation to repair the memory, it can notify the OS management unit of the current memory fault characteristic mode, or it can notify the OS management unit of the isolation repair technique used to repair the memory. This allows the OS management unit to use the isolation repair technique to repair the faulty area, resulting in higher accuracy in fault repair and reducing the probability of system crashes. Optionally, the second fault repair request sent by the management module to the processor firmware may also include fault address information of the memory (e.g., page address information) to indicate the specific area to be repaired by the processor firmware. Understandably, the management module can directly notify the OS management unit of the software isolation repair technology used to repair the memory, or it can only notify the OS management unit of the memory's fault characteristic mode, and the OS management unit can then determine the software isolation repair technology corresponding to that memory's fault characteristic mode.

[0019] In conjunction with the first aspect and the aforementioned possible implementations, in another possible implementation, the method further includes: the management module receiving a second fault repair response from the OS management unit, the second fault repair response carrying the repair result after the OS management unit repairs the memory. Based on this scheme, after the OS management unit repairs the memory, it feeds back the repair result to the management module, enabling the management module to predict the severity of the memory fault based on the repair result.

[0020] In conjunction with the first aspect and the aforementioned possible implementations, in another possible implementation, the method further includes: the management module sending a second fault repair information table to the OS management unit. This second fault repair information table indicates the fault characteristic mode and one or more software isolation repair techniques corresponding to that fault characteristic mode. Based on this solution, the OS management unit can learn about the software isolation repair techniques that can be used for the fault characteristic mode based on the second fault repair information table, thereby improving the OS management unit's repair capabilities.

[0021] In conjunction with the first aspect and the aforementioned possible implementations, another possible implementation includes at least one of page isolation, address isolation, process isolation, or software isolation and repair techniques that replace a specific memory address range. Based on this solution, the OS management unit can employ different software isolation and repair techniques for different fault characteristic modes, resulting in a high accuracy rate in repair.

[0022] Combining the first aspect and the aforementioned possible implementations, in another possible implementation, the aforementioned OS management unit is either the system management unit built into the OS or a device management agent installed in the OS. Based on this solution, both the system management unit and the device management agent installed in the OS can repair faulty areas of memory, demonstrating strong repair capabilities.

[0023] Combining the first aspect and the aforementioned possible implementations, in another possible implementation, the management module determines the fault characteristic pattern of the memory based on the memory error information using a machine learning algorithm. This includes: the management module determining the fault characteristic pattern of the memory based on the memory error information and a fault prediction model using a machine learning algorithm; the fault prediction model is used to predict the fault characteristic pattern of the memory. Based on this solution, the fault characteristic pattern of the memory can be determined based on the fault prediction model, improving the accuracy of the fault characteristic pattern. Optionally, the management module can also determine the fault characteristic pattern of the memory based on the memory error information, memory operating status data, and the fault prediction model using a machine learning algorithm.

[0024] In conjunction with the first aspect and the aforementioned possible implementations, another possible implementation further includes: the management module determining the severity of the memory fault; and, if the severity of the memory fault exceeds a preset threshold, the management module sending an alarm message to the upper-level operation and maintenance system. Based on this solution, the management module can predict the severity of memory faults and send alarm messages when the memory fault is severe, thus avoiding the risk of system downtime.

[0025] In conjunction with the first aspect and the aforementioned possible implementations, in another possible implementation, the management module determines the severity of the memory fault by: determining the severity of the memory fault based on at least one of a first fault repair response and a second fault repair response. Based on this solution, the management module can predict the severity of the memory fault based on the repair results fed back by the processor firmware and the OS management unit, thereby avoiding the risk of system downtime.

[0026] In conjunction with the first aspect and the aforementioned possible implementations, in another possible implementation, the management module determines the severity of the memory failure by: determining the severity of the memory failure based on the memory's error information and its operational status data. Based on this solution, the management module can predict the severity of memory failures based on memory error information and operational status data, thereby avoiding the risk of system downtime.

[0027] Combining the first aspect and the aforementioned possible implementations, in another possible implementation, the management module is a management unit for non-business modules. This management module includes a running status management unit, a management unit built into the processor, a management system in an external management chip, a server motherboard management control unit (BMC), a system management module (SMM), or a device management system in the operating system (OS). Based on this solution, communication between the non-business unit management unit and the processor firmware and OS management unit is possible, thereby locating the fault area more accurately, improving the accuracy of fault repair, and reducing the probability of system downtime.

[0028] A second aspect of this application provides a memory fault handling method, comprising: processor firmware sending memory error information to a management module; the processor firmware receiving a first fault repair request from the management module, the first fault repair request being used to request the processor firmware to repair the memory, the first fault repair request including at least one of a memory fault characteristic mode or an isolation repair technique used to repair the memory; and the processor firmware repairing the memory based on the isolation repair technique. Based on this solution, when the management module determines to use hardware isolation repair for memory, it can notify the processor firmware of the current memory fault characteristic mode or the isolation repair technique used to repair the memory, enabling the processor firmware to use the isolation repair technique to repair the faulty area. Therefore, the accuracy of fault repair is high, reducing the probability of system crashes. It is understood that the management module can directly notify the processor firmware of the hardware isolation repair technique used to repair the memory, or it can only notify the processor firmware of the memory fault characteristic mode, allowing the processor firmware to determine the isolation repair technique used to repair the memory fault characteristic mode. Optionally, the first fault repair request received by the processor firmware may also include memory fault address information (e.g., bank address information), based on which the processor firmware can determine the specific area to be repaired.

[0029] In conjunction with the second aspect, in one possible implementation, the aforementioned memory error information includes at least one of the following: the status of correctable errors (CEs), the time of CE occurrence, the number of CE errors, the physical address information of CEs; the status of uncorrectable errors, the time of uncorrectable errors, the number of uncorrectable errors, the physical address information of uncorrectable errors, the number of memory inspection errors, the address of the row with memory inspection errors, the address of the column with memory inspection errors, and the address of the row with the most memory inspection errors. The physical address information of the CEs is used to indicate the physical location of the CEs in memory, and the physical address information of the uncorrectable errors is used to indicate the physical location of the uncorrectable errors in memory. Based on this scheme, the processor firmware can send detailed memory error information to the management module, enabling the management module to accurately locate the specific location of the memory fault based on this detailed memory error information, thus improving the accuracy of memory fault location.

[0030] Combining the second aspect and the aforementioned possible implementations, in another possible implementation, the aforementioned fault characteristic modes include at least one of the following: single-bit fault mode, cell fault mode, row fault mode, column fault mode, bank fault mode, device fault mode, rank fault mode, channel fault mode, dual in-line memory (DIMM) fault mode, a small number of continuous errors fault mode, and a short-term sudden large number of errors fault mode. Based on this solution, the fault characteristic modes of the memory are located more accurately, and the specific isolation method is determined for each fault characteristic mode. Therefore, the accuracy of fault repair is high, and the probability of system downtime is reduced.

[0031] In conjunction with the second aspect and the aforementioned possible implementations, in another possible implementation, the method further includes: the processor firmware sending a first fault repair response to the management module, the first fault repair response carrying the repair result after the processor firmware repairs the memory. Based on this solution, after the processor firmware repairs the memory, by feeding back the repair result to the management module, the success rate of fault repair can be further improved. Moreover, the management module can predict the severity of the memory fault based on the repair result fed back by the processor firmware.

[0032] In conjunction with the second aspect and the aforementioned possible implementations, in another possible implementation, the method further includes: the processor firmware receiving a first fault repair information table from the management module, the first fault repair information table indicating a fault characteristic mode and one or more hardware isolation repair technologies corresponding to the fault characteristic mode. Based on this solution, the processor firmware can learn the hardware isolation repair technologies that can be used for the fault characteristic mode based on the first fault repair information table, thereby improving the repair capability of the processor firmware.

[0033] Combining the second aspect and the aforementioned possible implementations, in another possible implementation, the hardware isolation repair technology includes at least one of the following: bit isolation replacement, cell isolation replacement, row isolation replacement, column isolation replacement, bank isolation replacement, device isolation replacement, rank isolation replacement, channel isolation replacement, single-particle data correction (SDDC), single-particle error correction (SDEC), adaptive dual-particle data correction - multi-region ADDDC-MR, adaptive data correction - single-region ADC-SR, adaptive dual-particle error correction (ADDEC), partial cache data replacement (PCLS), adaptive cache row replacement (ACLS), hardware row replacement (hPPR), software row replacement (sPPR), row replacement (PPR), or hardware isolation repair technology that replaces a specific address range of memory. Based on this solution, the processor firmware can employ different hardware isolation repair technologies for different fault characteristic modes, resulting in a high repair accuracy.

[0034] In conjunction with the second aspect and the aforementioned possible implementations, in another possible implementation, the method further includes: the processor firmware determining the isolation repair technique to be used to repair the memory based on the memory fault characteristic patterns and the aforementioned first fault repair information table. Based on this solution, the processor firmware can learn the hardware isolation repair techniques that can be used for fault characteristic patterns based on the first fault repair information table, thereby improving the repair capability of the processor firmware.

[0035] Combining the second aspect and the aforementioned possible implementations, in another possible implementation, the processor firmware includes firmware, a basic input / output system (BIOS), a management engine (ME), or an intelligent management unit (IMU). Based on this solution, the firmware, BIOS, ME, or IMU can all repair faulty areas of the memory, demonstrating strong repair capabilities.

[0036] A third aspect of this application provides a memory fault handling method, comprising: an operating system (OS) management unit receiving a second fault repair request from a management module, the second fault repair request requesting the OS management unit to repair the memory, the second fault repair request including at least one of a fault characteristic pattern of the memory or an isolation repair technique used to repair the memory; and the OS management unit repairing the memory based on the isolation repair technique. Based on this solution, by receiving the memory fault characteristic pattern from the management module, or the isolation repair technique used to repair the memory, the OS management unit can use the isolation repair technique to repair the faulty area, thus achieving a high accuracy rate in fault repair and reducing the probability of system crashes. It is understood that the management module can directly notify the OS management unit of the software isolation repair technique used to repair the memory, or it can only notify the OS management unit of the memory fault characteristic pattern, allowing the OS management unit to determine the software isolation repair technique corresponding to the memory fault characteristic pattern. Optionally, the second fault repair request sent by the management module to the processor firmware may further include memory fault address information (e.g., page address information) to indicate the specific area to be repaired by the processor firmware.

[0037] In conjunction with the third aspect, in one possible implementation, the aforementioned fault characteristic modes include at least one of the following: Page fault mode, single-bit fault mode, Cell fault mode, Row fault mode, Column fault mode, Bank fault mode, Device fault mode, Rank fault mode, Channel fault mode, Dual In-line Memory Module (DIMM) fault mode, a small number of continuous errors fault mode, and a short-term sudden large number of errors fault mode. Based on this solution, the fault characteristic modes of the memory are located more accurately, and the specific isolation method is determined for each fault characteristic mode. Therefore, the accuracy of fault repair is high, and the probability of system downtime is reduced.

[0038] In conjunction with the third aspect and the aforementioned possible implementations, in another possible implementation, the method further includes: the OS management unit sending a second fault repair response to the management module, the second fault repair response carrying the repair result after the OS management unit repairs the memory. Based on this scheme, after the OS management unit repairs the memory, it feeds back the repair result to the management module, enabling the management module to predict the severity of the memory fault based on the repair result.

[0039] In conjunction with the third aspect and the aforementioned possible implementations, in another possible implementation, the method further includes: the OS management unit receiving a second fault repair information table from the management module. This second fault repair information table indicates a fault characteristic mode and one or more software isolation repair techniques corresponding to that fault characteristic mode. Based on this solution, the OS management unit can determine the software isolation repair techniques that can be used for a fault characteristic mode based on the second fault repair information table, thereby improving the OS management unit's repair capabilities.

[0040] In conjunction with the third aspect and the aforementioned possible implementations, another possible implementation includes at least one of page isolation, address isolation, process isolation, or software isolation and repair techniques that replace a specific memory address range. Based on this solution, the OS management unit can employ different software isolation and repair techniques for different fault characteristic modes, resulting in a high accuracy rate in repair.

[0041] In conjunction with the third aspect and the aforementioned possible implementations, in another possible implementation, the method further includes: the OS management unit determining the isolation repair technique to be used to repair the memory based on the memory fault characteristic patterns and the second fault repair information table. Based on this solution, the OS management unit can learn about the software isolation repair techniques that can be used for fault characteristic patterns based on the second fault repair information table, thereby improving the OS management unit's repair capabilities.

[0042] Combining the third aspect and the aforementioned possible implementations, in another possible implementation, the aforementioned OS management unit is either the system management unit built into the OS or a device management agent installed in the OS. Based on this solution, both the system management unit and the device management agent installed in the OS can repair faulty areas of the memory, demonstrating strong repair capabilities.

[0043] A fourth aspect of this application provides a management module that implements the memory fault handling method described in any of the first aspects above. This function can be implemented in hardware or by hardware executing corresponding software. The hardware or software includes one or more modules corresponding to the above-described functions.

[0044] A fifth aspect of this application provides processor firmware that has the function of implementing any of the memory fault handling methods described in the second aspect above. This function can be implemented in hardware or by hardware executing corresponding software. The hardware or software includes one or more modules corresponding to the above-described functions.

[0045] A sixth aspect of this application provides an OS management unit that has the function of implementing any of the memory fault handling methods described in the third aspect above. This function can be implemented by software. The software includes one or more modules corresponding to the above-described functions.

[0046] In a seventh aspect of this application, a computer-readable storage medium is provided, which stores instructions that, when executed on a computer, enable the computer to perform any of the memory fault handling methods described in the first to third aspects above.

[0047] In an eighth aspect of this application, this application provides a computer program product containing instructions that, when run on a computer, enable the computer to execute any of the memory fault handling methods described in the first to third aspects above.

[0048] A ninth aspect of this application provides a memory fault handling system, which includes a management module, processor firmware, and an OS management unit. The management module is used to implement any of the memory fault handling methods described in the first aspect, the processor firmware is used to implement any of the memory fault handling methods described in the second aspect, and the OS management unit is used to implement any of the memory fault handling methods described in the third aspect. Attached Figure Description

[0049] Figure 1 A schematic diagram illustrating a memory fault repair method provided in an embodiment of this application;

[0050] Figure 2 A schematic diagram illustrating a memory fault repair method provided in an embodiment of this application;

[0051] Figure 3 A schematic diagram of the structure of a computer system provided in an embodiment of this application;

[0052] Figure 4 A flowchart illustrating a memory fault handling method provided in an embodiment of this application;

[0053] Figure 5 A flowchart illustrating another memory fault handling method provided in an embodiment of this application;

[0054] Figure 6 A flowchart illustrating another memory fault handling method provided in an embodiment of this application;

[0055] Figure 7 A flowchart illustrating another memory fault handling method provided in an embodiment of this application;

[0056] Figure 8 A flowchart illustrating another memory fault handling method provided in an embodiment of this application;

[0057] Figure 9 A flowchart illustrating another memory fault handling method provided in an embodiment of this application;

[0058] Figure 10 This is a schematic diagram of the composition of a memory fault handling device provided in an embodiment of this application;

[0059] Figure 11 A schematic diagram illustrating the composition of another memory fault handling device provided in this application embodiment;

[0060] Figure 12 This is a schematic diagram illustrating the composition of another memory fault handling device provided in an embodiment of this application. Detailed Implementation

[0061] The technical solutions in the embodiments of this application will be described below with reference to the accompanying drawings. In this application, "at least one" means one or more, and "more than one" means two or more. "And / or" describes the relationship between related objects, indicating that there can be three relationships. For example, A and / or B can mean: A exists alone, A and B exist simultaneously, or B exists alone, where A and B can be singular or plural. The character " / " generally indicates that the related objects before and after are in an "or" relationship. "At least one of the following" or similar expressions refer to any combination of these items, including any combination of single or plural items. For example, at least one of a, b, or c can mean: a, b, c, a and b, a and c, b and c, or a and b and c, where a, b, and c can be single or multiple. Furthermore, to facilitate a clear description of the technical solutions in the embodiments of this application, the terms "first" and "second" are used in the embodiments of this application to distinguish identical or similar items with essentially the same function and effect. Those skilled in the art will understand that the terms "first" and "second" do not limit the quantity or execution order. For example, the "first" in the first fault repair request and the "second" in the second fault repair request in the embodiments of this application are only used to distinguish different fault repair requests. The descriptions of "first" and "second" appearing in the embodiments of this application are only for illustrative purposes and to distinguish the described objects; they do not indicate any order and do not represent a special limitation on the number of devices in the embodiments of this application, nor do they constitute any limitation on the embodiments of this application.

[0062] It should be noted that, in this application, the terms "exemplary" or "for example" are used to indicate that something is being described as an example, illustration, or illustration. Any embodiment or design described as "exemplary" or "for example" in this application should not be construed as being more preferred or advantageous than other embodiments or design solutions. Specifically, the use of terms such as "exemplary" or "for example" is intended to present the relevant concepts in a concrete manner.

[0063] In the embodiments of this application, "multiple" refers to two or more.

[0064] The descriptions of "first," "second," etc., appearing in the embodiments of this application are for illustrative purposes and to distinguish the objects being described. They have no order and do not indicate any special limitation on the number of devices in the embodiments of this application, nor do they constitute any limitation on the embodiments of this application.

[0065] The architectural scenarios described in this application are for the purpose of more clearly illustrating the technical solutions of this application, and do not constitute a limitation on the technical solutions provided in this application. As those skilled in the art will know, with the evolution of computer systems, the technical solutions provided in this application are also applicable to similar technical problems.

[0066] Current computing systems possess a certain degree of hardware repair capability for their memory. For example, when memory fails, redundant memory space can replace the faulty memory space, effectively isolating the faulty area in hardware. However, due to the limited amount of redundant space in memory, the number of times hardware isolation technology can be used is limited. For minor memory errors, error correction algorithms can generally be used to correct them. In the event of a more serious fault, redundant memory space is then used to replace and repair the faulty area.

[0067] For example, Figure 1 As a memory repair method, such as Figure 1 As shown, after the error correction mechanism inside the central processing unit (CPU) identifies a correctable memory error (CE), the basic input / output system (BIOS) counts the CEs and compares them with a threshold. When the number of CEs reaches the threshold, the BIOS issues a command to trigger the CPU's built-in low-level memory isolation and replacement action (such as bank isolation or cell isolation) to locally isolate the faulty area, that is, to stop using the faulty area memory to avoid reading and writing to the faulty area again.

[0068] However, due to the limited processing power of the BIOS, it can only accumulate the count of correctable memory errors, and cannot accurately determine the severity of memory faults or their precise row and column locations. This results in poor accuracy and coverage of fault isolation. Furthermore, setting the threshold too high will miss a large number of error scenarios; uncorrectable errors (UCEs) may occur before the threshold is reached, leading to system crashes. Setting the threshold too low may result in many minor faults being isolated and replaced, failing to realize the true value of isolation and replacement. Therefore, this method cannot accurately determine the location of memory faults, has a low accuracy rate in memory repair, and is more likely to cause system crashes.

[0069] For example, Figure 2 Another memory repair method, such as Figure 2 As shown, after the CPU identifies a correctable error, it reports it to the upper-level operating system (OS). The OS counts the correctable errors and judges the severity of the fault. When the number of correctable errors reaches a threshold, the OS issues a command to trigger the error isolation mechanism in the OS (such as page isolation) to isolate the virtual space of the faulty area in the OS and no longer use the memory address of the faulty area.

[0070] However, this method only allows the OS to perform isolation and replacement at the OS level, and cannot access the CPU's underlying memory resources, thus wasting the available hardware isolation capabilities at the lower level. Furthermore, OS-level isolation reduces memory space, especially for large page isolation, which carries a higher risk of system crashes. Therefore, this method has poor memory repair capabilities, making system crashes more likely.

[0071] To address the problem of system crashes caused by inaccurate memory fault location in existing technologies, this application provides a memory fault handling method. This method can accurately determine the location of memory faults, has a high fault repair accuracy rate, and reduces the probability of system crashes.

[0072] The memory fault handling method provided in this application embodiment can be applied to... Figure 3 The computer system 100 shown can be a server, storage controller, switch, router, base station controller, compute offloading card, compute accelerator card, etc. This embodiment of the application addresses... Figure 3 The specific form of the computer system shown is not limited. The following embodiments are only illustrated using the computer system as a server as an example. Figure 3 As shown, the computer system 100 includes a management module 101, a processor firmware 102, an operating system (OS) management unit 103, and memory 104.

[0073] The management module 101 can be a management unit for non-business modules, and it can also be called an out-of-band management module 101. For example, the management module 101 can remotely maintain and manage the server through a dedicated data channel. This management module 101 is completely independent of the server's operating system (OS) and can communicate with the BIOS and OS (or OS management unit) through the server's out-of-band management interface.

[0074] For example, management module 101 may include a server operating status management unit, a management unit built into the processor, a management system in a management chip outside the processor, a server motherboard management controller (BMC), a system management module (SMM), a management unit built into a business unit, or a device management system in the OS, etc. This application does not limit the specific form of the management module; it is merely an illustrative example. The following embodiments use BMC as an example to illustrate management module 101.

[0075] For example, management module 101 can be used to obtain error information and data related to the operating status of memory 104. Management module 101 can also, based on the error information and operating status data of memory 104, use machine learning algorithms to determine the fault characteristic mode of the memory, and determine whether the fault mode should be repaired using hardware isolation technology or software isolation technology. When management module 101 determines that hardware isolation technology should be used to repair the memory, management module 101 sends a repair request to processor firmware 102. When management module 101 determines that software isolation technology should be used to repair the memory, management module 101 sends a repair request to OS management unit 103.

[0076] The processor firmware 102 can be firmware, a basic input / output system BIOS, a management engine (ME), or an intelligent management unit (IMU), etc. This application does not limit the specific form of the processor firmware 102; it is merely illustrative. The following embodiments use a BIOS as an example for illustration only.

[0077] The processor firmware 102 can be used to detect error information when a memory failure occurs. This includes information related to correctable errors and information related to uncorrectable errors. It should be noted that the specific content of the memory error information described above is merely an exemplary example, and this application embodiment does not limit the specific content of the error information detected by the processor firmware 102.

[0078] For example, the OS management unit 103 can be a system management unit built into the OS, or it can be a device management agent program installed in the OS. This application embodiment does not limit this.

[0079] For example, memory 104 can be the running memory of computer system 100. There can be multiple memory 104s in computer system 100, and the memory 104 can be dynamic random access memory (DRAM).

[0080] It should be noted that, in specific implementations, the computer system 100 can be any system including... Figure 3 Devices with similar structures. This application does not limit the specific type of computer system 100. Furthermore, Figure 3 The structural composition shown herein does not constitute a limitation on the computer system 100, except... Figure 3 In addition to the components shown, the computer system 100 may include more or fewer components than illustrated, or combine certain components, or have different component arrangements.

[0081] Combination Figure 3 ,like Figure 4 As shown, this is a memory fault handling method provided in an embodiment of the present application, which includes steps S401-S403.

[0082] S401, The management module obtains memory error information.

[0083] For example, memory error information refers to information about errors that occur during memory operation. This memory error information may include: the status of correctable errors (CEs), the time of occurrence of CEs, the number of CE errors, the physical address information of CEs, the status of uncorrectable errors, the time of occurrence of uncorrectable errors, the number of times uncorrectable errors occur, the physical address information of uncorrectable errors, the number of memory check errors, the address of the row with memory check errors, the address of the column with memory check errors, and the address of the row with the most memory check errors. This application embodiment does not limit the specific content included in the memory error information; it is merely an illustrative example.

[0084] For example, the physical address information of the CE mentioned above is used to indicate the physical location of the CE in memory. That is, the specific physical location of the CE in memory can be determined based on the physical address information of the CE. For example, the physical address information of the CE may include one or more of the following: CPU node number, Channel number, DIMM slot number, logical Rank number, Bank group number, bank number, row number, column number, chip number, or bit position.

[0085] For example, the physical address information of the aforementioned uncorrectable error is used to indicate the physical location of the uncorrectable error in memory. That is, the specific physical location of the uncorrectable error in memory can be determined based on this physical address information. The physical address information of the uncorrectable error may include one or more of the following: CPU node number, channel number, DIMM slot number, logical rank number, bank group number, bank number, row number, column number, chip number, or bit position.

[0086] The embodiments of this application do not limit the specific content of the physical address information of the CE and the physical address information with uncorrectable errors mentioned above; they are merely illustrative examples.

[0087] Optionally, the aforementioned uncorrectable errors may have different names in different processors or computer systems. For example, in the x86 architecture, uncorrectable errors may be called Software Recoverable Action Required (SRAR), Software Recoverable Action Optional (SRAO), or Uncorrected No Action (UCNA); in the ARM architecture, uncorrectable errors may be called Uncorrected Error (UE), Unrecoverable Error (UEU), Signaled or Recoverable Error (UER), Latent or Restartable Error (UEO), or Deferred Error (DE). This application does not limit the specific name of uncorrectable errors.

[0088] For example, in step S401, the management module obtaining memory error information may include: the management module receiving memory error information from the processor firmware. For example, the BMC receives memory error information sent by the BIOS. Optionally, the BMC may also receive error information sent by other processor firmware (e.g., Firmware, ME, or IMU), which is not limited in this embodiment.

[0089] Optionally, before step S401, the processor firmware may also detect memory error information and send the detected error information to the management module.

[0090] Optionally, before step S401, the module may further include: the management module receiving memory operating status data collected from sensors. This memory operating status data is data that reflects the memory's operating condition. For example, the memory operating status data may include at least one of CPU utilization information, temperature information, running program information, and memory health status information. Optionally, the memory operating status data may also include other data that reflects the memory's operating condition; this embodiment is not limited in this regard. For example, the BMC may receive temperature information of each Device (particle) collected by a temperature sensor in the memory.

[0091] S402. The management module uses machine learning algorithms to determine the fault characteristic patterns of memory or the isolation repair technology used to repair memory based on memory error information.

[0092] For example, memory fault characteristic modes may include one or more of the following: page fault mode, single-bit fault mode, cell fault mode, row fault mode, column fault mode, bank fault mode, device fault mode, rank fault mode, channel fault mode, dual in-line memory module (DIMM) fault mode, small number of continuous errors fault mode, and short-term sudden large number of errors fault mode. The specific granularity of the memory fault characteristic modes in this application embodiment is not limited; it is merely an illustrative example. With technological advancements, finer or coarser granular fault characteristic modes may emerge in the future.

[0093] For example, the isolation repair technology used to repair memory determined by the machine learning algorithm can be either hardware isolation repair technology or software isolation repair technology, and this application embodiment does not limit it in this way.

[0094] For example, hardware isolation repair techniques may include one or more of the following repair techniques: bit isolation replacement, cell isolation replacement, row isolation replacement, column isolation replacement, bank isolation replacement, device isolation replacement, rank isolation replacement, channel isolation replacement, single device data correction (SDDC), single device error correction (SDEC), adaptive double device data correction-multiple region (ADDDC-MR), adaptive data correction-single region (ADC-SR), adaptive double device error correction (ADDEC), partial cache line sparing (PCLS), adaptive cache linesparing (ACLS), hardware post-package repair (hPPR), software post-package repair (sPPR), post-package repair (PPR), or hardware isolation repair techniques that replace a specific address range of memory. The embodiments in this application do not limit the specific type of hardware isolation repair technology; they are merely illustrative examples.

[0095] For example, software isolation and repair techniques may include one or more of the following: page isolation, address isolation, process isolation, or software isolation and repair techniques that replace a specific range of memory addresses. This application does not limit the specific type of software isolation and repair technique; it is merely an illustrative example.

[0096] For example, the machine learning algorithm in step S402 may include threshold-based decision-making algorithms, decision tree algorithms, supervised machine learning algorithms, unsupervised machine learning algorithms, memory pin link detection algorithms, etc. For instance, the management module may determine the fault characteristic pattern of memory or the isolation repair technology used to repair memory based on decision tree algorithms, random forest algorithms, or neural network algorithms. This application embodiment does not limit the specific type of machine learning algorithm used in determining the fault characteristic pattern of memory or the isolation repair technology used to repair memory; this is merely an illustrative example.

[0097] For example, in step S402, the management module determines the memory fault characteristic pattern based on the memory error information using a machine learning algorithm. This can include: the management module determining the memory fault characteristic pattern based on the memory error information and a fault prediction model using a machine learning algorithm. This fault prediction model is used to predict the memory fault characteristic pattern.

[0098] For example, this fault prediction model can be built by the upper-layer operation and maintenance system by statistically analyzing memory error information from multiple servers over a period of time, and then using a machine learning algorithm based on this large amount of error information. Optionally, the machine learning algorithm used to build the fault prediction model can be the same as the machine learning algorithm used to determine the fault characteristic patterns of memory.

[0099] Optionally, before step S402 above, the upper-level operation and maintenance system may send a fault prediction model to the management module, and the management module receives the fault prediction model. Thus, the management module can determine the fault characteristic pattern of the memory based on the fault prediction model. It is understood that the input parameters of the fault prediction model can be memory error information and memory operating status data, and the output parameter can be the fault characteristic pattern.

[0100] For example, after the management module receives the current error information of the memory in step S401, the management module determines the fault characteristic mode of the memory based on the memory error information using a machine learning algorithm in step S402. This may include: the management module combining the current error information of the memory with the historical error information of the memory (the historical error information is the error information received by the management module before receiving the current error information) to sequentially determine whether the current memory meets the conditions of single-bit fault mode, cell fault mode, row fault mode, column fault mode, bank fault mode, device fault mode, rank fault mode, DIMM fault mode, and channel fault mode, and generating a fault mode code for the current memory. This fault mode code is used to indicate which fault mode conditions the current memory meets. Based on multiple fault mode codes, the management module uses a machine learning algorithm to predict the fault mode of the memory and the probability of each fault mode causing a system-level fault, and determines the fault characteristic mode of the memory based on the probability of each fault mode causing a system-level fault.

[0101] For example, the management module can use a machine learning algorithm to sequentially determine which of the above fault modes the current memory meets. Optionally, the current memory can meet the conditions of one or more of the above fault modes. For example, the current memory can meet the conditions of the Row fault mode, the Bank fault mode, and the Device fault mode. It is understood that this application embodiment does not limit the specific fault modes that the current memory meets or the conditions of each fault mode; the specific fault modes that the current memory meets are related to the memory's operating state and are merely illustrative examples here.

[0102] Optionally, the conditions for the single-bit failure mode, cell failure mode, row failure mode, column failure mode, bank failure mode, device failure mode, rank failure mode, DIMM failure mode, and channel failure mode can be obtained based on a fault prediction model. For example, based on a fault prediction model, the condition for a single-bit failure mode can be determined as the number of errors of the same bit exceeding a threshold. As another example, based on a fault prediction model, the condition for a row failure mode can be determined as the number of errors occurring in the same row exceeding a threshold.

[0103] Optionally, after the management module determines that the current memory meets the conditions of one or more fault modes, when generating a fault mode code for the current memory, the fault mode code can be a code composed of multiple bits, where one bit can represent a fault mode, and different values ​​of one bit can be used to indicate whether the current memory meets the conditions of the fault mode corresponding to that bit.

[0104] For example, a fault mode is encoded using 9 bits, where a bit value of 1 indicates that the condition of the corresponding fault mode is met, and a bit value of 0 indicates that the condition of the corresponding fault mode is not met. Bit 0 being 1 can indicate that the current memory meets the condition of a single-bit fault mode; bit 1 being 1 can indicate that the current memory meets the condition of a cell fault mode; bit 2 being 1 can indicate that the current memory meets the condition of a row fault mode; bit 3 being 1 can indicate that the current memory meets the condition of a column fault mode; bit 4 being 1 can indicate that the current memory meets the condition of a bank fault mode; bit 5 being 1 can indicate that the current memory meets the condition of a device fault mode; bit 6 being 1 can indicate that the current memory meets the condition of a rank fault mode; bit 7 being 1 can indicate that the current memory meets the condition of a DIMM fault mode; and bit 8 being 1 can indicate that the current memory meets the condition of a channel fault mode. For example, the fault mode code determined by the management module is 000110100. This fault mode code is used to indicate the conditions for the current memory to meet the Row fault mode, the Bank fault mode, and the Device fault mode.

[0105] For example, each time the management module receives a memory error message, it determines a fault mode code. The management module can combine multiple historically determined fault mode codes and, based on the statistical values ​​of these codes, use a machine learning algorithm to predict the probability of different fault modes in memory causing system-level failures. Fault modes with a probability of causing system-level failures greater than a preset threshold are identified as memory fault characteristic modes. Optionally, the aforementioned statistical values ​​may include cumulative values, average values, sliding window average values, standard deviations, probability distribution parameters, and other results generated after statistical processing.

[0106] Optionally, the memory fault characteristic mode determined by the management module can be one or more, and this embodiment of the application is not limited in this regard. When the memory fault characteristic mode determined by the management module is one, the management module sends the fault characteristic mode to the processor firmware. When the memory fault characteristic mode determined by the management module is multiple, the management module can send the fault characteristic mode with the highest failure probability to the processor firmware, or it can send all of the multiple fault characteristic modes to the processor firmware.

[0107] Understandably, in step S402 above, the management module uses machine learning algorithms based on memory error information to determine the specific implementation method of the isolation repair technology used to repair memory. You can refer to the above implementation method of the management module using machine learning algorithms based on memory error information to determine the fault characteristic mode of memory, which will not be repeated here.

[0108] Optionally, if step S402 includes receiving memory operating status data collected from sensors before step S401, then step S402 may include: the management module using a machine learning algorithm to determine the memory's fault characteristic mode or the isolation repair technique used to repair the memory based on the memory's error information and operating status data. For example, the management module determines a fault mode code based on the memory's error information, and based on this fault mode code and the memory's operating status data, uses a machine learning algorithm to predict the memory's fault patterns and the probability of each fault mode causing a system-level failure, and determines the memory's fault characteristic mode based on the probability of each fault mode causing a system-level failure. It is understood that determining the memory's fault characteristic mode or the isolation repair technique used to repair the memory based on the memory's error information and operating status data can improve the accuracy of the predicted fault modes or repair techniques.

[0109] Optionally, when the management module determines that the memory fault characteristic mode is a DIMM fault mode or a more coarse-grained fault mode than DIMM (e.g., channel fault mode), the management module can send a warning message to remind the user to replace the memory module in order to repair the faulty memory.

[0110] Understandably, because the memory error information in this embodiment is detailed, down to the row and column addresses, it allows for accurate location of the memory fault area. Furthermore, by combining this detailed error information with machine learning algorithms, the identified memory fault characteristic patterns are quite accurate. Therefore, this solution can accurately locate the fault type and fault location.

[0111] S403. The management module determines whether to use at least one of hardware isolation or software isolation to repair the memory based on the memory fault characteristic mode or the isolation repair technology used to repair the memory.

[0112] Hardware isolation refers to using the CPU's built-in low-level memory resources to locally isolate the faulty area. In other words, redundant space at the CPU's lower level can be used to replace the faulty area, thus locally isolating it.

[0113] Software isolation refers to the OS layer isolating the region where a memory error occurs. For example, in page offline isolation, the OS layer can kill the process using the memory page, or it can close the application using the memory page. Optionally, the OS layer can isolate a memory page when an uncorrectable error occurs.

[0114] For example, the management module can determine, based on the different memory failure modes, whether to use hardware isolation to repair the faulty memory, or to use both hardware and software isolation to repair the faulty memory.

[0115] Optionally, when the memory fault characteristics include single-bit fault mode, cell fault mode, row fault mode, column fault mode, bank fault mode, device fault mode, rank fault mode, channel fault mode, DIMM fault mode, a small number of continuous errors fault mode, or a short-term sudden large number of errors fault mode, the management module can determine to use hardware isolation to repair the faulty memory. However, due to the limited redundancy space of the CPU's built-in underlying memory, hardware isolation may not be able to repair the faulty memory. When hardware isolation cannot repair the faulty memory, the management module can determine to use software isolation to repair the faulty memory.

[0116] For example, when the memory fault characteristic mode is Cell fault mode (or single-bit fault mode), the management module determines to use hardware isolation to repair the memory. If the redundant space of the underlying memory built into the CPU is insufficient and hardware isolation cannot repair the faulty memory, then the management module can determine to use software isolation to repair the faulty memory.

[0117] Optionally, when the memory failure mode is Page fault mode, the management module can determine to use software isolation to repair the memory.

[0118] In one implementation, the management module determines whether to use hardware isolation and / or software isolation to repair the memory based on the memory's fault characteristic mode. This can include: the management module preferentially determines to use hardware isolation to repair the faulty memory; if hardware isolation fails to repair the faulty memory, the management module can determine to use software isolation to repair the faulty memory. It should be noted that when the memory's fault characteristic mode is any fault mode other than the Page fault mode, the management module can use this implementation to determine whether to use hardware isolation or software isolation to repair the faulty memory. It should also be noted that in this implementation, the management module can obtain feedback information from the processor firmware indicating that hardware isolation cannot repair the faulty memory.

[0119] In another implementation, the management module determines whether to use hardware isolation and / or software isolation to repair the memory based on the isolation repair technology employed. This can include: when the isolation repair technology used is hardware isolation, the management module determines to use hardware isolation to repair the memory; when the isolation repair technology used is software isolation, the management module determines to use software isolation to repair the memory; and when both hardware and software isolation technologies are used, the management module determines to use both hardware and software isolation to repair the memory.

[0120] Understandably, the memory fault handling method provided in this embodiment obtains memory error information through a management module, and based on this error information, uses machine learning algorithms to determine the memory fault characteristic pattern or isolation and repair technology. Then, based on this fault characteristic pattern or isolation and repair technology, it determines whether to use hardware isolation and / or software isolation to repair the faulty memory. This solution, based on detailed memory error information and using machine learning algorithms, accurately determines the memory fault characteristic pattern. Furthermore, the management module can determine the specific isolation method to use for different fault characteristic patterns or different isolation and repair technologies, thus achieving a high accuracy rate in fault repair and reducing the probability of system downtime.

[0121] This application also provides a memory fault handling method, involving the interaction between a management module and processor firmware, such as... Figure 5 As shown, if step S403 determines that hardware isolation is used to repair the memory, the method may further include steps S501-S506 based on the above steps S401-S403. Figure 5 Steps S401-S403 are not shown in the diagram.

[0122] S501. If the management module determines that hardware isolation is used to repair the memory, the management module sends the first fault repair request to the processor firmware.

[0123] The first fault repair request is used to request the processor firmware to repair the memory. The first fault repair request includes at least one of the following: a memory fault characteristic pattern or an isolation repair technique used to repair the memory. That is, the management module can directly send the hardware isolation repair technique used to repair the memory to the processor firmware, or it can send the memory fault characteristic pattern to the processor firmware, allowing the processor firmware to determine the hardware isolation repair technique to use based on the memory fault characteristic pattern. Optionally, the management module can also send the memory fault characteristic pattern and the isolation repair technique used to repair the memory to the processor firmware, so that the processor firmware can repair the faulty memory based on the isolation repair technique.

[0124] Optionally, the first fault repair request sent by the management module to the processor firmware may also include the address information of the faulty region. For example, taking the memory fault characteristic mode as Cell fault mode, the first fault repair request sent by the management module to the processor firmware may include not only the Cell fault mode but also the specific address information of the faulty Cell.

[0125] For example, the management module can send a first fault repair request to the processor firmware through the out-of-band management interface between the management module and the processor firmware. For instance, if the BMC determines that hardware isolation technology should be used to repair the faulty memory, the BMC can send a first fault repair request to the BIOS through the communication interface between the BMC and the BIOS, requesting the BIOS to repair the faulty memory.

[0126] S502, The processor firmware receives the first fault repair request from the management module.

[0127] For example, the BIOS can receive a first fault repair request from the BMC. Based on the fault characteristic pattern of the memory and / or the isolation repair technology used to repair the memory included in the first fault repair request, the BIOS can determine the current fault type of the memory and / or the isolation repair technology used to repair the memory. Optionally, based on the address information of the fault region also included in the first fault repair request, the BIOS can determine the location of the fault region.

[0128] For example, when the first fault repair request includes an isolation repair technique for repairing memory, step S506 continues to be executed after steps S501-S502. That is, the processor firmware can repair the memory based on the isolation repair technique sent by the management module.

[0129] For example, when the first fault repair request does not include the isolation repair technique used to repair the memory (e.g., the first fault repair request only includes the memory fault characteristic pattern), steps S503-S506 continue to be executed after steps S501-S502. That is, the processor firmware can determine the isolation repair technique used to repair the memory based on the memory fault characteristic pattern sent by the management module, and then repair the memory based on the isolation repair technique.

[0130] (Optional) S503, processor firmware determines the isolation repair technology used to repair memory.

[0131] In one implementation, the processor firmware determining the isolation repair technique to use for memory repair may include: the processor firmware determining which hardware isolation repair technique to use to repair the faulty memory based on the memory's fault characteristic mode. For example, if the memory's fault characteristic mode is a Bank fault mode, the processor firmware may determine to use Bank isolation replacement to repair the faulty memory. As another example, if the memory's fault characteristic mode is a Cell fault mode, the processor firmware may determine to use Cell isolation replacement to repair the faulty memory. That is, in this implementation, the processor firmware itself determines which isolation repair technique to use based on the memory's fault characteristic mode.

[0132] In another implementation, the processor firmware can also determine the isolation repair technology used to repair the aforementioned memory based on the first fault repair information table sent by the management module. This first fault repair information table indicates the fault characteristic mode and the corresponding one or more hardware isolation repair technologies. That is, by querying this first fault information table, the management module can determine the hardware isolation repair technologies that can be used for the fault characteristic mode.

[0133] For example, the fault characteristic patterns in the first fault repair information table may include one or more of the following: single-bit fault pattern, cell fault pattern, row fault pattern, column fault pattern, bank fault pattern, device fault pattern, rank fault pattern, channel fault pattern, dual in-line memory module (DIMM) fault pattern, small number of continuous errors fault pattern, and short-term sudden large number of errors fault pattern.

[0134] For example, different fault characteristic modes in the first fault repair information table mentioned above can employ the same hardware isolation repair technology. Different fault characteristic modes can also employ different hardware isolation repair technologies. This application embodiment does not limit the specific type of hardware isolation repair technology used for each fault characteristic mode.

[0135] For example, a fault characteristic mode in the first fault repair information table mentioned above can be repaired using one hardware isolation technology or multiple hardware isolation technologies.

[0136] Optionally, if the processor firmware queries the first fault repair information table and determines that the memory fault characteristic mode corresponds to multiple hardware isolation repair technologies, then the processor firmware can determine one hardware isolation repair technology from these multiple hardware isolation repair technologies.

[0137] Optionally, if the processor firmware determines the isolation repair technology corresponding to the memory fault characteristic mode based on the first fault repair information table sent by the management module, steps S504-S505 may be included before step S503.

[0138] (Optional) S504, The management module sends the first fault repair information table to the processor firmware.

[0139] Optionally, the first fault repair information table may be included in the first fault repair request.

[0140] (Optional) S505, Processor firmware receives the first fault repair information table.

[0141] It is understood that the embodiments of this application do not limit the execution order of steps S504-S505 with other steps. Figure 5 This is merely an illustrative example. For instance, steps S504-S505 may also be performed before step S501.

[0142] S506 processor firmware repairs memory based on isolation repair technology.

[0143] For example, the processor firmware can repair the memory based on the isolation repair technology sent by the management module, or it can repair the memory based on the isolation repair technology determined by the processor firmware in step S503.

[0144] For example, taking the Bank isolation replacement technique sent by the management module as an example, the BIOS can use the Bank isolation replacement technique to isolate the faulty Bank using underlying resources. As another example, taking the fault characteristic mode as Cell fault mode, and the Cell fault mode corresponding to the isolation replacement technique in the first fault repair information table as Cell isolation replacement, the BIOS can use the Cell isolation replacement technique to isolate the faulty Cell using underlying resources.

[0145] It is understandable that the memory fault handling method provided in this application embodiment, based on detailed memory error information and employing machine learning algorithms, accurately determines the memory fault characteristic patterns or the isolation repair technology used to repair the memory. Furthermore, when the management module determines to use hardware isolation repair of the memory, it notifies the processor firmware, enabling the processor firmware to utilize underlying resources to repair the faulty area using appropriate isolation replacement technology. Therefore, the accuracy of fault repair is high, reducing the probability of system downtime.

[0146] Optionally, embodiments of this application also provide a method for handling memory faults, such as... Figure 6 As shown, after steps S501-S506, steps S507-S508 may also be included. Figure 6 Steps S401-S403 are not shown in the diagram.

[0147] S507, the processor firmware sends the first fault repair response to the management module.

[0148] The first fault repair response carries the repair result after the processor firmware repaired the memory. For example, the first fault repair response carries the processor firmware repair result as successful, or the first fault repair response carries the processor firmware repair result as unsuccessful.

[0149] For example, when the processor firmware successfully repairs the memory using the isolation and repair technology corresponding to the memory's fault characteristic mode, the processor firmware sends a repair result to the management module indicating a successful repair. When the processor firmware fails to repair the memory using the isolation and repair technology corresponding to the memory's fault characteristic mode, the processor firmware sends a repair result to the management module indicating a failed repair.

[0150] Understandably, due to the limited underlying resources of the processor, when these resources are insufficient, the processor firmware may be unable to repair the memory, thus causing the processor firmware to fail to repair the memory.

[0151] S508, the management module receives the first fault repair response.

[0152] For example, the management module can determine whether the processor firmware repair was successful or failed based on the repair result carried in the first fault repair response. When the repair result carried in the first fault repair response is a failure, the management module can determine that the CPU's underlying resources are insufficient. The management module can then send a repair request to the OS management unit, requesting the OS management unit to use software isolation technology to repair the faulty memory.

[0153] For example, if the CPU's built-in underlying memory has insufficient redundancy for a single cell, but the current memory fault characteristic mode is a cell fault mode, the processor firmware cannot successfully repair the memory using cell isolation repair technology. The processor firmware sends the current repair result to the management module as a repair failure. After receiving the repair result sent by the processor firmware, the management module can send a fault request to the OS management unit, requesting the OS management to use software isolation technology for repair.

[0154] Optionally, the management module can also determine the severity of the memory fault based on the repair results carried in the first fault repair response, and issue an early warning when the memory fault severity is high.

[0155] It is understandable that the memory fault handling method provided in this application, based on detailed memory error information and employing machine learning algorithms, accurately determines the memory fault characteristic patterns or the isolation repair technology used to repair the memory. Furthermore, when the management module determines to use hardware isolation repair of the memory, it notifies the processor firmware, enabling the processor firmware to utilize underlying resources to repair the faulty area using appropriate isolation replacement technology. Therefore, the accuracy of fault repair is high, reducing the probability of system downtime. Moreover, after the processor firmware repairs the memory, it feeds back the repair results to the management module, further improving the success rate of fault repair.

[0156] This application also provides a memory fault handling method, involving the interaction between a management module and an OS management unit, such as... Figure 7 As shown, if step S403 determines that software isolation is used to repair the memory, the method may further include steps S701-S706 based on the above steps S401-S403. Figure 5 Steps S401-S403 are not shown in the diagram.

[0157] S701. If the management module determines that software isolation is used to repair the memory, the management module sends a second fault repair request to the OS management unit.

[0158] The second fault repair request is used to request the OS management unit to repair the memory. The second fault repair request includes either the memory fault characteristic pattern or at least one of the isolation repair techniques used to repair the memory. That is, the management module can directly send the software isolation repair technique used to repair the memory to the OS management unit, or it can send the memory fault characteristic pattern to the OS management unit, which then determines the software isolation repair technique based on the memory fault characteristic pattern. Optionally, the management module can also send the memory fault characteristic pattern and the isolation repair technique used to repair the memory to the OS management unit, so that the OS management unit can repair the faulty memory based on the isolation repair technique.

[0159] Optionally, the second fault repair request sent by the management module to the OS management unit may also include the address information of the faulty region. For example, taking the memory fault characteristic mode as the Page fault mode, the second fault repair request may include not only the Page fault mode but also the specific information of the faulty Page.

[0160] For example, the management module can send a second fault repair request to the OS management unit through the out-of-band management interface between the management module and the OS management unit. For instance, if the BMC determines that software isolation technology should be used to repair the faulty memory, the BMC can send a second fault repair request to the OS management unit through the communication interface between the BMC and the OS management unit, requesting the OS management unit to repair the faulty memory.

[0161] S702, the OS management unit receives a second fault repair request from the management module.

[0162] For example, the OS management unit can receive a second fault request from the BMC. Based on the fault characteristic pattern included in the second fault repair request, the OS management unit can determine the current memory fault type. As another example, based on the isolation repair technique used to repair the memory included in the second fault repair request, the OS management unit can determine which repair technique to use. Optionally, the OS management unit can also determine the specific location of the fault region based on the address information of the fault region included in the second fault repair request.

[0163] For example, when the second fault repair request includes an isolation repair technique used to repair the memory, step S706 continues to be executed after steps S701-S702. That is, the OS management unit can repair the memory based on the isolation repair technique sent by the management module.

[0164] For example, when the second fault repair request does not include the isolation repair technique used to repair the memory (e.g., the second fault repair request only includes the memory fault characteristic pattern), steps S703-S706 continue to be executed after steps S701-S702. That is, the OS management unit can determine the isolation repair technique used to repair the memory based on the memory fault characteristic pattern sent by the management module, and then repair the memory based on the isolation repair technique.

[0165] (Optional) The S703 and OS management unit determine the isolation repair technology used to repair the memory.

[0166] In one implementation, the OS management unit's determination of the isolation repair technique to use for memory repair may include: the OS management unit determining which software isolation repair technique to use to repair the faulty memory based on the memory's fault characteristic mode. That is, in this implementation, the OS management unit itself determines the specific isolation repair technique to use based on the memory's fault characteristic mode. For example, if the memory's fault characteristic mode is a page fault mode, the OS management unit may determine to use page isolation (page offline) to repair the faulty memory.

[0167] In another implementation, the OS management unit can also determine the isolation repair technology used to repair the aforementioned memory based on the second fault repair information table sent by the management module. This second fault repair information table indicates the fault characteristic mode and one or more software isolation repair technologies corresponding to that mode. That is, by querying this second fault information table, the OS management unit can determine the software isolation repair technologies that can be used for the fault characteristic mode.

[0168] For example, the fault characteristic patterns in the second fault repair information table may include one or more of the following: Page fault pattern, single-bit fault pattern, Cell fault pattern, Row fault pattern, column fault pattern, Bank fault pattern, Device fault pattern, Rank fault pattern, channel fault pattern, Dual In-line Memory Module (DIMM) fault pattern, a small number of continuous errors fault pattern, and a short-term sudden large number of errors fault pattern.

[0169] For example, different fault characteristic modes in the second fault repair information table mentioned above can employ the same software isolation repair technology. Different fault characteristic modes can also employ different software isolation repair technologies. This application embodiment does not limit the specific type of software isolation repair technology used for each fault characteristic mode.

[0170] For example, a fault characteristic mode in the second fault repair information table mentioned above can be repaired using one software isolation technology or multiple software isolation technologies.

[0171] Optionally, if the OS management unit queries the second fault repair information table and determines that the memory fault characteristic mode corresponds to multiple software isolation repair technologies, then the OS management unit can determine one software isolation repair technology from these multiple software isolation repair technologies.

[0172] Optionally, if the OS management unit determines the isolation repair technology corresponding to the memory fault characteristic mode based on the second fault repair information table sent by the management module, steps S704-S705 may be included before step S703.

[0173] (Optional) S704, The management module sends the second fault repair information table to the OS management unit.

[0174] Optionally, the second fault repair information table can be carried in the second fault repair request.

[0175] (Optional) The S705 OS management unit receives the second fault repair information table.

[0176] It is understood that the embodiments of this application do not limit the execution order of steps S704-S705 with other steps. Figure 7 This is merely an illustrative example. For instance, steps S704-S705 may also be performed before step S701.

[0177] The S706 OS management unit repairs memory based on isolation and repair technology.

[0178] For example, the OS management unit can repair the memory based on the isolation repair technology sent by the management module, or it can repair the memory based on the isolation repair technology determined by the OS management unit through step S703.

[0179] For example, taking the isolation and repair technology sent by the management module as Page isolation replacement, the OS management unit can use Page isolation replacement technology to isolate the faulty Page.

[0180] It is understandable that the memory fault handling method provided in this application embodiment, based on detailed memory error information and employing machine learning algorithms, accurately determines the memory fault characteristic patterns or the isolation repair technology used to repair the memory. Furthermore, when the management module determines to use software isolation repair for the memory, it notifies the OS management unit, enabling the OS management unit to use corresponding software isolation replacement technology to repair the faulty area. Therefore, the accuracy of fault repair is high, reducing the probability of system downtime.

[0181] Optionally, embodiments of this application also provide a method for handling memory faults, such as... Figure 8 As shown, after steps S701-S706, steps S707-S708 may also be included. Figure 8 Steps S401-S403 are not shown in the diagram.

[0182] S707, the OS management unit sends a second fault repair response to the management module.

[0183] The second fault repair response carries the repair result after the OS management unit repaired the memory. For example, the second fault repair response carries the result of the OS management unit successfully repairing the memory, or the second fault repair response carries the result of the OS management unit failing to repair the memory.

[0184] For example, when the OS management unit successfully repairs the memory using the isolation and repair technology corresponding to the memory's fault characteristic mode, the OS management unit sends a repair success message to the management module. When the OS management unit fails to repair the memory using the isolation and repair technology corresponding to the memory's fault characteristic mode, the OS management unit sends a repair failure message to the management module.

[0185] S708, the management module receives the second fault repair response.

[0186] For example, the management module can determine whether the OS management unit has successfully repaired or failed based on the repair result carried in the second fault repair response.

[0187] Optionally, the management module can determine the severity of the memory fault based on the repair result in the second fault repair response. For example, when the repair result carried in the second fault repair response is a repair failure, the management module can further determine the severity of the memory fault based on the repair result and issue an alert when the memory fault severity is high.

[0188] It is understandable that the memory fault handling method provided in this application embodiment, based on detailed memory error information and employing machine learning algorithms, accurately determines the memory fault characteristic patterns or the isolation repair technology used to repair the memory. Furthermore, when the management module determines to use software isolation repair for the memory, it notifies the OS management unit, enabling the OS management unit to use corresponding software isolation replacement technology to repair the faulty area. Therefore, the accuracy of fault repair is high, reducing the probability of system downtime.

[0189] For example, embodiments of this application also provide a method for handling memory faults, such as... Figure 9 As shown, after steps S501-S508, and / or after steps S701-S708, steps S901-S902 may also be included. Figure 9 Steps S501-S508 and S701-S708 are not shown in the diagram.

[0190] S901, the management module determines the severity of memory faults.

[0191] In one implementation, the management module determining the severity of a memory fault may include: the management module determining the severity of a memory fault based on memory error information and memory operating status data.

[0192] In another implementation, the management module determining the severity of the memory fault may include: the management module determining the severity of the memory fault based on at least one of a first fault repair response and a second fault repair response. That is, the management module can determine the severity of the memory fault based on the repair results fed back by the processor firmware and the repair results fed back by the OS management unit.

[0193] Optionally, the management module can also combine at least one of the following: memory error information, memory operating status data, first fault repair response, and second fault repair response to determine the severity of the memory fault.

[0194] S902. When the severity of a memory failure exceeds a preset threshold, the management module sends an alarm message to the upper-level operation and maintenance system.

[0195] The alarm message may include risk assessment results (e.g., risk level) and early warning information.

[0196] Optionally, the management module can also display alarm information to prompt users to replace memory modules in a timely manner to avoid the risk of system crashes.

[0197] Optionally, the management module can also predict faults and assess the risk of memory failure based on memory error information, memory operating status data, first fault repair response, and second fault repair response.

[0198] Understandably, the memory fault handling method provided in this application, based on detailed memory error information and employing machine learning algorithms, accurately identifies memory fault characteristic patterns. Furthermore, when the management module determines to use software isolation to repair the memory, it notifies the OS management unit, enabling the OS management unit to use appropriate software isolation replacement technology to repair the faulty area. Therefore, the accuracy of fault repair is high, reducing the probability of system crashes. Moreover, by assessing the severity of the memory fault, a memory warning message can be issued to the user when the memory fault severity is high, avoiding the risk of system crashes.

[0199] The foregoing mainly describes the solutions provided by the embodiments of the present invention from the perspective of method steps. It is understood that, in order to implement the above functions, a computer includes corresponding hardware structures and / or software modules for executing each function. Those skilled in the art should readily recognize that, in conjunction with the units and algorithm steps of the various examples described in the embodiments disclosed herein, this application can be implemented in a combination of hardware and computer software. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementations should not be considered beyond the scope of the present invention.

[0200] This application embodiment can divide the computer into functional modules according to the above method example. For example, each function can be divided into its own functional modules, or two or more functions can be integrated into one processing module. The integrated module can be implemented in hardware or as a software functional module. It should be noted that the module division in this embodiment is illustrative and only represents one logical functional division; other division methods may be used in actual implementation.

[0201] Figure 10 A schematic diagram of a memory fault handling device 1000 is shown. The memory fault handling device can be the management module in the above embodiments, or it can be a chip within the management module. The memory fault handling device 1000 can be used to implement the methods and functions of the management module involved in any of the above embodiments.

[0202] The memory fault handling device 1000 includes a processing unit 1001 and a transceiver unit 1002. For example, the transceiver unit 1002 can be used to support communication between the management module and the processor firmware, OS management unit, and upper-layer operation and maintenance system in the above embodiments. The processing unit 1001 is used to control and manage the actions of the management module and to execute the processing performed by the management module in the above embodiments. Optionally, if the memory fault handling device 1000 includes a storage unit, the processing unit 1001 can also execute programs or instructions stored in the memory, so that the memory fault handling device 1000 implements the methods and functions involved in any of the above embodiments.

[0203] For example, the processing unit 1001 described above can be used to perform, for example... Figure 4 Steps S401-S403, or, Figure 9 Steps S901-S902 in the document, and / or other processes used in the technology described herein. The transceiver unit 1002 can be used to perform, for example... Figure 5 Steps S501 and S504 in the process, or, Figure 6 Step S508, or, Figure 7 Steps S701 and S704 in the text, or, Figure 8 Step S708 in the above method embodiments, and / or other processes used in the technology described herein (e.g., the transceiver unit 1002 can also be used to receive operating status data from the memory detected by the sensor). All relevant content regarding each step in the above method embodiments can be referenced to the functional description of the corresponding functional module, and will not be repeated here.

[0204] For example, in hardware implementation, the functions of processing unit 1001 can be executed by a processor, and the functions of transceiver unit 1002 can be executed by a transceiver (transmitter / receiver) and / or communication interface. Processing unit 1001 can be embedded in or independent of the processor of memory fault handling device 1000 in hardware form, or it can be stored in the memory of memory fault handling device 1000 in software form, so that the processor can call and execute the operations corresponding to the above functional units.

[0205] Figure 11 A schematic diagram of a memory fault handling device 1100 is shown. The memory fault handling device can be the processor firmware mentioned above, or it can be a chip within the processor firmware. The memory fault handling device 1100 can be used to implement the methods and functions of the processor firmware involved in any of the above embodiments.

[0206] The memory fault handling device 1100 includes a processing unit 1101 and a transceiver unit 1102. For example, the transceiver unit 1102 can be used to support communication between the processor firmware and the management module in the above embodiments. The processing unit 1101 is used to control and manage the operations of the processor firmware and to execute the processing performed by the processor firmware in the above embodiments. Optionally, if the memory fault handling device 1100 includes a storage unit, the processing unit 1101 can also execute programs or instructions stored in the memory, so that the memory fault handling device 1100 implements the methods and functions involved in any of the above embodiments.

[0207] For example, the processing unit 1101 described above can be used to perform actions such as detecting memory error information, or... Figure 5 Steps S503 and S506, and / or other processes used in the technology described herein. Transceiver unit 1102 can be used to perform, for example, sending memory error information to the management module, or... Figure 5 Steps S502 and S505, or, Figure 6 Steps S502, S505, and S507, and / or other processes used in the technology described herein. All relevant content regarding each step in the above method embodiments can be referenced to the functional description of the corresponding functional module, and will not be repeated here.

[0208] For example, in hardware implementation, the function of processing unit 1101 can be executed by a processor, and the function of transceiver unit 1102 can be executed by a transceiver (transmitter / receiver) and / or communication interface. Processing unit 1101 can be embedded in or independent of the processor of memory fault handling device 1100 in hardware form, or it can be stored in the memory of memory fault handling device 1100 in software form, so that the processor can call and execute the operations corresponding to the above functional units.

[0209] Figure 12 A schematic diagram of a memory fault handling device 1200 is shown. This memory fault handling device can be the OS management unit mentioned above. The memory fault handling device 1200 can be used to implement the methods and functions of the OS management unit involved in any of the above embodiments.

[0210] The memory fault handling device 1200 includes a processing unit 1201 and a transceiver unit 1202. For example, the transceiver unit 1202 can be used to support communication between the OS management unit and the management module in the above embodiments. The processing unit 1201 is used to control and manage the actions of the OS management unit and to execute the processing performed by the OS management unit in the above embodiments. Optionally, if the memory fault handling device 1200 includes a storage unit, the processing unit 1201 can also execute programs or instructions stored in the memory, so that the memory fault handling device 1200 implements the methods and functions involved in any of the above embodiments.

[0211] For example, the processing unit 1201 described above can be used to perform, for example... Figure 7 Steps S703 and S706, and / or other processes used in the technology described herein. The transceiver unit 1202 can be used to perform, for example... Figure 7 Steps S702 and S705, or, Figure 8 Steps S702, S705, and S707, and / or other processes used in the technology described herein. All relevant content regarding each step in the above method embodiments can be referenced to the functional description of the corresponding functional module, and will not be repeated here.

[0212] For example, in hardware implementation, the functions of processing unit 1201 can be executed by a processor, and the functions of transceiver unit 1202 can be executed by a transceiver (transmitter / receiver) and / or communication interface. Processing unit 1201 can be embedded in or independent of the processor of memory fault handling device 1200 in hardware form, or it can be stored in the memory of memory fault handling device 1200 in software form, so that the processor can call and execute the operations corresponding to the above functional units.

[0213] This application embodiment also provides a memory fault handling device, which includes a processor and may further include a transceiver and a memory. The transceiver is used to send and receive information or to communicate with other communication devices; the memory is used to store computer-executed instructions; and the processor is used to execute the computer-executed instructions to support the implementation of the management module. Figures 4 to 9 Memory fault handling method in any embodiment.

[0214] This application also provides a computer-readable storage medium storing instructions that, when executed on a computer, enable the computer to perform... Figures 4 to 9 Memory fault handling method in any embodiment.

[0215] This application also provides a computer program product that, when run on a computer, causes the computer to perform... Figures 4 to 9 Memory fault handling method in any embodiment.

[0216] This application embodiment also provides a memory fault handling device, which can exist in the form of a chip product. The device includes a processor and an interface circuit. The processor is used to communicate with other devices through a receiving circuit, enabling the device to perform... Figures 4 to 9 Memory fault handling method in any embodiment.

[0217] This application also provides a memory fault handling system, including a management module and processor firmware, which can execute the above-described... Figure 5 or Figure 6 Methods for handling memory failures in [the context of the text].

[0218] This application also provides a memory fault handling system, including a management module and an OS management unit, which can perform the above-described... Figure 7 or Figure 8 Methods for handling memory failures in [the context of the text].

[0219] This application also provides a memory fault handling system, including a management module, processor firmware, and OS management unit, which can perform the above-described... Figures 4 to 9 Memory fault handling method in any embodiment.

[0220] The steps of the methods or algorithms described in this application can be implemented in hardware or by a processor executing software instructions. The software instructions can consist of corresponding software modules, which can be stored in random access memory (RAM), flash memory, erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), registers, hard disks, portable hard disks, CD-ROMs, or any other form of storage medium known in the art. An exemplary storage medium is coupled to a processor, enabling the processor to read information from and write information to the storage medium. Of course, the storage medium can also be a component of the processor. The processor and storage medium can reside in an ASIC. Alternatively, the ASIC can reside in a core network interface device. Of course, the processor and storage medium can also exist as discrete components in the core network interface device.

[0221] Those skilled in the art will recognize that, in one or more of the examples above, the functions described in this invention can be implemented using hardware, software, firmware, or any combination thereof. When implemented in software, these functions can be stored in a computer-readable medium or transmitted as one or more instructions or code on a computer-readable medium. Computer-readable media include computer-readable storage media and communication media, wherein communication media include any medium that facilitates the transfer of a computer program from one place to another. Storage media can be any available medium accessible to a general-purpose or special-purpose computer.

[0222] The specific embodiments described above further illustrate the purpose, technical solution, and beneficial effects of the present invention. It should be understood that the above description is only a specific embodiment of the present invention and is not intended to limit the scope of protection of the present invention. Any modifications, equivalent substitutions, improvements, etc., made on the basis of the technical solution of the present invention should be included within the scope of protection of the present invention.

Claims

1. A memory failure handling method, characterized by, The method includes: The management module obtains the memory error information, which includes at least one of the following: the status of correctable error (CE), the time of CE occurrence, the number of CE errors, the physical address information of CE; the status of uncorrectable error, the time of uncorrectable error occurrence, the number of uncorrectable errors, the physical address information of uncorrectable error, the number of memory inspection errors, the address of the row with memory inspection errors, the address of the column with memory inspection errors, and the address of the row with the most memory inspection errors. Based on the error information of the memory, the management module uses machine learning algorithms to determine the fault characteristic pattern of the memory or the isolation repair technology used to repair the memory; The management module determines whether to use hardware isolation or software isolation to repair the memory based on the memory's fault characteristic pattern or the isolation repair technology used to repair the memory.

2. The method of claim 1, wherein, The physical address information of the CE is used to indicate the physical location of the CE in the memory, and the physical address information of the uncorrectable error is used to indicate the physical location of the uncorrectable error in the memory.

3. The method according to claim 1 or 2, characterized in that, The fault characteristic modes include at least one of the following: Page fault mode, single bit fault mode, Cell fault mode, Row fault mode, Column fault mode, Bank fault mode, Device fault mode, Rank fault mode, Channel fault mode, Dual In-line Memory Module (DIMM) fault mode, Small number of continuous errors fault mode, and Short-term sudden large number of errors fault mode.

4. The method according to claim 1 or 2, characterized in that, The method further includes: The management module acquires memory operating status data; the memory operating status data includes at least one of the following: CPU utilization information, temperature information, running program information, and memory health status information.

5. The method according to claim 4, characterized in that, Based on the error information of the memory, the management module uses machine learning algorithms to determine the fault characteristic pattern of the memory or the isolation repair technology used to repair the memory, including: Based on the memory error information and the memory's operating status data, the management module uses machine learning algorithms to determine the memory's fault characteristic patterns or the isolation repair technology used to repair the memory.

6. The method according to claim 1, characterized in that, The method further includes: If the management module determines that hardware isolation is used to repair the memory, the management module sends a first fault repair request to the processor firmware. The first fault repair request is used to request the processor firmware to repair the memory. The first fault repair request includes at least one of the fault characteristic mode of the memory or the isolation repair technology used to repair the memory.

7. The method according to claim 6, characterized in that, The method further includes: The management module receives a first fault repair response from the processor firmware, the first fault repair response carrying the repair result after the processor firmware repairs the memory.

8. The method according to claim 1, characterized in that, The method further includes: The management module sends a first fault repair information table to the processor firmware. The first fault repair information table is used to indicate the fault characteristic mode and one or more hardware isolation repair technologies corresponding to the fault characteristic mode.

9. The method according to claim 8, characterized in that, The hardware isolation and repair technologies include at least one of the following: bit isolation replacement, cell isolation replacement, row isolation replacement, column isolation replacement, bank isolation replacement, device isolation replacement, rank isolation replacement, channel isolation replacement, single-particle data correction (SDDC), single-particle error correction (SDEC), adaptive dual-particle data correction - multi-region ADDDC-MR, adaptive data correction - single-region ADC-SR, adaptive dual-particle error correction (ADDEC), partial cache data replacement (PCLS), adaptive cache row replacement (ACLS), hardware row replacement (hPPR), software row replacement (sPPR), row replacement (PPR), or hardware isolation and repair technologies that replace a specific address range of memory.

10. The method according to any one of claims 6-9, characterized in that, The processor firmware includes firmware, basic input / output system BIOS, management engine ME, or intelligent management unit IMU.

11. The method according to claim 1, 2, or 5, characterized in that, The method further includes: If the management module determines that software isolation is used to repair the memory, the management module sends a second fault repair request to the operating system (OS) management unit. The second fault repair request is used to request the OS management unit to repair the memory. The second fault repair request includes at least one of the fault characteristic mode of the memory or the isolation repair technology used to repair the memory.

12. The method according to claim 11, characterized in that, The method further includes: The management module receives a second fault repair response from the OS management unit, the second fault repair response carrying the repair result after the OS management unit repaired the memory.

13. The method according to claim 1, characterized in that, The method further includes: The management module sends a second fault repair information table to the OS management unit. The second fault repair information table is used to indicate the fault characteristic mode and one or more software isolation repair technologies corresponding to the fault characteristic mode.

14. The method according to claim 13, characterized in that, The software isolation and repair technology includes at least one of page isolation, address isolation, process isolation, or software isolation and repair technology that replaces a specific range of memory addresses.

15. The method according to any one of claims 12-14, characterized in that, The OS management unit is either the system management unit that comes with the OS or a device management agent program installed in the OS.

16. The method according to claim 1 or 2, characterized in that, Based on the error information of the memory, the management module uses machine learning algorithms to determine the fault characteristic patterns of the memory, including: The management module uses machine learning algorithms to determine the fault characteristic patterns of the memory based on the error information of the memory and the fault prediction model; the fault prediction model is used to predict the fault characteristic patterns of the memory.

17. The method according to claim 1 or 2, characterized in that, The method further includes: The management module determines the severity of the memory failure; If the severity of the memory failure exceeds a preset threshold, the management module sends an alarm message to the upper-level operation and maintenance system.

18. The method according to claim 17, characterized in that, The management module determines the severity of the memory fault, including: The management module determines the severity of the memory fault based on at least one of a first fault repair response and a second fault repair response.

19. The method according to claim 17, characterized in that, The management module determines the severity of the memory fault, including: The management module determines the severity of the memory failure based on the memory's error information and operating status data.

20. The method according to claim 1 or 2, characterized in that, The management module is a management unit for non-business modules. The management module includes a management unit for running status, a management unit built into the processor, a management system in a management chip outside the processor, a server motherboard management control unit (BMC), a system management module (SMM), or a device management system in the OS.

21. A memory fault handling method, characterized in that, The method includes: The processor firmware sends memory error information to the management module. The memory error information includes at least one of the following: the status of correctable error (CE), the time of CE occurrence, the number of CE errors, the physical address information of CE; the status of uncorrectable error, the time of uncorrectable error occurrence, the number of uncorrectable errors, the physical address information of uncorrectable errors, the number of memory inspection errors, the address of the row with memory inspection errors, the address of the column with memory inspection errors, and the address of the row with the most memory inspection errors. The processor firmware receives a first fault repair request from the management module. The first fault repair request is used to request the processor firmware to repair the memory. The first fault repair request includes at least one of the fault characteristic mode of the memory or the isolation repair technology used to repair the memory. The fault characteristic mode or the isolation repair technology used to repair the memory is determined by a machine learning algorithm based on the error information of the memory. The processor firmware repairs the memory based on the isolation and repair technology.

22. The method according to claim 21, characterized in that, The physical address information of the CE is used to indicate the physical location of the CE in the memory, and the physical address information of the uncorrectable error is used to indicate the physical location of the uncorrectable error in the memory.

23. The method according to claim 21 or 22, characterized in that, The fault characteristic modes include at least one of the following: single-bit fault mode, cell fault mode, row fault mode, column fault mode, bank fault mode, device fault mode, rank fault mode, channel fault mode, dual in-line memory module (DIMM) fault mode, small number of continuous errors fault mode, and short-term sudden large number of errors fault mode.

24. The method according to claim 21 or 22, characterized in that, The method further includes: The processor firmware sends a first fault repair response to the management module, the first fault repair response carrying the repair result after the processor firmware repairs the memory.

25. The method according to claim 21, characterized in that, The method further includes: The processor firmware receives a first fault repair information table from the management module. The first fault repair information table is used to indicate fault characteristic patterns and one or more hardware isolation repair technologies corresponding to the fault characteristic patterns.

26. The method according to claim 25, characterized in that, The hardware isolation and repair technologies include at least one of the following: bit isolation replacement, cell isolation replacement, row isolation replacement, column isolation replacement, bank isolation replacement, device isolation replacement, rank isolation replacement, channel isolation replacement, single-particle data correction (SDDC), single-particle error correction (SDEC), adaptive dual-particle data correction - multi-region ADDDC-MR, adaptive data correction - single-region ADC-SR, adaptive dual-particle error correction (ADDEC), partial cache data replacement (PCLS), adaptive cache row replacement (ACLS), hardware row replacement (hPPR), software row replacement (sPPR), row replacement (PPR), or hardware isolation and repair technologies that replace a specific address range of memory.

27. The method according to claim 25 or 26, characterized in that, The method further includes: The processor firmware determines the isolation repair technology to be used to repair the memory based on the fault characteristic patterns of the memory and the first fault repair information table.

28. The method according to claim 21 or 22, characterized in that, The processor firmware includes firmware, basic input / output system BIOS, management engine ME, or intelligent management unit IMU.

29. The method according to claim 21 or 22, characterized in that, The management module is a management unit for non-business modules. The management module includes a management unit for running status, a management unit built into the processor, a management system in a management chip outside the processor, a server motherboard management control unit (BMC), a system management module (SMM), or a device management system in the OS.

30. A memory fault handling method, characterized in that, The method includes: The operating system (OS) management unit receives a second fault repair request from the management module. The second fault repair request is used to request the OS management unit to repair the memory. The second fault repair request includes at least one of the fault characteristic mode of the memory or the isolation repair technology used to repair the memory. The fault characteristic mode or the isolation repair technology used to repair the memory is determined by a machine learning algorithm based on the memory error information. The memory error information includes at least one of the following: the status of correctable error (CE), CE occurrence time, CE error count, CE physical address information; the status of uncorrectable error, uncorrectable error occurrence time, uncorrectable error count, uncorrectable error physical address information; memory inspection error count; memory inspection error row address; memory inspection error column address; and memory inspection error maximum row address. The OS management unit repairs the memory based on the isolation and repair technology.

31. The method according to claim 30, characterized in that, The fault characteristic modes include at least one of the following: Page fault mode, single bit fault mode, Cell fault mode, Row fault mode, Column fault mode, Bank fault mode, Device fault mode, Rank fault mode, Channel fault mode, Dual In-line Memory Module (DIMM) fault mode, Small number of continuous errors fault mode, and Short-term sudden large number of errors fault mode.

32. The method according to claim 30 or 31, characterized in that, The method further includes: The OS management unit sends a second fault repair response to the management module, the second fault repair response carrying the repair result after the OS management unit repairs the memory.

33. The method according to claim 30, characterized in that, The method further includes: The OS management unit receives a second fault repair information table from the management module. The second fault repair information table is used to indicate fault characteristic patterns and one or more software isolation repair technologies corresponding to the fault characteristic patterns.

34. The method according to claim 33, characterized in that, The software isolation and repair technology includes at least one of page isolation, address isolation, process isolation, or software isolation and repair technology that replaces a specific range of memory addresses.

35. The method according to claim 33 or 34, characterized in that, The method further includes: The OS management unit determines the isolation repair technology to be used to repair the memory based on the fault characteristic patterns of the memory and the second fault repair information table.

36. The method according to claim 30 or 31, characterized in that, The OS management unit is either the system management unit that comes with the OS or a device management agent program installed in the OS.

37. The method according to claim 30 or 31, characterized in that, The management module is a management unit for non-business modules. The management module includes a management unit for running status, a management unit built into the processor, a management system in a management chip outside the processor, a server motherboard management control unit (BMC), a system management module (SMM), or a device management system in the OS.

38. A memory fault handling device, characterized in that, The apparatus includes a unit or means for performing the memory fault handling method as described in any one of claims 1-20.

39. A memory fault handling device, characterized in that, The apparatus includes a unit or means for performing the memory fault handling method as described in any one of claims 21-29.

40. A memory fault handling device, characterized in that, The apparatus includes a unit or means for performing the memory fault handling method as described in any one of claims 30-37.

41. A memory fault handling system, characterized in that, The system includes a management module, processor firmware, and an OS management unit. The management module is used to execute the memory fault handling method as described in any one of claims 1-20. The processor firmware is used to execute the memory fault handling method as described in any one of claims 21-29. The OS management unit is used to execute the memory fault handling method as described in any one of claims 30-37.

42. A computer-readable storage medium having computer program code therein, characterized in that, When the computer program code is run on the processor, it causes the processor to perform the memory fault handling method as described in any one of claims 1-37.

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