A computer

Abstract

The present application relates to storage technology, and in particular, to a computer comprising: a processor and an open-channel storage device; the processor adds a first-class address to a cache unit of a memory space of the open-channel storage device, the first-class address being the physical address of the storage device, the memory space being provided by the open-channel storage device; the processor generates an IO command by replacing a second-class address indicated by an IO command with an index of the cache unit, the second-class address being a logical address; the IO command is sent to the open-channel storage device; the open-channel storage device receives the IO command, obtains the first-class address from the cache unit according to the cache unit index in the IO command, and accesses a non-volatile memory (NVM) according to the first-class address. The present application provides a method, a host, and a storage device for accessing a storage device using a physical address without modifying the operating system kernel, thereby enabling applications to obtain the advantages provided by open-channel solid-state storage devices while avoiding the risks introduced by kernel modifications.

Description

Technical Field

[0001] The present application relates to storage technology, and in particular, to a computer comprising a controller memory buffer (CMB) for providing an open channel storage device. Background Art

[0002] Figure 1 is a block diagram of a storage device in the prior art. Storage device 102 is coupled to a host to provide storage capabilities for the host. The host and storage device 102 can be coupled in various ways, including but not limited to connecting the host and storage device 102 via, for example, SATA (Serial Advanced Technology Attachment), SCSI (Small Computer System Interface), SAS (Serial Attached SCSI), IDE (Integrated Drive Electronics), USB (Universal Serial Bus), PCIE (Peripheral Component Interconnect Express, PCIe), NVMe (NVM Express), Ethernet, Fibre Channel, wireless communication networks, and the like. The host can be an information processing device capable of communicating with the storage device via the aforementioned methods, such as a personal computer, tablet computer, server, portable computer, network switch, router, cellular phone, personal digital assistant, and the like. The storage device 102 includes an interface 103 , a control component 104 , one or more NVM chips 105 , and a DRAM (Dynamic Random Access Memory) 110 .

[0003] NAND flash memory, phase change memory, FeRAM (Ferroelectric RAM), MRAM (Magnetic Random Access Memory), RRAM (Resistive Random Access Memory), XPoint memory, etc. are common NVMs.

[0004] The interface 103 may be adapted to exchange data with the host via, for example, SATA, IDE, USB, PCIE, NVMe, SAS, Ethernet, Fibre Channel, or the like.

[0005] The control component 104 is used to control data transmission between the interface 103, the NVM chip 105 and the DRAM 110, and is also used for storage management, mapping of host logical addresses to flash physical addresses, erase leveling, bad block management, etc. The control component 104 can be implemented in a variety of ways such as software, hardware, firmware or a combination thereof. For example, the control component 104 can be in the form of an FPGA (Field-programmable gate array), an ASIC (Application Specific Integrated Circuit) or a combination thereof. The control component 104 can also include a processor or a controller, in which software is executed to manipulate the hardware of the control component 104 to process IO (Input / Output) commands. The control component 104 can also be coupled to the DRAM 110 and can access data in the DRAM 110. The FTL table and / or cached IO command data can be stored in the DRAM.

[0006] The control unit 104 includes a flash memory interface controller (also known as a media interface controller or a flash memory lane controller). The flash memory interface controller is coupled to the NVM chip 105 and issues commands to the NVM chip 105 in accordance with the interface protocol of the NVM chip 105 to operate the NVM chip 105, and receives command execution results output from the NVM chip 105. Known NVM chip interface protocols include "Toggle" and "ONFI".

[0007] In some storage devices, a Flash Translation Layer (FTL) is used to maintain mapping information from logical addresses to physical addresses. Logical addresses constitute the storage space of the storage device as perceived by a host accessing the storage device. Physical addresses are addresses used to access the physical storage units of the storage device. In related technologies, address mapping can also be implemented using intermediate address forms. For example, logical addresses are mapped to intermediate addresses, and then the intermediate addresses are further mapped to physical addresses. In these cases, the read / write commands received by the storage device indicate the logical address. The table structure that stores the mapping information from logical addresses to physical addresses is called an FTL table.

[0008] In some storage devices, the FTL is provided by the host coupled to the storage device. The host's memory stores the FTL table, and the host's CPU executes software to provide the FTL. In other cases, the FTL is provided by a storage management device located between the host and the storage device. In these cases, the physical address constitutes the storage space of the storage device as perceived by the host accessing the storage device, and the read / write commands received by the storage device indicate the physical address.

[0009] According to the NVMe protocol, the host uses a logical address to access the storage device, and the storage address space provided by the storage device to the host is a logical address space composed of logical addresses.

[0010] In recent years, open-channel solid-state drives (OSSDs) have also been introduced. The "Open-Channel Solid State Drives Specification" is available at http: / / lightnvm.io / docs / OCSSD-2_0-20180129.pdf, the entire text of which is incorporated herein by reference. The OCSSD specification provides extensions to the NVMe protocol. According to the OCSSD specification, a host accesses a storage device using physical addresses, and the storage address space provided to the host by the storage device is an address space consisting of physical addresses.

[0011] To implement the Open Channel Solid-State Storage Device Specification, the storage device must support the IO commands defined in the Open Channel Solid-State Storage Device Specification, and a driver must be added to the host's operating system kernel (for example, the LightNVM subsystem available from https: / / openchannelssd.readthedocs.io / en / latest / ).

[0012] Figure 2 is a schematic diagram of a solid-state storage device using an open channel in the prior art.

[0013] The host is coupled to an open-channel solid-state storage device. The host's operating system installs the NVMe device driver and the LightNVM subsystem. The host's user space runs an application. The application accesses the storage device (open-channel SSD). The NVMe device driver runs in the operating system kernel to access the NVMe storage device and is available at https: / / nvmexpress.org / resources / drivers / . The LightNVM subsystem runs in the kernel to access the open-channel SSD.

[0014] As an example, an application uses a logical address to access a storage device. The FTL running on the host converts the logical address into a physical address and provides it to the LightNVM subsystem. The LightNVM subsystem generates an IO command that complies with the "Open Channel Solid-State Storage Device Specification" through the NVMe device driver and provides it to the open channel SSD. The open channel SSD executes the IO command. The IO command indicates, for example, the host memory address, the physical address of the storage device, and the length of the data to be accessed by the IO command. Optionally, the IO command also indicates metadata generated by the storage device and additionally written to the non-volatile storage medium, for example in the NVMe protocol. Metadata includes, for example, the logical address associated with the stored data, verification information used to protect the data, etc.

[0015] As yet another example, an application provides the LightNVM subsystem with a physical address to access a storage device. Summary of the Invention

[0016] NVMe device drivers are generally considered mature and widely validated. However, using open-channel solid-state storage devices requires adding the LightNVM subsystem or a driver that provides similar functionality to the kernel, or using a newer operating system kernel version that includes the LightNVM subsystem. Modifying or updating the operating system kernel carries risks, and data centers, internet service providers, and other organizations are reluctant to take the risk of kernel modifications.

[0017] When using an open-channel solid-state storage device, the host is aware of the device's non-volatile storage media characteristics, such as the need to perform an erase operation before writing data to the storage medium. However, existing operating systems only provide read (read(), pread()) and write (write(), pwrite()) system calls for accessing storage devices. Therefore, without an operating system kernel update, user-space applications lack sufficient capabilities to operate open-channel solid-state storage devices.

[0018] According to an embodiment of the present application, a method, a host, and a storage device are provided for accessing a storage device using a physical address without modifying the operating system kernel, thereby enabling applications to obtain the advantages provided by open-channel solid-state storage devices while avoiding the risks introduced by modifying the kernel.

[0019] According to a first aspect of the present application, a first storage device according to the first aspect of the present application is provided, comprising: a command interface, a control component and an NVM; the storage device provides storage space and memory space to a host; a cache unit of the memory space stores a first-class address; the control component receives an IO command indicating a cache unit index through the command interface, and obtains the first-class address from the cache unit according to the cache unit index in the IO command, and accesses the NVM according to the first-class address.

[0020] According to the first storage device of the first aspect of the present application, a second storage device according to the first aspect of the present application is provided, wherein the cache unit index indicated by the IO command is a substitute for the second type address of the IO command.

[0021] According to the first or second storage device of the first aspect of the present application, a third storage device according to the first aspect of the present application is provided, wherein the first type of address is a physical address of the NVM of the index storage device, and the second type of address is a logical address that indexes the storage space.

[0022] According to one of the first to third storage devices of the first aspect of the present application, a fourth storage device according to the first aspect of the present application is provided, wherein, if the IO command indicates a second-class address for the storage device, the control component converts the second-class address into a first-class address according to a flash translation layer (FTL), and accesses the NVM according to the first-class address.

[0023] According to one of the first to third storage devices of the first aspect of the present application, there is provided a fifth storage device according to the first aspect of the present application, wherein if the IO command indicates a first type address for the storage device, the control component accesses the NVM according to the first type address.

[0024] According to one of the first to third storage devices of the first aspect of the present application, a sixth storage device according to the first aspect of the present application is provided, wherein, if an IO command indicates a keyword for a KV storage device for the storage device, the control component converts the keyword into a first-class address according to a flash translation layer (FTL) and accesses the NVM according to the first-class address.

[0025] According to one of the first to sixth storage devices of the first aspect of the present application, a seventh storage device according to the first aspect of the present application is provided, wherein the memory space provided by the storage device to the host is a controller memory buffer defined according to the NVMe protocol or a memory space defined according to the PCIe protocol.

[0026] According to the seventh storage device of the first aspect of the present application, there is provided an eighth storage device according to the first aspect of the present application, wherein the controller memory buffer is a non-volatile storage space.

[0027] According to one of the first to eighth storage devices of the first aspect of the present application, a ninth storage device according to the first aspect of the present application is provided, wherein the first type of address is a physical address that complies with the Open Channel Solid-State Storage Device Specification.

[0028] According to the ninth storage device of the first aspect of the present application, there is provided a tenth storage device according to the first aspect of the present application, wherein the IO command is generated by operating a storage device driver using pread() / pwrite() system calls.

[0029] According to the tenth storage device of the first aspect of the present application, an eleventh storage device according to the first aspect of the present application is provided, wherein, when using the pread() / pwrite() system call, the address parameter "__offset" is set to the cache unit index, and the storage device driver uses the address parameter "__offset" to generate a second type address of the IO command.

[0030] According to the tenth or eleventh storage device of the first aspect of the present application, there is provided a twelfth storage device according to the first aspect of the present application, wherein, if the IO command is a read command, the read command is generated by calling a Pread() system call.

[0031] According to one of the tenth to twelfth storage devices of the first aspect of the present application, a thirteenth storage device according to the first aspect of the present application is provided, wherein, if the IO command is a write command, the write command is generated by the storage device driver by calling the Pwead() system call.

[0032] According to one of the first to thirteenth storage devices of the first aspect of the present application, a fourteenth storage device according to the first aspect of the present application is provided, wherein the first type of address associated with the IO command is written into the cache unit corresponding to the cache unit index used to generate the IO command.

[0033] According to one of the first to fourteenth storage devices of the first aspect of the present application, a fifteenth storage device according to the first aspect of the present application is provided, wherein the control component generates a completion command in response to completion of IO command processing, and the completion command contains a cache unit index indicated by the corresponding IO command, so that the host releases the cache unit according to the cache unit index contained in the completion command.

[0034] According to one of the first to fourteenth storage devices of the first aspect of the present application, a sixteenth storage device according to the first aspect of the present application is provided, wherein, in response to a failure in IO command processing, the control component writes error information corresponding to the IO command into the cache unit indicated by the IO command, so that the host obtains the error information from the cache unit after knowing the failed processing result.

[0035] According to the fifteenth storage device of the first aspect of the present application, a seventeenth storage device according to the first aspect of the present application is provided, wherein the completion command is a command that complies with the NVMe specification.

[0036] According to one of the first to seventeenth storage devices of the first aspect of the present application, there is provided an eighteenth storage device according to the first aspect of the present application, wherein the cache unit further stores metadata associated with the IO command.

[0037] According to the eighteenth storage device of the first aspect of the present application, a nineteenth storage device according to the first aspect of the present application is provided, wherein the metadata associated with the IO command records the second type of address of the data accessed by the IO command and / or verification information of the data.

[0038] According to one of the first to nineteenth storage devices of the first aspect of the present application, a twentieth storage device according to the first aspect of the present application is provided, wherein the cache unit also stores extended information associated with the IO command, and the control unit obtains the extended information from the cache unit according to the cache unit index in the IO command, and knows the extended meaning of the IO command according to the extended information.

[0039] According to the twentieth storage device of the first aspect of the present application, there is provided a twenty-first storage device according to the first aspect of the present application, wherein the extended information is extended information representing an erase command.

[0040] According to the twentieth storage device of the first aspect of the present application, a twenty-second storage device according to the first aspect of the present application is provided, wherein the extended information is extended information representing the timing of providing a completion command corresponding to the IO command to the host, and the control unit provides the completion command to the host according to the timing indicated by the command.

[0041] According to the twenty-second storage device of the first aspect of the present application, there is provided a twenty-third storage device according to the first aspect of the present application, wherein the timing for providing the completion command to the host is to provide the completion command corresponding to the write command to the host immediately after the data to be written by the write command is moved to the cache unit, or to provide the completion command corresponding to the write command to the host after the data to be written by the write command is stored in the NVM.

[0042] According to the second aspect of the present application, a first method for accessing a storage device according to the second aspect of the present application is provided, comprising the following steps: adding a first type of address to a cache unit of a memory space of the storage device, wherein the memory space is a memory space provided by the storage device and accessible to the host; replacing the second type of address indicated by the IO command with an index of the cache unit to generate an IO command; and sending the IO command to the storage device.

[0043] According to the first method for accessing a storage device according to the second aspect of the present application, a second method for accessing a storage device according to the second aspect of the present application is provided, wherein the first type of address is the physical address of the NVM of the index storage device, and the second type of address is the logical address of the storage space of the index storage device.

[0044] According to the first or second method of accessing a storage device according to the second aspect of the present application, a third method of accessing a storage device according to the second aspect of the present application is provided, wherein the first type of address is a physical address that complies with the open channel solid-state storage device specification.

[0045] According to one of the first to third methods of accessing a storage device according to the second aspect of the present application, a fourth method of accessing a storage device according to the second aspect of the present application is provided, wherein the pread() / pwrite() system call is used to operate the storage device driver to generate IO commands.

[0046] According to the fourth method for accessing a storage device according to the second aspect of the present application, a fifth method for accessing a storage device according to the second aspect of the present application is provided, wherein, when using the pread() / pwrite() system call, the address parameter "__offset" is set to the cache unit index, and the storage device driver uses the address parameter "__offset" to generate an IO command.

[0047] According to one of the first to fifth methods of accessing a storage device according to the second aspect of the present application, a sixth method of accessing a storage device according to the second aspect of the present application is provided, wherein the first type of address is written to the cache unit of the storage device in a manner of accessing the host memory.

[0048] According to one of the first to sixth methods of accessing a storage device according to the second aspect of the present application, a seventh method of accessing a storage device according to the second aspect of the present application is provided, wherein a first-class address is generated based on the logical address of the storage space of the accessed storage device, or a URI or keyword is converted into a first-class address to store the first-class address in a cache unit of the storage device.

[0049] According to one of the first to seventh methods of accessing a storage device according to the second aspect of the present application, an eighth method of accessing a storage device according to the second aspect of the present application is provided, wherein the first type address is obtained by querying the FTL table according to the logical address of the accessed storage space.

[0050] According to one of the first to eighth methods of accessing a storage device according to the second aspect of the present application, a ninth method of accessing a storage device according to the second aspect of the present application is provided, wherein, in response to completion of IO command processing, the cache unit indicated by the IO command is released according to the completion command generated by the storage device for the IO command.

[0051] According to the ninth method for accessing a storage device according to the second aspect of the present application, a tenth method for accessing a storage device according to the second aspect of the present application is provided, wherein, according to the cache unit index contained in the completion command, the cache unit indicated by the cache unit index is released.

[0052] According to the ninth method for accessing a storage device according to the second aspect of the present application, an eleventh method for accessing a storage device according to the second aspect of the present application is provided, wherein, in response to obtaining a completion command, the cache unit is released according to the correspondence between the IO command sent to the storage device and the cache unit index used to generate the IO command.

[0053] According to one of the first to eighth methods of accessing a storage device according to the second aspect of the present application, a twelfth method of accessing a storage device according to the second aspect of the present application is provided, wherein, in response to a failure in IO command processing, error information corresponding to the IO command is obtained from a cache unit of the storage device.

[0054] According to one of the first to twelfth methods of accessing a storage device according to the second aspect of the present application, a thirteenth method of accessing a storage device according to the second aspect of the present application is provided, wherein, in response to adding a first-class address to a cache unit, metadata associated with the IO command is also added to the cache unit.

[0055] According to the thirteenth method for accessing a storage device according to the second aspect of the present application, a fourteenth method for accessing a storage device according to the second aspect of the present application is provided, wherein the metadata associated with the IO command records the second type address of the data accessed by the IO command and / or the verification information of the data accessed by the IO command.

[0056] According to one of the first to fourteenth methods of accessing a storage device according to the second aspect of the present application, a fifteenth method of accessing a storage device according to the second aspect of the present application is provided, wherein, in response to adding a first-class address to a cache unit, extended information associated with the IO command is also added to the cache unit, so that the storage device knows the extended meaning of the IO command based on the extended information.

[0057] According to the fifteenth method for accessing a storage device according to the second aspect of the present application, there is provided a sixteenth method for accessing a storage device according to the second aspect of the present application, wherein the extended information is extended information representing an erase command.

[0058] According to the fifteenth method of accessing a storage device according to the second aspect of the present application, a seventeenth method of accessing a storage device according to the second aspect of the present application is provided, wherein the extended information is extended information representing the timing at which the storage device provides a completion command corresponding to the IO command to the host.

[0059] According to the fifteenth method for accessing a storage device according to the second aspect of the present application, there is provided an eighteenth method for accessing a storage device according to the second aspect of the present application, wherein the timing at which the storage device provides a completion command to the host is immediately after moving the data to be written by the write command to the cache unit and providing the host with a completion command corresponding to the write command, or after storing the data to be written by the write command in the NVM and providing the host with a completion command corresponding to the write command.

[0060] According to a third aspect of the present application, a first computer according to the third aspect of the present application is provided, comprising: a processor and a storage device, wherein the processor executes one of the above-described methods. BRIEF DESCRIPTION OF THE DRAWINGS

[0061] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments recorded in this application. For ordinary technicians in this field, other drawings can also be obtained based on these drawings.

[0062] Figure 1 is a block diagram of a storage device in the prior art;

[0063] Figure 2 is a schematic diagram of a prior art open channel solid-state storage device;

[0064] Figure 3 is a schematic diagram of operating a storage device according to an embodiment of the present application;

[0065] Figure 4 is a schematic diagram of operating a storage device according to another embodiment of the present application;

[0066] Figure 5 is a schematic diagram of operating a storage device according to yet another embodiment of the present application. DETAILED DESCRIPTION

[0067] The following is a clear and complete description of the technical solutions in the embodiments of the present application in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without making creative efforts are within the scope of protection of this application.

[0068] Figure 3 is a schematic diagram of operating a storage device according to an embodiment of the present application.

[0069] A storage device, such as a solid-state drive (SSD), is coupled to a host. The SSD provides the host with an NVMe command interface and a CMB (Controller Memory Buffer). The NVMe command interface includes multiple command queues. The host provides the SSD with IO commands according to embodiments of the present application via the NVMe command interface and the CMB.

[0070] The IO command of the NVMe protocol indicates the logical address of the storage device. The IO command for accessing the open channel solid-state storage device indicates the physical address that complies with the open channel solid-state storage device specification. It should be pointed out that in the "Open-Channel Solid State Drives Specification Version 2.0 (Open Channel Solid State Storage Device Specification 2.0)" version released on January 29, 2018, "Logical Block Addresses (LBA)" is used to represent the address in the IO command provided to the open channel storage device, and its meaning is consistent with the "logical address" in the embodiment of this application. For the purpose of clarity, in this application, unless otherwise stated, the meaning of "logical address" or "LBA" is consistent with the logical address of the NVMe protocol, and the meaning of "physical address", "PPA" or "PBA" is consistent with the address used to access the storage device in the IO command that complies with the open channel solid-state storage device specification, or represents the address of the addressable physical storage unit of the non-volatile storage medium of the storage device.

[0071] According to the embodiment of the present application, the IO command indicates the CMB index. The CMB indexes the cache unit in the CMB, and the cache unit in the CMB stores the physical address of the SSD used by the IO command to access the SSD. Optionally, metadata and extended information associated with the IO command are also stored in the cache unit of the CMB. The metadata associated with the IO command records, for example, the logical address of the data accessed by the IO command and / or the verification information of the data. The extended information associated with the IO command records, for example, an extended opcode, which is used to indicate the extended meaning of the IO command. For example, when an erase command is indicated by an extended opcode, or when the host receives a completion command indicating that the write command has been processed, whether the data corresponding to the write command is written to the cache of the storage device or to the non-volatile storage medium.

[0072] Optionally, according to the IO commands of the embodiments of the present application, the IO commands of the NVMe protocol are used, and the part indicating the logical address in the IO commands of the NVMe protocol is replaced with the part indicating the CMB index without changing other structures of the IO commands of the NVMe protocol. Thus, by replacing the logical address provided to the NVMe device driver with the CMB index, the NVMe device driver can be used to generate the IO commands according to the embodiments of the present application.

[0073] The CMB is a host-accessible memory space provided by a storage device, as defined in the NVMe protocol. Alternatively, the CMB can be, for example, non-volatile. Still optionally, the CMB in the storage device according to embodiments of the present application can be replaced by a host-accessible memory space provided by the storage device, as defined in another protocol (e.g., the PCIe protocol).

[0074] The NVMe device driver runs in the kernel space of the host operating system. Applications run in the user space of the host. Applications access storage devices through existing technologies such as files.

[0075] The user space also runs an IO command management unit for generating IO commands according to embodiments of the present application based on application accesses to, for example, files. For example, the IO command management unit also includes an FTL table to generate a physical address for the SSD based on the storage space address accessed by the application. Alternatively, if the application accesses the storage space using, for example, a URI (Universal Resource Identifier) ​​or a keyword, the IO command management unit converts the URI or keyword into a physical address for the SSD.

[0076] To generate an IO command, the IO command management unit allocates available cache units from the CMB. From the host's perspective, the CMB is accessible memory space. According to an embodiment of the present application, the IO command management unit is responsible for allocating, using, and releasing cache units in the CMB.

[0077] The IO command management unit fills the physical address for the SSD generated for the IO command into the cache unit of the allocated CMB (whose index is CMBID).

[0078] The IO command management unit uses the NVMe device driver in the kernel to generate NVMe commands. To generate NVMe commands, the IO command management unit replaces the logical address of the storage space that should be provided to the NVMe device driver with the index of the cache unit (CMB ID) filled with the physical address of the SSD to be accessed by the IO command.

[0079] The NVMe device driver generates an NVMe command carrying the cache unit index of the CMB and provides it to the SSD through the NVMe command interface of the SSD.

[0080] The control component of the SSD obtains the IO command from the NVMe command interface, accesses the CMB according to the cache unit index of the CMB indicated by the IO command, obtains the physical address from the CMB cache unit, and accesses the non-volatile storage medium of the SSD according to the physical address. If the IO command is a read command, the SSD control component transfers the data read from the non-volatile storage medium to the storage space indicated by the host address of the IO command; if the IO command is a write command, the control component moves the data in the storage space indicated by the host address of the IO command to the non-volatile storage medium. After the IO command processing is completed, the control component of the SSD also generates a completion command indicating that the IO command processing is completed. The completion command is, for example, a completion command that complies with the NVMe specification.

[0081] In response to receiving a completion command corresponding to the IO command, the CMB cache unit used by the IO command is released. Optionally, the completion command indicates an index of the CMB cache unit to be released.

[0082] As an example, the IO command management unit uses system calls such as pread() / pwrite() to operate the NVMe device driver to generate NVMe commands. The parameter "__offset" of the system call Pread() / pwrite() is used to represent the logical address. In an embodiment according to the present application, when calling Pread() / pwrite(), the parameter "__offset" representing the logical address is filled with the index (CMB ID) of the CMB cache unit. In response to the system call, the NVMe device driver (or other similar storage device drivers) uses the parameter "__offset" provided by the Pread() / pwrite() system call to generate the logical address field in the NVMe command, thereby replacing the logical address in the IO command with the index (CMB ID) of the cache unit.

[0083] Still taking an example, in the prior art, in response to the Pread() system call, the NVMe device driver generates a read command and sends it to the storage device, and in response to the Pwead() system call, the NVMe device driver generates a write command and sends it to the storage device. According to an embodiment of the present application, the IO command management unit adds, for example, extended information to the cache unit of the CMB, so that although the IO command sent to the storage device is generated by using system calls such as pread() / pwrite(), the storage device knows the meaning of the IO command based on the extended information in the CMB cache unit corresponding to the IO command. For example, the E command (its own opcode indicates that it means a read command) sent to the storage device is generated using the pread() system call, and the extended information is used in the cache unit of the CMB to indicate that the E command is an erase command. Thus, according to an embodiment of the present application, by using, for example, the pread() system call, the storage device is instructed to perform an erase operation.

[0084] According to the SSD of the embodiment of the present application, two interfaces are provided to the host: a first interface such as an NVMe command interface, and a second interface such as a CMB. For each IO command, the host sends part of the IO command through the first interface and sends the other part of the IO command through the second interface. The SSD combines the commands received from each of the two interfaces to obtain a complete IO command and processes the IO command. In one embodiment, the first interface is a traditional storage device interface, and thus the storage device driver of the prior art is used to send part of the IO command to the SSD through the first interface; the second interface is a memory interface, and thus the other part of the IO command is sent to the SSD through the second interface using the prior art. Thus, there is no need to run other drivers in the kernel space of the host. In the SSD, the part of the IO command obtained by the first interface corresponds one to one with the other part of the IO command obtained through the second interface. The SSD combines the parts of the IO command from each interface to obtain a complete IO command and processes it.

[0085] The IO command management unit accesses the NVMe device driver and CMB through system calls such as ioctl and asynchronous IO (Linux Asynchronous I / O) provided by the Linux operating system kernel or user space libraries.

[0086] Figure 4 is a schematic diagram of operating a storage device according to another embodiment of the present application.

[0087] The host is coupled to the SSD and accesses the storage device address space provided by the SSD through a read command.

[0088] The read command provided by the host to the storage device indicates, for example, a physical address that complies with the Open Channel Solid-State Storage Device Specification. The read command provided to the IO command management unit running in the host's user space indicates, for example, a storage space address. The storage space address is, for example, a logical address, a URI, or a physical address. The read command provided to the IO command management unit also indicates a host address, which is used to receive data read from the SSD in response to the read command.

[0089] See Figure 4 , the host includes a memory (shown as a host memory). The memory includes a data cache and optionally a host address cache. The host address of the read command indicates the address of the data cache. In some cases, the data cache includes multiple continuous or discontinuous storage spaces, an address list including multiple entries is used to indicate the multiple storage spaces of the data cache, and the address list including multiple entries is stored in the host address cache. The read command uses the address of the host address cache to indicate the host address. The SSD obtains the address list from the host address cache according to the read command, and transfers the data read from the SSD to the multiple storage spaces corresponding to the host address according to the address list.

[0090] SSDs include command queues, completion queues, and CMBs. For example, the command queue is the SQ (Submission Queue) defined in the NVMe protocol, the completion queue is the CQ (Completion Queue) defined in the NVMe protocol, and the CMB is the controller memory buffer defined in the NVMe protocol. SSDs also include control components for processing I / O commands and NVM (non-volatile memory medium).

[0091] The command queue includes multiple entries, each of which is used to accommodate an IO command. The completion queue includes multiple entries, each of which is used to accommodate a completion command corresponding to an IO command. The CMB includes multiple cache units, each of which is used to accommodate a storage device address (physical address) corresponding to an IO command. Optionally, the cache unit is also used to store metadata and extended information associated with the IO command. Still optionally, the cache unit is also used to accommodate the IO command processing result to be passed to the host via the completion command.

[0092] According to an embodiment of the present application, the IO command management unit of the host allocates a cache unit of the CMB and provides an index of the allocated cache unit of the CMB to each IO command.

[0093] If the address for the IO command received by the IO command management unit is a logical address or a URI, the IO command management unit further generates a storage device address such as a physical address of an open channel solid-state storage device according to the logical address or the URI.

[0094] The IO command management unit writes the storage device address used for the IO command into the cache unit of the CMB allocated for the IO command ( Figure 4 , indicated by an arrow with sequence number (1). Optionally, the IO command management unit also writes metadata or extended information corresponding to the IO command into the cache unit of the CMB allocated for the IO command. The metadata corresponding to the IO command is, for example, the logical address accessed by the IO command.

[0095] The CMB is provided to the host as a memory space, so that the IO command management unit writes the storage device address into the cache unit of the CMB in a manner of accessing the host memory.

[0096] The IO command management unit also writes the read command into the command queue of the SSD ( Figure 4 In the example, the IO command management unit generates a read command that complies with the NVMe protocol through the host's NVMe device driver, and uses the index of the CMB's cache unit as the logical address for the SSD in the read command that complies with the NVMe protocol. As another example, the address for the read command received by the IO command management unit is a URI, and the IO command management unit replaces the URI of the read command added to the command queue with the index of the CMB cache unit that stores the physical address corresponding to the URI. Still as an example, the IO command management unit uses the pread() system call to write the read command to the command queue of the SSD, and when calling pread(), the parameter "__offset" representing the logical address is replaced with the index of the CMB cache unit.

[0097] The control unit of the storage device obtains a read command from the command queue. In response to recognizing that the read command indicates an index of a cache unit of the CMB, the control unit further accesses the cache unit of the CMB according to the index, obtains a physical address, for example, therefrom, and reads data from the NVM of the SSD according to the physical address. The data is then moved to the data cache in the host indicated by the host address of the read command. Optionally, if it is recognized that the read command does not indicate an index of a cache unit of the CMB, but instead indicates a logical address, physical address, or keyword for a KV storage device for the SSD, the control unit reads the data from the non-volatile storage medium according to the logical address, physical address, or keyword for the KV storage device indicated by the read command.

[0098] In response to the completion of processing the read command obtained from the command queue, the control component also generates a completion command for the read command and writes it to the completion queue. As an example, the index of the CMB cache unit indicated by the read command is also written into the completion command. The completion command also indicates, for example, the processing result of the read command, such as success, failure and / or error type. Optionally or further, in response to the failure of the read command processing, the control component writes the error information corresponding to the read command into the cache unit of the CMB indicated by the read command, thereby giving the host an opportunity to obtain the error information to decide how to handle the error. If the read command processing is successful, optionally, no additional information is written to the cache unit of the CMB indicated by the read command.

[0099] The IO command processing unit of the host obtains the completion command indicating the IO command processing result from the completion queue through the NVMe driver ( Figure 4 The processing result of the read command is obtained from the completion command. In one example, if the read command is successfully processed, the IO command management unit releases the cache unit of the CMB indicated by the completion command. Optionally, the index of the cache unit with the CMB is not written in the completion command, and the IO command management unit records the correspondence between the issued IO command and the index of the cache unit of the CMB, and in response to receiving the completion command, releases the CMB cache unit corresponding to the command ID of the completion command according to the command ID of the completion command.

[0100] In another example, if the read command processing fails, the IO command management unit accesses the CMB cache unit according to the CMB cache unit index obtained from the completion command, and reads the error information of the read command from the CMB cache unit ( Figure 4 , indicated by the arrow with sequence number (4)), and release the CMB cache unit corresponding to the completion command.

[0101] Figure 5 is a schematic diagram of operating a storage device according to yet another embodiment of the present application.

[0102] The write command provided by the host to the storage device specifies, for example, a physical address that complies with the Open Channel Solid-State Storage Device specification. The write command provided to the IO command management unit running in the host's user space specifies a storage space address. The storage space address is, for example, a logical address, a URI, or a physical address. The write command provided to the IO command management unit also specifies a host address, which is used to store the data to be written to the SSD.

[0103] A write command indicates the host address, for example, using an address from the host address cache. Based on the write command, the SSD retrieves an address list from the host address cache and, based on the address list, moves data from the multiple storage spaces corresponding to the host address to the SSD, writing the data to the non-volatile storage medium indicated by the physical address. Optionally, the one or more storage spaces corresponding to the host address are provided by a CMB. Before adding the write command to the command queue, the host has already moved some or all of the data to be written by the write command to the storage space provided by the CMB.

[0104] The SSD includes a command queue, a completion queue, and a CMB. The CMB includes multiple cache units, each of which is used to store the storage device address (physical address) corresponding to an IO command. Optionally, the cache unit is also used to store metadata and extended information associated with the IO command. Still optionally, the cache unit is also used to store the IO command processing results to be transmitted to the host via the completion command.

[0105] The IO command management unit of the host allocates a cache unit of the CMB and provides an index of the allocated cache unit of the CMB to each IO command.

[0106] The IO command management unit writes the storage device address used for the write command into the cache unit of the CMB allocated for the write command ( Figure 5 , indicated by the arrow with sequence number (1). Optionally, the IO command management unit also writes metadata or extended information corresponding to the write command into the cache unit of the CMB allocated for the write command. The metadata corresponding to the write command is, for example, the logical address accessed by the write command or the check information corresponding to the data to be written by the write command.

[0107] The IO command management unit also writes the write command into the command queue of the SSD ( Figure 5 In the example, the write command is indicated by the arrow with the sequence number (2), indicating the index of the CMB cache unit allocated for the write command, and the physical address for the write command has been written into the cache unit. Still for example, the IO command management unit uses the pwrite() system call to write the write command to the command queue of the SSD. When calling pwrite(), the parameter "__offset" representing the logical address is replaced with the index of the CMB cache unit.

[0108] The storage device's control unit retrieves a write command from the command queue. Based on the host address of the write command, it moves the data to be written to the SSD from the host's data cache to the SSD. Optionally, if the data to be written to the SSD by the write command is already in the CMB, moving the data from the data cache can be omitted.

[0109] In response to recognizing that the write command indicates the index of the CMB's cache unit, the control component also accesses the CMB's cache unit according to the index, obtains, for example, a physical address therefrom, and writes the data to be written to the SSD by the write command into the non-volatile storage medium indicated by the physical address according to the physical address.

[0110] Optionally, if it is identified that the write command does not indicate the index of the cache unit of the CMB, but indicates a logical address, physical address or keyword for the SSD or a KV storage device, the control component writes the data to be written to the SSD by the write command into the non-volatile storage medium of the SSD according to the logical address, physical address or keyword for the KV storage device indicated by the write command.

[0111] In response to the completion of processing a write command received from the command queue, the control component also generates a completion command for the write command and writes it to the completion queue. For example, the index of the CMB cache unit indicated by the write command is also written to the completion command. The completion command also indicates, for example, the processing result of the write command.

[0112] The IO command processing unit of the host obtains the completion command indicating the IO command processing result from the completion queue through the NVMe driver ( Figure 5 The processing result of the write command is obtained from the completion command. In one example, if the write command is successfully processed, the IO command management unit releases the cache unit of the CMB indicated by the completion command.

[0113] In another example, if the write command processing fails, the IO command management unit accesses the CMB cache unit according to the CMB cache unit index obtained from the completion command, and reads the error information of the write command from the CMB cache unit ( Figure 5 , indicated by the arrow with sequence number (4)), and release the CMB cache unit corresponding to the completion command.

[0114] In yet another example, the IO command management unit further writes extended information to the CMB cache unit to instruct the SSD whether to provide a completion command corresponding to the write command to the host immediately after moving the pending data to the SSD, or to provide the completion command corresponding to the write command to the host after storing the pending data to the SSD's non-volatile storage medium. In response, after receiving the write command, the SSD accesses the CMB cache unit based on the CMB cache unit index indicated by the write command, retrieves the extended information from the CMB cache unit, and determines when to provide the completion command corresponding to the write command to the host.

[0115] According to one embodiment of the present application, an application running in a host wishes to issue an erase command to an SSD through an IO command management unit. The IO command management unit allocates a cache unit of a CMB, and writes a physical address and extended information representing an erase command to the allocated cache unit. The IO command management unit also issues a so-called "read command" or "write command" to the SSD through a pread() or pwrite() system call. The parameter "__offset" of the "read command" or "write command" indicates the index of the cache unit of the allocated CMB. On the other hand, although the IO command obtained by the SSD is formally a "read command" or a "write command", the SSD recognizes that the command indicates the index of the cache unit of the CMB, and obtains the extended information and physical address from the corresponding CMB cache unit. Based on the obtained extended information, the SSD recognizes that the command indicates an erase operation, and implements the erase operation on the specified physical address.

[0116] Thus, the IO command management unit can issue commands other than read or write commands to the SSD through system calls such as read(), pread(), write(), and / or pwrite(). In this way, the host can also issue customized private commands to the SSD. The extended information stored in the CMB cache unit indicates the meaning of the private command and the parameters required to execute the private command. The SSD recognizes the meaning of the private command through the extended information and processes it.

[0117] Although the present application has been described with reference to examples, this is for illustrative purposes only and is not intended to limit the present application, and changes, additions and / or deletions to the embodiments may be made without departing from the scope of the present application.

[0118] The above description is merely a specific embodiment of the present application, but the scope of protection of the present application is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this application should be included in the scope of protection of this application. Therefore, the scope of protection of this application should be based on the scope of protection of the claims.

Claims

1. A computer comprising: processors and open-channel storage devices; The processor adds a first-class address to a cache unit of a memory space of the open channel storage device, wherein the first-class address is a physical address of the storage device, and the memory space is a memory space accessible to the processor and provided by the open channel storage device; replaces a second-class address indicated by an IO command with an index of the cache unit to generate an IO command, wherein the second-class address is a logical address; and sends the IO command to the open channel storage device; The open channel storage device receives the IO command, obtains a first-class address from the cache unit according to the cache unit index in the IO command, and accesses the NVM according to the first-class address.

2. The computer according to claim 1, wherein The open channel storage device receives the IO command, and in response to recognizing that the IO command does not indicate a cache unit index but indicates a keyword for a KV storage device, converts the keyword into a first-class address according to a flash translation layer (FTL), and accesses the NVM according to the first-class address.

3. The computer according to claim 1 or 2, wherein: The processor generates a first type address according to the logical address of the accessed storage space of the open channel storage device, or converts a URI or a keyword into a first type address, so as to store the first type address in a cache unit of the open channel storage device.

4. The computer according to claim 1 or 2, wherein: The processor operates the storage device driver to generate an IO command by using pread() / pwrite() system calls.

5. The computer according to claim 4, wherein When the processor uses the pread() / pwrite() system call, the address parameter "__offset" is set to the cache unit index, and the storage device driver uses the address parameter "__offset" to generate the second type address of the IO command.

6. The computer according to claim 1 or 2, wherein: In response to adding the first type of address to the cache unit, the processor also adds metadata associated with the IO command to the cache unit.

7. The computer according to claim 1 or 2, wherein: In response to adding the first type address to the cache unit, the processor further adds extended information associated with the IO command to the cache unit; The open channel storage device obtains extended information from the cache unit according to the cache unit index in the IO command, and learns the extended meaning of the IO command according to the extended information.

8. The computer according to claim 1 or 2, wherein: The open channel storage device generates a completion command in response to completion of the IO command processing, the completion command including a cache unit index indicated by the corresponding IO command; The processor releases the cache unit according to the cache unit index included in the completion command.

9. The computer according to claim 8, wherein The timing for the open channel storage device to provide the completion command to the host is to provide the completion command corresponding to the write command to the host immediately after moving the data to be written by the write command to the cache unit, or to provide the completion command corresponding to the write command to the host after storing the data to be written by the write command in the NVM.

10. The computer according to claim 1 or 2, wherein: In response to a failure in processing the IO command, the open channel storage device writes error information corresponding to the IO command into the cache unit indicated by the IO command; The processor obtains error information from the cache unit according to the failed processing result.

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