Data processing method, device, chip and medium

Abstract

This specification provides a data processing method, device, chip and medium, belonging to the field of data processing technology. The method obtains the instruction data, connection relationship data and weight data corresponding to the multi-core chip in the target task, and then associates and stores the instruction data, connection relationship data and weight data corresponding to the same neuron to the target location of the off-chip memory of the multi-core chip, so as to realize the off-chip associative storage of the instruction data, connection relationship data and weight data, thereby reducing the occurrence of insufficient storage space in the on-chip memory.

Description

Technical Field

[0001] The present invention relates to the field of data processing technology, and in particular to a data processing method, device, chip and medium. Background Art

[0002] With the increasing demand for high-performance computing, the research on many-core chips, as a chip with a large number of computing cores and strong computing power, has gradually become one of the important research directions in the field of chip research. Core chips can store various types of data, including instruction data, connection relationship data, weight data, etc., so that each computing core of the many-core chip can act as an executor of a neuron and execute the calculation process of the corresponding neuron based on the stored data, thereby realizing the corresponding data processing. Summary of the invention

[0003] This specification provides a data processing method, device, chip and medium.

[0004] According to a first aspect of an embodiment of this specification, a data processing method is provided, which is applied to a many-core chip, and the method includes:

[0005] Obtaining instruction data, connection relationship data and weight data corresponding to the many-core chip in the target task;

[0006] The instruction data, connection relationship data and weight data corresponding to the same neuron are stored in a target location of the off-chip memory of the multi-core chip in association with each other;

[0007] The instruction data is used to indicate the operation to be performed by the multi-core chip on each neuron, and the connection relationship data is used to indicate the connection relationship between each neuron.

[0008] In some embodiments of the present specification, after the instruction data, connection relationship data and weight data corresponding to the same neuron are stored in association at a target location of the off-chip memory of the many-core chip, the method further includes:

[0009] Obtain target instruction data, target connection relationship data, and target weight data of neurons corresponding to the target computing core from the target location of the off-chip memory;

[0010] Based on the target computing core, the data of the corresponding neuron is processed according to the target instruction data, the target connection relationship data and the target weight data.

[0011] In some embodiments of the present specification, the instruction data, connection relationship data and weight data corresponding to the same neuron are stored in association at a target location of the off-chip memory of the many-core chip, including:

[0012] For any neuron, determining first instruction data, first connection relationship data and first weight data corresponding to the neuron from the instruction data, the connection relationship data and the weight data corresponding to the many-core chip in the target task;

[0013] The first instruction data, the first connection relationship data and the first weight data are associated and stored at a target location of the off-chip memory.

[0014] In some embodiments of the present specification, the target position includes a first target position and a second target position;

[0015] The first instruction data, the first connection relationship data, and the first weight data are stored in association at a target location of the off-chip memory, including:

[0016] Obtaining an instruction identifier of the first instruction data, and associatively storing the instruction identifier, the first connection relationship data, and the first weight data at the first target location of the off-chip memory;

[0017] The first instruction data is stored in the second target location of the off-chip memory.

[0018] In some embodiments of the present specification, the method further includes:

[0019] When other neurons correspond to the first instruction data, the second connection relationship data and the second weight data, the instruction identifier, the second connection relationship data and the second weight data are associated and stored at the third target location of the off-chip memory.

[0020] In some embodiments of this specification, the instruction data, the connection relationship data, and the weight data correspond to neuron identifiers;

[0021] For any neuron, determining first instruction data, first connection relationship data, and first weight data corresponding to the neuron from the instruction data, the connection relationship data, and the weight data corresponding to the many-core chip in the target task, includes:

[0022] Based on the neuron identifier corresponding to the instruction data, the connection relationship data and the weight data, the instruction data, the connection relationship data and the weight data corresponding to the neuron identifier of the neuron are obtained from the instruction data, the connection relationship data and the weight data as the first instruction data, the first connection relationship data and the first weight data.

[0023] According to a second aspect of an embodiment of this specification, a data processing device is provided, which is applied to a multi-core chip, and the device includes:

[0024] An acquisition module is used to acquire instruction data, connection relationship data and weight data corresponding to the many-core chip in the target task;

[0025] A storage module, used for associatively storing instruction data, connection relationship data and weight data corresponding to the same neuron at a target location of an off-chip memory of the many-core chip;

[0026] The instruction data is used to indicate the operation to be performed by the multi-core chip on each neuron, and the connection relationship data is used to indicate the connection relationship between each neuron.

[0027] In some embodiments of the present specification, the acquisition module is further used to acquire target instruction data, target connection relationship data and target weight data of neurons corresponding to the target computing core from the target location of the off-chip memory;

[0028] The device also includes:

[0029] A processing module is used to process the data of the corresponding neuron based on the target computing core, according to the target instruction data, the target connection relationship data and the target weight data.

[0030] In some embodiments of the present specification, the storage module, when used to associate and store instruction data, connection relationship data, and weight data corresponding to the same neuron at a target location of an off-chip memory of the many-core chip, includes a determination unit and a storage unit;

[0031] The determination unit is used to determine, for any neuron, first instruction data, first connection relationship data and first weight data corresponding to the neuron from the instruction data, the connection relationship data and the weight data corresponding to the many-core chip in the target task;

[0032] The storage unit is used to associate and store the first instruction data, the first connection relationship data and the first weight data at a target location of the off-chip memory.

[0033] In some embodiments of the present specification, the target position includes a first target position and a second target position;

[0034] The storage unit, when used to associate and store the first instruction data, the first connection relationship data and the first weight data at a target location of the off-chip memory, is used to:

[0035] Obtaining an instruction identifier of the first instruction data, and associatively storing the instruction identifier, the first connection relationship data, and the first weight data at the first target location of the off-chip memory;

[0036] The first instruction data is stored in the second target location of the off-chip memory.

[0037] In some embodiments of the present specification, the storage unit is also used to store the instruction identifier, the second connection relationship data and the second weight data in an associated manner at a third target location of the off-chip memory when other neurons correspond to the first instruction data, the second connection relationship data and the second weight data.

[0038] In some embodiments of this specification, the instruction data, the connection relationship data, and the weight data correspond to neuron identifiers;

[0039] The determining unit, when used to determine, for any neuron, first instruction data, first connection relationship data, and first weight data corresponding to the neuron from the instruction data, the connection relationship data, and the weight data corresponding to the many-core chip in the target task, is used to:

[0040] Based on the neuron identifier corresponding to the instruction data, the connection relationship data and the weight data, the instruction data, the connection relationship data and the weight data corresponding to the neuron identifier of the neuron are obtained from the instruction data, the connection relationship data and the weight data as the first instruction data, the first connection relationship data and the first weight data.

[0041] According to a third aspect of an embodiment of this specification, a many-core chip is provided, comprising a memory, multiple computing cores, and a computer program stored in the memory and executable on the computing cores, wherein the computing cores implement the operations performed by the above-mentioned data processing method when executing the computer program.

[0042] According to a fourth aspect of the embodiments of this specification, a computer-readable storage medium is provided, on which a program is stored, and the program is used by a computing core to execute the operations performed by the above-mentioned data processing method.

[0043] According to a fifth aspect of the embodiments of this specification, a computer program product is provided, including a computer program, which implements the operations performed by the above-mentioned data processing method when executed by a computing core.

[0044] The technical solutions provided by the embodiments of this specification may have the following beneficial effects:

[0045] By obtaining the instruction data, connection relationship data and weight data corresponding to the many-core chip during the target task process, the instruction data, connection relationship data and weight data corresponding to the same neuron are associated and stored in the target location of the off-chip memory of the many-core chip to realize the off-chip associative storage of the instruction data, connection relationship data and weight data, thereby reducing the occurrence of insufficient storage space in the on-chip memory.

[0046] It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present specification. BRIEF DESCRIPTION OF THE DRAWINGS

[0047] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the specification and, together with the description, serve to explain the principles of the specification.

[0048] Figure 1 It is a flow chart of a data processing method shown in this specification according to an exemplary embodiment.

[0049] Figure 2 It is a schematic diagram of a data processing method according to an exemplary embodiment of the present specification.

[0050] Figure 3 It is a block diagram of a data processing device shown in this specification according to an exemplary embodiment. DETAILED DESCRIPTION

[0051] Exemplary embodiments will be described in detail herein, examples of which are shown in the accompanying drawings. When the following description refers to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The implementations described in the following exemplary embodiments do not represent all implementations consistent with this specification. Instead, they are merely examples of devices and methods consistent with some aspects of this specification as detailed in this application.

[0052] The terms used in this specification are only for the purpose of describing specific embodiments and are not intended to limit this specification. The singular forms of "a", "the" and "the" used in this application are also intended to include plural forms unless the context clearly indicates other meanings. It should also be understood that the term "and / or" used in this article refers to and includes any or all possible combinations of one or more associated listed items.

[0053] It should be understood that although the terms first, second, third, etc. may be used in this specification to describe various information, these information should not be limited to these terms. These terms are only used to distinguish the same type of information from each other. For example, without departing from the scope of this specification, the first instruction data may also be referred to as the second instruction data, and similarly, the second instruction data may also be referred to as the first instruction data. Depending on the context, the word "if" as used herein may be interpreted as "at the time of" or "when" or "in response to determining".

[0054] In the related art, the weight data of the many-core chip is stored in the off-chip memory of the many-core chip, while the instruction data and connection relationship data are stored in the on-chip memory of the many-core chip. However, since the storage space of the on-chip memory of the many-core chip is limited, as the amount of stored data increases, the storage space of the on-chip memory will be insufficient.

[0055] Based on the above situation, the present application provides a data processing method that can be applied to a many-core chip, and is used to store data acquired by the many-core chip, including instruction data, connection relationship data, and weight data. Among them, the many-core chip is a chip including multiple computing cores, and the computing core can be used as an executor of a neuron in a neural network to execute the computing process corresponding to the neuron, so that the many-core chip can complete the data processing process of the neural network based on the neuron.

[0056] When processing data through the many-core chip, the corresponding neural network can be mapped to the many-core chip, so that the calculation process corresponding to each neuron in the neural network is executed based on the multiple computing cores included in the many-core chip.

[0057] Optionally, when the computing core executes the computing process corresponding to a neuron, one computing core can execute the computing process corresponding to one neuron, one computing core can execute the computing process corresponding to multiple neurons at the same time, or multiple computing cores can execute the computing process corresponding to one neuron at the same time. This application does not limit this.

[0058] Optionally, the many-core chip is a computing chip, or the many-core chip is a sensing chip, etc., and the present application does not limit the chip type of the many-core chip. The many-core chip can be applied to various types of computing devices, for example, the many-core chip can be applied to a server, or the many-core chip can be applied to a terminal, such as a desktop computer, a portable computer, a tablet computer, a smart phone, a smart watch, etc., and the present application does not limit this.

[0059] The above is a relevant introduction to the application scenarios of the present application. Next, in conjunction with the embodiments of this specification, the data processing method provided by the present application is described in detail.

[0060] like Figure 1 As shown, Figure 1 This is a flow chart of a data processing method according to an exemplary embodiment of the present specification, which is applied to a multi-core chip. The method includes the following steps:

[0061] Step 101: Obtain instruction data, connection relationship data and weight data corresponding to the many-core chip in the target task.

[0062] The many-core chip may include multiple computing cores for executing computing processes corresponding to neurons included in the neural network mapped in the many-core chip. One computing core may process one or more neurons, or multiple computing cores may process one neuron.

[0063] The instruction data is used to indicate the operation to be performed by the multi-core chip on each neuron, and the instruction data corresponding to different neurons can be the same or different. The above operation can be a convolution operation, a pooling operation, etc., and the specific type of operation is not limited in this application.

[0064] The connection relationship data is used to indicate the connection relationship between each neuron, which can be the connection relationship between a neuron and other neurons mapped in the same computing core, or the connection relationship between a neuron and other neurons mapped in different computing cores. Generally speaking, the connection relationship data corresponding to each neuron is different.

[0065] The weight data is used to indicate the weight parameters corresponding to each neuron. Generally speaking, the weight data corresponding to each neuron is different.

[0066] It should be noted that the target task may be a training task or other computing task for the neural network composed of the multiple neurons. Accordingly, the instruction data corresponding to the many-core chip in the target task may be the instruction data used by the many-core chip in the process of executing the target task, for example, it may be data generated according to the settings of relevant technicians and used to indicate the operations performed by each neuron.

[0067] The connection relationship data corresponding to the many-core chip in the target task may be the data of the connection relationship between various neurons required by the many-core chip in the process of executing the target task. For example, it may be data generated according to the settings of relevant technicians to indicate how various neurons are connected to form the neural network.

[0068] The weight data corresponding to the many-core chip in the target task may be the weight data required by the many-core chip in the process of executing the target task, for example, the weight parameters corresponding to each neuron obtained through training.

[0069] In a possible implementation, the neural network composed of the multiple neurons may be trained in advance, and when the training is completed, the instruction data, connection relationship data and weight data corresponding to the trained neural network are obtained.

[0070] The above is only an exemplary description of the target task. In more possible implementations, the target task may also be other tasks. This application does not limit the specific type of the target task.

[0071] Step 102: Associate and store the instruction data, connection relationship data and weight data corresponding to the same neuron at a target location of the off-chip memory of the many-core chip.

[0072] It should be noted that the many-core chip includes an on-chip memory. In addition, the many-core chip is also associated with an off-chip memory, so that the data of the many-core chip can be stored together through the on-chip memory and the off-chip memory. In a possible implementation, each computing core in the many-core chip is provided with an independent storage unit, and the storage unit of each computing core in the many-core chip can also be referred to as the "on-chip memory" inside the many-core chip. In the embodiment of the present application, the off-chip memory and the on-chip memory are relative to the on-chip or off-chip of the many-core chip.

[0073] In one possible implementation, the instruction data, connection relationship data, and weight data corresponding to the same neuron can be stored in the same location, while the instruction data, connection relationship data, and weight data corresponding to different neurons can be stored in another location, thereby realizing neuron-based classification storage, so that the instruction data, connection relationship data, and weight data corresponding to different neurons can be stored in different locations of the off-chip memory, thereby realizing the associated storage of instruction data, connection relationship data, and weight data.

[0074] It should be noted that the above process of realizing the associative storage of instruction data, connection relationship data and weight data by limiting the storage location is only an exemplary way to realize the associative storage. In other embodiments, other methods can also be used to realize the associative storage of instruction data, connection relationship data and weight data, and the present application does not limit this.

[0075] Through the above-mentioned associative storage process, the binding of instruction data, connection relationship data and weight data of the same neuron can be achieved, so that the multi-core chip can quickly obtain the various data required for the data processing process implemented by the computing core from the off-chip memory, thereby improving data acquisition efficiency.

[0076] The solution provided in the present application obtains the instruction data, connection relationship data and weight data corresponding to the many-core chip in the target task, and then associates and stores the instruction data, connection relationship data and weight data corresponding to the same neuron at the target location of the off-chip memory of the many-core chip, so as to realize the off-chip associative storage of the instruction data, connection relationship data and weight data, thereby reducing the occurrence of insufficient storage space in the on-chip memory.

[0077] After introducing the basic implementation process of the present application, various non-limiting implementation methods of the present application are specifically introduced below.

[0078] In some embodiments, the instruction data, connection relationship data, and weight data corresponding to the same neuron are stored in association at a target location of an off-chip memory of the many-core chip, including:

[0079] Step 1021: For any neuron, determine the first instruction data, first connection relationship data and first weight data corresponding to the neuron from the instruction data, connection relationship data and weight data corresponding to the many-core chip in the target task.

[0080] It should be noted that since the neural network mapped in the many-core chip includes multiple neurons, the connection relationship data and weight data corresponding to different neurons are generally different, and when the instruction data, connection relationship data and weight data are stored, they are stored based on neuron classification. Therefore, when storing the instruction data, connection relationship data and weight data, the instruction data, connection relationship data and weight data corresponding to each neuron can be first determined from all the instruction data, connection relationship data and weight data corresponding to the target task, so that neuron-based classification storage can be realized later.

[0081] Step 1022: associate and store the first instruction data, the first connection relationship data, and the first weight data at a target location in an off-chip memory.

[0082] The target location may be any storage location in the off-chip memory. For example, when the instruction data, connection relationship data, and weight data are stored in association, it is implemented in an exemplary manner by limiting the storage location, and the instruction data, connection relationship data, and weight data of different neurons have different corresponding target locations.

[0083] In some embodiments, the instruction data, connection relationship data and weight data corresponding to the many-core chip in the target task all correspond to corresponding neuron identifiers to indicate which neuron these instruction data, connection relationship data and weight data are data corresponding to. Therefore, for the above step 1021, when determining the first instruction data, first connection relationship data and first weight data corresponding to the neuron from the instruction data, connection relationship data and weight data corresponding to the many-core chip in the target task for any neuron, the following implementation methods can be used:

[0084] In one possible implementation, based on the neuron identifier corresponding to the instruction data, connection relationship data and weight data, the instruction data, connection relationship data and weight data corresponding to the neuron identifier of the neuron are obtained from the instruction data, connection relationship data and weight data as the first instruction data, first connection relationship data and first weight data.

[0085] For the sake of convenience of explanation, any neuron involved in the above step 1021 is called the first neuron, so that based on the neuron identifier corresponding to the instruction data, connection relationship data and weight data corresponding to the multi-core chip in the target task, the instruction data, connection relationship data and weight data corresponding to the neuron identifier of the first neuron are obtained from these data, and the obtained data are also the first instruction data, the first connection relationship data and the first weight data.

[0086] It should be noted that the above is only the process of obtaining the first instruction data, the first connection relationship data and the first weight data corresponding to the first neuron. For other neurons (such as the second neuron, the third neuron,..., the Nth neuron), the process of obtaining the instruction data, connection relationship data and weight data corresponding to other neurons is the same as the above process, which will not be repeated here.

[0087] After obtaining the instruction data, connection relationship data and weight data corresponding to each neuron, the instruction data, connection relationship data and weight data corresponding to each neuron can be associated and stored respectively. The specific process of storing data is described by taking the storage process of the first instruction data, the first connection relationship data and the first weight data corresponding to any neuron as an example.

[0088] Take the example of implementing the associated storage of instruction data, connection relationship data, and weight data by limiting the storage location. In some embodiments, the target location includes a first target location and a second target location. Based on this, for the above step 1022, when the first instruction data, the first connection relationship data, and the first weight data are associated and stored at the target location of the off-chip memory, the following implementation methods can be used:

[0089] The first instruction data, the first connection relationship data and the first weight data corresponding to the first neuron are associated and stored in a first target location of the off-chip memory, and the second instruction data, the second connection relationship data and the second weight data corresponding to the second neuron are associated and stored in a second target location of the off-chip memory, thereby realizing neuron-based classification storage.

[0090] The first instruction data and the second instruction data may be the same instruction data or different instruction data, which is not limited in the present application.

[0091] The above process is only explained by taking the storage process of data corresponding to two neurons as an example. For the data corresponding to other neurons, the data corresponding to the third neuron, the data corresponding to the fourth neuron, ..., the data corresponding to the Mth neuron can be stored in the third target position, the fourth target position, ..., the Mth target position of the off-chip memory in sequence. The specific process is the same as the above process and will not be repeated here.

[0092] The above process is explained by taking the direct associative storage of instruction data, connection relationship data and weight data as an example. In more possible implementations, the association of instruction data, connection relationship data and weight data can also be achieved through instruction identification. In this case, the first target location can be used to achieve the associative storage of instruction identification, connection relationship data and weight data, and the second target location can be used to achieve the storage of instruction data. That is, the above step 1022 can also be achieved through the following steps:

[0093] Step 1: Obtain an instruction identifier of the first instruction data, and associate and store the instruction identifier, first connection relationship data, and first weight data at a first target location in an off-chip memory.

[0094] Among them, the instruction identifier is used to identify the instruction data. Since the instruction data is divided according to the instruction type, the instruction data corresponding to the same type of instructions are the same. Therefore, the instruction identifier can also indicate the type of instruction to be executed, so that the corresponding instruction data can be determined based on the instruction identifier.

[0095] Step 2: Store the first instruction data at a second target location in the off-chip memory.

[0096] It should be noted that the order of step 1 and step 2 above does not limit the actual execution order.

[0097] Since the instruction data corresponding to different neurons can be the same, the above steps 1 and 2 store the instruction identifier, connection relationship data, and weight data in association, and store the actual instruction data separately, so that when the instruction data corresponding to other neurons is the same as that of the neuron, there is no need to store the instruction data repeatedly, but the instruction identifier and the connection relationship and weight data corresponding to other neurons can be stored together. This method can effectively reduce the repeated storage of the same instruction data and can effectively save the storage of off-chip memory.

[0098] That is, when other neurons correspond to the first instruction data, the second connection relationship data and the second weight data, the instruction identifier of the first instruction data, the second connection relationship data and the second weight data can be associated and stored in the off-chip memory, for example, in the third target location of the off-chip memory.

[0099] By storing the instruction identifier, connection relationship data and weight data in an associated manner and storing the actual instruction data separately, multiple neurons can reuse the instruction data stored in the off-chip memory, thereby reducing the storage pressure of the off-chip memory and increasing the data storage speed.

[0100] The above-mentioned embodiments are explained by taking the process of realizing the associative storage of instruction data, connection relationship data and weight data by limiting the storage location as an example. In other embodiments, other methods can also be used to realize the associative storage of instruction data, connection relationship data and weight data. The present application does not limit the specific method used to realize the associative storage.

[0101] The storage principles of the above embodiments can be found in Figure 2 , Figure 2 is a schematic diagram of a data processing method according to an exemplary embodiment of the present specification. Figure 2 Taking a many-core chip including 9 computing cores as an example, the many-core chip is associated with an off-chip memory, in which the instruction data, connection relationship data and weight data corresponding to each neuron are stored respectively, thereby realizing the off-chip associative storage of instruction data, connection relationship data and weight data corresponding to multiple neurons.

[0102] In some embodiments, after step 102, that is, after the instruction data, connection relationship data and weight data corresponding to the same neuron are stored in the target location of the off-chip memory of the many-core chip, the data processing method may further include the following steps:

[0103] Step 103: Obtain target instruction data, target connection relationship data, and target weight data of neurons corresponding to the target computing core from the target location of the off-chip memory.

[0104] Optionally, when the instruction data, connection relationship data and weight data are stored in an off-chip associative manner, the stored instruction data, connection relationship data and weight data may be marked with a neuron identifier, so that the neuron to which the stored data corresponds can be determined based on the marked neuron identifier. Based on this, the above step 103 may be implemented as follows:

[0105] In one possible implementation, based on the neuron identifiers of neurons included in a neural network used for data processing, instruction data, connection relationship data, and weight data marked with the neuron identifiers are obtained from a target location in an off-chip memory as target instruction data, target connection relationship data, and target weight data for neurons corresponding to a target computing core.

[0106] Among them, the many-core chip includes multiple computing cores, and the target computing core is a computing core among the multiple computing cores, which is used to execute the computing process of the neurons included in the above-mentioned neural network.

[0107] Step 104: Based on the target computing core, the data of the corresponding neuron is processed according to the target instruction data, the target connection relationship data and the target weight data.

[0108] The neuron data may be input data to the multi-core chip, or may be activation values ​​or calculation result data of other neurons. The present application does not limit the specific type of neuron data processed.

[0109] In one possible implementation, the target computing core can process the data of the corresponding neurons based on the target weight data of the corresponding neurons and in accordance with the connection relationship between neurons indicated by the target connection relationship data, by executing the operation indicated by the target instruction data, thereby obtaining the corresponding data processing results, so as to realize the data processing process of the many-core chip.

[0110] Optionally, when processing the data of the corresponding neurons, feature extraction processing, convolution processing, prediction processing, etc. can be used. Accordingly, the data processing results can be calculation results (such as feature extraction results, convolution calculation results, etc.), prediction results (such as predicted user behaviors, etc.), etc., which are not limited in this application.

[0111] In the above embodiment, in the process of executing the calculation operation corresponding to the neuron mapped to the many-core chip, the instruction data, connection relationship data and weight data of the corresponding neuron can be obtained from the off-chip memory of the many-core chip, so as to execute the calculation process corresponding to the neuron based on the obtained instruction data, connection relationship data and weight data. In this way, the data of the corresponding neuron can be obtained from the off-chip memory and the calculation process can be performed, and the calculation of the corresponding neuron is not limited to performing the calculation of the corresponding neuron on the basis of storing the instruction data on the chip.

[0112] Corresponding to the embodiments of the aforementioned method, this specification also provides embodiments of a device and a multi-core chip used therein.

[0113] like Figure 3 As shown, Figure 3 is a block diagram of a data processing device according to an exemplary embodiment of the present specification, the device comprising:

[0114] An acquisition module 301 is used to acquire instruction data, connection relationship data and weight data corresponding to the many-core chip in the target task;

[0115] A storage module 302 is used to associate and store instruction data, connection relationship data and weight data corresponding to the same neuron at a target location of an off-chip memory of the many-core chip;

[0116] The instruction data is used to indicate the operation to be performed by the multi-core chip on each neuron, and the connection relationship data is used to indicate the connection relationship between each neuron.

[0117] In some embodiments of the present specification, the acquisition module 301 is further used to acquire target instruction data, target connection relationship data and target weight data of neurons corresponding to the target computing core from the target location of the off-chip memory;

[0118] The device also includes:

[0119] A processing module is used to process the data of the corresponding neuron based on the target computing core, according to the target instruction data, the target connection relationship data and the target weight data.

[0120] In some embodiments of the present specification, the storage module 302, when used to associate and store instruction data, connection relationship data, and weight data corresponding to the same neuron at a target location of an off-chip memory of the many-core chip, includes a determination unit and a storage unit;

[0121] The determination unit is used to determine, for any neuron, first instruction data, first connection relationship data and first weight data corresponding to the neuron from the instruction data, the connection relationship data and the weight data corresponding to the many-core chip in the target task;

[0122] The storage unit is used to associate and store the first instruction data, the first connection relationship data and the first weight data at a target location of the off-chip memory.

[0123] In some embodiments of the present specification, the target position includes a first target position and a second target position;

[0124] The storage unit, when used to associate and store the first instruction data, the first connection relationship data and the first weight data at a target location of the off-chip memory, is used to:

[0125] Obtaining an instruction identifier of the first instruction data, and associatively storing the instruction identifier, the first connection relationship data, and the first weight data at the first target location of the off-chip memory;

[0126] The first instruction data is stored in the second target location of the off-chip memory.

[0127] In some embodiments of the present specification, the storage unit is also used to store the instruction identifier, the second connection relationship data and the second weight data in an associated manner at a third target location of the off-chip memory when other neurons correspond to the first instruction data, the second connection relationship data and the second weight data.

[0128] In some embodiments of this specification, the instruction data, the connection relationship data, and the weight data correspond to neuron identifiers;

[0129] The determining unit, when used to determine, for any neuron, first instruction data, first connection relationship data, and first weight data corresponding to the neuron from the instruction data, the connection relationship data, and the weight data corresponding to the many-core chip in the target task, is used to:

[0130] Based on the neuron identifier corresponding to the instruction data, the connection relationship data and the weight data, the instruction data, the connection relationship data and the weight data corresponding to the neuron identifier of the neuron are obtained from the instruction data, the connection relationship data and the weight data as the first instruction data, the first connection relationship data and the first weight data.

[0131] The implementation process of the functions and effects of each module and unit in the above-mentioned device is specifically described in the implementation process of the corresponding steps in the above-mentioned method, which will not be repeated here.

[0132] For the device embodiment, since it basically corresponds to the method embodiment, the relevant parts can refer to the partial description of the method embodiment. The device embodiment described above is only schematic, wherein the modules described as separate components may or may not be physically separated, and the components displayed as modules may or may not be physical modules, that is, they may be located in one place, or they may be distributed on multiple network modules. Some or all of the modules may be selected according to actual needs to achieve the purpose of the scheme of this specification. A person of ordinary skill in the art can understand and implement it without paying creative labor.

[0133] The present application also provides a many-core chip, which includes a memory and multiple computing cores, and a computer program stored in the memory and executable on the computing cores, wherein the computing cores implement the operations performed by the data processing method described in any embodiment when executing the program.

[0134] The present application also provides a computer-readable storage medium, which can be in various forms. For example, in different examples, the computer-readable storage medium can be: RAM (Radom Access Memory), volatile memory, non-volatile memory, flash memory, storage drive (such as hard disk drive), solid state drive, any type of storage disk (such as optical disk, DVD, etc.), or similar storage medium, or a combination thereof. In particular, the computer-readable storage medium can also be paper or other suitable medium capable of printing programs. A computer program is stored on the computer-readable storage medium, and when the computer program is executed by the computing core, the data processing method provided in any embodiment of the present application is implemented.

[0135] The present application also provides a computer program product, including a computer program, which implements the data processing method provided in any embodiment of the present application when the computer program is executed by a computing core.

[0136] It should be understood by those skilled in the art that one or more embodiments of the present specification may be provided as methods, devices, chips, computer-readable storage media or computer program products. Therefore, one or more embodiments of the present specification may take the form of a complete hardware embodiment, a complete software embodiment or an embodiment combining software and hardware. Moreover, one or more embodiments of the present specification may take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program codes.

[0137] Each embodiment in this specification is described in a progressive manner, and the same or similar parts between the embodiments can be referred to each other, and each embodiment focuses on the differences from other embodiments. In particular, for the embodiment corresponding to the chip, since it is basically similar to the method embodiment, the description is relatively simple, and the relevant parts can be referred to the partial description of the method embodiment.

[0138] The above specific embodiments of this specification are described. Other embodiments are within the scope of this application. In some cases, the actions or steps recorded in this application can be performed in an order different from that in the embodiments and still achieve the desired results. In addition, the process depicted in the accompanying drawings does not necessarily require the specific order or continuous order shown to achieve the desired results. In some embodiments, multitasking and parallel processing are also possible or may be advantageous.

[0139] The embodiments of the subject matter and functional operations described in this specification may be implemented in the following: digital electronic circuits, tangibly embodied computer software or firmware, hardware including the structures disclosed in this specification and their structural equivalents, or a combination of one or more of them. The embodiments of the subject matter described in this specification may be implemented as one or more computer programs, i.e., one or more modules in computer program instructions encoded on a tangible non-transitory program carrier to be executed by a data processing device or to control the operation of the data processing device. Alternatively or additionally, the program instructions may be encoded on an artificially generated propagation signal, such as a machine-generated electrical, optical or electromagnetic signal, which is generated to encode information and transmit it to a suitable receiver device for execution by a data processing device. The computer-readable storage medium may be a machine-readable storage device, a machine-readable storage substrate, a random or serial access memory device, or a combination of one or more of them.

[0140] Although this specification includes many specific implementation details, these should not be interpreted as limiting the scope of any invention or the scope of protection claimed, but are mainly used to describe the features of the specific embodiments of specific inventions. Certain features described in multiple embodiments in this specification may also be implemented in combination in a single embodiment. On the other hand, the various features described in a single embodiment may also be implemented separately in multiple embodiments or in any suitable sub-combination. In addition, although features may work in certain combinations as described above and even initially claim protection, one or more features from the claimed combination may be removed from the combination in some cases, and the claimed combination may point to a sub-combination or a variation of a sub-combination.

[0141] Similarly, although operations are depicted in a particular order in the accompanying drawings, this should not be understood as requiring that these operations be performed in the particular order shown or performed sequentially, or requiring that all illustrated operations be performed to achieve the desired results. In some cases, multitasking and parallel processing may be advantageous. In addition, the separation of various system modules and components in the above-described embodiments should not be understood as requiring such separation in all embodiments, and it should be understood that the described program components and systems can generally be integrated together in a single software product, or packaged into multiple software products.

[0142] Thus, specific embodiments of the subject matter have been described. Other embodiments are within the scope of the present application. In some cases, the actions described in the present application can be performed in a different order and still achieve the desired results. In addition, the processing depicted in the accompanying drawings does not necessarily require the specific order or sequential order shown to achieve the desired results. In some implementations, multitasking and parallel processing may be advantageous.

[0143] Those skilled in the art will readily appreciate other embodiments of the present specification after considering the specification and practicing the invention claimed herein. The present specification is intended to cover any variations, uses or adaptations of the present specification that follow the general principles of the present specification and include common knowledge or customary techniques in the art that are not claimed in the present specification. That is, the present specification is not limited to the precise structure described above and shown in the accompanying drawings, and various modifications and changes may be made without departing from the scope thereof.

[0144] The above description is only an optional embodiment of this specification and is not intended to limit this specification. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of this specification should be included in the scope of protection of this specification.

Claims

1. A data processing method, characterized in that: Applied to a many-core chip, the method includes: Obtaining instruction data, connection relationship data and weight data corresponding to the many-core chip in the target task; The instruction data, connection relationship data and weight data corresponding to the same neuron are stored in a target location of the off-chip memory of the many-core chip in association with each other; wherein the instruction data is used to indicate the operation to be performed by the many-core chip on each neuron, and the connection relationship data is used to indicate the connection relationship between each neuron; Wherein, the target position includes a first target position and a second target position; The method of associatively storing the instruction data, connection relationship data and weight data corresponding to the same neuron at a target location of the off-chip memory of the many-core chip includes: For any neuron, determining first instruction data, first connection relationship data and first weight data corresponding to the neuron from the instruction data, the connection relationship data and the weight data corresponding to the many-core chip in the target task; Acquire an instruction identifier of the first instruction data, and associate and store the instruction identifier, the first connection relationship data, and the first weight data at the first target location of the off-chip memory; The first instruction data is stored in the second target location of the off-chip memory.

2. The method according to claim 1, characterized in that After the instruction data, connection relationship data and weight data corresponding to the same neuron are stored in association at a target location of the off-chip memory of the many-core chip, the method further includes: Acquire target instruction data, target connection relationship data, and target weight data of neurons corresponding to a target computing core from a target location of the off-chip memory; Based on the target computing core, the data of the corresponding neuron is processed according to the target instruction data, the target connection relationship data and the target weight data.

3. The method according to claim 1, characterized in that: The method further comprises: In the case where other neurons correspond to the first instruction data, the second connection relationship data and the second weight data, the instruction identifier, the second connection relationship data and the second weight data are associated and stored at a third target location of the off-chip memory.

4. The method according to claim 1, characterized in that The instruction data, the connection relationship data and the weight data correspond to neuron identifiers; The step of determining, for any neuron, first instruction data, first connection relationship data, and first weight data corresponding to the neuron from the instruction data, the connection relationship data, and the weight data corresponding to the many-core chip in the target task comprises: Based on the neuron identifiers corresponding to the instruction data, the connection relationship data and the weight data, the instruction data, the connection relationship data and the weight data corresponding to the neuron identifier of the neuron are obtained from the instruction data, the connection relationship data and the weight data as the first instruction data, the first connection relationship data and the first weight data.

5. A data processing device, characterized in that: Applied to a multi-core chip, the device comprises: An acquisition module, used to acquire instruction data, connection relationship data and weight data corresponding to the many-core chip in the target task; A storage module, used to associate and store instruction data, connection relationship data and weight data corresponding to the same neuron at a target location of an off-chip memory of the many-core chip; wherein the instruction data is used to indicate an operation to be performed by the many-core chip on each neuron, and the connection relationship data is used to indicate a connection relationship between each neuron; Wherein, the target position includes a first target position and a second target position; The storage module, when used to associate and store instruction data, connection relationship data and weight data corresponding to the same neuron at a target location of an off-chip memory of the many-core chip, comprises a determination unit and a storage unit; The determining unit is used to determine, for any neuron, first instruction data, first connection relationship data and first weight data corresponding to the neuron from the instruction data, the connection relationship data and the weight data corresponding to the many-core chip in the target task; The storage unit is used to obtain an instruction identifier of the first instruction data, and associate and store the instruction identifier, the first connection relationship data, and the first weight data at the first target location of the off-chip memory; The storage unit is further used to store the first instruction data at the second target location of the off-chip memory.

6. The device according to claim 5, characterized in that The acquisition module is further used to acquire target instruction data, target connection relationship data and target weight data of neurons corresponding to the target computing core from the target location of the off-chip memory; The device also includes: A processing module is used to process the data of the corresponding neuron based on the target computing core, according to the target instruction data, the target connection relationship data and the target weight data.

7. A many-core chip, characterized in that: The many-core chip includes a memory and multiple computing cores, and a computer program stored in the memory and executable on the computing cores, wherein the computing cores implement the operations performed by the data processing method as described in any one of claims 1 to 4 when executing the program.

8. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a program, and the program is used by a computing core to execute the operations performed by the data processing method according to any one of claims 1 to 4.

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